diff --git a/components/freertos/CMakeLists.txt b/components/freertos/CMakeLists.txt index 46686a18e8..d40948ec8a 100644 --- a/components/freertos/CMakeLists.txt +++ b/components/freertos/CMakeLists.txt @@ -81,7 +81,6 @@ if(CONFIG_IDF_TARGET_ARCH_XTENSA) "${kernel_dir}/portable/${arch}/xtensa_context.S" "${kernel_dir}/portable/${arch}/xtensa_init.c" "${kernel_dir}/portable/${arch}/xtensa_overlay_os_hook.c" - "${kernel_dir}/portable/${arch}/xtensa_vector_defaults.S" "${kernel_dir}/portable/${arch}/xtensa_vectors.S") endif() diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vector_defaults.S b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vector_defaults.S deleted file mode 100644 index 628b75aef5..0000000000 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vector_defaults.S +++ /dev/null @@ -1,230 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "xtensa_rtos.h" -#include "esp_private/panic_reason.h" -#include "sdkconfig.h" -#include "soc/soc.h" - -/* -This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. -The default behaviour is to just exit the interrupt or call the panic handler on the exceptions -*/ - - -#if XCHAL_HAVE_DEBUG - .global xt_debugexception - .weak xt_debugexception - .set xt_debugexception, _xt_debugexception - .section .iram1,"ax" - .type _xt_debugexception,@function - .align 4 - -_xt_debugexception: -#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) -#define XT_DEBUGCAUSE_DI (5) - getcoreid a0 -#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM) - beqz a0, 1f -#else - bnez a0, 1f -#endif - - rsr a0, DEBUGCAUSE - extui a0, a0, XT_DEBUGCAUSE_DI, 1 - bnez a0, _xt_debug_di_exc -1: -#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) - - movi a0,PANIC_RSN_DEBUGEXCEPTION - wsr a0,EXCCAUSE - /* _xt_panic assumes a level 1 exception. As we're - crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL - to level 1. */ - rsr a0,(EPC + XCHAL_DEBUGLEVEL) - wsr a0,EPC_1 - rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) - wsr a0,EXCSAVE_1 - call0 _xt_panic /* does not return */ - rfi XCHAL_DEBUGLEVEL - -#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) - .align 4 -_xt_debug_di_exc: - - /* - The delay time can be calculated by the following formula: - T = ceil(0.25 + max(t1, t2)) us - - t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2 - - f1: PSRAM access frequency, unit: MHz. - f2: Flash access frequency, unit: MHz. - - When flash is slow/fast read, N = 1. - When flash is DOUT/DIO read, N = 2. - When flash is QOUT/QIO read, N = 4. - - And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times. - */ -#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT) - -# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) - movi a0, 54 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 108 -# else - movi a0, 135 -# endif - -#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT) - -# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 135 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 189 -# else - movi a0, 243 -# endif - -#else - movi a0, 243 -#endif - -1: addi a0, a0, -1 /* delay_us(N) */ - .rept 4 - nop - .endr - bnez a0, 1b - - rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL - rfi XCHAL_DEBUGLEVEL -#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) -#endif /* Debug exception */ - - -#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 - .global xt_highint2 - .weak xt_highint2 - .set xt_highint2, _xt_highint2 - .section .iram1,"ax" - .type _xt_highint2,@function - .align 4 -_xt_highint2: - - /* Default handler does nothing; just returns */ - .align 4 -.L_xt_highint2_exit: - rsr a0, EXCSAVE_2 /* restore a0 */ - rfi 2 - -#endif /* Level 2 */ - -#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 - - .global xt_highint3 - .weak xt_highint3 - .set xt_highint3, _xt_highint3 - .section .iram1,"ax" - .type _xt_highint3,@function - .align 4 -_xt_highint3: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint3_exit: - rsr a0, EXCSAVE_3 /* restore a0 */ - rfi 3 - -#endif /* Level 3 */ - -#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 - - .global xt_highint4 - .weak xt_highint4 - .set xt_highint4, _xt_highint4 - .section .iram1,"ax" - .type _xt_highint4,@function - .align 4 -_xt_highint4: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint4_exit: - rsr a0, EXCSAVE_4 /* restore a0 */ - rfi 4 - -#endif /* Level 4 */ - -#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 - - .global xt_highint5 - .weak xt_highint5 - .set xt_highint5, _xt_highint5 - .section .iram1,"ax" - .type _xt_highint5,@function - .align 4 -_xt_highint5: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint5_exit: - rsr a0, EXCSAVE_5 /* restore a0 */ - rfi 5 - - -#endif /* Level 5 */ - -#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 - - .global _xt_highint6 - .global xt_highint6 - .weak xt_highint6 - .set xt_highint6, _xt_highint6 - .section .iram1,"ax" - .type _xt_highint6,@function - .align 4 -_xt_highint6: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint6_exit: - rsr a0, EXCSAVE_6 /* restore a0 */ - rfi 6 - -#endif /* Level 6 */ - -#if XCHAL_HAVE_NMI - - .global _xt_nmi - .global xt_nmi - .weak xt_nmi - .set xt_nmi, _xt_nmi - .section .iram1,"ax" - .type _xt_nmi,@function - .align 4 -_xt_nmi: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_nmi_exit: - rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ - rfi XCHAL_NMILEVEL - -#endif /* NMI */ diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vectors.S b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vectors.S index 61e1c79968..d0eaef4140 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vectors.S +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/xtensa_vectors.S @@ -442,8 +442,102 @@ _DebugExceptionVector: .end literal_prefix + .global xt_debugexception + .weak xt_debugexception + .set xt_debugexception, _xt_debugexception + .section .iram1,"ax" + .type _xt_debugexception,@function + .align 4 +_xt_debugexception: +#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) +#define XT_DEBUGCAUSE_DI (5) + getcoreid a0 +#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM) + beqz a0, 1f +#else + bnez a0, 1f #endif + rsr a0, DEBUGCAUSE + extui a0, a0, XT_DEBUGCAUSE_DI, 1 + bnez a0, _xt_debug_di_exc +1: +#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + + movi a0,PANIC_RSN_DEBUGEXCEPTION + wsr a0,EXCCAUSE + /* _xt_panic assumes a level 1 exception. As we're + crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL + to level 1. */ + rsr a0,(EPC + XCHAL_DEBUGLEVEL) + wsr a0,EPC_1 + rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) + wsr a0,EXCSAVE_1 + call0 _xt_panic /* does not return */ + rfi XCHAL_DEBUGLEVEL + +#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + .align 4 +_xt_debug_di_exc: + + /* + The delay time can be calculated by the following formula: + T = ceil(0.25 + max(t1, t2)) us + + t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2 + + f1: PSRAM access frequency, unit: MHz. + f2: Flash access frequency, unit: MHz. + + When flash is slow/fast read, N = 1. + When flash is DOUT/DIO read, N = 2. + When flash is QOUT/QIO read, N = 4. + + And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times. + */ +#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT) + +# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) + movi a0, 54 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 108 +# else + movi a0, 135 +# endif + +#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT) + +# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 135 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 189 +# else + movi a0, 243 +# endif + +#else + movi a0, 243 +#endif + +1: addi a0, a0, -1 /* delay_us(N) */ + .rept 4 + nop + .endr + bnez a0, 1b + + rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL + rfi XCHAL_DEBUGLEVEL +#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) +#endif // XCHAL_HAVE_DEBUG + /* -------------------------------------------------------------------------------- Double Exception. @@ -1587,9 +1681,9 @@ the minimum necessary before jumping to the handler in the .text section. *******************************************************************************/ /* -These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define -these in an external assembly source file. If these symbols are not defined anywhere -else, the defaults in xtensa_vector_defaults.S are used. +Currently only shells for high priority interrupt handlers are provided +here. However a template and example can be found in the Cadence Design Systems tools +documentation: "Microprocessor Programmer's Guide". */ #if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 @@ -1602,10 +1696,37 @@ else, the defaults in xtensa_vector_defaults.S are used. .align 4 _Level2Vector: wsr a0, EXCSAVE_2 /* preserve a0 */ - call0 xt_highint2 /* load interrupt handler */ + call0 xt_highint2 /* load interrupt handler */ .end literal_prefix + .global xt_highint2 + .weak xt_highint2 + .set xt_highint2, _xt_highint2 + .section .iram1, "ax" + .type _xt_highint2,@function + .align 4 +_xt_highint2: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 2<<2 + beqz a0, 1f +.Ln_xt_highint2_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint2_exit: + rsr a0, EXCSAVE_2 /* restore a0 */ + rfi 2 + #endif /* Level 2 */ #if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 @@ -1618,11 +1739,38 @@ _Level2Vector: .align 4 _Level3Vector: wsr a0, EXCSAVE_3 /* preserve a0 */ - call0 xt_highint3 /* load interrupt handler */ + call0 xt_highint3 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ .end literal_prefix + .global xt_highint3 + .weak xt_highint3 + .set xt_highint3, _xt_highint3 + .section .iram1, "ax" + .type _xt_highint3,@function + .align 4 +_xt_highint3: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 3<<2 + beqz a0, 1f +.Ln_xt_highint3_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint3_exit: + rsr a0, EXCSAVE_3 /* restore a0 */ + rfi 3 + #endif /* Level 3 */ #if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 @@ -1635,11 +1783,38 @@ _Level3Vector: .align 4 _Level4Vector: wsr a0, EXCSAVE_4 /* preserve a0 */ - call0 xt_highint4 /* load interrupt handler */ + call0 xt_highint4 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ .end literal_prefix + .global xt_highint4 + .weak xt_highint4 + .set xt_highint4, _xt_highint4 + .section .iram1, "ax" + .type _xt_highint4,@function + .align 4 +_xt_highint4: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 4<<2 + beqz a0, 1f +.Ln_xt_highint4_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint4_exit: + rsr a0, EXCSAVE_4 /* restore a0 */ + rfi 4 + #endif /* Level 4 */ #if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 @@ -1657,6 +1832,33 @@ _Level5Vector: .end literal_prefix + .global xt_highint5 + .weak xt_highint5 + .set xt_highint5, _xt_highint5 + .section .iram1, "ax" + .type _xt_highint5,@function + .align 4 +_xt_highint5: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 5<<2 + beqz a0, 1f +.Ln_xt_highint5_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint5_exit: + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + #endif /* Level 5 */ #if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 @@ -1674,6 +1876,33 @@ _Level6Vector: .end literal_prefix + .global xt_highint6 + .weak xt_highint6 + .set xt_highint6, _xt_highint6 + .section .iram1, "ax" + .type _xt_highint6,@function + .align 4 +_xt_highint6: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 6<<2 + beqz a0, 1f +.Ln_xt_highint6_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint6_exit: + rsr a0, EXCSAVE_6 /* restore a0 */ + rfi 6 + #endif /* Level 6 */ #if XCHAL_HAVE_NMI @@ -1691,6 +1920,33 @@ _NMIExceptionVector: .end literal_prefix + .global xt_nmi + .weak xt_nmi + .set xt_nmi, _xt_nmi + .section .iram1, "ax" + .type _xt_nmi,@function + .align 4 +_xt_nmi: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, XCHAL_NMILEVEL<<2 + beqz a0, 1f +.Ln_xt_nmi_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE. + */ + + .align 4 +.L_xt_nmi_exit: + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ + rfi XCHAL_NMILEVEL + #endif /* NMI */ diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vector_defaults.S b/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vector_defaults.S deleted file mode 100644 index 0784dd8092..0000000000 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vector_defaults.S +++ /dev/null @@ -1,236 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "xtensa_rtos.h" -#include "esp_private/panic_reason.h" -#include "sdkconfig.h" -#include "soc/soc.h" - -/* -This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. -The default behaviour is to just exit the interrupt or call the panic handler on the exceptions -*/ - - -#if XCHAL_HAVE_DEBUG - .global xt_debugexception - .weak xt_debugexception - .set xt_debugexception, _xt_debugexception - .section .iram1,"ax" - .type _xt_debugexception,@function - .align 4 - -_xt_debugexception: -#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) - s32i a0, sp, XT_STK_EXIT - -#define XT_DEBUGCAUSE_DI (5) - getcoreid a0 -#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM) - beqz a0, 1f -#else - bnez a0, 1f -#endif - - rsr a0, DEBUGCAUSE - extui a0, a0, XT_DEBUGCAUSE_DI, 1 - bnez a0, _xt_debug_di_exc -1: -#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) - - movi a0,PANIC_RSN_DEBUGEXCEPTION - wsr a0,EXCCAUSE - /* _xt_panic assumes a level 1 exception. As we're - crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL - to level 1. */ - rsr a0,(EPC + XCHAL_DEBUGLEVEL) - wsr a0,EPC_1 - rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) - wsr a0,EXCSAVE_1 -#if CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME - J _xt_panic_gdbstub /* For gdbstub we make jump */ -#else - call0 _xt_panic /* does not return */ -#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME - rfi XCHAL_DEBUGLEVEL - -#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) - .align 4 -_xt_debug_di_exc: - - /* - The delay time can be calculated by the following formula: - T = ceil(0.25 + max(t1, t2)) us - - t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2 - - f1: PSRAM access frequency, unit: MHz. - f2: Flash access frequency, unit: MHz. - - When flash is slow/fast read, N = 1. - When flash is DOUT/DIO read, N = 2. - When flash is QOUT/QIO read, N = 4. - - And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times. - */ -#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT) - -# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) - movi a0, 54 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 108 -# else - movi a0, 135 -# endif - -#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT) - -# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 81 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 135 -# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) - movi a0, 189 -# else - movi a0, 243 -# endif - -#else - movi a0, 243 -#endif - -1: addi a0, a0, -1 /* delay_us(N) */ - .rept 4 - nop - .endr - bnez a0, 1b - - rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL - rfi XCHAL_DEBUGLEVEL -#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) -#endif /* Debug exception */ - - -#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 - .global xt_highint2 - .weak xt_highint2 - .set xt_highint2, _xt_highint2 - .section .iram1,"ax" - .type _xt_highint2,@function - .align 4 -_xt_highint2: - - /* Default handler does nothing; just returns */ - .align 4 -.L_xt_highint2_exit: - rsr a0, EXCSAVE_2 /* restore a0 */ - rfi 2 - -#endif /* Level 2 */ - -#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 - - .global xt_highint3 - .weak xt_highint3 - .set xt_highint3, _xt_highint3 - .section .iram1,"ax" - .type _xt_highint3,@function - .align 4 -_xt_highint3: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint3_exit: - rsr a0, EXCSAVE_3 /* restore a0 */ - rfi 3 - -#endif /* Level 3 */ - -#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 - - .global xt_highint4 - .weak xt_highint4 - .set xt_highint4, _xt_highint4 - .section .iram1,"ax" - .type _xt_highint4,@function - .align 4 -_xt_highint4: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint4_exit: - rsr a0, EXCSAVE_4 /* restore a0 */ - rfi 4 - -#endif /* Level 4 */ - -#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 - - .global xt_highint5 - .weak xt_highint5 - .set xt_highint5, _xt_highint5 - .section .iram1,"ax" - .type _xt_highint5,@function - .align 4 -_xt_highint5: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint5_exit: - rsr a0, EXCSAVE_5 /* restore a0 */ - rfi 5 - - -#endif /* Level 5 */ - -#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 - - .global _xt_highint6 - .global xt_highint6 - .weak xt_highint6 - .set xt_highint6, _xt_highint6 - .section .iram1,"ax" - .type _xt_highint6,@function - .align 4 -_xt_highint6: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_highint6_exit: - rsr a0, EXCSAVE_6 /* restore a0 */ - rfi 6 - -#endif /* Level 6 */ - -#if XCHAL_HAVE_NMI - - .global _xt_nmi - .global xt_nmi - .weak xt_nmi - .set xt_nmi, _xt_nmi - .section .iram1,"ax" - .type _xt_nmi,@function - .align 4 -_xt_nmi: - - /* Default handler does nothing; just returns */ - - .align 4 -.L_xt_nmi_exit: - rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ - rfi XCHAL_NMILEVEL - -#endif /* NMI */ diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S b/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S index 2b42dec014..40c372abe7 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S @@ -442,8 +442,108 @@ _DebugExceptionVector: .end literal_prefix + .global xt_debugexception + .weak xt_debugexception + .set xt_debugexception, _xt_debugexception + .section .iram1,"ax" + .type _xt_debugexception,@function + .align 4 +_xt_debugexception: +#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + s32i a0, sp, XT_STK_EXIT + +#define XT_DEBUGCAUSE_DI (5) + getcoreid a0 +#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM) + beqz a0, 1f +#else + bnez a0, 1f #endif + rsr a0, DEBUGCAUSE + extui a0, a0, XT_DEBUGCAUSE_DI, 1 + bnez a0, _xt_debug_di_exc +1: +#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + + movi a0,PANIC_RSN_DEBUGEXCEPTION + wsr a0,EXCCAUSE + /* _xt_panic assumes a level 1 exception. As we're + crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL + to level 1. */ + rsr a0,(EPC + XCHAL_DEBUGLEVEL) + wsr a0,EPC_1 + rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) + wsr a0,EXCSAVE_1 +#if CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + J _xt_panic_gdbstub /* For gdbstub we make jump */ +#else + call0 _xt_panic /* does not return */ +#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + rfi XCHAL_DEBUGLEVEL + +#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + .align 4 +_xt_debug_di_exc: + + /* + The delay time can be calculated by the following formula: + T = ceil(0.25 + max(t1, t2)) us + + t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2 + + f1: PSRAM access frequency, unit: MHz. + f2: Flash access frequency, unit: MHz. + + When flash is slow/fast read, N = 1. + When flash is DOUT/DIO read, N = 2. + When flash is QOUT/QIO read, N = 4. + + And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times. + */ +#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT) + +# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) + movi a0, 54 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 108 +# else + movi a0, 135 +# endif + +#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT) + +# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 135 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 189 +# else + movi a0, 243 +# endif + +#else + movi a0, 243 +#endif + +1: addi a0, a0, -1 /* delay_us(N) */ + .rept 4 + nop + .endr + bnez a0, 1b + + rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL + rfi XCHAL_DEBUGLEVEL +#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) +#endif // XCHAL_HAVE_DEBUG + /* -------------------------------------------------------------------------------- Double Exception. @@ -1588,9 +1688,9 @@ the minimum necessary before jumping to the handler in the .text section. *******************************************************************************/ /* -These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define -these in an external assembly source file. If these symbols are not defined anywhere -else, the defaults in xtensa_vector_defaults.S are used. +Currently only shells for high priority interrupt handlers are provided +here. However a template and example can be found in the Cadence Design Systems tools +documentation: "Microprocessor Programmer's Guide". */ #if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 @@ -1603,10 +1703,37 @@ else, the defaults in xtensa_vector_defaults.S are used. .align 4 _Level2Vector: wsr a0, EXCSAVE_2 /* preserve a0 */ - call0 xt_highint2 /* load interrupt handler */ + call0 xt_highint2 /* load interrupt handler */ .end literal_prefix + .global xt_highint2 + .weak xt_highint2 + .set xt_highint2, _xt_highint2 + .section .iram1, "ax" + .type _xt_highint2,@function + .align 4 +_xt_highint2: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 2<<2 + beqz a0, 1f +.Ln_xt_highint2_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint2_exit: + rsr a0, EXCSAVE_2 /* restore a0 */ + rfi 2 + #endif /* Level 2 */ #if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 @@ -1619,11 +1746,38 @@ _Level2Vector: .align 4 _Level3Vector: wsr a0, EXCSAVE_3 /* preserve a0 */ - call0 xt_highint3 /* load interrupt handler */ + call0 xt_highint3 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ .end literal_prefix + .global xt_highint3 + .weak xt_highint3 + .set xt_highint3, _xt_highint3 + .section .iram1, "ax" + .type _xt_highint3,@function + .align 4 +_xt_highint3: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 3<<2 + beqz a0, 1f +.Ln_xt_highint3_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint3_exit: + rsr a0, EXCSAVE_3 /* restore a0 */ + rfi 3 + #endif /* Level 3 */ #if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 @@ -1636,11 +1790,38 @@ _Level3Vector: .align 4 _Level4Vector: wsr a0, EXCSAVE_4 /* preserve a0 */ - call0 xt_highint4 /* load interrupt handler */ + call0 xt_highint4 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ .end literal_prefix + .global xt_highint4 + .weak xt_highint4 + .set xt_highint4, _xt_highint4 + .section .iram1, "ax" + .type _xt_highint4,@function + .align 4 +_xt_highint4: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 4<<2 + beqz a0, 1f +.Ln_xt_highint4_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint4_exit: + rsr a0, EXCSAVE_4 /* restore a0 */ + rfi 4 + #endif /* Level 4 */ #if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 @@ -1658,6 +1839,33 @@ _Level5Vector: .end literal_prefix + .global xt_highint5 + .weak xt_highint5 + .set xt_highint5, _xt_highint5 + .section .iram1, "ax" + .type _xt_highint5,@function + .align 4 +_xt_highint5: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 5<<2 + beqz a0, 1f +.Ln_xt_highint5_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint5_exit: + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + #endif /* Level 5 */ #if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 @@ -1675,6 +1883,33 @@ _Level6Vector: .end literal_prefix + .global xt_highint6 + .weak xt_highint6 + .set xt_highint6, _xt_highint6 + .section .iram1, "ax" + .type _xt_highint6,@function + .align 4 +_xt_highint6: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 6<<2 + beqz a0, 1f +.Ln_xt_highint6_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint6_exit: + rsr a0, EXCSAVE_6 /* restore a0 */ + rfi 6 + #endif /* Level 6 */ #if XCHAL_HAVE_NMI @@ -1692,6 +1927,33 @@ _NMIExceptionVector: .end literal_prefix + .global xt_nmi + .weak xt_nmi + .set xt_nmi, _xt_nmi + .section .iram1, "ax" + .type _xt_nmi,@function + .align 4 +_xt_nmi: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, XCHAL_NMILEVEL<<2 + beqz a0, 1f +.Ln_xt_nmi_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE. + */ + + .align 4 +.L_xt_nmi_exit: + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ + rfi XCHAL_NMILEVEL + #endif /* NMI */