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bugfix(i2s): fix bck polarity issue when using pll clock.

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reported from github: https://github.com/espressif/esp-idf/issues/1119

Digital team think it is due to the decimal divider.
We can reset the i2s tx and rx when calling i2s_stop to avoid this.
This commit is contained in:
Wangjialin 2017-10-19 23:23:01 +08:00
parent 6cc8099610
commit a84db78eb1
1 changed files with 6 additions and 0 deletions
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6
components/driver/i2s.c
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@ -344,6 +344,7 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
i2s_stop(i2s_num);
uint32_t cur_mode = 0;
if (p_i2s_obj[i2s_num]->channel_num != ch) {
p_i2s_obj[i2s_num]->channel_num = (ch == 2) ? 2 : 1;
@ -682,6 +683,11 @@ esp_err_t i2s_stop(i2s_port_t i2s_num)
I2S[i2s_num]->lc_conf.in_rst = 0;
I2S[i2s_num]->lc_conf.out_rst = 1;
I2S[i2s_num]->lc_conf.out_rst = 0;
I2S[i2s_num]->conf.tx_reset = 1;
I2S[i2s_num]->conf.tx_reset = 0;
I2S[i2s_num]->conf.rx_reset = 1;
I2S[i2s_num]->conf.rx_reset = 0;
I2S_EXIT_CRITICAL();
return 0;
}