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Merge branch 'bugfix/emac_structs_cpp_build' into 'master'

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fixed emac soc structs names to be able to build under C++

Closes IDFGH-10003

See merge request espressif/esp-idf!23658
This commit is contained in:
Ondrej Kosta 2023-05-12 16:38:12 +08:00
commit a76eab4d39
4 changed files with 38 additions and 38 deletions
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6
components/hal/include/hal/emac_hal.h
View File

@ -157,9 +157,9 @@ typedef struct {
ESP_STATIC_ASSERT(sizeof(eth_dma_rx_descriptor_t) == 32, "eth_dma_rx_descriptor_t should occupy 32 bytes in memory");
volatile typedef struct emac_mac_dev_t *emac_mac_soc_regs_t;
volatile typedef struct emac_dma_dev_t *emac_dma_soc_regs_t;
volatile typedef struct emac_ext_dev_t *emac_ext_soc_regs_t;
typedef struct emac_mac_dev_s *emac_mac_soc_regs_t;
typedef struct emac_dma_dev_s *emac_dma_soc_regs_t;
typedef struct emac_ext_dev_s *emac_ext_soc_regs_t;
typedef struct {
emac_mac_soc_regs_t mac_regs;

14
components/soc/esp32/include/soc/emac_dma_struct.h
View File

@ -12,8 +12,8 @@ extern "C"
#include <stdint.h>
typedef volatile struct emac_dma_dev_t {
union {
typedef struct emac_dma_dev_s {
volatile union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/
uint32_t dma_arb_sch : 1; /*This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/
@ -38,7 +38,7 @@ typedef volatile struct emac_dma_dev_t {
uint32_t dmarxpolldemand; /*When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.*/
uint32_t dmarxbaseaddr; /*This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/
uint32_t dmatxbaseaddr; /*This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.*/
union {
volatile union {
struct {
uint32_t trans_int : 1; /*This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor.*/
uint32_t trans_proc_stop : 1; /*This bit is set when the transmission is stopped.*/
@ -68,7 +68,7 @@ typedef volatile struct emac_dma_dev_t {
};
uint32_t val;
} dmastatus;
union {
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t start_stop_rx : 1; /*When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame.*/
@ -94,7 +94,7 @@ typedef volatile struct emac_dma_dev_t {
};
uint32_t val;
} dmaoperation_mode;
union {
volatile union {
struct {
uint32_t dmain_tie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled.*/
uint32_t dmain_tse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled.*/
@ -116,7 +116,7 @@ typedef volatile struct emac_dma_dev_t {
};
uint32_t val;
} dmain_en;
union {
volatile union {
struct {
uint32_t missed_fc : 16; /*This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/
uint32_t overflow_bmfc : 1; /*This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
@ -126,7 +126,7 @@ typedef volatile struct emac_dma_dev_t {
};
uint32_t val;
} dmamissedfr;
union {
volatile union {
struct {
uint32_t riwtc : 8; /*This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/
uint32_t reserved8 : 24;

12
components/soc/esp32/include/soc/emac_ext_struct.h
View File

@ -11,8 +11,8 @@ extern "C" {
#include <stdint.h>
typedef volatile struct emac_ext_dev_t {
union {
typedef struct emac_ext_dev_s {
volatile union {
struct {
uint32_t div_num : 4;
uint32_t h_div_num : 4;
@ -21,7 +21,7 @@ typedef volatile struct emac_ext_dev_t {
};
uint32_t val;
} ex_clkout_conf;
union {
volatile union {
struct {
uint32_t div_num_10m : 6;
uint32_t h_div_num_10m : 6;
@ -32,7 +32,7 @@ typedef volatile struct emac_ext_dev_t {
};
uint32_t val;
} ex_oscclk_conf;
union {
volatile union {
struct {
uint32_t ext_en : 1;
uint32_t int_en : 1;
@ -44,7 +44,7 @@ typedef volatile struct emac_ext_dev_t {
};
uint32_t val;
} ex_clk_ctrl;
union {
volatile union {
struct {
uint32_t int_revmii_rx_clk_sel : 1;
uint32_t ext_revmii_rx_clk_sel : 1;
@ -61,7 +61,7 @@ typedef volatile struct emac_ext_dev_t {
};
uint32_t val;
} ex_phyinf_conf;
union {
volatile union {
struct {
uint32_t ram_pd_en : 2;
uint32_t reserved2 : 30;

44
components/soc/esp32/include/soc/emac_mac_struct.h
View File

@ -11,8 +11,8 @@ extern "C" {
#include <stdint.h>
volatile typedef struct emac_mac_dev_t {
union {
typedef struct emac_mac_dev_s {
volatile union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
uint32_t rx : 1; /*When this bit is set the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII.*/
@ -43,7 +43,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} gmacconfig;
union {
volatile union {
struct {
uint32_t pmode : 1; /*When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/
uint32_t reserved1 : 1;
@ -67,7 +67,7 @@ volatile typedef struct emac_mac_dev_t {
} gmacff;
uint32_t reserved_1008;
uint32_t reserved_100c;
union {
volatile union {
struct {
uint32_t miibusy : 1; /*This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present.*/
uint32_t miiwrite : 1; /*When set this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register.*/
@ -78,14 +78,14 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} emacgmiiaddr;
union {
volatile union {
struct {
uint32_t mii_data : 16; /*This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/
uint32_t reserved16 : 16;
};
uint32_t val;
} emacmiidata;
union {
volatile union {
struct {
uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled.*/
uint32_t tfce : 1; /*In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled.*/
@ -101,7 +101,7 @@ volatile typedef struct emac_mac_dev_t {
} gmacfc;
uint32_t reserved_101c;
uint32_t reserved_1020;
union {
volatile union {
struct {
uint32_t macrpes : 1; /*When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.*/
uint32_t macrffcs : 2; /*When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/
@ -124,7 +124,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacdebug;
uint32_t pmt_rwuffr; /*The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets*/
union {
volatile union {
struct {
uint32_t pwrdwn : 1; /*When set the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high.*/
uint32_t mgkpkten : 1; /*When set enables generation of a power management event because of magic packet reception.*/
@ -141,7 +141,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} pmt_csr;
union {
volatile union {
struct {
uint32_t tlpien : 1; /*When set this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/
uint32_t tlpiex : 1; /*When set this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/
@ -159,7 +159,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} gmaclpi_crs;
union {
volatile union {
struct {
uint32_t lpi_tw_timer : 16; /*This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/
uint32_t lpi_ls_timer : 10; /*This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
@ -167,7 +167,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} gmaclpitimerscontrol;
union {
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
@ -185,7 +185,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} emacints;
union {
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
@ -198,7 +198,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} emacintmask;
union {
volatile union {
struct {
uint32_t address0_hi : 16; /*This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
uint32_t reserved16 : 15;
@ -207,7 +207,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr0high;
uint32_t emacaddr0low; /*This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
union {
volatile union {
struct {
uint32_t mac_address1_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the second 6-byte MAC Address.*/
uint32_t reserved16 : 8;
@ -218,7 +218,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr1high;
uint32_t emacaddr1low; /*This field contains the lower 32 bits of the second 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
union {
volatile union {
struct {
uint32_t mac_address2_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the third 6-byte MAC address.*/
uint32_t reserved16 : 8;
@ -229,7 +229,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr2high;
uint32_t emacaddr2low; /*This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
union {
volatile union {
struct {
uint32_t mac_address3_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the fourth 6-byte MAC address.*/
uint32_t reserved16 : 8;
@ -240,7 +240,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr3high;
uint32_t emacaddr3low; /*This field contains the lower 32 bits of the fourth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
union {
volatile union {
struct {
uint32_t mac_address4_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the fifth 6-byte MAC address.*/
uint32_t reserved16 : 8;
@ -251,7 +251,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr4high;
uint32_t emacaddr4low; /*This field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
union {
volatile union {
struct {
uint32_t mac_address5_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the sixth 6-byte MAC address.*/
uint32_t reserved16 : 8;
@ -262,7 +262,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr5high;
uint32_t emacaddr5low; /*This field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.*/
union {
volatile union {
struct {
uint32_t mac_address6_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the seventh 6-byte MAC Address.*/
uint32_t reserved16 : 8;
@ -273,7 +273,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t val;
} emacaddr6high;
uint32_t emacaddr6low; /*This field contains the lower 32 bits of the seventh 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
union {
volatile union {
struct {
uint32_t mac_address7_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address.*/
uint32_t reserved16 : 8;
@ -306,7 +306,7 @@ volatile typedef struct emac_mac_dev_t {
uint32_t reserved_10cc;
uint32_t reserved_10d0;
uint32_t reserved_10d4;
union {
volatile union {
struct {
uint32_t link_mode : 1; /*This bit indicates the current mode of operation of the link: 1'b0: Half-duplex mode. 1'b1: Full-duplex mode.*/
uint32_t link_speed : 2; /*This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz.*/
@ -319,7 +319,7 @@ volatile typedef struct emac_mac_dev_t {
};
uint32_t val;
} emaccstatus;
union {
volatile union {
struct {
uint32_t wdogto : 14; /*When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame.*/
uint32_t reserved14 : 2;