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Merge branch 'feat/support_gptimer_on_c61' into 'master'

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feat(gptimer): add gptimer support on c61

Closes IDF-9306

See merge request espressif/esp-idf!32278
This commit is contained in:
morris 2024-07-25 15:24:27 +08:00
commit a746ecc1f2
13 changed files with 374 additions and 418 deletions
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4
components/driver/test_apps/legacy_timer_driver/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

4
components/esp_driver_gptimer/test_apps/gptimer/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

6
components/hal/esp32c61/include/hal/timer_ll.h
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@ -17,8 +17,6 @@
#include "soc/pcr_struct.h"
#include "soc/soc_etm_source.h"
// TODO: [ESP32C61] IDF-9306, inherit from c6
#ifdef __cplusplus
extern "C" {
#endif
@ -113,10 +111,10 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num,
case GPTIMER_CLK_SRC_XTAL:
clk_id = 0;
break;
case GPTIMER_CLK_SRC_PLL_F80M:
case GPTIMER_CLK_SRC_RC_FAST:
clk_id = 1;
break;
case GPTIMER_CLK_SRC_RC_FAST:
case GPTIMER_CLK_SRC_PLL_F80M:
clk_id = 2;
break;
default:

8
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
@ -391,6 +395,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TIMER_GROUP_SUPPORT_RC_FAST
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default n

4
components/soc/esp32c61/include/soc/soc_caps.h
View File

@ -22,7 +22,7 @@
#define SOC_UART_SUPPORTED 1 //TODO: [ESP32C61] IDF-9320
// \#define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
// \#define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
// \#define SOC_GPTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9306
#define SOC_GPTIMER_SUPPORTED 1
// \#define SOC_BT_SUPPORTED 1
// \#define SOC_IEEE802154_SUPPORTED 1
// \#define SOC_ASYNC_MEMCPY_SUPPORTED 1 //TODO: [ESP32C61] IDF-9315
@ -378,7 +378,7 @@
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
// #define SOC_TIMER_SUPPORT_ETM (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/

440
components/soc/esp32c61/include/soc/timer_group_reg.h
View File

@ -15,53 +15,55 @@ extern "C" {
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
#define TIMG_T0_USE_XTAL_V 0x00000001U
#define TIMG_T0_USE_XTAL_S 9
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
* Configures whether or not to enable the timer 0 alarm function. This bit will be
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
* Configures whether or not to reset the timer 0 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
* Represents the timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
* Configures whether or not to enable the timer 0 auto-reload function at the time of
* alarm.
* 0: No effect
* 1: Enable
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
* Configures the counting direction of the timer 0 time-base counter.
* 0: Decrement
* 1: Increment
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
* Configures whether or not to enable the timer 0 time-base counter.
* 0: Disable
* 1: Enable
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
@ -73,8 +75,9 @@ extern "C" {
*/
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
* Represents the low 32 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
@ -86,8 +89,9 @@ extern "C" {
*/
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
* of timer 0 can be read here.
* Represents the high 22 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
@ -95,11 +99,13 @@ extern "C" {
#define TIMG_T0_HI_S 0
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
* Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
*/
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
@ -111,7 +117,9 @@ extern "C" {
*/
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, low 32 bits.
* Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
@ -123,7 +131,9 @@ extern "C" {
*/
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, high 22 bits.
* Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
@ -135,8 +145,9 @@ extern "C" {
*/
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer 0 time-base
* Counter.
* Configures low 32 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
@ -148,8 +159,9 @@ extern "C" {
*/
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer 0 time-base
* Configures high 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
@ -157,261 +169,139 @@ extern "C" {
#define TIMG_T0_LOAD_HI_S 0
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
* Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG
*/
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer 0 time-base counter reload.
*
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
/** TIMG_T1CONFIG_REG register
* Timer 1 configuration register
*/
#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24)
/** TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T1_USE_XTAL (BIT(9))
#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S)
#define TIMG_T1_USE_XTAL_V 0x00000001U
#define TIMG_T1_USE_XTAL_S 9
/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
#define TIMG_T1_ALARM_EN_V 0x00000001U
#define TIMG_T1_ALARM_EN_S 10
/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 1 's clock divider counter will be reset.
*/
#define TIMG_T1_DIVCNT_RST (BIT(12))
#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
#define TIMG_T1_DIVCNT_RST_V 0x00000001U
#define TIMG_T1_DIVCNT_RST_S 12
/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 1 clock (T1_clk) prescaler value.
*/
#define TIMG_T1_DIVIDER 0x0000FFFFU
#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
#define TIMG_T1_DIVIDER_V 0x0000FFFFU
#define TIMG_T1_DIVIDER_S 13
/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 1 auto-reload at alarm is enabled.
*/
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
#define TIMG_T1_AUTORELOAD_V 0x00000001U
#define TIMG_T1_AUTORELOAD_S 29
/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 1 time-base counter will increment every clock tick. When
* cleared, the timer 1 time-base counter will decrement.
*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
#define TIMG_T1_INCREASE_V 0x00000001U
#define TIMG_T1_INCREASE_S 30
/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer 1 time-base counter is enabled.
*/
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S)
#define TIMG_T1_EN_V 0x00000001U
#define TIMG_T1_EN_S 31
/** TIMG_T1LO_REG register
* Timer 1 current value, low 32 bits
*/
#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28)
/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
* of timer 1 can be read here.
*/
#define TIMG_T1_LO 0xFFFFFFFFU
#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S)
#define TIMG_T1_LO_V 0xFFFFFFFFU
#define TIMG_T1_LO_S 0
/** TIMG_T1HI_REG register
* Timer 1 current value, high 22 bits
*/
#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c)
/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
* of timer 1 can be read here.
*/
#define TIMG_T1_HI 0x003FFFFFU
#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S)
#define TIMG_T1_HI_V 0x003FFFFFU
#define TIMG_T1_HI_S 0
/** TIMG_T1UPDATE_REG register
* Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
*/
#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30)
/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
*/
#define TIMG_T1_UPDATE (BIT(31))
#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
#define TIMG_T1_UPDATE_V 0x00000001U
#define TIMG_T1_UPDATE_S 31
/** TIMG_T1ALARMLO_REG register
* Timer 1 alarm value, low 32 bits
*/
#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34)
/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer 1 alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T1_ALARM_LO 0xFFFFFFFFU
#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T1_ALARM_LO_S 0
/** TIMG_T1ALARMHI_REG register
* Timer 1 alarm value, high bits
*/
#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38)
/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer 1 alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T1_ALARM_HI 0x003FFFFFU
#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
#define TIMG_T1_ALARM_HI_V 0x003FFFFFU
#define TIMG_T1_ALARM_HI_S 0
/** TIMG_T1LOADLO_REG register
* Timer 1 reload value, low 32 bits
*/
#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c)
/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer 1 time-base
* Counter.
*/
#define TIMG_T1_LOAD_LO 0xFFFFFFFFU
#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T1_LOAD_LO_S 0
/** TIMG_T1LOADHI_REG register
* Timer 1 reload value, high 22 bits
*/
#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40)
/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer 1 time-base
* counter.
*/
#define TIMG_T1_LOAD_HI 0x003FFFFFU
#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
#define TIMG_T1_LOAD_HI_V 0x003FFFFFU
#define TIMG_T1_LOAD_HI_S 0
/** TIMG_T1LOAD_REG register
* Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
*/
#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44)
/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer 1 time-base counter reload.
*/
#define TIMG_T1_LOAD 0xFFFFFFFFU
#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
#define TIMG_T1_LOAD_V 0xFFFFFFFFU
#define TIMG_T1_LOAD_S 0
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
* Configures whether to enable flash boot protection.
* 0: Disable
* 1: Enable
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
* Configures the system reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
* Configures the CPU reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk, 1-xtal_clk.
*/
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
#define TIMG_WDT_USE_XTAL_V 0x00000001U
#define TIMG_WDT_USE_XTAL_S 21
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
* Configures to update the WDT configuration registers.
* 0: No effect
* 1: Update
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 0. Valid only when write protection is
* disabled.
* 0: No effect
* 1: Interrupt
* 2: Reset CPU
* 3: Reset system
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
* Configures whether or not to enable the MWDT. Valid only when write protection is
* disabled.
* 0: Disable
* 1: Enable
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
@ -423,15 +313,18 @@ extern "C" {
*/
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
* Configures whether to reset WDT 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
* Configures MWDT clock prescaler value. Valid only when write protection is
* disabled.
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
@ -443,7 +336,8 @@ extern "C" {
*/
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
* Configures the stage 0 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
@ -455,7 +349,8 @@ extern "C" {
*/
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
* Configures the stage 1 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
@ -467,7 +362,8 @@ extern "C" {
*/
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
* Configures the stage 2 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
@ -479,7 +375,8 @@ extern "C" {
*/
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
* Configures the stage 3 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
@ -491,7 +388,7 @@ extern "C" {
*/
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
* Write any value to feed the MWDT. Valid only when write protection is disabled.
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
@ -503,8 +400,7 @@ extern "C" {
*/
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
* Configures a different value than its reset value to enable write protection.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
@ -512,11 +408,13 @@ extern "C" {
#define TIMG_WDT_WKEY_S 0
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
* RTC frequency calculation configuration register 0
*/
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
* Configures the frequency calculation mode.
* 0: one-shot frequency calculation
* 1: periodic frequency calculation
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
@ -530,21 +428,26 @@ extern "C" {
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
* Represents whether one-shot frequency calculation is done.
* 0: Not done
* 1: Done
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
* Configures the time to calculate RTC slow clock's frequency.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
* Configures whether to enable one-shot frequency calculation.
* 0: Disable
* 1: Enable
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
@ -552,19 +455,21 @@ extern "C" {
#define TIMG_RTC_CALI_START_S 31
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
* RTC frequency calculation configuration register 1
*/
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
* Represents whether periodic frequency calculation is done.
* 0: Not done
* 1: Done
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
* Represents the value countered by XTAL_CLK when one-shot or periodic frequency
* calculation is done. It is used to calculate RTC slow clock's frequency.
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
@ -576,21 +481,14 @@ extern "C" {
*/
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
* Write 1 to enable the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
#define TIMG_T1_INT_ENA_V 0x00000001U
#define TIMG_T1_INT_ENA_S 1
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
* Write 1 to enable the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
@ -602,21 +500,14 @@ extern "C" {
*/
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
* The raw interrupt status bit of the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
#define TIMG_T1_INT_RAW_V 0x00000001U
#define TIMG_T1_INT_RAW_S 1
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
* The raw interrupt status bit of the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
@ -628,21 +519,14 @@ extern "C" {
*/
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
* The masked interrupt status bit of the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
#define TIMG_T1_INT_ST_V 0x00000001U
#define TIMG_T1_INT_ST_S 1
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
* The masked interrupt status bit of the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
@ -654,21 +538,14 @@ extern "C" {
*/
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
* Write 1 to clear the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
#define TIMG_T1_INT_CLR_V 0x00000001U
#define TIMG_T1_INT_CLR_S 1
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
* Write 1 to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
@ -676,26 +553,30 @@ extern "C" {
#define TIMG_WDT_INT_CLR_S 2
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
* RTC frequency calculation configuration register 2
*/
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
* Represents whether RTC frequency calculation is timeout.
* 0: No timeout
* 1: Timeout
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
* Configures the cycles that reset frequency calculation timeout.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
* Configures the threshold value for the RTC frequency calculation timer. If the
* timer's value exceeds this threshold, a timeout is triggered.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
@ -707,7 +588,7 @@ extern "C" {
*/
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
* Timer version control register
* Version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
@ -719,29 +600,18 @@ extern "C" {
*/
#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
* Configures whether to enable timer's ETM task and event.
* 0: Disable
* 1: Enable
*/
#define TIMG_ETM_EN (BIT(28))
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
#define TIMG_ETM_EN_V 0x00000001U
#define TIMG_ETM_EN_S 28
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
* Configures whether to enable gate clock signal for registers.
* 0: Force clock on for registers
* 1: Support clock only when registers are read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)

283
components/soc/esp32c61/include/soc/timer_group_struct.h
View File

@ -12,41 +12,46 @@ extern "C" {
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
* Timer 0 configuration register
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
uint32_t reserved_0:10;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
* Configures whether or not to enable the timer 0 alarm function. This bit will be
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
* Configures whether or not to reset the timer 0 's clock divider counter.
* 0: No effect
* 1: Reset
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
* Represents the timer 0 clock (T0_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
* Configures whether or not to enable the timer 0 auto-reload function at the time of
* alarm.
* 0: No effect
* 1: Enable
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
* Configures the counting direction of the timer 0 time-base counter.
* 0: Decrement
* 1: Increment
*/
uint32_t tx_increase:1;
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
* Configures whether or not to enable the timer 0 time-base counter.
* 0: Disable
* 1: Enable
*/
uint32_t tx_en:1;
};
@ -54,13 +59,14 @@ typedef union {
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
* Timer 0 current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
* Represents the low 32 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
uint32_t tx_lo:32;
};
@ -68,13 +74,14 @@ typedef union {
} timg_txlo_reg_t;
/** Type of txhi register
* Timer x current value, high 22 bits
* Timer 0 current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
* of timer x can be read here.
* Represents the high 22 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
@ -83,13 +90,15 @@ typedef union {
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
* Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
uint32_t tx_update:1;
};
@ -97,12 +106,14 @@ typedef union {
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer x alarm value, low 32 bits
* Timer 0 alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer x alarm trigger time-base counter value, low 32 bits.
* Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
uint32_t tx_alarm_lo:32;
};
@ -110,12 +121,14 @@ typedef union {
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer x alarm value, high bits
* Timer 0 alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer x alarm trigger time-base counter value, high 22 bits.
* Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
@ -124,13 +137,14 @@ typedef union {
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer x reload value, low 32 bits
* Timer 0 reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer x time-base
* Counter.
* Configures low 32 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
uint32_t tx_load_lo:32;
};
@ -138,13 +152,14 @@ typedef union {
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer x reload value, high 22 bits
* Timer 0 reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer x time-base
* Configures high 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
@ -153,13 +168,13 @@ typedef union {
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
* Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
* Write any value to trigger a timer 0 time-base counter reload.
*
* Write any value to trigger a timer x time-base counter reload.
*/
uint32_t tx_load:32;
};
@ -175,53 +190,93 @@ typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
* Configures whether to enable flash boot protection.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
* Configures the system reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
* Configures the CPU reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk, 1-xtal_clk.
*/
uint32_t wdt_use_xtal:1;
uint32_t reserved_21:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
* Configures to update the WDT configuration registers.
* 0: No effect
* 1: Update
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
* Configures the timeout action of stage 0. Valid only when write protection is
* disabled.
* 0: No effect
* 1: Interrupt
* 2: Reset CPU
* 3: Reset system
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
* Configures whether or not to enable the MWDT. Valid only when write protection is
* disabled.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_en:1;
};
@ -234,13 +289,16 @@ typedef union {
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
* Configures whether to reset WDT 's clock divider counter.
* 0: No effect
* 1: Reset
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
* Configures MWDT clock prescaler value. Valid only when write protection is
* disabled.
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
@ -253,7 +311,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
* Configures the stage 0 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg0_hold:32;
};
@ -266,7 +325,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
* Configures the stage 1 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg1_hold:32;
};
@ -279,7 +339,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
* Configures the stage 2 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg2_hold:32;
};
@ -292,7 +353,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
* Configures the stage 3 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg3_hold:32;
};
@ -305,7 +367,7 @@ typedef union {
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
* Write any value to feed the MWDT. Valid only when write protection is disabled.
*/
uint32_t wdt_feed:32;
};
@ -318,8 +380,7 @@ typedef union {
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
* Configures a different value than its reset value to enable write protection.
*/
uint32_t wdt_wkey:32;
};
@ -329,13 +390,15 @@ typedef union {
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
* RTC frequency calculation configuration register 0
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
* Configures the frequency calculation mode.
* 0: one-shot frequency calculation
* 1: periodic frequency calculation
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
@ -343,15 +406,20 @@ typedef union {
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
* Represents whether one-shot frequency calculation is done.
* 0: Not done
* 1: Done
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
* Configures the time to calculate RTC slow clock's frequency.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
* Configures whether to enable one-shot frequency calculation.
* 0: Disable
* 1: Enable
*/
uint32_t rtc_cali_start:1;
};
@ -359,18 +427,20 @@ typedef union {
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
* RTC frequency calculation configuration register 1
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
* Represents whether periodic frequency calculation is done.
* 0: Not done
* 1: Done
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
* Represents the value countered by XTAL_CLK when one-shot or periodic frequency
* calculation is done. It is used to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value:25;
};
@ -378,22 +448,26 @@ typedef union {
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
* RTC frequency calculation configuration register 2
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
* Represents whether RTC frequency calculation is timeout.
* 0: No timeout
* 1: Timeout
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
* Configures the cycles that reset frequency calculation timeout.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
* Configures the threshold value for the RTC frequency calculation timer. If the
* timer's value exceeds this threshold, a timeout is triggered.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_timeout_thres:25;
};
@ -408,15 +482,12 @@ typedef union {
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
* Write 1 to enable the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_ena:1;
/** t1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_ena:1;
uint32_t reserved_1:1;
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
* Write 1 to enable the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_3:29;
@ -430,15 +501,12 @@ typedef union {
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
* The raw interrupt status bit of the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_raw:1;
/** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_raw:1;
uint32_t reserved_1:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
* The raw interrupt status bit of the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_3:29;
@ -452,15 +520,12 @@ typedef union {
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
* The masked interrupt status bit of the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_st:1;
/** t1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_st:1;
uint32_t reserved_1:1;
/** wdt_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
* The masked interrupt status bit of the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_3:29;
@ -474,15 +539,12 @@ typedef union {
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
* Write 1 to clear the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_clr:1;
/** t1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_clr:1;
uint32_t reserved_1:1;
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
* Write 1 to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_3:29;
@ -498,7 +560,7 @@ typedef union {
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
* Timer version control register
* Version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
@ -515,20 +577,16 @@ typedef union {
struct {
uint32_t reserved_0:28;
/** etm_en : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
* Configures whether to enable timer's ETM task and event.
* 0: Disable
* 1: Enable
*/
uint32_t etm_en:1;
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
uint32_t wdt_clk_is_active:1;
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
uint32_t timer_clk_is_active:1;
uint32_t reserved_29:2;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
* Configures whether to enable gate clock signal for registers.
* 0: Force clock on for registers
* 1: Support clock only when registers are read or written to by software.
*/
uint32_t clk_en:1;
};
@ -550,7 +608,8 @@ typedef struct {
typedef struct timg_dev_t {
volatile timg_hwtimer_reg_t hw_timer[2];
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;

24
components/soc/esp32c61/timer_periph.c Normal file
View File

@ -0,0 +1,24 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/timer_periph.h"
const timer_group_signal_conn_t timer_group_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_TIMG0_MODULE,
.timer_irq_id = {
[0] = ETS_TG0_T0_INTR_SOURCE,
}
},
[1] = {
.module = PERIPH_TIMG1_MODULE,
.timer_irq_id = {
[0] = ETS_TG1_T0_INTR_SOURCE,
}
}
}
};

3
docs/docs_not_updated/esp32c61.txt
View File

@ -95,7 +95,6 @@ api-reference/peripherals/dac.rst
api-reference/peripherals/spi_slave.rst
api-reference/peripherals/etm.rst
api-reference/peripherals/i2s.rst
api-reference/peripherals/gptimer.rst
api-reference/peripherals/touch_element.rst
api-reference/peripherals/ppa.rst
api-reference/peripherals/ana_cmpr.rst
@ -110,7 +109,6 @@ api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst
api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst
api-reference/peripherals/spi_flash/index.rst
api-reference/peripherals/sdm.rst
api-reference/peripherals/touch_pad.rst
api-reference/peripherals/lcd/i80_lcd.rst
api-reference/peripherals/lcd/spi_lcd.rst
@ -123,7 +121,6 @@ api-reference/peripherals/spi_slave_hd.rst
api-reference/peripherals/parlio.rst
api-reference/peripherals/ds.rst
api-reference/peripherals/i2c.rst
api-reference/peripherals/dedic_gpio.rst
api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/spi_master.rst
api-reference/peripherals/index.rst

4
examples/peripherals/timer_group/gptimer/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# Example: General Purpose Timer

4
examples/peripherals/timer_group/wiegand_interface/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# Wiegand Interface Example

4
examples/system/sysview_tracing/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# Example: Application Level Tracing - SystemView Tracing (sysview_tracing)
This test code shows how to perform system-wide behavioral analysis of the program using [SEGGER SystemView tool](https://www.segger.com/products/development-tools/systemview/).

4
examples/system/sysview_tracing_heap_log/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# SystemView Heap and Log Tracing Example