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feat(gdma): set default valid memory range for gdma

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This commit is contained in:
morris 2024-04-25 15:20:48 +08:00
parent bf415f580f
commit a6d8251366
4 changed files with 28 additions and 0 deletions
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12
components/hal/esp32p4/include/hal/ahb_dma_ll.h
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@ -57,6 +57,18 @@ static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
dev->misc_conf.ahbm_rst_inter = 0;
}
/**
* @brief Preset valid memory range for AHB-DMA
*
* @param dev DMA register base address
*/
static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev)
{
// AHB-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
dev->intr_mem_start_addr.val = 0x40000000;
dev->intr_mem_end_addr.val = 0x4FFC0000;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word

14
components/hal/esp32p4/include/hal/axi_dma_ll.h
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@ -59,6 +59,20 @@ static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
dev->misc_conf.axim_rst_wr_inter = 0;
}
/**
* @brief Preset valid memory range for AXI-DMA
*
* @param dev DMA register base address
*/
static inline void axi_dma_ll_set_default_memory_range(axi_dma_dev_t *dev)
{
// AXI-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
dev->intr_mem_start_addr.val = 0x4FC00000;
dev->intr_mem_end_addr.val = 0x4FFC0000;
dev->extr_mem_start_addr.val = 0x40000000;
dev->extr_mem_end_addr.val = 0x4C000000;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word

1
components/hal/gdma_hal_ahb_v2.c
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@ -244,4 +244,5 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if SOC_GDMA_SUPPORT_ETM
hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
#endif // SOC_GDMA_SUPPORT_ETM
ahb_dma_ll_set_default_memory_range(hal->ahb_dma_dev);
}

1
components/hal/gdma_hal_axi.c
View File

@ -244,4 +244,5 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if SOC_GDMA_SUPPORT_ETM
hal->enable_etm_task = gdma_axi_hal_enable_etm_task;
#endif // SOC_GDMA_SUPPORT_ETM
axi_dma_ll_set_default_memory_range(hal->axi_dma_dev);
}