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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
psram: support psram 2T mode to fix single bit error
1. add enable PSRAM 2T mode function 2. abort when himem and 2T mode are enabled meanwhile 3. set SPIRAM_2T_MODE as "n" by default, enable it when needed
This commit is contained in:
chenjianqiang
parent
acdba0eb46
commit
a6b08cb025
@ -174,6 +174,9 @@ menu "ESP32-specific"
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#Note that this is limited to 62 banks, as esp_spiram_writeback_cache needs some kind of mapping of
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#some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is
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#enabled.
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If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
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unusable.
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config SPIRAM_BANKSWITCH_RESERVE
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int "Amount of 32K pages to reserve for bank switching"
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depends on SPIRAM_BANKSWITCH_ENABLE
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@ -343,6 +346,20 @@ menu "ESP32-specific"
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For ESP32-PICO chip, the default value of this config should be 7.
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config SPIRAM_2T_MODE
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bool "Enable SPI PSRAM 2T mode"
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depends on ESP32_SPIRAM_SUPPORT
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default "n"
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help
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Enable this option to fix single bit errors inside 64Mbit PSRAM.
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Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple
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fixed bit positions.
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Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size.
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Applications will not be affected unless the use the esp_himem APIs, which are not supported
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in 2T mode.
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endmenu # "SPI RAM config"
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config ESP32_MEMMAP_TRACEMEM
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@ -172,7 +172,8 @@ typedef enum {
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static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
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static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK;
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static uint32_t s_psram_id = 0;
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static uint64_t s_psram_id = 0;
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static bool s_2t_mode_enabled = false;
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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@ -397,11 +398,12 @@ static void psram_disable_qio_mode(psram_spi_num_t spi_num)
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}
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//read psram id
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static void psram_read_id(uint32_t* dev_id)
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static void psram_read_id(uint64_t* dev_id)
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{
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psram_spi_num_t spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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uint32_t dummy_bits = 0 + extra_dummy;
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uint32_t psram_id[2] = {0};
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psram_cmd_t ps_cmd;
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uint32_t addr = 0;
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@ -425,14 +427,15 @@ static void psram_read_id(uint32_t* dev_id)
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ps_cmd.addr = &addr;
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ps_cmd.txDataBitLen = 0;
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ps_cmd.txData = NULL;
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ps_cmd.rxDataBitLen = 4 * 8;
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ps_cmd.rxData = dev_id;
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ps_cmd.rxDataBitLen = 8 * 8;
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ps_cmd.rxData = psram_id;
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ps_cmd.dummyBitLen = dummy_bits;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_clear_spi_fifo(spi_num);
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psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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*dev_id = (uint64_t)(((uint64_t)psram_id[1] << 32) | psram_id[0]);
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}
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//enter QPI mode
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@ -467,6 +470,182 @@ static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
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return ESP_OK;
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}
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#if CONFIG_SPIRAM_2T_MODE
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// use SPI user mode to write psram
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static void spi_user_psram_write(psram_spi_num_t spi_num, uint32_t address, uint32_t *data_buffer, uint32_t data_len)
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{
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uint32_t addr = (PSRAM_QUAD_WRITE << 24) | (address & 0x7fffff);
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psram_cmd_t ps_cmd;
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ps_cmd.cmdBitLen = 0;
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ps_cmd.cmd = 0;
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ps_cmd.addr = &addr;
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ps_cmd.addrBitLen = 4 * 8;
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ps_cmd.txDataBitLen = 32 * 8;
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ps_cmd.txData = NULL;
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ps_cmd.rxDataBitLen = 0;
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ps_cmd.rxData = NULL;
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ps_cmd.dummyBitLen = 0;
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for(uint32_t i=0; i<data_len; i+=32) {
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psram_clear_spi_fifo(spi_num);
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addr = (PSRAM_QUAD_WRITE << 24) | ((address & 0x7fffff) + i);
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ps_cmd.txData = data_buffer + (i / 4);
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psram_cmd_config(spi_num, &ps_cmd);
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psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_QPI);
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}
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psram_cmd_end(spi_num);
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}
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// use SPI user mode to read psram
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static void spi_user_psram_read(psram_spi_num_t spi_num, uint32_t address, uint32_t *data_buffer, uint32_t data_len)
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{
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uint32_t addr = (PSRAM_FAST_READ_QUAD << 24) | (address & 0x7fffff);
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uint32_t dummy_bits = PSRAM_FAST_READ_QUAD_DUMMY + 1;
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psram_cmd_t ps_cmd;
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ps_cmd.cmdBitLen = 0;
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ps_cmd.cmd = 0;
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ps_cmd.addr = &addr;
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ps_cmd.addrBitLen = 4 * 8;
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ps_cmd.txDataBitLen = 0;
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ps_cmd.txData = NULL;
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ps_cmd.rxDataBitLen = 32 * 8;
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ps_cmd.dummyBitLen = dummy_bits + extra_dummy;
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for(uint32_t i=0; i<data_len; i+=32) {
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psram_clear_spi_fifo(spi_num);
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addr = (PSRAM_FAST_READ_QUAD << 24) | ((address & 0x7fffff) + i);
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ps_cmd.rxData = data_buffer + (i / 4);
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psram_cmd_config(spi_num, &ps_cmd);
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psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_QPI);
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}
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psram_cmd_end(spi_num);
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}
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//enable psram 2T mode
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static esp_err_t IRAM_ATTR psram_2t_mode_enable(psram_spi_num_t spi_num)
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{
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psram_disable_qio_mode(spi_num);
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// configure psram clock as 5 MHz
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uint32_t div = rtc_clk_apb_freq_get() / 5000000;
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esp_rom_spiflash_config_clk(div, spi_num);
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psram_cmd_t ps_cmd;
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// setp1: send cmd 0x5e
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// send one more bit clock after send cmd
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ps_cmd.cmd = 0x5e;
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ps_cmd.cmdBitLen = 8;
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ps_cmd.addrBitLen = 0;
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ps_cmd.addr = 0;
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ps_cmd.txDataBitLen = 0;
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ps_cmd.txData = NULL;
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ps_cmd.rxDataBitLen =0;
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ps_cmd.rxData = NULL;
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ps_cmd.dummyBitLen = 1;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_clear_spi_fifo(spi_num);
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psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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// setp2: send cmd 0x5f
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// send one more bit clock after send cmd
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ps_cmd.cmd = 0x5f;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_clear_spi_fifo(spi_num);
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psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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// setp3: keep cs as high level
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// send 128 cycles clock
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// send 1 bit high levle in ninth clock from the back to PSRAM SIO1
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GPIO_OUTPUT_SET(D0WD_PSRAM_CS_IO, 1);
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gpio_matrix_out(D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
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gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
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gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
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uint32_t w_data_2t[4] = {0x0, 0x0, 0x0, 0x00010000};
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ps_cmd.cmd = 0;
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ps_cmd.cmdBitLen = 0;
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ps_cmd.txDataBitLen = 128;
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ps_cmd.txData = w_data_2t;
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ps_cmd.dummyBitLen = 0;
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psram_clear_spi_fifo(spi_num);
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psram_cmd_config(spi_num, &ps_cmd);
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psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
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gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
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gpio_matrix_out(D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
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// setp4: send cmd 0x5f
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// send one more bit clock after send cmd
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ps_cmd.cmd = 0x5f;
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ps_cmd.cmdBitLen = 8;
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ps_cmd.txDataBitLen = 0;
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ps_cmd.txData = NULL;
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ps_cmd.dummyBitLen = 1;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_clear_spi_fifo(spi_num);
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psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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// configure psram clock back to the default value
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switch (s_psram_mode) {
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case PSRAM_CACHE_F80M_S40M:
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case PSRAM_CACHE_F40M_S40M:
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esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, spi_num);
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break;
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case PSRAM_CACHE_F80M_S80M:
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esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, spi_num);
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break;
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default:
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break;
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}
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psram_enable_qio_mode(spi_num);
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return ESP_OK;
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}
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#define CHECK_DATA_LEN (1024)
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#define CHECK_ADDR_STEP (0x100000)
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#define SIZE_32MBIT (0x400000)
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#define SIZE_64MBIT (0x800000)
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static esp_err_t psram_2t_mode_check(psram_spi_num_t spi_num)
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{
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uint8_t w_check_data[CHECK_DATA_LEN] = {0};
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uint8_t r_check_data[CHECK_DATA_LEN] = {0};
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for (uint32_t addr=0; addr<SIZE_32MBIT; addr+=CHECK_ADDR_STEP) {
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spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, CHECK_DATA_LEN);
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}
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memset(w_check_data, 0xff, sizeof(w_check_data));
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for (uint32_t addr=SIZE_32MBIT; addr<SIZE_64MBIT; addr+=CHECK_ADDR_STEP) {
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spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, CHECK_DATA_LEN);
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}
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for (uint32_t addr=0; addr<SIZE_32MBIT; addr+=CHECK_ADDR_STEP) {
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spi_user_psram_read(spi_num, addr, (uint32_t *)r_check_data, CHECK_DATA_LEN);
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for (uint32_t j=0; j<CHECK_DATA_LEN; j++) {
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if (r_check_data[j] != 0xff) {
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return ESP_FAIL;
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}
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}
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}
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return ESP_OK;
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}
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#endif
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void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
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{
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if (clk_mode == PSRAM_CLK_MODE_NORM) {
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@ -600,7 +779,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_mode_t
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psram_size_t psram_get_size()
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{
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if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
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return PSRAM_SIZE_64MBITS;
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return s_2t_mode_enabled ? PSRAM_SIZE_32MBITS : PSRAM_SIZE_64MBITS;
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} else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
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return PSRAM_SIZE_32MBITS;
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} else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
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@ -770,6 +949,27 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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psram_set_cs_timing(PSRAM_SPI_1, s_clk_mode);
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psram_set_cs_timing(_SPI_CACHE_PORT, s_clk_mode);
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psram_enable_qio_mode(PSRAM_SPI_1);
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if(((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id))) {
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#if CONFIG_SPIRAM_2T_MODE
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#if CONFIG_SPIRAM_BANKSWITCH_ENABLE
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ESP_EARLY_LOGE(TAG, "PSRAM 2T mode and SPIRAM bank switching can not enabled meanwhile. Please read the help text for SPIRAM_2T_MODE in the project configuration menu.");
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abort();
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#endif
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/* Note: 2T mode command should not be sent twice,
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otherwise psram would get back to normal mode. */
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if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
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psram_2t_mode_enable(PSRAM_SPI_1);
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if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "PSRAM 2T mode enable fail!");
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return ESP_FAIL;
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}
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}
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s_2t_mode_enabled = true;
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ESP_EARLY_LOGI(TAG, "PSRAM is in 2T mode");
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#endif
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}
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psram_cache_init(mode, vaddrmode);
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return ESP_OK;
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}
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