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psram: remove CS/CLK pin settings in kconfig on ESP32S2/S3

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This commit is contained in:
gaoxu 2022-09-16 14:43:52 +08:00 committed by Armando
parent 3f2f35bd5e
commit a67409275e
7 changed files with 29 additions and 35 deletions
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22
components/esp_psram/esp32s2/Kconfig.spiram
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@ -40,22 +40,14 @@ menu "SPI RAM config"
This should only be used for tasks where the stack is never accessed while the cache is disabled.
Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH.
menu "PSRAM clock and cs IO for ESP32S2"
depends on SPIRAM
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
config SPIRAM_CLK_IO
int
default 30
config SPIRAM_CS_IO
int
default 26
config DEFAULT_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 26
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n

4
components/esp_psram/esp32s2/esp_psram_impl_quad.c
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@ -72,8 +72,8 @@ static const char* TAG = "quad_psram";
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
// PSRAM clock and cs IO should be configured based on hardware design.
#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30
#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26
#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM

22
components/esp_psram/esp32s3/Kconfig.spiram
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@ -49,22 +49,14 @@ menu "SPI RAM config"
This should only be used for tasks where the stack is never accessed while the cache is disabled.
Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH.
menu "PSRAM Clock and CS IO for ESP32S3"
depends on SPIRAM
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
config SPIRAM_CLK_IO
int
default 30
config SPIRAM_CS_IO
int
default 26
config DEFAULT_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 26
help
The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n

2
components/esp_psram/esp32s3/esp_psram_impl_octal.c
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@ -29,7 +29,7 @@
#define OCT_PSRAM_ADDR_BITLEN 32
#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_CS1_IO CONFIG_DEFAULT_PSRAM_CS_IO
#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM
#define OCT_PSRAM_CS_SETUP_TIME 3
#define OCT_PSRAM_CS_HOLD_TIME 3

4
components/esp_psram/esp32s3/esp_psram_impl_quad.c
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@ -68,8 +68,8 @@ static const char* TAG = "quad_psram";
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
// PSRAM clock and cs IO should be configured based on hardware design.
#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30
#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26
#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM

5
components/esp_psram/sdkconfig.rename.esp32s2 Normal file
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@ -0,0 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO
CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO

5
components/esp_psram/sdkconfig.rename.esp32s3 Normal file
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@ -0,0 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO
CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO