diff --git a/components/esp_driver_gptimer/include/driver/gptimer.h b/components/esp_driver_gptimer/include/driver/gptimer.h index e17e20d7b4..b9c0b8b14b 100644 --- a/components/esp_driver_gptimer/include/driver/gptimer.h +++ b/components/esp_driver_gptimer/include/driver/gptimer.h @@ -169,9 +169,11 @@ typedef struct { /** * @brief Set alarm event actions for GPTimer. * - * @note This function is allowed to run within ISR context, so that user can set new alarm action immediately in the ISR callback. + * @note This function is allowed to run within ISR context, so you can update new alarm action immediately in any ISR callback. * @note If `CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` is enabled, this function will be placed in the IRAM by linker, * makes it possible to execute even when the Flash Cache is disabled. + * In this case, please also ensure the `gptimer_alarm_config_t` instance is placed in the static data section + * instead of in the read-only data section. e.g.: `static gptimer_alarm_config_t alarm_config = { ... };` * * @param[in] timer Timer handle created by `gptimer_new_timer` * @param[in] config Alarm configuration, especially, set config to NULL means disabling the alarm function diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 65b2c3cb7f..2e085fcc9d 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -126,7 +126,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } /* Prepare calibration */ - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel); + // calibration clock source is set by PCR register: PCR_32K_SEL + // REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); /* Figure out how long to wait for calibration to finish */ diff --git a/components/hal/esp32c5/include/hal/timer_ll.h b/components/hal/esp32c5/include/hal/timer_ll.h index 40a33c070d..9915ddbce2 100644 --- a/components/hal/esp32c5/include/hal/timer_ll.h +++ b/components/hal/esp32c5/include/hal/timer_ll.h @@ -10,14 +10,12 @@ #pragma once #include -#include "sdkconfig.h" // TODO: remove #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" -// TODO: [ESP32C5] IDF-8693 -// #include "soc/soc_etm_source.h" +#include "soc/soc_etm_source.h" #ifdef __cplusplus extern "C" { @@ -27,6 +25,31 @@ extern "C" { #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) +#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ + (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \ + [GPTIMER_ETM_TASK_START_COUNT] = TIMER0_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER0_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TIMER0_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TIMER0_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TIMER0_TASK_CNT_CAP_TIMER0, \ + }}, \ + {{ \ + [GPTIMER_ETM_TASK_START_COUNT] = TIMER1_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER1_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TIMER1_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TIMER1_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TIMER1_TASK_CNT_CAP_TIMER0, \ + }}, \ + }[group][timer][task] + +#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event) \ + (uint32_t [2][1][GPTIMER_ETM_EVENT_MAX]){{{ \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER0_EVT_CNT_CMP_TIMER0, \ + }}, \ + {{ \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER1_EVT_CNT_CMP_TIMER0, \ + }}, \ + }[group][timer][event] /** * @brief Enable the bus clock for timer group module @@ -134,11 +157,7 @@ __attribute__((always_inline)) static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en) { (void)timer_num; -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].config.tx_alarm_en = en; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -154,12 +173,8 @@ static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_nu if (divider >= 65536) { divider = 0; } -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); hw->hw_timer[timer_num].config.tx_divcnt_rst = 1; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -173,11 +188,7 @@ static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_nu __attribute__((always_inline)) static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].config.tx_autoreload = en; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -189,11 +200,7 @@ static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_nu */ static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP); -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -207,11 +214,7 @@ static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_n __attribute__((always_inline)) static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].config.tx_en = en; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -223,15 +226,11 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].update.tx_update = 1; // Timer register is in a different clock domain from Timer hardware logic // We need to wait for the update to take effect before fetching the count value while (hw->hw_timer[timer_num].update.tx_update) { } -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -245,12 +244,7 @@ static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_ __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); - return 0; -#endif } /** @@ -263,12 +257,8 @@ static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer __attribute__((always_inline)) static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -281,12 +271,8 @@ static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, __attribute__((always_inline)) static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32); hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** @@ -299,12 +285,7 @@ static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, __attribute__((always_inline)) static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo); -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); - return 0; -#endif } /** @@ -316,11 +297,7 @@ static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_ __attribute__((always_inline)) static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num) { -#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION hw->hw_timer[timer_num].load.tx_load = 1; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION - abort(); -#endif } /** diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index 702196b042..036953edfa 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED bool default y +config SOC_GPTIMER_SUPPORTED + bool + default y + config SOC_SUPPORTS_SECURE_DL_MODE bool default y @@ -275,6 +279,18 @@ config SOC_TIMER_GROUP_TIMERS_PER_GROUP int default 1 +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS int default 3 diff --git a/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h b/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h index 16beaefa11..1872aedd81 100644 --- a/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h @@ -5,6 +5,8 @@ */ #pragma once +#include "soc/soc_caps.h" + #ifdef __cplusplus extern "C" { #endif @@ -19,7 +21,7 @@ extern "C" { * * 2) External 40/48MHz Crystal Clock: XTAL * - * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description) * * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock * can be computed in runtime through calibration. @@ -168,7 +170,11 @@ typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6) * } * @endcode */ -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL} +#if SOC_CLK_TREE_SUPPORTED +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#else +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL} +#endif /** * @brief Type of GPTimer clock source @@ -177,7 +183,11 @@ typedef enum { GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if SOC_CLK_TREE_SUPPORTED GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +#else + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#endif // SOC_CLK_TREE_SUPPORTED } soc_periph_gptimer_clk_src_t; /** @@ -186,7 +196,11 @@ typedef enum { typedef enum { TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ +#if SOC_CLK_TREE_SUPPORTED TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ +#else + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Timer group clock source default choice is XTAL */ +#endif // SOC_CLK_TREE_SUPPORTED } soc_periph_tg_clk_src_legacy_t; //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index 905f175505..96f0b9812d 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -22,7 +22,7 @@ #define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722 // #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 // #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 -// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8705 +#define SOC_GPTIMER_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683 // #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 @@ -428,10 +428,10 @@ /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) -// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) -// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) // #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) -// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) // #define SOC_TIMER_SUPPORT_ETM (1) /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ diff --git a/components/soc/esp32c5/mp/include/soc/timer_group_reg.h b/components/soc/esp32c5/mp/include/soc/timer_group_reg.h index df51ff4390..b00cdf705c 100644 --- a/components/soc/esp32c5/mp/include/soc/timer_group_reg.h +++ b/components/soc/esp32c5/mp/include/soc/timer_group_reg.h @@ -1,7 +1,7 @@ /** * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -15,14 +15,6 @@ extern "C" { * Timer 0 configuration register */ #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) -/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; - * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source - * clock of timer group. - */ -#define TIMG_T0_USE_XTAL (BIT(9)) -#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) -#define TIMG_T0_USE_XTAL_V 0x00000001U -#define TIMG_T0_USE_XTAL_S 9 /** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; * Configures whether or not to enable the timer 0 alarm function. This bit will be * automatically cleared once an alarm occurs.\\ @@ -190,185 +182,6 @@ extern "C" { #define TIMG_T0_LOAD_V 0xFFFFFFFFU #define TIMG_T0_LOAD_S 0 -/** TIMG_T1CONFIG_REG register - * Timer 1 configuration register - */ -#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24) -/** TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0; - * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source - * clock of timer group. - */ -#define TIMG_T1_USE_XTAL (BIT(9)) -#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S) -#define TIMG_T1_USE_XTAL_V 0x00000001U -#define TIMG_T1_USE_XTAL_S 9 -/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; - * Configures whether or not to enable the timer 1 alarm function. This bit will be - * automatically cleared once an alarm occurs.\\ - * 0: Disable \\ - * 1: Enable \\ - */ -#define TIMG_T1_ALARM_EN (BIT(10)) -#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) -#define TIMG_T1_ALARM_EN_V 0x00000001U -#define TIMG_T1_ALARM_EN_S 10 -/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0; - * Configures whether or not to reset the timer 1 's clock divider counter. \\ - * 0: No effect \\ - * 1: Reset \\ - */ -#define TIMG_T1_DIVCNT_RST (BIT(12)) -#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S) -#define TIMG_T1_DIVCNT_RST_V 0x00000001U -#define TIMG_T1_DIVCNT_RST_S 12 -/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; - * Represents the timer 1 clock (T1_clk) prescaler value. - */ -#define TIMG_T1_DIVIDER 0x0000FFFFU -#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) -#define TIMG_T1_DIVIDER_V 0x0000FFFFU -#define TIMG_T1_DIVIDER_S 13 -/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; - * Configures whether or not to enable the timer 1 auto-reload function at the time of - * alarm. \\ - * 0: No effect \\ - * 1: Enable \\ - */ -#define TIMG_T1_AUTORELOAD (BIT(29)) -#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) -#define TIMG_T1_AUTORELOAD_V 0x00000001U -#define TIMG_T1_AUTORELOAD_S 29 -/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; - * Configures the counting direction of the timer 1 time-base counter. \\ - * 0: Decrement \\ - * 1: Increment \\ - * - */ -#define TIMG_T1_INCREASE (BIT(30)) -#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) -#define TIMG_T1_INCREASE_V 0x00000001U -#define TIMG_T1_INCREASE_S 30 -/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0; - * Configures whether or not to enable the timer 1 time-base counter. \\ - * 0: Disable \\ - * 1: Enable \\ - */ -#define TIMG_T1_EN (BIT(31)) -#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) -#define TIMG_T1_EN_V 0x00000001U -#define TIMG_T1_EN_S 31 - -/** TIMG_T1LO_REG register - * Timer 1 current value, low 32 bits - */ -#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28) -/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; - * Represents the low 32 bits of the time-base counter of timer 1. Valid only after - * writing to TIMG_T1UPDATE_REG. \\ - * Measurement unit: T1_clk \\ - */ -#define TIMG_T1_LO 0xFFFFFFFFU -#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) -#define TIMG_T1_LO_V 0xFFFFFFFFU -#define TIMG_T1_LO_S 0 - -/** TIMG_T1HI_REG register - * Timer 1 current value, high 22 bits - */ -#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c) -/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0; - * Represents the high 22 bits of the time-base counter of timer 1. Valid only after - * writing to TIMG_T1UPDATE_REG. \\ - * Measurement unit: T1_clk \\ - */ -#define TIMG_T1_HI 0x003FFFFFU -#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) -#define TIMG_T1_HI_V 0x003FFFFFU -#define TIMG_T1_HI_S 0 - -/** TIMG_T1UPDATE_REG register - * Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG - */ -#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30) -/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0; - * Configures to latch the counter value. \\ - * 0: Latch \\ - * 1: Latch \\ - */ -#define TIMG_T1_UPDATE (BIT(31)) -#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) -#define TIMG_T1_UPDATE_V 0x00000001U -#define TIMG_T1_UPDATE_S 31 - -/** TIMG_T1ALARMLO_REG register - * Timer 1 alarm value, low 32 bits - */ -#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34) -/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; - * Configures the low 32 bits of timer 1 alarm trigger time-base counter value. Valid - * only when TIMG_T1_ALARM_EN is 1. \\ - * Measurement unit: T1_clk \\ - */ -#define TIMG_T1_ALARM_LO 0xFFFFFFFFU -#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) -#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU -#define TIMG_T1_ALARM_LO_S 0 - -/** TIMG_T1ALARMHI_REG register - * Timer 1 alarm value, high bits - */ -#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38) -/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0; - * Configures the high 22 bits of timer 1 alarm trigger time-base counter value. Valid - * only when TIMG_T1_ALARM_EN is 1. \\ - * Measurement unit: T1_clk \\ - */ -#define TIMG_T1_ALARM_HI 0x003FFFFFU -#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) -#define TIMG_T1_ALARM_HI_V 0x003FFFFFU -#define TIMG_T1_ALARM_HI_S 0 - -/** TIMG_T1LOADLO_REG register - * Timer 1 reload value, low 32 bits - */ -#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c) -/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * Configures low 32 bits of the value that a reload will load onto timer 1 time-base - * counter. \\ - * Measurement unit: T1_clk \\ - */ -#define TIMG_T1_LOAD_LO 0xFFFFFFFFU -#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) -#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU -#define TIMG_T1_LOAD_LO_S 0 - -/** TIMG_T1LOADHI_REG register - * Timer 1 reload value, high 22 bits - */ -#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40) -/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0; - * Configures high 22 bits of the value that a reload will load onto timer 1 time-base - * counter. \\ - * Measurement unit: T1_clk \\ - */ -#define TIMG_T1_LOAD_HI 0x003FFFFFU -#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) -#define TIMG_T1_LOAD_HI_V 0x003FFFFFU -#define TIMG_T1_LOAD_HI_S 0 - -/** TIMG_T1LOAD_REG register - * Write to reload timer from TIMG_T1LOADLO_REG or TIMG_T1LOADHI_REG - */ -#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44) -/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0; - * Write any value to trigger a timer 1 time-base counter reload. - * - */ -#define TIMG_T1_LOAD 0xFFFFFFFFU -#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) -#define TIMG_T1_LOAD_V 0xFFFFFFFFU -#define TIMG_T1_LOAD_S 0 - /** TIMG_WDTCONFIG0_REG register * Watchdog timer configuration register */ @@ -441,13 +254,6 @@ extern "C" { #define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) #define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U #define TIMG_WDT_CPU_RESET_LENGTH_S 18 -/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0; - * choose WDT clock:0-apb_clk, 1-xtal_clk. - */ -#define TIMG_WDT_USE_XTAL (BIT(21)) -#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S) -#define TIMG_WDT_USE_XTAL_V 0x00000001U -#define TIMG_WDT_USE_XTAL_S 21 /** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; * Configures to update the WDT configuration registers.\\ * 0: No effect \\ @@ -620,16 +426,6 @@ extern "C" { #define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) #define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U #define TIMG_RTC_CALI_START_CYCLING_S 12 -/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; - * Configures to select the clock to be calibrated\\ - * 0: RTC_SLOW_CLK\\ - * 1: RC_FAST_DIV_CLK\\ - * 2: XTAL32K_CLK\\ - */ -#define TIMG_RTC_CALI_CLK_SEL 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) -#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_S 13 /** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; * Represents whether one-shot frequency calculation is done.\\ * 0: Not done \\ @@ -690,13 +486,6 @@ extern "C" { #define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) #define TIMG_T0_INT_ENA_V 0x00000001U #define TIMG_T0_INT_ENA_S 0 -/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable the TIMG_T1_INT interrupt. - */ -#define TIMG_T1_INT_ENA (BIT(1)) -#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) -#define TIMG_T1_INT_ENA_V 0x00000001U -#define TIMG_T1_INT_ENA_S 1 /** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; * Write 1 to enable the TIMG_WDT_INT interrupt. */ @@ -716,13 +505,6 @@ extern "C" { #define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) #define TIMG_T0_INT_RAW_V 0x00000001U #define TIMG_T0_INT_RAW_S 0 -/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status bit of the TIMG_T1_INT interrupt. - */ -#define TIMG_T1_INT_RAW (BIT(1)) -#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) -#define TIMG_T1_INT_RAW_V 0x00000001U -#define TIMG_T1_INT_RAW_S 1 /** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; * The raw interrupt status bit of the TIMG_WDT_INT interrupt. */ @@ -742,13 +524,6 @@ extern "C" { #define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) #define TIMG_T0_INT_ST_V 0x00000001U #define TIMG_T0_INT_ST_S 0 -/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit of the TIMG_T1_INT interrupt. - */ -#define TIMG_T1_INT_ST (BIT(1)) -#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) -#define TIMG_T1_INT_ST_V 0x00000001U -#define TIMG_T1_INT_ST_S 1 /** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; * The masked interrupt status bit of the TIMG_WDT_INT interrupt. */ @@ -768,13 +543,6 @@ extern "C" { #define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) #define TIMG_T0_INT_CLR_V 0x00000001U #define TIMG_T0_INT_CLR_S 0 -/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear the TIMG_T1_INT interrupt. - */ -#define TIMG_T1_INT_CLR (BIT(1)) -#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) -#define TIMG_T1_INT_CLR_V 0x00000001U -#define TIMG_T1_INT_CLR_S 1 /** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; * Write 1 to clear the TIMG_WDT_INT interrupt. */ @@ -839,24 +607,6 @@ extern "C" { #define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) #define TIMG_ETM_EN_V 0x00000001U #define TIMG_ETM_EN_S 28 -/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1; - * Configures whether to enable WDT's clock. \\ - * 0: Disable \\ - * 1: Enable \\ - */ -#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) -#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S) -#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U -#define TIMG_WDT_CLK_IS_ACTIVE_S 29 -/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1; - * Configures whether to enable Timer $x's clock.\\ - * 0: Disable \\ - * 1: Enable \\ - */ -#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) -#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S) -#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U -#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 /** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; * Configures whether to enable gate clock signal for registers. \\ * 0: Force clock on for registers \\ diff --git a/components/soc/esp32c5/mp/include/soc/timer_group_struct.h b/components/soc/esp32c5/mp/include/soc/timer_group_struct.h index 044b078041..90f04512bc 100644 --- a/components/soc/esp32c5/mp/include/soc/timer_group_struct.h +++ b/components/soc/esp32c5/mp/include/soc/timer_group_struct.h @@ -1,7 +1,7 @@ /** * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,179 +10,173 @@ extern "C" { #endif -/** Group: T0 Control and configuration registers */ +/** Group: Timer Control and configuration registers */ /** Type of txconfig register - * Timer 0 configuration register + * Timer x configuration register */ typedef union { struct { - uint32_t reserved_0:9; - /** tx_use_xtal : R/W; bitpos: [9]; default: 0; - * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source - * clock of timer group. - */ - uint32_t tx_use_xtal:1; + uint32_t reserved_0: 10; /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; - * Configures whether or not to enable the timer 0 alarm function. This bit will be + * Configures whether or not to enable the timer alarm function. This bit will be * automatically cleared once an alarm occurs.\\ * 0: Disable \\ * 1: Enable \\ */ - uint32_t tx_alarm_en:1; - uint32_t reserved_11:1; + uint32_t tx_alarm_en: 1; + uint32_t reserved_11: 1; /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; - * Configures whether or not to reset the timer 0 's clock divider counter. \\ + * Configures whether or not to reset the timer's clock divider counter. \\ * 0: No effect \\ * 1: Reset \\ */ - uint32_t tx_divcnt_rst:1; + uint32_t tx_divcnt_rst: 1; /** tx_divider : R/W; bitpos: [28:13]; default: 1; - * Represents the timer 0 clock (T0_clk) prescaler value. + * Represents the timer clock (Tx_clk) prescaler value. */ - uint32_t tx_divider:16; + uint32_t tx_divider: 16; /** tx_autoreload : R/W; bitpos: [29]; default: 1; - * Configures whether or not to enable the timer 0 auto-reload function at the time of + * Configures whether or not to enable the timer auto-reload function at the time of * alarm. \\ * 0: No effect \\ * 1: Enable \\ */ - uint32_t tx_autoreload:1; + uint32_t tx_autoreload: 1; /** tx_increase : R/W; bitpos: [30]; default: 1; - * Configures the counting direction of the timer 0 time-base counter. \\ + * Configures the counting direction of the timer time-base counter. \\ * 0: Decrement \\ * 1: Increment \\ * */ - uint32_t tx_increase:1; + uint32_t tx_increase: 1; /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; - * Configures whether or not to enable the timer 0 time-base counter. \\ + * Configures whether or not to enable the timer time-base counter. \\ * 0: Disable \\ * 1: Enable \\ */ - uint32_t tx_en:1; + uint32_t tx_en: 1; }; uint32_t val; } timg_txconfig_reg_t; /** Type of txlo register - * Timer 0 current value, low 32 bits + * Timer x current value, low 32 bits */ typedef union { struct { /** tx_lo : RO; bitpos: [31:0]; default: 0; - * Represents the low 32 bits of the time-base counter of timer 0. Valid only after + * Represents the low 32 bits of the time-base counter of timer x. Valid only after * writing to TIMG_T0UPDATE_REG. \\ - * Measurement unit: T0_clk \\ + * Measurement unit: Tx_clk \\ */ - uint32_t tx_lo:32; + uint32_t tx_lo: 32; }; uint32_t val; } timg_txlo_reg_t; /** Type of txhi register - * Timer 0 current value, high 22 bits + * Timer x current value, high 22 bits */ typedef union { struct { /** tx_hi : RO; bitpos: [21:0]; default: 0; - * Represents the high 22 bits of the time-base counter of timer 0. Valid only after + * Represents the high 22 bits of the time-base counter of timer x. Valid only after * writing to TIMG_T0UPDATE_REG. \\ - * Measurement unit: T0_clk \\ + * Measurement unit: Tx_clk \\ */ - uint32_t tx_hi:22; - uint32_t reserved_22:10; + uint32_t tx_hi: 22; + uint32_t reserved_22: 10; }; uint32_t val; } timg_txhi_reg_t; /** Type of txupdate register - * Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG + * Write to copy current timer value to TIMGn_TxLO_REG or TIMGn_TxHI_REG */ typedef union { struct { - uint32_t reserved_0:31; + uint32_t reserved_0: 31; /** tx_update : R/W/SC; bitpos: [31]; default: 0; * Configures to latch the counter value. \\ * 0: Latch \\ * 1: Latch \\ */ - uint32_t tx_update:1; + uint32_t tx_update: 1; }; uint32_t val; } timg_txupdate_reg_t; /** Type of txalarmlo register - * Timer 0 alarm value, low 32 bits + * Timer x alarm value, low 32 bits */ typedef union { struct { /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; - * Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid - * only when TIMG_T0_ALARM_EN is 1. \\ - * Measurement unit: T0_clk \\ + * Configures the low 32 bits of timer x alarm trigger time-base counter value. Valid + * only when TIMG_Tx_ALARM_EN is 1. \\ + * Measurement unit: Tx_clk \\ */ - uint32_t tx_alarm_lo:32; + uint32_t tx_alarm_lo: 32; }; uint32_t val; } timg_txalarmlo_reg_t; /** Type of txalarmhi register - * Timer 0 alarm value, high bits + * Timer x alarm value, high bits */ typedef union { struct { /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; - * Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid - * only when TIMG_T0_ALARM_EN is 1. \\ - * Measurement unit: T0_clk \\ + * Configures the high 22 bits of timer x alarm trigger time-base counter value. Valid + * only when TIMG_Tx_ALARM_EN is 1. \\ + * Measurement unit: Tx_clk \\ */ - uint32_t tx_alarm_hi:22; - uint32_t reserved_22:10; + uint32_t tx_alarm_hi: 22; + uint32_t reserved_22: 10; }; uint32_t val; } timg_txalarmhi_reg_t; /** Type of txloadlo register - * Timer 0 reload value, low 32 bits + * Timer x reload value, low 32 bits */ typedef union { struct { /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; - * Configures low 32 bits of the value that a reload will load onto timer 0 time-base + * Configures low 32 bits of the value that a reload will load onto timer x time-base * counter. \\ - * Measurement unit: T0_clk \\ + * Measurement unit: Tx_clk \\ */ - uint32_t tx_load_lo:32; + uint32_t tx_load_lo: 32; }; uint32_t val; } timg_txloadlo_reg_t; /** Type of txloadhi register - * Timer 0 reload value, high 22 bits + * Timer x reload value, high 22 bits */ typedef union { struct { /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; - * Configures high 22 bits of the value that a reload will load onto timer 0 time-base + * Configures high 22 bits of the value that a reload will load onto timer x time-base * counter. \\ - * Measurement unit: T0_clk \\ + * Measurement unit: Tx_clk \\ */ - uint32_t tx_load_hi:22; - uint32_t reserved_22:10; + uint32_t tx_load_hi: 22; + uint32_t reserved_22: 10; }; uint32_t val; } timg_txloadhi_reg_t; /** Type of txload register - * Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG + * Write to reload timer from TIMG_TxLOADLO_REG or TIMG_TxLOADHI_REG */ typedef union { struct { /** tx_load : WT; bitpos: [31:0]; default: 0; - * Write any value to trigger a timer 0 time-base counter reload. - * + * Write any value to trigger a timer x time-base counter reload. */ - uint32_t tx_load:32; + uint32_t tx_load: 32; }; uint32_t val; } timg_txload_reg_t; @@ -194,14 +188,14 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:12; + uint32_t reserved_0: 12; /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; * Configures whether to mask the CPU reset generated by MWDT. Valid only when write * protection is disabled. \\ * 0: Mask \\ * 1: Unmask \\ */ - uint32_t wdt_appcpu_reset_en:1; + uint32_t wdt_appcpu_reset_en: 1; /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; * Configures whether to mask the CPU reset generated by MWDT. Valid only when write * protection is disabled. \\ @@ -209,13 +203,13 @@ typedef union { * 1: Unmask \\ * */ - uint32_t wdt_procpu_reset_en:1; + uint32_t wdt_procpu_reset_en: 1; /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; * Configures whether to enable flash boot protection.\\ * 0: Disable \\ * 1: Enable \\ */ - uint32_t wdt_flashboot_mod_en:1; + uint32_t wdt_flashboot_mod_en: 1; /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; * Configures the system reset signal length. Valid only when write protection is * disabled. \\ @@ -231,7 +225,7 @@ typedef union { * 7: 256 \\ * \end{multicols} */ - uint32_t wdt_sys_reset_length:3; + uint32_t wdt_sys_reset_length: 3; /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; * Configures the CPU reset signal length. Valid only when write protection is * disabled.\\ @@ -247,32 +241,29 @@ typedef union { * 7: 256 \\ * \end{multicols} */ - uint32_t wdt_cpu_reset_length:3; - /** wdt_use_xtal : R/W; bitpos: [21]; default: 0; - * choose WDT clock:0-apb_clk, 1-xtal_clk. - */ - uint32_t wdt_use_xtal:1; + uint32_t wdt_cpu_reset_length: 3; + uint32_t reserved_21: 1; /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; * Configures to update the WDT configuration registers.\\ * 0: No effect \\ * 1: Update \\ */ - uint32_t wdt_conf_update_en:1; + uint32_t wdt_conf_update_en: 1; /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; * Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only * when write protection is disabled. */ - uint32_t wdt_stg3:2; + uint32_t wdt_stg3: 2; /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; * Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only * when write protection is disabled. */ - uint32_t wdt_stg2:2; + uint32_t wdt_stg2: 2; /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; * Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only * when write protection is disabled. */ - uint32_t wdt_stg1:2; + uint32_t wdt_stg1: 2; /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; * Configures the timeout action of stage 0. Valid only when write protection is * disabled. \\ @@ -281,14 +272,14 @@ typedef union { * 2: Reset CPU \\ * 3: Reset system \\ */ - uint32_t wdt_stg0:2; + uint32_t wdt_stg0: 2; /** wdt_en : R/W; bitpos: [31]; default: 0; * Configures whether or not to enable the MWDT. Valid only when write protection is * disabled. \\ * 0: Disable \\ * 1: Enable \\ */ - uint32_t wdt_en:1; + uint32_t wdt_en: 1; }; uint32_t val; } timg_wdtconfig0_reg_t; @@ -303,14 +294,14 @@ typedef union { * 0: No effect \\ * 1: Reset \\ */ - uint32_t wdt_divcnt_rst:1; - uint32_t reserved_1:15; + uint32_t wdt_divcnt_rst: 1; + uint32_t reserved_1: 15; /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; * Configures MWDT clock prescaler value. Valid only when write protection is * disabled. \\ * MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. \\ */ - uint32_t wdt_clk_prescale:16; + uint32_t wdt_clk_prescale: 16; }; uint32_t val; } timg_wdtconfig1_reg_t; @@ -325,7 +316,7 @@ typedef union { * \\ * Measurement unit: mwdt_clk \\ */ - uint32_t wdt_stg0_hold:32; + uint32_t wdt_stg0_hold: 32; }; uint32_t val; } timg_wdtconfig2_reg_t; @@ -340,7 +331,7 @@ typedef union { * disabled.\\ * Measurement unit: mwdt_clk \\ */ - uint32_t wdt_stg1_hold:32; + uint32_t wdt_stg1_hold: 32; }; uint32_t val; } timg_wdtconfig3_reg_t; @@ -355,7 +346,7 @@ typedef union { * \\ * Measurement unit: mwdt_clk \\ */ - uint32_t wdt_stg2_hold:32; + uint32_t wdt_stg2_hold: 32; }; uint32_t val; } timg_wdtconfig4_reg_t; @@ -370,7 +361,7 @@ typedef union { * \\ * Measurement unit: mwdt_clk \\ */ - uint32_t wdt_stg3_hold:32; + uint32_t wdt_stg3_hold: 32; }; uint32_t val; } timg_wdtconfig5_reg_t; @@ -383,7 +374,7 @@ typedef union { /** wdt_feed : WT; bitpos: [31:0]; default: 0; * Write any value to feed the MWDT. Valid only when write protection is disabled. */ - uint32_t wdt_feed:32; + uint32_t wdt_feed: 32; }; uint32_t val; } timg_wdtfeed_reg_t; @@ -396,7 +387,7 @@ typedef union { /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; * Configures a different value than its reset value to enable write protection. */ - uint32_t wdt_wkey:32; + uint32_t wdt_wkey: 32; }; uint32_t val; } timg_wdtwprotect_reg_t; @@ -408,37 +399,31 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:12; + uint32_t reserved_0: 12; /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; * Configures the frequency calculation mode. \\ * 0: one-shot frequency calculation \\ * 1: periodic frequency calculation \\ */ - uint32_t rtc_cali_start_cycling:1; - /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; - * Configures to select the clock to be calibrated\\ - * 0: RTC_SLOW_CLK\\ - * 1: RC_FAST_DIV_CLK\\ - * 2: XTAL32K_CLK\\ - */ - uint32_t rtc_cali_clk_sel:2; + uint32_t rtc_cali_start_cycling: 1; + uint32_t reserved_13: 2; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; * Represents whether one-shot frequency calculation is done.\\ * 0: Not done \\ * 1: Done \\ */ - uint32_t rtc_cali_rdy:1; + uint32_t rtc_cali_rdy: 1; /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; * Configures the time to calculate RTC slow clock's frequency. \\ * Measurement unit: XTAL_CLK \\ */ - uint32_t rtc_cali_max:15; + uint32_t rtc_cali_max: 15; /** rtc_cali_start : R/W; bitpos: [31]; default: 0; * Configures whether to enable one-shot frequency calculation. \\ * 0: Disable \\ * 1: Enable \\ */ - uint32_t rtc_cali_start:1; + uint32_t rtc_cali_start: 1; }; uint32_t val; } timg_rtccalicfg_reg_t; @@ -453,13 +438,13 @@ typedef union { * 0: Not done \\ * 1: Done \\ */ - uint32_t rtc_cali_cycling_data_vld:1; - uint32_t reserved_1:6; + uint32_t rtc_cali_cycling_data_vld: 1; + uint32_t reserved_1: 6; /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; * Represents the value countered by XTAL_CLK when one-shot or periodic frequency * calculation is done. It is used to calculate RTC slow clock's frequency. */ - uint32_t rtc_cali_value:25; + uint32_t rtc_cali_value: 25; }; uint32_t val; } timg_rtccalicfg1_reg_t; @@ -474,19 +459,19 @@ typedef union { * 0: No timeout \\ * 1: Timeout \\ */ - uint32_t rtc_cali_timeout:1; - uint32_t reserved_1:2; + uint32_t rtc_cali_timeout: 1; + uint32_t reserved_1: 2; /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; * Configures the cycles that reset frequency calculation timeout. \\ * Measurement unit: XTAL_CLK \\ */ - uint32_t rtc_cali_timeout_rst_cnt:4; + uint32_t rtc_cali_timeout_rst_cnt: 4; /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; * Configures the threshold value for the RTC frequency calculation timer. If the * timer's value exceeds this threshold, a timeout is triggered.\\ * Measurement unit: XTAL_CLK \\ */ - uint32_t rtc_cali_timeout_thres:25; + uint32_t rtc_cali_timeout_thres: 25; }; uint32_t val; } timg_rtccalicfg2_reg_t; @@ -501,16 +486,13 @@ typedef union { /** t0_int_ena : R/W; bitpos: [0]; default: 0; * Write 1 to enable the TIMG_T0_INT interrupt. */ - uint32_t t0_int_ena:1; - /** t1_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable the TIMG_T1_INT interrupt. - */ - uint32_t t1_int_ena:1; + uint32_t t0_int_ena: 1; + uint32_t reserved_1: 1; /** wdt_int_ena : R/W; bitpos: [2]; default: 0; * Write 1 to enable the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_ena:1; - uint32_t reserved_3:29; + uint32_t wdt_int_ena: 1; + uint32_t reserved_3: 29; }; uint32_t val; } timg_int_ena_timers_reg_t; @@ -523,16 +505,13 @@ typedef union { /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; * The raw interrupt status bit of the TIMG_T0_INT interrupt. */ - uint32_t t0_int_raw:1; - /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status bit of the TIMG_T1_INT interrupt. - */ - uint32_t t1_int_raw:1; + uint32_t t0_int_raw: 1; + uint32_t reserved_1: 1; /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; * The raw interrupt status bit of the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_raw:1; - uint32_t reserved_3:29; + uint32_t wdt_int_raw: 1; + uint32_t reserved_3: 29; }; uint32_t val; } timg_int_raw_timers_reg_t; @@ -545,16 +524,13 @@ typedef union { /** t0_int_st : RO; bitpos: [0]; default: 0; * The masked interrupt status bit of the TIMG_T0_INT interrupt. */ - uint32_t t0_int_st:1; - /** t1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit of the TIMG_T1_INT interrupt. - */ - uint32_t t1_int_st:1; + uint32_t t0_int_st: 1; + uint32_t reserved_1: 1; /** wdt_int_st : RO; bitpos: [2]; default: 0; * The masked interrupt status bit of the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_st:1; - uint32_t reserved_3:29; + uint32_t wdt_int_st: 1; + uint32_t reserved_3: 29; }; uint32_t val; } timg_int_st_timers_reg_t; @@ -567,16 +543,13 @@ typedef union { /** t0_int_clr : WT; bitpos: [0]; default: 0; * Write 1 to clear the TIMG_T0_INT interrupt. */ - uint32_t t0_int_clr:1; - /** t1_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear the TIMG_T1_INT interrupt. - */ - uint32_t t1_int_clr:1; + uint32_t t0_int_clr: 1; + uint32_t reserved_1: 1; /** wdt_int_clr : WT; bitpos: [2]; default: 0; * Write 1 to clear the TIMG_WDT_INT interrupt. */ - uint32_t wdt_int_clr:1; - uint32_t reserved_3:29; + uint32_t wdt_int_clr: 1; + uint32_t reserved_3: 29; }; uint32_t val; } timg_int_clr_timers_reg_t; @@ -591,8 +564,8 @@ typedef union { /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; * Version control register */ - uint32_t ntimgs_date:28; - uint32_t reserved_28:4; + uint32_t ntimgs_date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } timg_ntimers_date_reg_t; @@ -604,55 +577,40 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:28; + uint32_t reserved_0: 28; /** etm_en : R/W; bitpos: [28]; default: 1; * Configures whether to enable timer's ETM task and event. \\ * 0: Disable \\ * 1: Enable \\ */ - uint32_t etm_en:1; - /** wdt_clk_is_active : R/W; bitpos: [29]; default: 1; - * Configures whether to enable WDT's clock. \\ - * 0: Disable \\ - * 1: Enable \\ - */ - uint32_t wdt_clk_is_active:1; - /** timer_clk_is_active : R/W; bitpos: [30]; default: 1; - * Configures whether to enable Timer $x's clock.\\ - * 0: Disable \\ - * 1: Enable \\ - */ - uint32_t timer_clk_is_active:1; + uint32_t etm_en: 1; + uint32_t reserved_29: 2; /** clk_en : R/W; bitpos: [31]; default: 0; * Configures whether to enable gate clock signal for registers. \\ * 0: Force clock on for registers \\ * 1: Support clock only when registers are read or written to by software. \\ */ - uint32_t clk_en:1; + uint32_t clk_en: 1; }; uint32_t val; } timg_regclk_reg_t; typedef struct { - volatile timg_txconfig_reg_t t0config; - volatile timg_txlo_reg_t t0lo; - volatile timg_txhi_reg_t t0hi; - volatile timg_txupdate_reg_t t0update; - volatile timg_txalarmlo_reg_t t0alarmlo; - volatile timg_txalarmhi_reg_t t0alarmhi; - volatile timg_txloadlo_reg_t t0loadlo; - volatile timg_txloadhi_reg_t t0loadhi; - volatile timg_txload_reg_t t0load; - volatile timg_txconfig_reg_t t1config; - volatile timg_txlo_reg_t t1lo; - volatile timg_txhi_reg_t t1hi; - volatile timg_txupdate_reg_t t1update; - volatile timg_txalarmlo_reg_t t1alarmlo; - volatile timg_txalarmhi_reg_t t1alarmhi; - volatile timg_txloadlo_reg_t t1loadlo; - volatile timg_txloadhi_reg_t t1loadhi; - volatile timg_txload_reg_t t1load; + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; + +typedef struct timg_dev_t { + volatile timg_hwtimer_reg_t hw_timer[1]; + uint32_t reserved_024[9]; volatile timg_wdtconfig0_reg_t wdtconfig0; volatile timg_wdtconfig1_reg_t wdtconfig1; volatile timg_wdtconfig2_reg_t wdtconfig2; diff --git a/components/soc/esp32c5/mp/timer_periph.c b/components/soc/esp32c5/mp/timer_periph.c new file mode 100644 index 0000000000..4273eec72e --- /dev/null +++ b/components/soc/esp32c5/mp/timer_periph.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/timer_periph.h" + +const timer_group_signal_conn_t timer_group_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_TIMG0_MODULE, + .timer_irq_id = { + [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE, + } + }, + [1] = { + .module = PERIPH_TIMG1_MODULE, + .timer_irq_id = { + [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE, + } + } + } +};