diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index ef28947543..417dc47db2 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -47,8 +47,8 @@ __attribute__((weak)) void bootloader_clock_configure(void) #endif /* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz */ clk_cfg.cpu_freq_mhz = cpu_freq_mhz; - clk_cfg.slow_freq = rtc_clk_slow_freq_get(); - clk_cfg.fast_freq = rtc_clk_fast_freq_get(); + clk_cfg.slow_clk_src = rtc_clk_slow_src_get(); + clk_cfg.fast_clk_src = rtc_clk_fast_src_get(); rtc_clk_init(clk_cfg); } diff --git a/components/bt/controller/esp32/bt.c b/components/bt/controller/esp32/bt.c index 67a1f5709d..7062f11768 100644 --- a/components/bt/controller/esp32/bt.c +++ b/components/bt/controller/esp32/bt.c @@ -1647,7 +1647,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value #if CONFIG_BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL // check whether or not EXT_CRYS is working - if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; // External 32kHz XTAL #ifdef CONFIG_PM_ENABLE s_btdm_allow_light_sleep = true; diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 0a96826939..9296b86ec4 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -1047,7 +1047,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value #if CONFIG_BT_CTRL_LPCLK_SEL_EXT_32K_XTAL // check whether or not EXT_CRYS is working - if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; // External 32 kHz XTAL s_lp_cntl.no_light_sleep = 0; } else { @@ -1056,7 +1056,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) } #elif CONFIG_BT_CTRL_LPCLK_SEL_RTC_SLOW // check whether or not EXT_CRYS is working - if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) { + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_RTC_SLOW; // Internal 150 kHz RC oscillator ESP_LOGW(BTDM_LOG_TAG, "Internal 150kHz RC osciallator. The accuracy of this clock is a lot larger than 500ppm which is " "required in Bluetooth communication, so don't select this option in scenarios such as BLE connection state."); diff --git a/components/bt/controller/esp32s3/bt.c b/components/bt/controller/esp32s3/bt.c index d318c3e0cf..036be6d6ce 100644 --- a/components/bt/controller/esp32s3/bt.c +++ b/components/bt/controller/esp32s3/bt.c @@ -1015,7 +1015,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value #if CONFIG_BT_CTRL_LPCLK_SEL_EXT_32K_XTAL // check whether or not EXT_CRYS is working - if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; // External 32 kHz XTAL s_lp_cntl.no_light_sleep = 0; } else { @@ -1024,7 +1024,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) } #elif CONFIG_BT_CTRL_LPCLK_SEL_RTC_SLOW // check whether or not EXT_CRYS is working - if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) { + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_RTC_SLOW; // Internal 150 kHz RC oscillator ESP_LOGW(BTDM_LOG_TAG, "Internal 150kHz RC osciallator. The accuracy of this clock is a lot larger than 500ppm which is " "required in Bluetooth communication, so don't select this option in scenarios such as BLE connection state."); diff --git a/components/driver/esp32/touch_sensor.c b/components/driver/esp32/touch_sensor.c index 674e61766c..452eff7311 100644 --- a/components/driver/esp32/touch_sensor.c +++ b/components/driver/esp32/touch_sensor.c @@ -266,12 +266,12 @@ esp_err_t touch_pad_config(touch_pad_t touch_num, uint16_t threshold) uint16_t meas_cycle = 0; uint32_t wait_time_ms = 0; uint32_t wait_tick = 0; - uint32_t rtc_clk = rtc_clk_slow_freq_get_hz(); + uint32_t rtc_clk_freq = rtc_clk_slow_freq_get_hz(); touch_pad_set_group_mask((1 << touch_num), (1 << touch_num), (1 << touch_num)); touch_pad_get_meas_time(&sleep_time, &meas_cycle); //If the FSM mode is 'TOUCH_FSM_MODE_TIMER', The data will be ready after one measurement cycle //after this function is executed, otherwise, the "touch_value" by "touch_pad_read" is 0. - wait_time_ms = sleep_time / (rtc_clk / 1000) + meas_cycle / (RTC_FAST_CLK_FREQ_APPROX / 1000); + wait_time_ms = sleep_time / (rtc_clk_freq / 1000) + meas_cycle / (SOC_CLK_RC_FAST_FREQ_APPROX / 1000); wait_tick = wait_time_ms / portTICK_PERIOD_MS; vTaskDelay(wait_tick ? wait_tick : 1); s_touch_pad_init_bit |= (1 << touch_num); diff --git a/components/driver/rmt/rmt_common.c b/components/driver/rmt/rmt_common.c index 9df192c4eb..fc2b7fe5b4 100644 --- a/components/driver/rmt/rmt_common.c +++ b/components/driver/rmt/rmt_common.c @@ -135,7 +135,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t break; #endif // SOC_RMT_SUPPORT_XTAL #if SOC_RMT_SUPPORT_REF_TICK - case RMT_CLK_SRC_APB_F1M: + case RMT_CLK_SRC_REF_TICK: periph_src_clk_hz = REF_CLK_FREQ; break; #endif // SOC_RMT_SUPPORT_REF_TICK diff --git a/components/esp_hw_support/clk_ctrl_os.c b/components/esp_hw_support/clk_ctrl_os.c index 7ccca19b9b..1d6ff03909 100644 --- a/components/esp_hw_support/clk_ctrl_os.c +++ b/components/esp_hw_support/clk_ctrl_os.c @@ -43,7 +43,7 @@ uint32_t periph_rtc_dig_clk8m_get_freq(void) { #if CONFIG_IDF_TARGET_ESP32H2 /* Workaround: H2 doesn't have 8MD256 clk, so calibration cannot be done, we just return its theoretic frequency */ - return RTC_FAST_CLK_FREQ_APPROX; + return SOC_CLK_RC_FAST_FREQ_APPROX; #else return s_rtc_clk_freq * 256; #endif diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index 96ac34d341..abc915d172 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -32,12 +32,6 @@ #include "regi2c_apll.h" #include "regi2c_bbpll.h" -/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */ -#define RTC_FAST_CLK_FREQ_8M 8500000 -#define RTC_SLOW_CLK_FREQ_150K 150000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - /* BBPLL configuration values */ #define BBPLL_ENDIV5_VAL_320M 0x43 #define BBPLL_BBADC_DSMP_VAL_320M 0x84 @@ -217,7 +211,7 @@ void rtc_clk_32k_bootstrap(uint32_t cycle) gpio_ll_set_level(&GPIO, pin_32, 1); gpio_ll_set_level(&GPIO, pin_33, 0); - const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2); + const uint32_t delay_us = (1000000 / SOC_CLK_XTAL32K_FREQ_APPROX / 2); while(cycle){ gpio_ll_set_level(&GPIO, pin_32, 1); gpio_ll_set_level(&GPIO, pin_33, 0); @@ -372,38 +366,38 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32 } } -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + (slow_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } -rtc_slow_freq_t rtc_clk_slow_freq_get(void) +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); } uint32_t rtc_clk_slow_freq_get_hz(void) { - switch(rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; - case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; - case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + switch(rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: return SOC_CLK_RC_FAST_D256_FREQ_APPROX; } return 0; } -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); } -rtc_fast_freq_t rtc_clk_fast_freq_get(void) +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } @@ -506,7 +500,7 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref); REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); - uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ? + uint32_t delay_pll_en = (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K; esp_rom_delay_us(delay_pll_en); s_cur_pll_freq = pll_freq; @@ -539,7 +533,7 @@ static void rtc_clk_cpu_freq_to_8m(void) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); + rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); } static void rtc_clk_bbpll_disable(void) @@ -608,61 +602,10 @@ void rtc_clk_cpu_freq_set_xtal(void) rtc_clk_bbpll_disable(); } -void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config) -{ - uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; - uint32_t freq_mhz; - uint32_t divider; - - switch (cpu_freq) { - case RTC_CPU_FREQ_XTAL: - case RTC_CPU_FREQ_2M: - source_freq_mhz = rtc_clk_xtal_freq_get(); - source = RTC_CPU_FREQ_SRC_XTAL; - if (cpu_freq == RTC_CPU_FREQ_2M) { - freq_mhz = 2; - divider = source_freq_mhz / 2; - } else { - freq_mhz = source_freq_mhz; - divider = 1; - } - break; - case RTC_CPU_FREQ_80M: - source = RTC_CPU_FREQ_SRC_PLL; - source_freq_mhz = RTC_PLL_FREQ_320M; - divider = 4; - freq_mhz = 80; - break; - case RTC_CPU_FREQ_160M: - source = RTC_CPU_FREQ_SRC_PLL; - source_freq_mhz = RTC_PLL_FREQ_320M; - divider = 2; - freq_mhz = 160; - break; - case RTC_CPU_FREQ_240M: - source = RTC_CPU_FREQ_SRC_PLL; - source_freq_mhz = RTC_PLL_FREQ_480M; - divider = 2; - freq_mhz = 240; - break; - default: - ESP_HW_LOGE(TAG, "invalid rtc_cpu_freq_t value"); - abort(); - } - - *out_config = (rtc_cpu_freq_config_t) { - .source = source, - .source_freq_mhz = source_freq_mhz, - .div = divider, - .freq_mhz = freq_mhz - }; -} - bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config) { uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t divider; uint32_t real_freq_mhz; @@ -676,20 +619,20 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* ou } source_freq_mhz = xtal_freq; - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_320M; divider = 4; } else if (freq_mhz == 160) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_320M; divider = 2; } else if (freq_mhz == 240) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 2; } else { @@ -716,37 +659,37 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config) if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) { rtc_clk_bbpll_disable(); } - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { if (config->div > 1) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); } - } else if (config->source == RTC_CPU_FREQ_SRC_PLL) { + } else if (config->source == SOC_CPU_CLK_SRC_PLL) { rtc_clk_bbpll_enable(); rtc_clk_wait_for_slow_cycle(); rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } else if (config->source == RTC_CPU_FREQ_SRC_8M) { + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); } } void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) { - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t source_freq_mhz; uint32_t div; uint32_t freq_mhz; uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); switch (soc_clk_sel) { case RTC_CNTL_SOC_CLK_SEL_XTL: { - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT) + 1; source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); freq_mhz = source_freq_mhz / div; } break; case RTC_CNTL_SOC_CLK_SEL_PLL: { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) { source_freq_mhz = RTC_PLL_FREQ_320M; @@ -767,7 +710,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) break; } case RTC_CNTL_SOC_CLK_SEL_8M: - source = RTC_CPU_FREQ_SRC_8M; + source = SOC_CPU_CLK_SRC_RC_FAST; source_freq_mhz = 8; div = 1; freq_mhz = source_freq_mhz; @@ -787,9 +730,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config) { - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == RTC_CPU_FREQ_SRC_PLL && + } else if (config->source == SOC_CPU_CLK_SRC_PLL && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else { @@ -855,3 +798,7 @@ bool rtc_dig_8m_enabled(void) * TODO: update the library to use rtc_clk_xtal_freq_get */ rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get"))); +/* TODO: will be replaced by clk_tree API, unavoidable change to the examples + * Aliasing for now, will be added to migration guide + */ +uint32_t rtc_clk_slow_freq_get_hz(void) __attribute__((alias("rtc_clk_slow_freq_get_hz"))); diff --git a/components/esp_hw_support/port/esp32/rtc_clk_init.c b/components/esp_hw_support/port/esp32/rtc_clk_init.c index f4ebfba8c3..89731b256e 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32/rtc_clk_init.c @@ -119,15 +119,15 @@ void rtc_clk_init(rtc_clk_config_t cfg) cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); /* Slow & fast clocks setup */ - if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { rtc_clk_32k_enable(true); } - if (cfg.fast_freq == RTC_FAST_FREQ_8M) { - bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; + if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { + bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256; rtc_clk_8m_enable(true, need_8md256); } - rtc_clk_fast_freq_set(cfg.fast_freq); - rtc_clk_slow_freq_set(cfg.slow_freq); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); } static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void) @@ -148,7 +148,7 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void) * (shifted by RTC_CLK_CAL_FRACT bits). * Xtal frequency will be (cal_val * 8M / 256) / 2^19 */ - uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT; + uint32_t freq_mhz = (cal_val * SOC_CLK_RC_FAST_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT; /* Guess the XTAL type. For now, only 40 and 26MHz are supported. */ switch (freq_mhz) { diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index c871ccf72c..de16b48d38 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -8,13 +8,11 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/dport_reg.h" -#include "soc/rtc.h" #include "soc/i2s_periph.h" #include "soc/timer_periph.h" #include "soc/bb_reg.h" #include "soc/nrx_reg.h" #include "soc/fe_reg.h" -#include "soc/rtc.h" #include "esp32/rom/ets_sys.h" #include "esp32/rom/rtc.h" #include "hal/rtc_cntl_ll.h" diff --git a/components/esp_hw_support/port/esp32/rtc_time.c b/components/esp_hw_support/port/esp32/rtc_time.c index 5de5743c27..76e5017656 100644 --- a/components/esp_hw_support/port/esp32/rtc_time.c +++ b/components/esp_hw_support/port/esp32/rtc_time.c @@ -50,15 +50,15 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); /* Figure out how long to wait for calibration to finish */ uint32_t expected_freq; - rtc_slow_freq_t slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); if (cal_clk == RTC_CAL_32K_XTAL || - (cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_32K_XTAL)) { - expected_freq = 32768; /* standard 32k XTAL */ + (cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)) { + expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; /* standard 32k XTAL */ } else if (cal_clk == RTC_CAL_8MD256 || - (cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_8MD256)) { - expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; + (cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256)) { + expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; } else { - expected_freq = 150000; /* 150k internal oscillator */ + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; /* 150k internal oscillator */ } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Check if the required number of slowclk_cycles may result in an overflow of TIMG_RTC_CALI_VALUE */ diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index da2eff4118..d9b1b43e66 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -65,7 +65,7 @@ bool rtc_clk_8md256_enabled(void) return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); @@ -73,33 +73,33 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead? */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_EXT_CLK) ? 1 : 0); + (slow_freq == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } -rtc_slow_freq_t rtc_clk_slow_freq_get(void) +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); } uint32_t rtc_clk_slow_freq_get_hz(void) { - switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; - case RTC_SLOW_FREQ_EXT_CLK: return RTC_SLOW_CLK_FREQ_EXT; - case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + switch (rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: return SOC_CLK_RC_FAST_D256_FREQ_APPROX; } return 0; } -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); } -rtc_fast_freq_t rtc_clk_fast_freq_get(void) +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } @@ -173,7 +173,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) { uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t divider; uint32_t real_freq_mhz; @@ -187,15 +187,15 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou } source_freq_mhz = xtal_freq; - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 6; } else if (freq_mhz == 120) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 4; } else { @@ -214,18 +214,18 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) { uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) { rtc_clk_bbpll_disable(); } - } else if (config->source == RTC_CPU_FREQ_SRC_PLL) { + } else if (config->source == SOC_CPU_CLK_SRC_PLL) { if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) { rtc_clk_bbpll_enable(); rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); } rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } else if (config->source == RTC_CPU_FREQ_SRC_8M) { + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) { rtc_clk_bbpll_disable(); @@ -235,21 +235,21 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t source_freq_mhz; uint32_t div; uint32_t freq_mhz; uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); switch (soc_clk_sel) { case DPORT_SOC_CLK_SEL_XTAL: { - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); freq_mhz = source_freq_mhz / div; } break; case DPORT_SOC_CLK_SEL_PLL: { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); source_freq_mhz = RTC_PLL_FREQ_480M; // PLL clock on ESP32-C2 was fixed to 480MHz if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) { @@ -265,7 +265,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) break; } case DPORT_SOC_CLK_SEL_8M: - source = RTC_CPU_FREQ_SRC_8M; + source = SOC_CPU_CLK_SRC_RC_FAST; source_freq_mhz = 8; div = 1; freq_mhz = source_freq_mhz; @@ -284,9 +284,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == RTC_CPU_FREQ_SRC_PLL && + } else if (config->source == SOC_CPU_CLK_SRC_PLL && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else { @@ -323,7 +323,7 @@ static void rtc_clk_cpu_freq_to_8m(void) ets_update_cpu_frequency(8); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); + rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk_common.h b/components/esp_hw_support/port/esp32c2/rtc_clk_common.h index 488a9c1c98..7311d32c17 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk_common.h +++ b/components/esp_hw_support/port/esp32c2/rtc_clk_common.h @@ -15,8 +15,6 @@ #define DPORT_SOC_CLK_SEL_PLL 1 #define DPORT_SOC_CLK_SEL_8M 2 -#define RTC_FAST_CLK_FREQ_8M 8500000 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk_init.c b/components/esp_hw_support/port/esp32c2/rtc_clk_init.c index 025ed6dfd9..ef48528415 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk_init.c @@ -67,10 +67,10 @@ void rtc_clk_init(rtc_clk_config_t cfg) cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); /* fast clocks setup */ - if (cfg.fast_freq == RTC_FAST_FREQ_8M) { - bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; + if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { + bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256; rtc_clk_8m_enable(true, need_8md256); } - rtc_clk_fast_freq_set(cfg.fast_freq); - rtc_clk_slow_freq_set(cfg.slow_freq); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); } diff --git a/components/esp_hw_support/port/esp32c2/rtc_init.c b/components/esp_hw_support/port/esp32c2/rtc_init.c index 37ca6a5742..9d3219c5b6 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_init.c @@ -142,13 +142,11 @@ static void calibrate_ocode(void) 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 5. set cpu to old-config. */ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_ext_clk = RTC_SLOW_FREQ_EXT_CLK; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_ext_clk)) { + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { cal_clk = RTC_CAL_EXT_CLK; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } diff --git a/components/esp_hw_support/port/esp32c2/rtc_sleep.c b/components/esp_hw_support/port/esp32c2/rtc_sleep.c index 640e47934a..a64f411d6b 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c2/rtc_sleep.c @@ -10,13 +10,11 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" -#include "soc/rtc.h" #include "soc/bb_reg.h" #include "soc/nrx_reg.h" #include "soc/fe_reg.h" #include "soc/timer_group_reg.h" #include "soc/system_reg.h" -#include "soc/rtc.h" #include "esp32c2/rom/ets_sys.h" #include "esp32c2/rom/rtc.h" #include "regi2c_ctrl.h" diff --git a/components/esp_hw_support/port/esp32c2/rtc_time.c b/components/esp_hw_support/port/esp32c2/rtc_time.c index 247cb617f9..206d9f7365 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_time.c +++ b/components/esp_hw_support/port/esp32c2/rtc_time.c @@ -37,10 +37,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) * The following code emulates ESP32 behavior: */ if (cal_clk == RTC_CAL_RTC_MUX) { - rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_EXT_CLK) { + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { cal_clk = RTC_CAL_EXT_CLK; - } else if (slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } } @@ -71,13 +71,13 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t expected_freq; if (cal_clk == RTC_CAL_EXT_CLK) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_EXT; + expected_freq = SOC_CLK_OSC_SLOW_FREQ_APPROX; } else if (cal_clk == RTC_CAL_8MD256) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_8MD256; + expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_150K; + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 414934ab36..dea9f93d8d 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -115,7 +115,7 @@ bool rtc_clk_8md256_enabled(void) return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); @@ -123,33 +123,33 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead? */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + (slow_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } -rtc_slow_freq_t rtc_clk_slow_freq_get(void) +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); } uint32_t rtc_clk_slow_freq_get_hz(void) { - switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; - case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; - case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + switch (rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: return SOC_CLK_RC_FAST_D256_FREQ_APPROX; } return 0; } -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); } -rtc_fast_freq_t rtc_clk_fast_freq_get(void) +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } @@ -289,7 +289,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) { uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t divider; uint32_t real_freq_mhz; @@ -303,15 +303,15 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou } source_freq_mhz = xtal_freq; - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 6; } else if (freq_mhz == 160) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 3; } else { @@ -330,19 +330,19 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) { uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { // We don't turn off the bbpll if some consumers only depends on bbpll rtc_clk_bbpll_disable(); } - } else if (config->source == RTC_CPU_FREQ_SRC_PLL) { + } else if (config->source == SOC_CPU_CLK_SRC_PLL) { if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) { rtc_clk_bbpll_enable(); rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); } rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } else if (config->source == RTC_CPU_FREQ_SRC_8M) { + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { // We don't turn off the bbpll if some consumers only depends on bbpll @@ -353,21 +353,21 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t source_freq_mhz; uint32_t div; uint32_t freq_mhz; uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); switch (soc_clk_sel) { case DPORT_SOC_CLK_SEL_XTAL: { - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); freq_mhz = source_freq_mhz / div; } break; case DPORT_SOC_CLK_SEL_PLL: { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; @@ -385,7 +385,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) break; } case DPORT_SOC_CLK_SEL_8M: - source = RTC_CPU_FREQ_SRC_8M; + source = SOC_CPU_CLK_SRC_RC_FAST; source_freq_mhz = 8; div = 1; freq_mhz = source_freq_mhz; @@ -404,9 +404,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == RTC_CPU_FREQ_SRC_PLL && + } else if (config->source == SOC_CPU_CLK_SRC_PLL && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else { @@ -446,7 +446,7 @@ static void rtc_clk_cpu_freq_to_8m(void) ets_update_cpu_frequency(8); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); + rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk_common.h b/components/esp_hw_support/port/esp32c3/rtc_clk_common.h index 07f8c1243c..44f6e2b7c4 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk_common.h +++ b/components/esp_hw_support/port/esp32c3/rtc_clk_common.h @@ -15,8 +15,6 @@ #define DPORT_SOC_CLK_SEL_PLL 1 #define DPORT_SOC_CLK_SEL_8M 2 -#define RTC_FAST_CLK_FREQ_8M 8500000 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c index 3ef606dfce..32eeb79424 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c @@ -68,13 +68,13 @@ void rtc_clk_init(rtc_clk_config_t cfg) cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); /* Slow & fast clocks setup */ - if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { rtc_clk_32k_enable(true); } - if (cfg.fast_freq == RTC_FAST_FREQ_8M) { - bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; + if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { + bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256; rtc_clk_8m_enable(true, need_8md256); } - rtc_clk_fast_freq_set(cfg.fast_freq); - rtc_clk_slow_freq_set(cfg.slow_freq); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); } diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 094555deb8..50b8f6c207 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -218,13 +218,11 @@ static void calibrate_ocode(void) 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 5. set cpu to old-config. */ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_x32k)) { + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index 3a4948116b..079f7f4854 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -10,14 +10,12 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" -#include "soc/rtc.h" #include "soc/i2s_reg.h" #include "soc/bb_reg.h" #include "soc/nrx_reg.h" #include "soc/fe_reg.h" #include "soc/timer_group_reg.h" #include "soc/system_reg.h" -#include "soc/rtc.h" #include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/rtc.h" #include "regi2c_ctrl.h" diff --git a/components/esp_hw_support/port/esp32c3/rtc_time.c b/components/esp_hw_support/port/esp32c3/rtc_time.c index 55d1048c66..31a29098bf 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_time.c +++ b/components/esp_hw_support/port/esp32c3/rtc_time.c @@ -37,10 +37,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) * The following code emulates ESP32 behavior: */ if (cal_clk == RTC_CAL_RTC_MUX) { - rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } } else if (cal_clk == RTC_CAL_INTERNAL_OSC) { @@ -80,13 +80,13 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t expected_freq; if (cal_clk == RTC_CAL_32K_XTAL) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_32K; + expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_8MD256) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_8MD256; + expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_150K; + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/esp_hw_support/port/esp32h2/Kconfig.rtc b/components/esp_hw_support/port/esp32h2/Kconfig.rtc index f4b071ec11..9d43def0e9 100644 --- a/components/esp_hw_support/port/esp32h2/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32h2/Kconfig.rtc @@ -12,13 +12,13 @@ choice RTC_CLK_SRC config RTC_CLK_SRC_EXT_OSC bool "External 32kHz oscillator at 32K_XP pin" select ESP_SYSTEM_RTC_EXT_OSC - config RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + config RTC_CLK_SRC_INT_RC32K + bool "Internal 32kHz RC oscillator" endchoice config RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K default 576 if RTC_CLK_SRC_INT_RC range 0 125000 help diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index 09292a1921..83aed1de4c 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -28,7 +28,7 @@ static const char *TAG = "rtc_clk"; #define RTC_PLL_FREQ_96M 96 -#define RTC_OSC_FREQ_RC8M 18 +#define RTC_OSC_FREQ_RC8M 8 #define DELAY_RTC_CLK_SWITCH 5 #define RTC_CNTL_ANA_CONF0_CAL_REG 0x6000e040 #define RTC_CNTL_ANA_CONF0_CAL_START BIT(2) @@ -101,36 +101,36 @@ bool rtc_clk_32k_enabled(void) return !disabled; } -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); - rtc_clk_32k_enable((slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - rtc_clk_rc32k_enable((slow_freq == RTC_SLOW_FREQ_RC32K) ? 1 : 0); + rtc_clk_32k_enable((slow_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0); + rtc_clk_rc32k_enable((slow_freq == SOC_RTC_SLOW_CLK_SRC_RC32K) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } -rtc_slow_freq_t rtc_clk_slow_freq_get(void) +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); } uint32_t rtc_clk_slow_freq_get_hz(void) { - switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; - case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; - case RTC_SLOW_FREQ_RC32K: return RTC_SLOW_CLK_FREQ_RC32; + switch (rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX; } return 0; } -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); } -rtc_fast_freq_t rtc_clk_fast_freq_get(void) +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } @@ -204,11 +204,11 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) { uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t divider; uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get(); if (freq_mhz > xtal_freq) { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_96M; divider = RTC_PLL_FREQ_96M / freq_mhz; rtc_clk_ahb_freq_set(2); @@ -240,35 +240,35 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t source_freq_mhz; uint32_t div; uint32_t freq_mhz; uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); switch (soc_clk_sel) { case DPORT_SOC_CLK_SEL_XTAL: { - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); freq_mhz = source_freq_mhz / div; break; } case DPORT_SOC_CLK_SEL_PLL: { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; source_freq_mhz = RTC_PLL_FREQ_96M; freq_mhz = source_freq_mhz / div; break; } case DPORT_SOC_CLK_SEL_8M: { - source = RTC_CPU_FREQ_SRC_8M; + source = SOC_CPU_CLK_SRC_RC_FAST; source_freq_mhz = RTC_OSC_FREQ_RC8M; div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; freq_mhz = source_freq_mhz / div; break; } case DPORT_SOC_CLK_SEL_XTAL_D2: { - source = RTC_CPU_FREQ_SRC_XTAL_D2; + source = SOC_CPU_CLK_SRC_XTAL_D2; div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); freq_mhz = source_freq_mhz / div / 2; @@ -289,9 +289,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == RTC_CPU_FREQ_SRC_PLL && + } else if (config->source == SOC_CPU_CLK_SRC_PLL && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else { @@ -429,24 +429,24 @@ uint32_t root_clk_slt(uint32_t source) { uint32_t root_clk_freq_mhz; switch (source) { - case RTC_CPU_FREQ_SRC_XTAL: + case SOC_CPU_CLK_SRC_XTAL: root_clk_freq_mhz = RTC_XTAL_FREQ_32M; rtc_clk_bbpll_disable(); break; - case RTC_CPU_FREQ_SRC_PLL: + case SOC_CPU_CLK_SRC_PLL: // SPLL_ENABLE root_clk_freq_mhz = RTC_PLL_FREQ_96M; rtc_clk_bbpll_enable(); rtc_clk_bbpll_configure(RTC_XTAL_FREQ_32M, root_clk_freq_mhz); rtc_clk_bbpll_cali_stop(); break; - case RTC_CPU_FREQ_SRC_8M: + case SOC_CPU_CLK_SRC_RC_FAST: root_clk_freq_mhz = RTC_OSC_FREQ_RC8M; rtc_dig_clk8m_enable(); rtc_clk_8m_divider_set(1); rtc_clk_bbpll_disable(); break; - case RTC_CPU_FREQ_SRC_XTAL_D2: + case SOC_CPU_CLK_SRC_XTAL_D2: root_clk_freq_mhz = RTC_XTAL_FREQ_32M / 2; rtc_clk_bbpll_disable(); break; diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_common.h b/components/esp_hw_support/port/esp32h2/rtc_clk_common.h index 76e3fd3208..ea32098590 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk_common.h +++ b/components/esp_hw_support/port/esp32h2/rtc_clk_common.h @@ -16,8 +16,6 @@ #define DPORT_SOC_CLK_SEL_8M 2 #define DPORT_SOC_CLK_SEL_XTAL_D2 3 -#define RTC_FAST_CLK_FREQ_8M 8500000 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c index c237338399..f9efc1cdbc 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c @@ -80,12 +80,12 @@ void rtc_clk_init(rtc_clk_config_t cfg) cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); /* Slow & fast clocks setup */ - if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { rtc_clk_32k_enable(true); } - if (cfg.fast_freq == RTC_FAST_FREQ_8M) { + if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { rtc_dig_clk8m_enable(); } - rtc_clk_fast_freq_set(cfg.fast_freq); - rtc_clk_slow_freq_set(cfg.slow_freq); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); } diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c index 44f47aff53..f9947fe327 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_time.c +++ b/components/esp_hw_support/port/esp32h2/rtc_time.c @@ -37,10 +37,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) * The following code emulates ESP32 behavior: */ if (cal_clk == RTC_CAL_RTC_MUX) { - rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_freq == RTC_SLOW_FREQ_RC32K) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { cal_clk = RTC_CAL_RC32K; } } @@ -77,13 +77,13 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t expected_freq; if (cal_clk == RTC_CAL_32K_XTAL) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_32K; + expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_RC32K) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_RC32; + expected_freq = SOC_CLK_RC32K_FREQ_APPROX; } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_150K; + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk.c b/components/esp_hw_support/port/esp32s2/rtc_clk.c index 00f4096218..c4c66ac0e9 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s2/rtc_clk.c @@ -208,7 +208,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32 } } -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); @@ -216,33 +216,33 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead? */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + (slow_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } -rtc_slow_freq_t rtc_clk_slow_freq_get(void) +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); } uint32_t rtc_clk_slow_freq_get_hz(void) { - switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_90K; - case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; - case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + switch (rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: return SOC_CLK_RC_FAST_D256_FREQ_APPROX; } return 0; } -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); } -rtc_fast_freq_t rtc_clk_fast_freq_get(void) +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } @@ -352,7 +352,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config) { uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t divider; uint32_t real_freq_mhz; @@ -366,20 +366,20 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* ou } source_freq_mhz = xtal_freq; - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 6; } else if (freq_mhz == 160) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 3; } else if (freq_mhz == 240) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 2; } else { @@ -404,36 +404,36 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config) if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && config->source_freq_mhz != s_cur_pll_freq) { rtc_clk_bbpll_disable(); } - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { if (config->div > 1) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); } - } else if (config->source == RTC_CPU_FREQ_SRC_PLL) { + } else if (config->source == SOC_CPU_CLK_SRC_PLL) { rtc_clk_bbpll_enable(); rtc_clk_bbpll_configure(RTC_XTAL_FREQ, config->source_freq_mhz); rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } else if (config->source == RTC_CPU_FREQ_SRC_8M) { + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); } } void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) { - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t source_freq_mhz; uint32_t div; uint32_t freq_mhz; uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); switch (soc_clk_sel) { case DPORT_SOC_CLK_SEL_XTAL: { - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1; source_freq_mhz = RTC_XTAL_FREQ; freq_mhz = source_freq_mhz / div; } break; case DPORT_SOC_CLK_SEL_PLL: { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); uint32_t pllfreq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; @@ -454,7 +454,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) break; } case DPORT_SOC_CLK_SEL_8M: - source = RTC_CPU_FREQ_SRC_8M; + source = SOC_CPU_CLK_SRC_RC_FAST; source_freq_mhz = 8; div = 1; freq_mhz = source_freq_mhz; @@ -474,9 +474,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config) { - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == RTC_CPU_FREQ_SRC_PLL && + } else if (config->source == SOC_CPU_CLK_SRC_PLL && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else { @@ -518,7 +518,7 @@ static void rtc_clk_cpu_freq_to_8m(void) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); + rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk_common.h b/components/esp_hw_support/port/esp32s2/rtc_clk_common.h index 570c34c865..210c617cf7 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk_common.h +++ b/components/esp_hw_support/port/esp32s2/rtc_clk_common.h @@ -20,8 +20,6 @@ #define DPORT_SOC_CLK_SEL_8M 2 #define DPORT_SOC_CLK_SEL_APLL 3 -#define RTC_FAST_CLK_FREQ_8M 8500000 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk_init.c b/components/esp_hw_support/port/esp32s2/rtc_clk_init.c index 63a880847e..2d7d3399dc 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_clk_init.c @@ -66,13 +66,13 @@ void rtc_clk_init(rtc_clk_config_t cfg) cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); /* Slow & fast clocks setup */ - if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { rtc_clk_32k_enable(true); } - if (cfg.fast_freq == RTC_FAST_FREQ_8M) { - bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; + if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { + bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256; rtc_clk_8m_enable(true, need_8md256); } - rtc_clk_fast_freq_set(cfg.fast_freq); - rtc_clk_slow_freq_set(cfg.slow_freq); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); } diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index e1176bcf91..e71d831d0f 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -244,13 +244,11 @@ static void calibrate_ocode(void) 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 5. set cpu to old-config. */ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_x32k)) { + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } diff --git a/components/esp_hw_support/port/esp32s2/rtc_sleep.c b/components/esp_hw_support/port/esp32s2/rtc_sleep.c index cf587fa38e..c138239934 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s2/rtc_sleep.c @@ -10,13 +10,11 @@ #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" #include "soc/dport_reg.h" -#include "soc/rtc.h" #include "soc/i2s_reg.h" #include "soc/timer_group_reg.h" #include "soc/bb_reg.h" #include "soc/nrx_reg.h" #include "soc/fe_reg.h" -#include "soc/rtc.h" #include "esp32s2/rom/ets_sys.h" #include "esp32s2/rom/rtc.h" #include "hal/rtc_cntl_ll.h" diff --git a/components/esp_hw_support/port/esp32s2/rtc_time.c b/components/esp_hw_support/port/esp32s2/rtc_time.c index 4dca202b23..840fc34012 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_time.c +++ b/components/esp_hw_support/port/esp32s2/rtc_time.c @@ -53,13 +53,13 @@ static uint32_t rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk, uint32_t slow uint32_t expected_freq; if (cal_clk == RTC_CAL_32K_XTAL) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_32K; + expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_8MD256) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_8MD256; + expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_90K; + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ @@ -140,10 +140,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui * The following code emulates ESP32 behavior: */ if (cal_clk == RTC_CAL_RTC_MUX) { - rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } } else if (cal_clk == RTC_CAL_INTERNAL_OSC) { diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 9a7028b660..9b222885c2 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -126,17 +126,17 @@ bool rtc_clk_8md256_enabled(void) static void wait_dig_dbias_valid(uint64_t rtc_cycles) { - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); + soc_rtc_slow_clk_src_t slow_clk_freq = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) { + } else if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } rtc_clk_cal(cal_clk, rtc_cycles); } -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); @@ -144,33 +144,33 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead? */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + (slow_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } -rtc_slow_freq_t rtc_clk_slow_freq_get(void) +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); } uint32_t rtc_clk_slow_freq_get_hz(void) { - switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; - case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; - case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + switch (rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: return SOC_CLK_RC_FAST_D256_FREQ_APPROX; } return 0; } -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); esp_rom_delay_us(DELAY_FAST_CLK_SWITCH); } -rtc_fast_freq_t rtc_clk_fast_freq_get(void) +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } @@ -321,7 +321,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) { uint32_t source_freq_mhz; - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t divider; uint32_t real_freq_mhz; @@ -335,20 +335,20 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou } source_freq_mhz = xtal_freq; - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 6; } else if (freq_mhz == 160) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 3; } else if (freq_mhz == 240) { real_freq_mhz = freq_mhz; - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; source_freq_mhz = RTC_PLL_FREQ_480M; divider = 2; } else { @@ -367,19 +367,19 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) { uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { // We don't turn off the bbpll if some consumers only depends on bbpll rtc_clk_bbpll_disable(); } - } else if (config->source == RTC_CPU_FREQ_SRC_PLL) { + } else if (config->source == SOC_CPU_CLK_SRC_PLL) { if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) { rtc_clk_bbpll_enable(); rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); } rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } else if (config->source == RTC_CPU_FREQ_SRC_8M) { + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) { // We don't turn off the bbpll if some consumers only depends on bbpll @@ -390,21 +390,21 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { - rtc_cpu_freq_src_t source; + soc_cpu_clk_src_t source; uint32_t source_freq_mhz; uint32_t div; uint32_t freq_mhz; uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); switch (soc_clk_sel) { case DPORT_SOC_CLK_SEL_XTAL: { - source = RTC_CPU_FREQ_SRC_XTAL; + source = SOC_CPU_CLK_SRC_XTAL; div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); freq_mhz = source_freq_mhz / div; } break; case DPORT_SOC_CLK_SEL_PLL: { - source = RTC_CPU_FREQ_SRC_PLL; + source = SOC_CPU_CLK_SRC_PLL; uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); uint32_t pllfreq_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; @@ -425,7 +425,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) break; } case DPORT_SOC_CLK_SEL_8M: - source = RTC_CPU_FREQ_SRC_8M; + source = SOC_CPU_CLK_SRC_RC_FAST; source_freq_mhz = 8; div = 1; freq_mhz = source_freq_mhz; @@ -444,9 +444,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { - if (config->source == RTC_CPU_FREQ_SRC_XTAL) { + if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == RTC_CPU_FREQ_SRC_PLL && + } else if (config->source == SOC_CPU_CLK_SRC_PLL && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else { @@ -496,7 +496,7 @@ static void rtc_clk_cpu_freq_to_8m(void) wait_dig_dbias_valid(2); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); + rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk_common.h b/components/esp_hw_support/port/esp32s3/rtc_clk_common.h index 01b3c1cea2..c6b8e17be8 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk_common.h +++ b/components/esp_hw_support/port/esp32s3/rtc_clk_common.h @@ -19,8 +19,6 @@ #define DPORT_SOC_CLK_SEL_PLL 1 #define DPORT_SOC_CLK_SEL_8M 2 -#define RTC_FAST_CLK_FREQ_8M 8500000 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk_init.c b/components/esp_hw_support/port/esp32s3/rtc_clk_init.c index a2343b644a..47168babac 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk_init.c @@ -64,13 +64,13 @@ void rtc_clk_init(rtc_clk_config_t cfg) cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); /* Slow & fast clocks setup */ - if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { rtc_clk_32k_enable(true); } - if (cfg.fast_freq == RTC_FAST_FREQ_8M) { - bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; + if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { + bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256; rtc_clk_8m_enable(true, need_8md256); } - rtc_clk_fast_freq_set(cfg.fast_freq); - rtc_clk_slow_freq_set(cfg.slow_freq); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); } diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index 3866a4b682..d9bbbb976b 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -260,13 +260,11 @@ static void calibrate_ocode(void) 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 5. set cpu to old-config. */ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_x32k)) { + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index ca6e3784dd..18f92184b0 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -10,16 +10,13 @@ #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" #include "soc/dport_reg.h" -#include "soc/rtc.h" #include "soc/i2s_reg.h" #include "soc/timer_group_reg.h" #include "soc/bb_reg.h" #include "soc/nrx_reg.h" #include "soc/fe_reg.h" -#include "soc/rtc.h" #include "regi2c_ctrl.h" #include "regi2c_dig_reg.h" -#include "soc/rtc.h" #define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) diff --git a/components/esp_hw_support/port/esp32s3/rtc_time.c b/components/esp_hw_support/port/esp32s3/rtc_time.c index ed7eaabda2..060c97de23 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_time.c +++ b/components/esp_hw_support/port/esp32s3/rtc_time.c @@ -36,10 +36,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) * The following code emulates ESP32 behavior: */ if (cal_clk == RTC_CAL_RTC_MUX) { - rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } } else if (cal_clk == RTC_CAL_INTERNAL_OSC) { @@ -78,13 +78,13 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t expected_freq; if (cal_clk == RTC_CAL_32K_XTAL) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_32K; + expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_8MD256) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_8MD256; + expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_150K; + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/esp_hw_support/sdkconfig.rename.esp32h2 b/components/esp_hw_support/sdkconfig.rename.esp32h2 index d72afa34e0..b9df04f7d0 100644 --- a/components/esp_hw_support/sdkconfig.rename.esp32h2 +++ b/components/esp_hw_support/sdkconfig.rename.esp32h2 @@ -4,5 +4,4 @@ CONFIG_ESP32H2_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC CONFIG_ESP32H2_RTC_CLK_SRC_EXT_CRYS CONFIG_RTC_CLK_SRC_EXT_CRYS CONFIG_ESP32H2_RTC_CLK_SRC_EXT_OSC CONFIG_RTC_CLK_SRC_EXT_OSC -CONFIG_ESP32H2_RTC_CLK_SRC_INT_8MD256 CONFIG_RTC_CLK_SRC_INT_8MD256 CONFIG_ESP32H2_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 97ece34de8..170a8e4560 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -396,7 +396,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) #if SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 //Keep the RTC8M_CLK on if RTC clock is 8MD256. - bool rtc_using_8md256 = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_8MD256); + bool rtc_using_8md256 = (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256); #else bool rtc_using_8md256 = false; #endif diff --git a/components/esp_hw_support/test/test_rtc_clk.c b/components/esp_hw_support/test/test_rtc_clk.c index d293f1f997..b264f72288 100644 --- a/components/esp_hw_support/test/test_rtc_clk.c +++ b/components/esp_hw_support/test/test_rtc_clk.c @@ -48,7 +48,11 @@ #include "esp32c2/rom/rtc.h" #endif +// ESP32C2 does not support SLOW_CLK_32K_XTAL, so no need to test related test cases +// Please notice this when enabling the rtc_clk test for ESP32C2! +#if !CONFIG_IDF_TARGET_ESP32C2 extern void rtc_clk_select_rtc_slow_clk(void); +#endif #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2) @@ -83,8 +87,8 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") if (cal_ext_slow_clk == 0) { printf("EXT CLOCK by PIN has not started up"); } else { - printf("switching to RTC_SLOW_FREQ_EXT_CLK: "); - rtc_clk_slow_freq_set(RTC_SLOW_FREQ_EXT_CLK); + printf("switching to SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: "); + rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW); printf("done\n"); CALIBRATE_ONE(RTC_CAL_RTC_MUX); @@ -96,8 +100,8 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") if (cal_32k == 0) { printf("32K XTAL OSC has not started up"); } else { - printf("switching to RTC_SLOW_FREQ_32K_XTAL: "); - rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL); + printf("switching to SOC_RTC_SLOW_CLK_SRC_XTAL32K: "); + rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_XTAL32K); printf("done\n"); CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(RTC_CAL_8MD256); @@ -105,8 +109,8 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") } #endif - printf("switching to RTC_SLOW_FREQ_8MD256: "); - rtc_clk_slow_freq_set(RTC_SLOW_FREQ_8MD256); + printf("switching to SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: "); + rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256); printf("done\n"); CALIBRATE_ONE(RTC_CAL_RTC_MUX); @@ -181,7 +185,7 @@ TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]") uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100); uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period; printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz); - TEST_ASSERT_INT32_WITHIN(650000, RTC_FAST_CLK_FREQ_APPROX, rtc_fast_freq_hz); + TEST_ASSERT_INT32_WITHIN(650000, SOC_CLK_RC_FAST_FREQ_APPROX, rtc_fast_freq_hz); } TEST_CASE("Test switching between PLL and XTAL", "[rtc_clk]") @@ -218,12 +222,12 @@ void stop_rtc_external_quartz(void){ gpio_ll_output_disable(&GPIO, pin_33); } -static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_ms) +static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay_ms) { int i = 0, fail = 0; uint32_t start_time; uint32_t end_time; - rtc_slow_freq_t selected_src_freq; + soc_rtc_slow_clk_src_t selected_src; stop_rtc_external_quartz(); #ifdef CONFIG_RTC_CLK_SRC_EXT_CRYS uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES; @@ -247,10 +251,10 @@ static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_m rtc_clk_32k_bootstrap(bootstrap_cycles); esp_rom_delay_us(start_delay_ms * 1000); rtc_clk_select_rtc_slow_clk(); - selected_src_freq = rtc_clk_slow_freq_get(); + selected_src = rtc_clk_slow_src_get(); end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ); printf(" [time=%d] ", (end_time - start_time) - start_delay_ms); - if(selected_src_freq != required_src_freq){ + if(selected_src != required_src){ printf("FAIL. Time measurement..."); fail = 1; } else { @@ -323,8 +327,8 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk][test_env=UT_T1_32kXTAL]") { - start_freq(RTC_SLOW_FREQ_32K_XTAL, 200); - start_freq(RTC_SLOW_FREQ_32K_XTAL, 0); + start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 200); + start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 0); } TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][test_env=UT_T1_no32kXTAL]") @@ -337,8 +341,8 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_ "will switch to the internal RC circuit. If the switch to the internal RC circuit " "was successful then the test succeeded.\n"); - start_freq(RTC_SLOW_FREQ_RTC, 200); - start_freq(RTC_SLOW_FREQ_RTC, 0); + start_freq(SOC_RTC_SLOW_CLK_SRC_RC_SLOW, 200); + start_freq(SOC_RTC_SLOW_CLK_SRC_RC_SLOW, 0); } #endif // !IDF_CI_BUILD || !CONFIG_SPIRAM_BANKSWITCH_ENABLE diff --git a/components/esp_system/port/include/esp_clk_internal.h b/components/esp_system/port/include/esp_clk_internal.h index cc9d121285..b69d7cfcea 100644 --- a/components/esp_system/port/include/esp_clk_internal.h +++ b/components/esp_system/port/include/esp_clk_internal.h @@ -6,6 +6,8 @@ #pragma once +#include "sdkconfig.h" + #ifdef __cplusplus extern "C" { #endif @@ -34,10 +36,12 @@ void esp_clk_init(void); */ void esp_perip_clk_init(void); +#if !CONFIG_IDF_TARGET_ESP32C2 /* Selects an external clock source (32 kHz) for RTC. * Only internal use in unit test. */ void rtc_clk_select_rtc_slow_clk(void); +#endif #ifdef __cplusplus } diff --git a/components/esp_system/port/soc/esp32/clk.c b/components/esp_system/port/soc/esp32/clk.c index 251415a02f..67ee2854d0 100644 --- a/components/esp_system/port/soc/esp32/clk.c +++ b/components/esp_system/port/soc/esp32/clk.c @@ -47,20 +47,20 @@ static const char* TAG = "clk"; */ #define EXT_OSC_FLAG BIT(3) -/* This is almost the same as rtc_slow_freq_t, except that we define +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. */ typedef enum { - SLOW_CLK_150K = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin + SLOW_CLK_150K = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator + SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL + SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256 + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) { - rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; uint32_t cal_val = 0; /* number of times to repeat 32k XTAL calibration * before giving up and switching to the internal RC @@ -68,7 +68,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) int retry_32k_xtal = RTC_XTAL_CAL_RETRY; do { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { /* 32k XTAL oscillator needs to be enabled and running before it can * be used. Hardware doesn't have a direct way of checking if the * oscillator is running. Here we use rtc_clk_cal function to count @@ -90,13 +90,13 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) continue; } ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); - rtc_slow_freq = RTC_SLOW_FREQ_RTC; + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { rtc_clk_8m_enable(true, true); } - rtc_clk_slow_freq_set(rtc_slow_freq); + rtc_clk_slow_src_set(rtc_slow_clk_src); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. @@ -132,7 +132,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO); #endif - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #ifdef CONFIG_BOOTLOADER_WDT_ENABLE // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. @@ -156,7 +156,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) select_rtc_slow_clk(SLOW_CLK_8MD256); #else - select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); + select_rtc_slow_clk(SLOW_CLK_150K); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -308,5 +308,5 @@ __attribute__((weak)) void esp_perip_clk_init(void) void rtc_clk_select_rtc_slow_clk(void) { - select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL); + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); } diff --git a/components/esp_system/port/soc/esp32c2/clk.c b/components/esp_system/port/soc/esp32c2/clk.c index 112b3347f5..c07abd9d74 100644 --- a/components/esp_system/port/soc/esp32c2/clk.c +++ b/components/esp_system/port/soc/esp32c2/clk.c @@ -46,14 +46,14 @@ */ #define EXT_OSC_FLAG BIT(3) -/* This is almost the same as rtc_slow_freq_t, except that we define +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_EXT_CLK | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin + SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator + SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256 + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW | EXT_OSC_FLAG //!< External 32k oscillator connected to pin0 } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); @@ -74,7 +74,7 @@ static const char *TAG = "clk"; assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -97,7 +97,7 @@ static const char *TAG = "clk"; #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) select_rtc_slow_clk(SLOW_CLK_8MD256); #else - select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); + select_rtc_slow_clk(SLOW_CLK_RTC); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -131,15 +131,15 @@ static const char *TAG = "clk"; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) { - rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; uint32_t cal_val = 0; - /* number of times to repeat 32k XTAL calibration + /* number of times to repeat external clock calibration * before giving up and switching to the internal RC */ int retry_ext_clk = 3; do { - if (rtc_slow_freq == RTC_SLOW_FREQ_EXT_CLK) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { /* external clock needs to be connected to PIN0 before it can * be used. Here we use rtc_clk_cal function to count * the number of ext clk cycles in the given number of ext clk @@ -155,13 +155,13 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) continue; } ESP_EARLY_LOGW(TAG, "external clock connected to pin0 not found, switching to internal 150 kHz oscillator"); - rtc_slow_freq = RTC_SLOW_FREQ_RTC; + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { rtc_clk_8m_enable(true, true); } - rtc_clk_slow_freq_set(rtc_slow_freq); + rtc_clk_slow_src_set(rtc_slow_clk_src); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. @@ -177,11 +177,6 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) esp_clk_slowclk_cal_set(cal_val); } -void rtc_clk_select_rtc_slow_clk(void) -{ - select_rtc_slow_clk(RTC_SLOW_FREQ_EXT_CLK); -} - /* This function is not exposed as an API at this point. * All peripheral clocks are default enabled after chip is powered on. * This function disables some peripheral clocks when cpu starts. diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index ed7569f82b..19ab41fbe9 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -47,15 +47,15 @@ */ #define EXT_OSC_FLAG BIT(3) -/* This is almost the same as rtc_slow_freq_t, except that we define +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin + SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator + SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL + SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256 + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); @@ -76,7 +76,7 @@ static const char *TAG = "clk"; assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -101,7 +101,7 @@ static const char *TAG = "clk"; #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) select_rtc_slow_clk(SLOW_CLK_8MD256); #else - select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); + select_rtc_slow_clk(SLOW_CLK_RTC); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -135,7 +135,7 @@ static const char *TAG = "clk"; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) { - rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; uint32_t cal_val = 0; /* number of times to repeat 32k XTAL calibration * before giving up and switching to the internal RC @@ -143,7 +143,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) int retry_32k_xtal = 3; do { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { /* 32k XTAL oscillator needs to be enabled and running before it can * be used. Hardware doesn't have a direct way of checking if the * oscillator is running. Here we use rtc_clk_cal function to count @@ -165,13 +165,13 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) continue; } ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); - rtc_slow_freq = RTC_SLOW_FREQ_RTC; + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { rtc_clk_8m_enable(true, true); } - rtc_clk_slow_freq_set(rtc_slow_freq); + rtc_clk_slow_src_set(rtc_slow_clk_src); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. @@ -189,7 +189,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) void rtc_clk_select_rtc_slow_clk(void) { - select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL); + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); } /* This function is not exposed as an API at this point. diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 3045393b19..a8fde2b0cc 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -47,15 +47,15 @@ */ #define EXT_OSC_FLAG BIT(3) -/* This is almost the same as rtc_slow_freq_t, except that we define +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL - SLOW_CLK_RC32K = RTC_SLOW_FREQ_RC32K, //!< Internal 32 KHz RC oscillator - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin + SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator + SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL + SLOW_CLK_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32 KHz RC oscillator + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); @@ -75,7 +75,7 @@ static const char *TAG = "clk"; assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M); - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #ifdef CONFIG_BOOTLOADER_WDT_ENABLE // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. @@ -96,10 +96,10 @@ static const char *TAG = "clk"; select_rtc_slow_clk(SLOW_CLK_32K_XTAL); #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC); -#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) - select_rtc_slow_clk(SLOW_CLK_8MD256); +#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K) + select_rtc_slow_clk(SLOW_CLK_RC32K); #else - select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); + select_rtc_slow_clk(SLOW_CLK_RTC); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -133,7 +133,7 @@ static const char *TAG = "clk"; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) { - rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; uint32_t cal_val = 0; /* number of times to repeat 32k XTAL calibration * before giving up and switching to the internal RC @@ -141,7 +141,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) int retry_32k_xtal = 3; do { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { /* 32k XTAL oscillator needs to be enabled and running before it can * be used. Hardware doesn't have a direct way of checking if the * oscillator is running. Here we use rtc_clk_cal function to count @@ -163,12 +163,13 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) continue; } ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); - rtc_slow_freq = RTC_SLOW_FREQ_RTC; + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(true); } - rtc_clk_slow_freq_set(rtc_slow_freq); + rtc_clk_slow_src_set(rtc_slow_clk_src); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. @@ -186,7 +187,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) void rtc_clk_select_rtc_slow_clk(void) { - select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL); + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); } /* This function is not exposed as an API at this point. diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c index 4d3fe1e6b7..482183b22c 100644 --- a/components/esp_system/port/soc/esp32s2/clk.c +++ b/components/esp_system/port/soc/esp32s2/clk.c @@ -52,15 +52,15 @@ static const char *TAG = "clk"; */ #define EXT_OSC_FLAG BIT(3) -/* This is almost the same as rtc_slow_freq_t, except that we define +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 90 kHz RC oscillator - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin + SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 90 kHz RC oscillator + SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL + SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256 + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); @@ -74,7 +74,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); } rtc_init(cfg); - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #ifdef CONFIG_BOOTLOADER_WDT_ENABLE // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. @@ -98,7 +98,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) select_rtc_slow_clk(SLOW_CLK_8MD256); #else - select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); + select_rtc_slow_clk(SLOW_CLK_RTC); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -137,7 +137,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) #ifdef CONFIG_IDF_ENV_FPGA return; #endif - rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; uint32_t cal_val = 0; /* number of times to repeat 32k XTAL calibration * before giving up and switching to the internal RC @@ -145,7 +145,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) int retry_32k_xtal = RTC_XTAL_CAL_RETRY; do { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { /* 32k XTAL oscillator needs to be enabled and running before it can * be used. Hardware doesn't have a direct way of checking if the * oscillator is running. Here we use rtc_clk_cal function to count @@ -167,13 +167,13 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) continue; } ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator"); - rtc_slow_freq = RTC_SLOW_FREQ_RTC; + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { rtc_clk_8m_enable(true, true); } - rtc_clk_slow_freq_set(rtc_slow_freq); + rtc_clk_slow_src_set(rtc_slow_clk_src); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. @@ -191,7 +191,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) void rtc_clk_select_rtc_slow_clk(void) { - select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL); + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); } /* This function is not exposed as an API at this point. diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 9c7f5a6749..11abfe62c3 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -47,15 +47,15 @@ static const char *TAG = "clk"; */ #define EXT_OSC_FLAG BIT(3) -/* This is almost the same as rtc_slow_freq_t, except that we define +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin + SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator + SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL + SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256 + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); @@ -73,7 +73,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #ifdef CONFIG_BOOTLOADER_WDT_ENABLE // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. @@ -97,7 +97,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); #elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) select_rtc_slow_clk(SLOW_CLK_8MD256); #else - select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); + select_rtc_slow_clk(SLOW_CLK_RTC); #endif #ifdef CONFIG_BOOTLOADER_WDT_ENABLE @@ -133,7 +133,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) { - rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; uint32_t cal_val = 0; /* number of times to repeat 32k XTAL calibration * before giving up and switching to the internal RC @@ -141,7 +141,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) int retry_32k_xtal = RTC_XTAL_CAL_RETRY; do { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { /* 32k XTAL oscillator needs to be enabled and running before it can * be used. Hardware doesn't have a direct way of checking if the * oscillator is running. Here we use rtc_clk_cal function to count @@ -163,13 +163,13 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) continue; } ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); - rtc_slow_freq = RTC_SLOW_FREQ_RTC; + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) { + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { rtc_clk_8m_enable(true, true); } - rtc_clk_slow_freq_set(rtc_slow_freq); + rtc_clk_slow_src_set(rtc_slow_clk_src); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. @@ -187,7 +187,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) void rtc_clk_select_rtc_slow_clk(void) { - select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL); + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); } /* This function is not exposed as an API at this point. diff --git a/components/hal/esp32/include/hal/dac_ll.h b/components/hal/esp32/include/hal/dac_ll.h index ec1c20c4fb..7c0ca0e640 100644 --- a/components/hal/esp32/include/hal/dac_ll.h +++ b/components/hal/esp32/include/hal/dac_ll.h @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -126,7 +118,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable) */ static inline void dac_ll_cw_set_freq(uint32_t freq) { - uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX; + uint32_t sw_freq = freq * 0xFFFF / SOC_CLK_RC_FAST_FREQ_APPROX; HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq); } diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index df042e6097..5dd7ad62cb 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -90,7 +90,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, case RMT_CLK_SRC_APB: dev->conf_ch[channel].conf1.ref_always_on = 1; break; - case RMT_CLK_SRC_APB_F1M: + case RMT_CLK_SRC_REF_TICK: dev->conf_ch[channel].conf1.ref_always_on = 0; break; default: @@ -538,7 +538,7 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint if (dev->conf_ch[channel].conf1.ref_always_on) { return RMT_CLK_SRC_APB; } - return RMT_CLK_SRC_APB_F1M; + return RMT_CLK_SRC_REF_TICK; } static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h index 07f17d4b65..21850c9b97 100644 --- a/components/hal/esp32/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32/include/hal/touch_sensor_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE diff --git a/components/hal/esp32s2/include/hal/dac_ll.h b/components/hal/esp32s2/include/hal/dac_ll.h index 28c8ae2066..66ebb1ac33 100644 --- a/components/hal/esp32s2/include/hal/dac_ll.h +++ b/components/hal/esp32s2/include/hal/dac_ll.h @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -147,7 +139,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable) */ static inline void dac_ll_cw_set_freq(uint32_t freq) { - uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX; + uint32_t sw_freq = freq * 0xFFFF / SOC_CLK_RC_FAST_FREQ_APPROX; HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq); } diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h index 290270632c..ae23a8431b 100644 --- a/components/hal/esp32s2/include/hal/rmt_ll.h +++ b/components/hal/esp32s2/include/hal/rmt_ll.h @@ -95,7 +95,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, case RMT_CLK_SRC_APB: dev->conf_ch[channel].conf1.ref_always_on = 1; break; - case RMT_CLK_SRC_APB_F1M: + case RMT_CLK_SRC_REF_TICK: dev->conf_ch[channel].conf1.ref_always_on = 0; break; default: @@ -679,7 +679,7 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint if (dev->conf_ch[channel].conf1.ref_always_on) { return RMT_CLK_SRC_APB; } - return RMT_CLK_SRC_APB_F1M; + return RMT_CLK_SRC_REF_TICK; } static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) diff --git a/components/hal/esp32s2/include/hal/touch_sensor_hal.h b/components/hal/esp32s2/include/hal/touch_sensor_hal.h index 2f1629067f..5f0c266018 100644 --- a/components/hal/esp32s2/include/hal/touch_sensor_hal.h +++ b/components/hal/esp32s2/include/hal/touch_sensor_hal.h @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE diff --git a/components/hal/esp32s2/include/hal/touch_sensor_ll.h b/components/hal/esp32s2/include/hal/touch_sensor_ll.h index 30c3cc1014..450d0fb1f8 100644 --- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE diff --git a/components/hal/include/hal/touch_sensor_hal.h b/components/hal/include/hal/touch_sensor_hal.h index dc125c5bad..d2c28f88be 100644 --- a/components/hal/include/hal/touch_sensor_hal.h +++ b/components/hal/include/hal/touch_sensor_hal.h @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE diff --git a/components/soc/esp32/include/soc/clk_tree_defs.h b/components/soc/esp32/include/soc/clk_tree_defs.h index b641cde6f2..b1e149012e 100644 --- a/components/soc/esp32/include/soc/clk_tree_defs.h +++ b/components/soc/esp32/include/soc/clk_tree_defs.h @@ -38,6 +38,7 @@ extern "C" { /* With the default value of CK8M_DFREQ = 172, RC_FAST clock frequency is 8.5 MHz +/- 7% */ #define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 +/* With the default value of DCAP, range is +/- 5% */ #define SOC_CLK_RC_SLOW_FREQ_APPROX 150000 #define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 @@ -58,34 +59,37 @@ typedef enum { /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ - SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_APLL, /*!< Select APLL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_APLL = 3, /*!< Select APLL_CLK as CPU_CLK source */ } soc_cpu_clk_src_t; /** * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; /** - * @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.) + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) * Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] * {[upstream]clock_name}: APB, APLL, (BB)PLL, etc. * [attr] - optional: FAST, SLOW, D, F @@ -104,7 +108,7 @@ typedef enum { SOC_MOD_CLK_RC_FAST = 7, /*< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST_D256 = 8, /*< RC_FAST_D256_CLK comes from the internal 8MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL = 9, /*< XTAL_CLK comes from the external crystal (2~40MHz) */ - SOC_MOD_CLK_APB_F1M = 10, /*< APB_F1M_CLK (referred as REF_TICK in TRM) is derived from APB, it has a fixed frequency of 1MHz even when APB frequency changes */ + SOC_MOD_CLK_REF_TICK = 10, /*< REF_TICK is derived from APB, it has a fixed frequency of 1MHz even when APB frequency changes */ SOC_MOD_CLK_APLL = 11, /*< APLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */ } soc_module_clk_t; @@ -162,25 +166,25 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of RMT */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_APB_F1M} +#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_REF_TICK} /** * @brief Type of RMT clock source */ typedef enum { - RMT_CLK_SRC_NONE = 0, /*!< No clock source is selected */ - RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ - RMT_CLK_SRC_APB_F1M = SOC_MOD_CLK_APB_F1M, /*!< Select APB_F1M (a.k.a REF_TICK) as the source clock */ - RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ + RMT_CLK_SRC_NONE = 0, /*!< No clock source is selected */ + RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + RMT_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ } soc_periph_rmt_clk_src_t; /** * @brief Type of RMT clock source, reserved for the legacy RMT driver */ typedef enum { - RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB CLK */ - RMT_BASECLK_REF = SOC_MOD_CLK_APB_F1M, /*!< RMT source clock is APB_F1M */ - RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ + RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB CLK */ + RMT_BASECLK_REF = SOC_MOD_CLK_REF_TICK, /*!< RMT source clock is REF_TICK */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ } soc_periph_rmt_clk_src_legacy_t; //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// @@ -199,9 +203,9 @@ typedef enum { * @brief Type of UART clock source, reserved for the legacy UART driver */ typedef enum { - UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ - UART_SCLK_REF_TICK = SOC_MOD_CLK_APB_F1M, /*!< UART source clock is APB_F1M */ - UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ + UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ + UART_SCLK_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< UART source clock is REF_TICK */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ } soc_periph_uart_clk_src_legacy_t; #ifdef __cplusplus diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index 13b96d09e6..4a34733380 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -10,6 +10,7 @@ #include #include "soc/soc.h" #include "soc/rtc_periph.h" +#include "soc/clk_tree_defs.h" #define MHZ (1000000) @@ -58,57 +59,16 @@ typedef enum { RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL } rtc_xtal_freq_t; -/** - * @brief CPU frequency values - */ -typedef enum { - RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency - RTC_CPU_FREQ_80M = 1, //!< 80 MHz - RTC_CPU_FREQ_160M = 2, //!< 160 MHz - RTC_CPU_FREQ_240M = 3, //!< 240 MHz - RTC_CPU_FREQ_2M = 4, //!< 2 MHz -} rtc_cpu_freq_t; - -/** - * @brief CPU clock source - */ -typedef enum { - RTC_CPU_FREQ_SRC_XTAL, //!< XTAL - RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) - RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator - RTC_CPU_FREQ_SRC_APLL //!< APLL -} rtc_cpu_freq_src_t; - /** * @brief CPU clock configuration structure */ typedef struct rtc_cpu_freq_config_s { - rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived uint32_t source_freq_mhz; //!< Source clock frequency uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div uint32_t freq_mhz; //!< CPU clock frequency } rtc_cpu_freq_config_t; -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator - RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL - RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 -} rtc_slow_freq_t; - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef enum { - RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 - RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator -} rtc_fast_freq_t; - -/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - /** * @brief Clock source to be calibrated using rtc_clk_cal function */ @@ -122,13 +82,13 @@ typedef enum { * Initialization parameters for rtc_clk_init */ typedef struct rtc_clk_config_s { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set - rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set - uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose + uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -137,8 +97,8 @@ typedef struct rtc_clk_config_s { #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = RTC_XTAL_FREQ_AUTO, \ .cpu_freq_mhz = 80, \ - .fast_freq = RTC_FAST_FREQ_8M, \ - .slow_freq = RTC_SLOW_FREQ_RTC, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_8m_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ @@ -281,22 +241,22 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32 /** * @brief Select source for RTC_SLOW_CLK - * @param slow_freq clock source (one of rtc_slow_freq_t values) + * @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values) */ -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq); /** * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of rtc_slow_freq_t values) + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -rtc_slow_freq_t rtc_clk_slow_freq_get(void); +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 - * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 - * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~33000 * * rtc_clk_cal function can be used to get more precise value by comparing * RTC_SLOW_CLK frequency to the frequency of main XTAL. @@ -306,23 +266,21 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void); uint32_t rtc_clk_slow_freq_get_hz(void); /** - * @brief Select source for RTC_FAST_CLK - * @param fast_freq clock source (one of rtc_fast_freq_t values) + * @brief Alias of rtc_clk_slow_freq_get_hz */ -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values) + */ +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq); /** * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of rtc_fast_freq_t values) + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -rtc_fast_freq_t rtc_clk_fast_freq_get(void); - -/** - * @brief Get CPU frequency config corresponding to a rtc_cpu_freq_t value - * @param cpu_freq CPU frequency enumeration value - * @param[out] out_config Output, CPU frequency configuration structure - */ - void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config); +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); /** * @brief Get CPU frequency config for a given frequency diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h index e4b601822f..fe9f684513 100644 --- a/components/soc/esp32c2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h @@ -26,20 +26,19 @@ extern "C" { * This RC oscillator generates a ~150kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock * can be computed in runtime through calibration. * - * 4) External Slow Clock (optional): XTAL32K + * 4) External Slow Clock (optional): OSC_SLOW * - * A clock signal generated by an external circuit can be connected to the 32K_XN pin to be the clock source for the - * RTC_SLOW_CLK. In such case, a 1nF capacitor should be placed between the 32K_XN pin and ground, so the 32K_XP pin - * cannot be used as a GPIO pin. + * A clock signal generated by an external circuit with frequency no more than 150kHz can be connected to GPIO0 pin + * to be the clock source for the RTC_SLOW_CLK. * - * XTAL32K_CLK can also be calibrated to get its exact frequency. + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. */ /* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 #define SOC_CLK_RC_SLOW_FREQ_APPROX 150000 #define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) -#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /** * @brief Root clock @@ -52,38 +51,41 @@ typedef enum { SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8MHz RC oscillator */ SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 150kHz RC oscillator */ SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ - SOC_ROOT_CLK_EXT_XTAL32K, /*!< External ~32kHz clock signal */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at GPIO0 */ } soc_root_clk_t; /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ - SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ } soc_cpu_clk_src_t; /** * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 1, /*!< Select OSC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; /** - * @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.) + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) * Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] * {[upstream]clock_name}: (BB)PLL etc. * [attr] - optional: FAST, SLOW, D, F @@ -99,7 +101,7 @@ typedef enum { SOC_MOD_CLK_PLL_F40M = 4, /*< PLL_F40M_CLK is derived from PLL, and has a fixed frequency of 40MHz */ SOC_MOD_CLK_PLL_F60M = 5, /*< PLL_F60M_CLK is derived from PLL, and has a fixed frequency of 60MHz */ SOC_MOD_CLK_PLL_F80M = 6, /*< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */ - SOC_MOD_CLK_XTAL32K = 7, /*< XTAL32K_CLK comes from the external 32kHz clock signal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_OSC_SLOW = 7, /*< OSC_SLOW_CLK comes from an external slow clock signal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST = 8, /*< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST_D256 = 9, /*< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL = 10, /*< XTAL_CLK comes from the external 40MHz crystal */ diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h index 4d473d3595..268d3e7fb6 100644 --- a/components/soc/esp32c2/include/soc/rtc.h +++ b/components/soc/esp32c2/include/soc/rtc.h @@ -9,6 +9,7 @@ #include #include #include "soc/soc.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -49,10 +50,6 @@ extern "C" { #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_150K 150000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) -#define RTC_SLOW_CLK_FREQ_EXT 32768 - #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 @@ -134,45 +131,16 @@ typedef enum { RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; -/** - * @brief CPU clock source - */ -typedef enum { - RTC_CPU_FREQ_SRC_XTAL, //!< XTAL - RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M) - RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator -} rtc_cpu_freq_src_t; - /** * @brief CPU clock configuration structure */ typedef struct rtc_cpu_freq_config_s { - rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived uint32_t source_freq_mhz; //!< Source clock frequency uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div uint32_t freq_mhz; //!< CPU clock frequency } rtc_cpu_freq_config_t; -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator - RTC_SLOW_FREQ_EXT_CLK = 1, //!< External clock input by pin0 with frequency no more than 150k - RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 -} rtc_slow_freq_t; - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef enum { - RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 - RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator -} rtc_fast_freq_t; - -/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO @@ -184,21 +152,21 @@ typedef enum { typedef enum { RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 - RTC_CAL_EXT_CLK = 2 //!< External CLK + RTC_CAL_EXT_CLK = 2 //!< External CLK } rtc_cal_sel_t; /** * Initialization parameters for rtc_clk_init */ typedef struct { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set - rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose uint32_t clk_rtc_clk_div : 8; - uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -207,8 +175,8 @@ typedef struct { #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = RTC_XTAL_FREQ_40M, \ .cpu_freq_mhz = 80, \ - .fast_freq = RTC_FAST_FREQ_8M, \ - .slow_freq = RTC_SLOW_FREQ_RTC, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 0, \ .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ @@ -304,22 +272,22 @@ bool rtc_clk_8md256_enabled(void); /** * @brief Select source for RTC_SLOW_CLK - * @param slow_freq clock source (one of rtc_slow_freq_t values) + * @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values) */ -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq); /** * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of rtc_slow_freq_t values) + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -rtc_slow_freq_t rtc_clk_slow_freq_get(void); +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 - * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 - * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000 * * rtc_clk_cal function can be used to get more precise value by comparing * RTC_SLOW_CLK frequency to the frequency of main XTAL. @@ -330,15 +298,15 @@ uint32_t rtc_clk_slow_freq_get_hz(void); /** * @brief Select source for RTC_FAST_CLK - * @param fast_freq clock source (one of rtc_fast_freq_t values) + * @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values) */ -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq); /** * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of rtc_fast_freq_t values) + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -rtc_fast_freq_t rtc_clk_fast_freq_get(void); +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); /** * @brief Get CPU frequency config for a given frequency diff --git a/components/soc/esp32c3/include/soc/clk_tree_defs.h b/components/soc/esp32c3/include/soc/clk_tree_defs.h index 89e101a19e..48a9fbc5f4 100644 --- a/components/soc/esp32c3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c3/include/soc/clk_tree_defs.h @@ -58,33 +58,36 @@ typedef enum { /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ - SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ } soc_cpu_clk_src_t; /** * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; /** - * @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.) + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) * Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] * {[upstream]clock_name}: APB, (BB)PLL, etc. * [attr] - optional: FAST, SLOW, D, F diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 07b39a5431..18af6d27ff 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -9,6 +9,7 @@ #include #include #include "soc/soc.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -49,10 +50,6 @@ extern "C" { #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_150K 150000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 @@ -135,59 +132,16 @@ typedef enum { RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; -/** - * @brief CPU frequency values - */ -typedef enum { - RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency - RTC_CPU_FREQ_80M = 1, //!< 80 MHz - RTC_CPU_FREQ_160M = 2, //!< 160 MHz - RTC_CPU_FREQ_240M = 3, //!< 240 MHz - RTC_CPU_FREQ_2M = 4, //!< 2 MHz - RTC_CPU_320M_80M = 5, //!< for test - RTC_CPU_320M_160M = 6, //!< for test - RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset -} rtc_cpu_freq_t; - -/** - * @brief CPU clock source - */ -typedef enum { - RTC_CPU_FREQ_SRC_XTAL, //!< XTAL - RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) - RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator -} rtc_cpu_freq_src_t; - /** * @brief CPU clock configuration structure */ typedef struct rtc_cpu_freq_config_s { - rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived uint32_t source_freq_mhz; //!< Source clock frequency uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div uint32_t freq_mhz; //!< CPU clock frequency } rtc_cpu_freq_config_t; -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator - RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL - RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 -} rtc_slow_freq_t; - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef enum { - RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 - RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator -} rtc_fast_freq_t; - -/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO @@ -207,14 +161,14 @@ typedef enum { * Initialization parameters for rtc_clk_init */ typedef struct { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set - rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose uint32_t clk_rtc_clk_div : 8; - uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -223,8 +177,8 @@ typedef struct { #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = RTC_XTAL_FREQ_40M, \ .cpu_freq_mhz = 80, \ - .fast_freq = RTC_FAST_FREQ_8M, \ - .slow_freq = RTC_SLOW_FREQ_RTC, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 0, \ .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ @@ -363,22 +317,22 @@ bool rtc_clk_8md256_enabled(void); /** * @brief Select source for RTC_SLOW_CLK - * @param slow_freq clock source (one of rtc_slow_freq_t values) + * @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values) */ -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq); /** * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of rtc_slow_freq_t values) + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -rtc_slow_freq_t rtc_clk_slow_freq_get(void); +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 - * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 - * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000 * * rtc_clk_cal function can be used to get more precise value by comparing * RTC_SLOW_CLK frequency to the frequency of main XTAL. @@ -389,15 +343,15 @@ uint32_t rtc_clk_slow_freq_get_hz(void); /** * @brief Select source for RTC_FAST_CLK - * @param fast_freq clock source (one of rtc_fast_freq_t values) + * @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values) */ -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq); /** * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of rtc_fast_freq_t values) + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -rtc_fast_freq_t rtc_clk_fast_freq_get(void); +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); /** * @brief Get CPU frequency config for a given frequency diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index fac148f0b0..b981cec8b2 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -34,7 +34,7 @@ extern "C" { * * XTAL32K_CLK can also be calibrated to get its exact frequency. * - * 5) Internal 32kHz RC Oscillator: RC_32K + * 5) Internal 32kHz RC Oscillator: RC32K * * The exact frequency of this clock can be computed in runtime through calibration. */ @@ -45,7 +45,7 @@ extern "C" { #define SOC_CLK_RC_SLOW_FREQ_APPROX 130000 #define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /* With the default value of DFREQ = 707 */ //<---- DFREQ to be adjusted! -#define SOC_CLK_RC_32K_FREQ_APPROX 32768 +#define SOC_CLK_RC32K_FREQ_APPROX 32768 #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /** @@ -60,39 +60,42 @@ typedef enum { SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 150kHz RC oscillator */ SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */ SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */ - SOC_ROOT_CLK_INT_RC_32K /*!< Internal 32kHz RC oscillator */ + SOC_ROOT_CLK_INT_RC32K /*!< Internal 32kHz RC oscillator */ } soc_root_clk_t; /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */ - SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_XTAL_DIV, /*!< Select XTAL_D2_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL_D2 = 3, /*!< Select XTAL_D2_CLK as CPU_CLK source */ } soc_cpu_clk_src_t; /** * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC_32K, /*!< Select RC_32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; /** - * @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.) + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) * Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] * {[upstream]clock_name}: AHB etc. * [attr] - optional: FAST, SLOW, D, F @@ -103,7 +106,7 @@ typedef enum { SOC_MOD_CLK_CPU = 1, /*< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or XTAL_D2 by configuring soc_cpu_clk_src_t */ // For RTC domain SOC_MOD_CLK_RTC_FAST = 2, /*< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ - SOC_MOD_CLK_RTC_SLOW = 3, /*< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_32K by configuring soc_rtc_slow_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW = 3, /*< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */ // For digital domain: peripherals, WIFI, BLE SOC_MOD_CLK_AHB = 4, /*< AHB_CLK sources from CPU with a configurable divider */ SOC_MOD_CLK_XTAL32K = 5, /*< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index b5ca94a553..b02c736346 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -9,6 +9,7 @@ #include #include #include "soc/soc.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -49,10 +50,6 @@ extern "C" { #define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_150K 130000 -#define RTC_SLOW_CLK_FREQ_32K 32768 -#define RTC_SLOW_CLK_FREQ_RC32 32768 - #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 @@ -146,46 +143,16 @@ typedef enum { RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; -/** - * @brief CPU clock source - */ -typedef enum { - RTC_CPU_FREQ_SRC_XTAL, //!< XTAL - RTC_CPU_FREQ_SRC_PLL, //!< PLL (96M) - RTC_CPU_FREQ_SRC_8M, //!< Internal 18M RTC oscillator - RTC_CPU_FREQ_SRC_XTAL_D2 //!< XTAL/2 -} rtc_cpu_freq_src_t; - /** * @brief CPU clock configuration structure */ typedef struct rtc_cpu_freq_config_s { - rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived uint32_t source_freq_mhz; //!< Source clock frequency uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div uint32_t freq_mhz; //!< CPU clock frequency } rtc_cpu_freq_config_t; -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator - RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL - RTC_SLOW_FREQ_RC32K = 2, //!< Internal 32 KHz RC oscillator -} rtc_slow_freq_t; - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef enum { - RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 - RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator -} rtc_fast_freq_t; - -/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO @@ -204,15 +171,15 @@ typedef enum { * Initialization parameters for rtc_clk_init */ typedef struct { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set - rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose uint32_t clk_rtc_clk_div : 8; - uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) - uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M) + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) + uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M) } rtc_clk_config_t; /** @@ -221,8 +188,8 @@ typedef struct { #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = RTC_XTAL_FREQ_32M, \ .cpu_freq_mhz = 32, \ - .fast_freq = RTC_FAST_FREQ_8M, \ - .slow_freq = RTC_SLOW_FREQ_RTC, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 1, \ .clk_8m_clk_div = 1, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ @@ -339,6 +306,12 @@ bool rtc_clk_32k_enabled(void); */ void rtc_clk_32k_bootstrap(uint32_t cycle); +/** + * @brief Enable or disable 32 kHz internal rc oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_rc32k_enable(bool enable); + /** * @brief Enable or disable 8 MHz internal oscillator * @@ -371,22 +344,22 @@ bool rtc_clk_8md256_enabled(void); /** * @brief Select source for RTC_SLOW_CLK - * @param slow_freq clock source (one of rtc_slow_freq_t values) + * @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values) */ -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq); /** * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of rtc_slow_freq_t values) + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -rtc_slow_freq_t rtc_clk_slow_freq_get(void); +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 - * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 - * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~33000 * * rtc_clk_cal function can be used to get more precise value by comparing * RTC_SLOW_CLK frequency to the frequency of main XTAL. @@ -397,15 +370,15 @@ uint32_t rtc_clk_slow_freq_get_hz(void); /** * @brief Select source for RTC_FAST_CLK - * @param fast_freq clock source (one of rtc_fast_freq_t values) + * @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values) */ -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq); /** * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of rtc_fast_freq_t values) + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -rtc_fast_freq_t rtc_clk_fast_freq_get(void); +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); /** * @brief Get CPU frequency config for a given frequency diff --git a/components/soc/esp32s2/include/soc/clk_tree_defs.h b/components/soc/esp32s2/include/soc/clk_tree_defs.h index 86bcbbab19..4d63a2f008 100644 --- a/components/soc/esp32s2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s2/include/soc/clk_tree_defs.h @@ -58,34 +58,37 @@ typedef enum { /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ - SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_APLL, /*!< Select APLL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_APLL = 3, /*!< Select APLL_CLK as CPU_CLK source */ } soc_cpu_clk_src_t; /** * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; /** - * @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.) + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) * Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] * {[upstream]clock_name}: APB, APLL, (BB)PLL, etc. * [attr] - optional: FAST, SLOW, D, F @@ -104,7 +107,7 @@ typedef enum { SOC_MOD_CLK_RC_FAST = 7, /*< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST_D256 = 8, /*< RC_FAST_D256_CLK is derived from the internal 8MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL = 9, /*< XTAL_CLK comes from the external 40MHz crystal */ - SOC_MOD_CLK_APB_F1M = 10, /*< APB_F1M_CLK (referred as REF_TICK in TRM) is derived from APB, it has a fixed frequency of 1MHz even when APB frequency changes */ + SOC_MOD_CLK_REF_TICK = 10, /*< REF_TICK is derived from XTAL or RC_FAST via a divider, it has a fixed frequency of 1MHz by default */ SOC_MOD_CLK_APLL = 11, /*< APLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */ SOC_MOD_CLK_TEMP_SENSOR = 12, /*< TEMP_SENSOR_CLK comes directly from the internal 8MHz rc oscillator */ } soc_module_clk_t; @@ -165,25 +168,25 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of RMT */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_APB_F1M} +#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_REF_TICK} /** * @brief Type of RMT clock source */ typedef enum { - RMT_CLK_SRC_NONE = 0, /*!< No clock source is selected */ - RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ - RMT_CLK_SRC_APB_F1M = SOC_MOD_CLK_APB_F1M, /*!< Select APB_F1M (a.k.a REF_TICK) as the source clock */ - RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ + RMT_CLK_SRC_NONE = 0, /*!< No clock source is selected */ + RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + RMT_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ } soc_periph_rmt_clk_src_t; /** * @brief Type of RMT clock source, reserved for the legacy RMT driver */ typedef enum { - RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB CLK */ - RMT_BASECLK_REF = SOC_MOD_CLK_APB_F1M, /*!< RMT source clock is APB_F1M */ - RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ + RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB CLK */ + RMT_BASECLK_REF = SOC_MOD_CLK_REF_TICK, /*!< RMT source clock is REF_TICK */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ } soc_periph_rmt_clk_src_legacy_t; //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// @@ -207,9 +210,9 @@ typedef enum { * @brief Type of UART clock source, reserved for the legacy UART driver */ typedef enum { - UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ - UART_SCLK_REF_TICK = SOC_MOD_CLK_APB_F1M, /*!< UART source clock is APB_F1M */ - UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ + UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ + UART_SCLK_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< UART source clock is REF_TICK */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ } soc_periph_uart_clk_src_legacy_t; #ifdef __cplusplus diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 99cac34c07..ce07b0ebce 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -9,6 +9,7 @@ #include #include #include "soc/soc.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -49,10 +50,6 @@ extern "C" { #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_90K 90000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 @@ -145,60 +142,16 @@ typedef enum { */ #define RTC_XTAL_FREQ RTC_XTAL_FREQ_40M -/** - * @brief CPU frequency values - */ -typedef enum { - RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency - RTC_CPU_FREQ_80M = 1, //!< 80 MHz - RTC_CPU_FREQ_160M = 2, //!< 160 MHz - RTC_CPU_FREQ_240M = 3, //!< 240 MHz - RTC_CPU_FREQ_2M = 4, //!< 2 MHz - RTC_CPU_320M_80M = 5, //!< for test - RTC_CPU_320M_160M = 6, //!< for test - RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset -} rtc_cpu_freq_t; - -/** - * @brief CPU clock source - */ -typedef enum { - RTC_CPU_FREQ_SRC_XTAL, //!< XTAL - RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) - RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator - RTC_CPU_FREQ_SRC_APLL //!< APLL -} rtc_cpu_freq_src_t; - /** * @brief CPU clock configuration structure */ typedef struct rtc_cpu_freq_config_s { - rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived uint32_t source_freq_mhz; //!< Source clock frequency uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div uint32_t freq_mhz; //!< CPU clock frequency } rtc_cpu_freq_config_t; -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 90 kHz RC oscillator - RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL - RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 -} rtc_slow_freq_t; - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef enum { - RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 - RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator -} rtc_fast_freq_t; - -/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO @@ -218,14 +171,14 @@ typedef enum { * Initialization parameters for rtc_clk_init */ typedef struct { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set - rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose uint32_t clk_rtc_clk_div : 8; - uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 90k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 90k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -234,8 +187,8 @@ typedef struct { #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = RTC_XTAL_FREQ_40M, \ .cpu_freq_mhz = 80, \ - .fast_freq = RTC_FAST_FREQ_8M, \ - .slow_freq = RTC_SLOW_FREQ_RTC, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 0, \ .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ @@ -428,22 +381,22 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32 /** * @brief Select source for RTC_SLOW_CLK - * @param slow_freq clock source (one of rtc_slow_freq_t values) + * @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values) */ -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq); /** * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of rtc_slow_freq_t values) + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -rtc_slow_freq_t rtc_clk_slow_freq_get(void); +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~90000 - * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 - * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~90000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~33000 * * rtc_clk_cal function can be used to get more precise value by comparing * RTC_SLOW_CLK frequency to the frequency of main XTAL. @@ -454,15 +407,15 @@ uint32_t rtc_clk_slow_freq_get_hz(void); /** * @brief Select source for RTC_FAST_CLK - * @param fast_freq clock source (one of rtc_fast_freq_t values) + * @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values) */ -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq); /** * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of rtc_fast_freq_t values) + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -rtc_fast_freq_t rtc_clk_fast_freq_get(void); +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); /** * @brief Get CPU frequency config for a given frequency diff --git a/components/soc/esp32s3/include/soc/clk_tree_defs.h b/components/soc/esp32s3/include/soc/clk_tree_defs.h index ae98e5e4c6..90478bfc3e 100644 --- a/components/soc/esp32s3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s3/include/soc/clk_tree_defs.h @@ -58,33 +58,36 @@ typedef enum { /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ - SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ } soc_cpu_clk_src_t; /** * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; /** * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; /** - * @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.) + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) * Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] * {[upstream]clock_name}: APB, (BB)PLL, etc. * [attr] - optional: FAST, SLOW, D, F diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 730ab3eab1..2d7faa9d09 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -10,6 +10,7 @@ #include #include #include "soc/soc.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -50,10 +51,6 @@ extern "C" { #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_150K 150000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 @@ -135,59 +132,16 @@ typedef enum { RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; -/** - * @brief CPU frequency values - */ -typedef enum { - RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency - RTC_CPU_FREQ_80M = 1, //!< 80 MHz - RTC_CPU_FREQ_160M = 2, //!< 160 MHz - RTC_CPU_FREQ_240M = 3, //!< 240 MHz - RTC_CPU_FREQ_2M = 4, //!< 2 MHz - RTC_CPU_320M_80M = 5, //!< for test - RTC_CPU_320M_160M = 6, //!< for test - RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset -} rtc_cpu_freq_t; - -/** - * @brief CPU clock source - */ -typedef enum { - RTC_CPU_FREQ_SRC_XTAL, //!< XTAL - RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) - RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator -} rtc_cpu_freq_src_t; - /** * @brief CPU clock configuration structure */ typedef struct rtc_cpu_freq_config_s { - rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived uint32_t source_freq_mhz; //!< Source clock frequency uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div uint32_t freq_mhz; //!< CPU clock frequency } rtc_cpu_freq_config_t; -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator - RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL - RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 -} rtc_slow_freq_t; - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef enum { - RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 - RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator -} rtc_fast_freq_t; - -/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO @@ -207,14 +161,14 @@ typedef enum { * Initialization parameters for rtc_clk_init */ typedef struct { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set - rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose uint32_t clk_rtc_clk_div : 8; - uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -223,8 +177,8 @@ typedef struct { #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = RTC_XTAL_FREQ_40M, \ .cpu_freq_mhz = 80, \ - .fast_freq = RTC_FAST_FREQ_8M, \ - .slow_freq = RTC_SLOW_FREQ_RTC, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 0, \ .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ @@ -371,22 +325,22 @@ bool rtc_clk_8md256_enabled(void); /** * @brief Select source for RTC_SLOW_CLK - * @param slow_freq clock source (one of rtc_slow_freq_t values) + * @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values) */ -void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq); /** * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of rtc_slow_freq_t values) + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -rtc_slow_freq_t rtc_clk_slow_freq_get(void); +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 - * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 - * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000 * * rtc_clk_cal function can be used to get more precise value by comparing * RTC_SLOW_CLK frequency to the frequency of main XTAL. @@ -397,15 +351,15 @@ uint32_t rtc_clk_slow_freq_get_hz(void); /** * @brief Select source for RTC_FAST_CLK - * @param fast_freq clock source (one of rtc_fast_freq_t values) + * @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values) */ -void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq); /** * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of rtc_fast_freq_t values) + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -rtc_fast_freq_t rtc_clk_fast_freq_get(void); +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); /** * @brief Get CPU frequency config for a given frequency diff --git a/components/ulp/ulp_common/ulp_common.c b/components/ulp/ulp_common/ulp_common.c index bdf23b3e43..caa48115e8 100644 --- a/components/ulp/ulp_common/ulp_common.c +++ b/components/ulp/ulp_common/ulp_common.c @@ -39,13 +39,11 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us) REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t), SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles); #elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_x32k)) { + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 0d8b1b5517..ea5819b4a6 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -787,7 +787,6 @@ components/hal/esp32/include/hal/aes_ll.h components/hal/esp32/include/hal/can_hal.h components/hal/esp32/include/hal/can_types.h components/hal/esp32/include/hal/clk_gate_ll.h -components/hal/esp32/include/hal/dac_ll.h components/hal/esp32/include/hal/interrupt_controller_ll.h components/hal/esp32/include/hal/mpu_ll.h components/hal/esp32/include/hal/rtc_io_ll.h @@ -797,7 +796,6 @@ components/hal/esp32/include/hal/sigmadelta_ll.h components/hal/esp32/include/hal/soc_ll.h components/hal/esp32/include/hal/spi_flash_encrypted_ll.h components/hal/esp32/include/hal/touch_sensor_hal.h -components/hal/esp32/include/hal/touch_sensor_ll.h components/hal/esp32/include/hal/trace_ll.h components/hal/esp32/include/hal/uart_ll.h components/hal/esp32/interrupt_descriptor_table.c @@ -838,7 +836,6 @@ components/hal/esp32s2/include/hal/cp_dma_hal.h components/hal/esp32s2/include/hal/cp_dma_ll.h components/hal/esp32s2/include/hal/crypto_dma_ll.h components/hal/esp32s2/include/hal/dac_hal.h -components/hal/esp32s2/include/hal/dac_ll.h components/hal/esp32s2/include/hal/dedic_gpio_ll.h components/hal/esp32s2/include/hal/i2c_ll.h components/hal/esp32s2/include/hal/interrupt_controller_ll.h @@ -851,8 +848,6 @@ components/hal/esp32s2/include/hal/sigmadelta_ll.h components/hal/esp32s2/include/hal/soc_ll.h components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h components/hal/esp32s2/include/hal/systimer_ll.h -components/hal/esp32s2/include/hal/touch_sensor_hal.h -components/hal/esp32s2/include/hal/touch_sensor_ll.h components/hal/esp32s2/include/hal/trace_ll.h components/hal/esp32s2/include/hal/usb_ll.h components/hal/esp32s2/interrupt_descriptor_table.c @@ -896,7 +891,6 @@ components/hal/include/hal/spi_slave_hal.h components/hal/include/hal/spi_slave_hd_hal.h components/hal/include/hal/systimer_hal.h components/hal/include/hal/systimer_types.h -components/hal/include/hal/touch_sensor_hal.h components/hal/include/hal/twai_types.h components/hal/include/hal/uhci_types.h components/hal/include/hal/usb_hal.h diff --git a/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c b/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c index 81bbdd78c1..35903c6421 100644 --- a/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c +++ b/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c @@ -77,7 +77,7 @@ void ref_clock_init(void) // Initialize RMT rmt_tx_channel_config_t tx_chan_config = { - .clk_src = RMT_CLK_SRC_APB_F1M, // REF_TICK clock source + .clk_src = RMT_CLK_SRC_REF_TICK, // REF_TICK clock source .gpio_num = REF_CLOCK_GPIO, .mem_block_symbols = 64, .resolution_hz = 10000, // channel resolution doesn't really matter, because we only utilize the carrier