From 8a5b5610b933449e91ecb890bd310818985a8c69 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 11 Apr 2023 12:59:20 +0800 Subject: [PATCH] ulp-riscv: enable ULP-RISCV ADC example for esp32s2 ADC can now be used from the ULP-RISCV on S2 after the RTC power parameters were fixed in a624d8d0619de8d3 Closes https://github.com/espressif/esp-idf/issues/11052 Closes https://github.com/espressif/esp-idf/issues/11040 --- examples/system/.build-test-rules.yml | 2 +- examples/system/ulp_riscv/adc/README.md | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 38ed5bb74d..bf2b8f4771 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -187,7 +187,7 @@ examples/system/ulp_fsm/ulp_adc: examples/system/ulp_riscv/adc: enable: - - if: IDF_TARGET in ["esp32s3"] + - if: IDF_TARGET in ["esp32s2", "esp32s3"] temporary: true reason: the other targets are not tested yet diff --git a/examples/system/ulp_riscv/adc/README.md b/examples/system/ulp_riscv/adc/README.md index 5344d54504..a875063982 100644 --- a/examples/system/ulp_riscv/adc/README.md +++ b/examples/system/ulp_riscv/adc/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-S3 | -| ----------------- | -------- | +| Supported Targets | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | # ULP-RISC-V ADC Example