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Merge branch 'feature/update_intr_wdt_for_freertos_smp' into 'master'
esp_system: Fix SMP FreeRTOS INT WDT and tidy up Closes IDF-4749 See merge request espressif/esp-idf!18000
This commit is contained in:
Darian
commit
a4c4d8c59b
@ -1,67 +0,0 @@
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __ESP_INT_WDT_H
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#define __ESP_INT_WDT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Watchdog_APIs
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* @{
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*/
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/*
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This routine enables a watchdog to catch instances of processes disabling
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interrupts for too long, or code within interrupt handlers taking too long.
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It does this by setting up a watchdog which gets fed from the FreeRTOS
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task switch interrupt. When this watchdog times out, initially it will call
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a high-level interrupt routine that will panic FreeRTOS in order to allow
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for forensic examination of the state of the both CPUs. When this interrupt
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handler is not called and the watchdog times out a second time, it will
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reset the SoC.
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This uses the TIMERG1 WDT.
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*/
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/**
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* @brief Initialize the non-CPU-specific parts of interrupt watchdog.
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* This is called in the init code if the interrupt watchdog
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* is enabled in menuconfig.
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*
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*/
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void esp_int_wdt_init(void);
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/**
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* @brief Enable the interrupt watchdog on the current CPU. This is called
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* in the init code by both CPUs if the interrupt watchdog is enabled
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* in menuconfig.
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*
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*/
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void esp_int_wdt_cpu_init(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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33
components/esp_system/include/esp_private/esp_int_wdt.h
Normal file
33
components/esp_system/include/esp_private/esp_int_wdt.h
Normal file
@ -0,0 +1,33 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Initialize the non-CPU-specific parts of interrupt watchdog.
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*
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* This function is automatically called during application startup if the
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* interrupt watchdog is enabled in menuconfig.
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*/
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void esp_int_wdt_init(void);
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/**
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* @brief Enable the interrupt watchdog on the current CPU.
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*
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* This function is automatically called during application startup for each CPU
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* that has enabled the interrupt watchdog in menuconfig.
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*
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* @note esp_int_wdt_init() must be called first before calling this function
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*/
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void esp_int_wdt_cpu_init(void);
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#ifdef __cplusplus
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}
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#endif
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@ -6,35 +6,31 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_types.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_chip_info.h"
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#include "esp_freertos_hooks.h"
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#include "soc/timer_periph.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_int_wdt.h"
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#include "esp_private/system_internal.h"
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#include "soc/soc_caps.h"
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#include "hal/cpu_hal.h"
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#include "hal/timer_types.h"
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#include "hal/wdt_hal.h"
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#include "hal/interrupt_controller_hal.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "esp_chip_info.h"
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#include "esp_freertos_hooks.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_int_wdt.h"
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#include "esp_private/system_internal.h"
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#if CONFIG_ESP_INT_WDT
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#define WDT_INT_NUM ETS_T1_WDT_INUM
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#define IWDT_INSTANCE WDT_MWDT1
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#define IWDT_PRESCALER MWDT1_TICK_PRESCALER //Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_PRESCALER MWDT1_TICK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_TICKS_PER_US MWDT1_TICKS_PER_US
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#define IWDT_INITIAL_TIMEOUT_S 5
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static wdt_hal_context_t iwdt_context;
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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@ -43,83 +39,74 @@ static wdt_hal_context_t iwdt_context;
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* identify the live lock.
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*/
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#define IWDT_LIVELOCK_TIMEOUT_MS (20)
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extern uint32_t _lx_intr_livelock_counter, _lx_intr_livelock_max;
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#endif
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//Take care: the tick hook can also be called before esp_int_wdt_init() is called.
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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//Not static; the ISR assembly checks this.
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bool int_wdt_app_cpu_ticked = false;
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volatile bool int_wdt_cpu1_ticked = false;
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#endif
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static void IRAM_ATTR tick_hook(void)
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{
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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if (cpu_hal_get_core_id() != 0) {
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int_wdt_app_cpu_ticked = true;
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int_wdt_cpu1_ticked = true;
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} else {
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//Only feed wdt if app cpu also ticked.
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if (int_wdt_app_cpu_ticked) {
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//Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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// Only feed wdt if app cpu also ticked.
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if (int_wdt_cpu1_ticked) {
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// Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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wdt_hal_write_protect_disable(&iwdt_context);
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//Reconfigure stage timeouts
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// Reconfigure stage timeouts
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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_lx_intr_livelock_counter = 0;
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0,
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CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US / (_lx_intr_livelock_max + 1), WDT_STAGE_ACTION_INT); //Set timeout before interrupt
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CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US / (_lx_intr_livelock_max + 1), WDT_STAGE_ACTION_INT); // Set timeout before interrupt
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#else
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); // Set timeout before interrupt
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#endif
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); // Set timeout before reset
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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int_wdt_app_cpu_ticked = false;
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int_wdt_cpu1_ticked = false;
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}
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}
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}
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#else
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static void IRAM_ATTR tick_hook(void)
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{
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#if !CONFIG_FREERTOS_UNICORE
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#else // CONFIG_ESP_INT_WDT_CHECK_CPU1
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if (cpu_hal_get_core_id() != 0) {
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return;
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}
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#endif
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//Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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} else {
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// Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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wdt_hal_write_protect_disable(&iwdt_context);
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//Reconfigure stage timeouts
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
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// Reconfigure stage timeouts
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); // Set timeout before interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); // Set timeout before reset
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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}
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#endif // CONFIG_ESP_INT_WDT_CHECK_CPU1
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}
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#endif
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void esp_int_wdt_init(void)
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{
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periph_module_enable(PERIPH_TIMG1_MODULE);
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//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
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//it to their actual value.
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/*
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* Initialize the WDT timeout stages. Note that the initial timeout is set to 5 seconds as variable startup times of
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* each CPU can lead to a timeout. The tick hooks will set the WDT timers to the actual timeout.
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* Todo: Fix this
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*/
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wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
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wdt_hal_write_protect_disable(&iwdt_context);
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//1st stage timeout: interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
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//2nd stage timeout: reset system
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);
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//Enable WDT
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wdt_hal_enable(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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#define APB_DCRSET (0x200c)
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#define APB_ITCTRL (0x3f00)
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#define ERI_ADDR(APB) (0x100000 + (APB))
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#define _SYM2STR(x) # x
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#define SYM2STR(x) _SYM2STR(x)
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#define APB_DCRSET (0x200c)
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#define APB_ITCTRL (0x3f00)
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#define ERI_ADDR(APB) (0x100000 + (APB))
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#define _SYM2STR(x) # x
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#define SYM2STR(x) _SYM2STR(x)
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uint32_t eriadrs, scratch = 0, immediate = 0;
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if (soc_has_cache_lock_bug()) {
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if (xPortGetCoreID() != CONFIG_BTDM_CTRL_PINNED_TO_CORE) {
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@ -140,25 +127,25 @@ void esp_int_wdt_init(void)
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);
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}
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}
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#endif
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#endif // (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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}
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void esp_int_wdt_cpu_init(void)
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{
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assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!");
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esp_register_freertos_tick_hook_for_cpu(tick_hook, cpu_hal_get_core_id());
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ESP_INTR_DISABLE(WDT_INT_NUM);
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#if SOC_TIMER_GROUPS > 1
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assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to be at least twice the RTOS tick period!");
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// Register tick hook for current CPU to feed the INT WDT
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esp_register_freertos_tick_hook_for_cpu(tick_hook, cpu_hal_get_core_id());
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/*
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* Register INT WDT interrupt for current CPU. We do this manually as the timeout interrupt should call an assembly
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* panic handler (see riscv/vector.S and xtensa_vectors.S).
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*/
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esp_intr_disable_source(WDT_INT_NUM);
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esp_rom_route_intr_matrix(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
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#endif
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/* Set the type and priority to watch dog interrupts */
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#if SOC_CPU_HAS_FLEXIBLE_INTC
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interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
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interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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#endif
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/*
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* This is a workaround for issue 3.15 in "ESP32 ECO and workarounds for
|
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@ -171,11 +158,11 @@ void esp_int_wdt_cpu_init(void)
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_lx_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS / IWDT_LIVELOCK_TIMEOUT_MS - 1;
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}
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#endif
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// We do not register a handler for the watchdog interrupt because:
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// 1. Interrupt level 4 on Xtensa architecture is not servicable from C
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// 2. Instead, we set the entry of watchdog interrupt to the panic handler, see riscv/vector.S and xtensa_vectors.S
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ESP_INTR_ENABLE(WDT_INT_NUM);
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esp_intr_enable_source(WDT_INT_NUM);
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#else // SOC_TIMER_GROUPS > 1
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// TODO: Clean up code for ESP32-C2, IDF-4114
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ESP_EARLY_LOGW("INT_WDT", "ESP32-C2 only has one timer group");
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#endif // SOC_TIMER_GROUPS > 1
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}
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#endif
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#endif // CONFIG_ESP_INT_WDT
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@ -259,7 +259,7 @@ xt_highintx:
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#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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/* Check if the cause is the app cpu failing to tick.*/
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movi a0, int_wdt_app_cpu_ticked
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movi a0, int_wdt_cpu1_ticked
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
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|
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@ -1,16 +1,8 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#include <xtensa/coreasm.h>
|
||||
@ -92,7 +84,7 @@ xt_highint4:
|
||||
1:
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||||
#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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/* Check if the cause is the app cpu failing to tick.*/
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||||
movi a0, int_wdt_app_cpu_ticked
|
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movi a0, int_wdt_cpu1_ticked
|
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
|
||||
|
||||
@ -198,7 +198,11 @@ This file get's pulled into assembly sources. Therefore, some includes need to b
|
||||
#else
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#endif
|
||||
#if CONFIG_FREERTOS_USE_TICK_HOOK
|
||||
#define configUSE_TICK_HOOK 1
|
||||
#else
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#endif
|
||||
#if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 0
|
||||
#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL
|
||||
|
||||
@ -17,17 +17,17 @@
|
||||
#include "xtensa/config/core.h"
|
||||
#include "xtensa/config/core-isa.h"
|
||||
#include "xtensa/xtruntime.h"
|
||||
#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
|
||||
#include "esp_private/esp_int_wdt.h"
|
||||
#include "esp_heap_caps.h"
|
||||
#include "esp_system.h"
|
||||
#include "esp_task.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp_int_wdt.h"
|
||||
#include "esp_task_wdt.h"
|
||||
#include "esp_heap_caps_init.h"
|
||||
#include "esp_freertos_hooks.h"
|
||||
#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
|
||||
#include "esp32/spiram.h" /* Required by esp_spiram_reserve_dma_pool() */
|
||||
#ifdef CONFIG_APPTRACE_ENABLE
|
||||
#include "esp_app_trace.h"
|
||||
@ -620,15 +620,14 @@ BaseType_t xPortSysTickHandler(void)
|
||||
portbenchmarkIntLatency();
|
||||
traceISR_ENTER(SYSTICK_INTR_ID);
|
||||
BaseType_t ret;
|
||||
esp_vApplicationTickHook();
|
||||
if (portGET_CORE_ID() == 0) {
|
||||
//Only Core 0 calls xTaskIncrementTick();
|
||||
// FreeRTOS SMP requires that only core 0 calls xTaskIncrementTick()
|
||||
ret = xTaskIncrementTick();
|
||||
} else {
|
||||
//Manually call the IDF tick hooks
|
||||
esp_vApplicationTickHook();
|
||||
ret = pdFALSE;
|
||||
}
|
||||
if(ret != pdFALSE) {
|
||||
if (ret != pdFALSE) {
|
||||
portYIELD_FROM_ISR();
|
||||
} else {
|
||||
traceISR_EXIT();
|
||||
@ -657,13 +656,6 @@ void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, c
|
||||
}
|
||||
#endif
|
||||
|
||||
#if ( configUSE_TICK_HOOK > 0 )
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
esp_vApplicationTickHook();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK
|
||||
/*
|
||||
By default, the port uses vApplicationMinimalIdleHook() to run IDF style idle
|
||||
|
||||
@ -8,9 +8,9 @@
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "portmacro.h"
|
||||
#include "esp_private/esp_int_wdt.h"
|
||||
#include "esp_system.h"
|
||||
#include "esp_heap_caps_init.h"
|
||||
#include "esp_int_wdt.h"
|
||||
#include "esp_task_wdt.h"
|
||||
#include "esp_task.h"
|
||||
#include "esp_private/crosscore_int.h"
|
||||
|
||||
@ -65,9 +65,9 @@
|
||||
#include <xtensa/xtensa_context.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "esp_private/crosscore_int.h"
|
||||
#include "esp_private/esp_int_wdt.h"
|
||||
#include "esp_system.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_int_wdt.h"
|
||||
#ifdef CONFIG_APPTRACE_ENABLE
|
||||
#include "esp_app_trace.h" /* Required for esp_apptrace_init. [refactor-todo] */
|
||||
#endif
|
||||
|
||||
@ -126,7 +126,6 @@ INPUT = \
|
||||
$(PROJECT_PATH)/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h \
|
||||
$(PROJECT_PATH)/components/esp_system/include/esp_expression_with_stack.h \
|
||||
$(PROJECT_PATH)/components/esp_system/include/esp_freertos_hooks.h \
|
||||
$(PROJECT_PATH)/components/esp_system/include/esp_int_wdt.h \
|
||||
$(PROJECT_PATH)/components/esp_system/include/esp_system.h \
|
||||
$(PROJECT_PATH)/components/esp_system/include/esp_task_wdt.h \
|
||||
$(PROJECT_PATH)/components/esp_timer/include/esp_timer.h \
|
||||
|
||||
@ -6,24 +6,44 @@ Overview
|
||||
|
||||
The ESP-IDF has support for multiple types of watchdogs, with the two main ones being: The Interrupt Watchdog Timer and the Task Watchdog Timer (TWDT). The Interrupt Watchdog Timer and the TWDT can both be enabled using :ref:`project-configuration-menu`, however the TWDT can also be enabled during runtime. The Interrupt Watchdog is responsible for detecting instances where FreeRTOS task switching is blocked for a prolonged period of time. The TWDT is responsible for detecting instances of tasks running without yielding for a prolonged period.
|
||||
|
||||
Interrupt watchdog
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
ESP-IDF has support for the following types of watchdog timers:
|
||||
|
||||
The interrupt watchdog makes sure the FreeRTOS task switching interrupt isn't blocked for a long time. This is bad because no other tasks, including potentially important ones like the WiFi task and the idle task, can't get any CPU runtime. A blocked task switching interrupt can happen because a program runs into an infinite loop with interrupts disabled or hangs in an interrupt.
|
||||
.. list::
|
||||
|
||||
The default action of the interrupt watchdog is to invoke the panic handler causing a register dump and an opportunity for the programmer to find out, using either OpenOCD or gdbstub, what bit of code is stuck with interrupts disabled. Depending on the configuration of the panic handler, it can also blindly reset the CPU, which may be preferred in a production environment.
|
||||
- Interrupt Watchdog Timer (IWDT)
|
||||
- Task Watchdog Timer (TWDT)
|
||||
:SOC_XT_WDT_SUPPORTED: - Crystal 32K Watchdog Timer (XTWDT)
|
||||
|
||||
The interrupt watchdog is built around the hardware watchdog in timer group 1. If this watchdog for some reason cannot execute the NMI handler that invokes the panic handler (e.g. because IRAM is overwritten by garbage), it will hard-reset the SOC. If the panic handler executes, it will display the panic reason as "Interrupt wdt timeout on CPU0" or "Interrupt wdt timeout on CPU1" (as applicable).
|
||||
The various watchdog timers can be enabled using the :ref:`project-configuration-menu`. However, the TWDT can also be enabled during runtime.
|
||||
|
||||
Interrupt Watchdog Timer (IWDT)
|
||||
-------------------------------
|
||||
|
||||
The purpose of the IWDT is to ensure that interrupt service routines (ISRs) are not blocked from running for a prolonged period of time (i.e., the IWDT timeout period). Blocking ISRs from running in a timely manner is undesirable as it can increases ISR latency, and also prevents task switching (as task switching is executed form an ISR). The things that can block ISRs from running include:
|
||||
|
||||
- Disabling interrupts
|
||||
- Critical Sections (also disables interrupts)
|
||||
- Other same/higher priority ISRs (will block same/lower priority ISRs from running it completes execution)
|
||||
|
||||
The IWDT utilizes the watchdog timer in Timer Group 1 as its underlying hardware timer and leverages the FreeRTOS tick interrupt on each CPU to feed the watchdog timer. If the tick interrupt on a particular CPU is not run at within the IWDT timeout period, it is indicative that something is blocking ISRs from being run on that CPU (see the list of reasons above).
|
||||
|
||||
When the IWDT times out, the default action is to invoke the panic handler and display the panic reason as ``Interrupt wdt timeout on CPU0`` or ``Interrupt wdt timeout on CPU1`` (as applicable). Depending on the panic handler's configured behavior (see :ref:`CONFIG_ESP_SYSTEM_PANIC`), users can then debug the source of the IWDT timeout (via the backtrace, OpenOCD, gdbstub etc) or simply reset the chip (which may be preferred in a production environment).
|
||||
|
||||
If for whatever reason the panic handler is unable to run after an IWDT timeout, the IWDT has a secondary timeout that will hard-reset the chip (i.e., a system reset).
|
||||
|
||||
Configuration
|
||||
"""""""""""""
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
The interrupt watchdog is enabled by default via the :ref:`CONFIG_ESP_INT_WDT` configuration flag. The timeout is configured by setting :ref:`CONFIG_ESP_INT_WDT_TIMEOUT_MS`. The default timeout is higher if PSRAM support is enabled, as a critical section or interrupt routine that accesses a large amount of PSRAM will take longer to complete in some circumstances. The INT WDT timeout should always be longer than the period between FreeRTOS ticks (see :ref:`CONFIG_FREERTOS_HZ`).
|
||||
- The IWDT is enabled by default via the :ref:`CONFIG_ESP_INT_WDT` option.
|
||||
- The IWDT's timeout is configured by setting the :ref:`CONFIG_ESP_INT_WDT_TIMEOUT_MS` option.
|
||||
|
||||
- Note that the default timeout is higher if PSRAM support is enabled, as a critical section or interrupt routine that accesses a large amount of PSRAM will take longer to complete in some circumstances.
|
||||
- The timeout should always at least twice longer than the period between FreeRTOS ticks (see :ref:`CONFIG_FREERTOS_HZ`).
|
||||
|
||||
Tuning
|
||||
""""""
|
||||
^^^^^^
|
||||
|
||||
If you find the Interrupt watchdog timeout is triggered because an interrupt or critical section is running longer than the timeout period, consider rewriting the code:
|
||||
If you find the IWDT timeout is triggered because an interrupt or critical section is running longer than the timeout period, consider rewriting the code:
|
||||
|
||||
- Critical sections should be made as short as possible. Any non-critical code/computation should be placed outside the critical section.
|
||||
- Interrupt handlers should also perform the minimum possible amount of computation. Users can consider deferring any computation to a task by having the ISR push data to a task using queues.
|
||||
@ -32,8 +52,8 @@ Neither critical sections or interrupt handlers should ever block waiting for an
|
||||
|
||||
.. _task-watchdog-timer:
|
||||
|
||||
Task Watchdog Timer
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
Task Watchdog Timer (TWDT)
|
||||
--------------------------
|
||||
|
||||
{IDF_TARGET_IDLE_TASKS:default="Idle task", esp32="Idle Tasks of each CPU"}
|
||||
|
||||
@ -42,7 +62,7 @@ The Task Watchdog Timer (TWDT) is used to monitor particular tasks, ensuring tha
|
||||
The TWDT is built around the Hardware Watchdog Timer in Timer Group 0. When a timeout occurs, an interrupt is triggered. Users can redefine the function `esp_task_wdt_isr_user_handler` in the user code, in order to receive the timeout event and handle it differently.
|
||||
|
||||
Usage
|
||||
"""""
|
||||
^^^^^
|
||||
|
||||
The following functions can be used to watch tasks using the TWDT:
|
||||
|
||||
@ -60,7 +80,7 @@ In the case where applications need to watch at a more granular level (i.e., ens
|
||||
- :cpp:func:`esp_task_wdt_delete_user` unsubscribes an arbitrary user of the TWDT.
|
||||
|
||||
Configuration
|
||||
"""""""""""""
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
The default timeout period for the TWDT is set using config item :ref:`CONFIG_ESP_TASK_WDT_TIMEOUT_S`. This should be set to at least as long as you expect any single task will need to monopolize the CPU (for example, if you expect the app will do a long intensive calculation and should not yield to other tasks). It is also possible to change this timeout at runtime by calling :cpp:func:`esp_task_wdt_init`.
|
||||
|
||||
@ -83,47 +103,36 @@ The following config options control TWDT configuration at startup. They are all
|
||||
- :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0` - {IDF_TARGET_IDLE_TASK} is subscribed to the TWDT during startup. If this option is disabled, it is still possible to subscribe the idle task by calling :cpp:func:`esp_task_wdt_init` again.
|
||||
:not CONFIG_FREERTOS_UNICORE: - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` - CPU1 Idle task is subscribed to the TWDT during startup.
|
||||
|
||||
|
||||
JTAG and watchdogs
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
While debugging using OpenOCD, the CPUs will be halted every time a breakpoint is reached. However if the watchdog timers continue to run when a breakpoint is encountered, they will eventually trigger a reset making it very difficult to debug code. Therefore OpenOCD will disable the hardware timers of both the interrupt and task watchdogs at every breakpoint. Moreover, OpenOCD will not reenable them upon leaving the breakpoint. This means that interrupt watchdog and task watchdog functionality will essentially be disabled. No warnings or panics from either watchdogs will be generated when the {IDF_TARGET_NAME} is connected to OpenOCD via JTAG.
|
||||
|
||||
|
||||
.. only:: SOC_XT_WDT_SUPPORTED
|
||||
|
||||
XTAL32K Watchdog Timer (XTWDT)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
------------------------------
|
||||
|
||||
The XTAL32K watchdog makes sure the (optional) external 32 KHz crystal or oscillator is functioning correctly.
|
||||
One of the optional clock inputs to the {IDF_TARGET_NAME} is an external 32 KHz crystal or oscillator (XTAL32K) that is used as a clock source (``XTAL32K_CLK``) to various subsystems (such as the RTC).
|
||||
|
||||
When `XTAL32K_CLK` works as the clock source of `RTC_SLOW_CLK` and stops oscillating, the XTAL32K watchdog timer will detect this and generate an interrupt. It also provides functionality for automatically switching over to the internal, but less accurate oscillator as the `RTC_SLOW_CLK` source.
|
||||
The XTWDT is a dedicated watchdog timer used to ensure that the XTAL32K is functioning correctly. When ``XTAL32K_CLK`` works as the clock source of ``RTC_SLOW_CLK`` and stops oscillating, the XTWDT will detect this and generate an interrupt. It also provides functionality for automatically switching over to the internal, but less accurate oscillator as the `RTC_SLOW_CLK` source.
|
||||
|
||||
Since the switch to the backup clock is done in hardware it can also happen during deep sleep. This means that even if `XTAL32K_CLK` stops functioning while the chip in deep sleep, waiting for a timer to expire, it will still be able to wake-up as planned.
|
||||
Since the switch to the backup clock is done in hardware it can also happen during deep sleep. This means that even if ``XTAL32K_CLK`` stops functioning while the chip in deep sleep, waiting for a timer to expire, it will still be able to wake-up as planned.
|
||||
|
||||
If the `XTAL32K_CLK` starts functioning normally again, you can call `esp_xt_wdt_restore_clk` to switch back to this clock source and re-enable the watchdog timer.
|
||||
If the ``XTAL32K_CLK`` starts functioning normally again, you can call ``esp_xt_wdt_restore_clk`` to switch back to this clock source and re-enable the watchdog timer.
|
||||
|
||||
Configuration
|
||||
"""""""""""""
|
||||
|
||||
When the external 32KHz crystal or oscillator is selected (:ref:`CONFIG_RTC_CLK_SRC`) the XTAL32K watchdog can be enabled via the :ref:`CONFIG_ESP_XT_WDT` configuration flag. The timeout is configured by setting :ref:`CONFIG_ESP_XT_WDT_TIMEOUT`. The automatic backup clock functionality is enabled via the ref:`CONFIG_ESP_XT_WDT_BACKUP_CLK_ENABLE` configuration.
|
||||
- When the external 32KHz crystal or oscillator is selected (:ref:`CONFIG_RTC_CLK_SRC`) the XTWDT can be enabled via the :ref:`CONFIG_ESP_XT_WDT` configuration option.
|
||||
- The timeout is configured by setting the :ref:`CONFIG_ESP_XT_WDT_TIMEOUT` option.
|
||||
- The automatic backup clock functionality is enabled via the ref:`CONFIG_ESP_XT_WDT_BACKUP_CLK_ENABLE` configuration option.
|
||||
|
||||
Interrupt Watchdog API Reference
|
||||
--------------------------------
|
||||
JTAG & Watchdogs
|
||||
----------------
|
||||
|
||||
Header File
|
||||
^^^^^^^^^^^
|
||||
While debugging using OpenOCD, the CPUs will be halted every time a breakpoint is reached. However if the watchdog timers continue to run when a breakpoint is encountered, they will eventually trigger a reset making it very difficult to debug code. Therefore OpenOCD will disable the hardware timers of both the interrupt and task watchdogs at every breakpoint. Moreover, OpenOCD will not reenable them upon leaving the breakpoint. This means that interrupt watchdog and task watchdog functionality will essentially be disabled. No warnings or panics from either watchdogs will be generated when the {IDF_TARGET_NAME} is connected to OpenOCD via JTAG.
|
||||
|
||||
* :component_file:`esp_system/include/esp_int_wdt.h`
|
||||
API Reference
|
||||
-------------
|
||||
|
||||
|
||||
Functions
|
||||
---------
|
||||
|
||||
.. doxygenfunction:: esp_int_wdt_init
|
||||
|
||||
Task Watchdog API Reference
|
||||
----------------------------
|
||||
Task Watchdog
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
A full example using the Task Watchdog is available in esp-idf: :example:`system/task_watchdog`
|
||||
|
||||
|
||||
@ -60,6 +60,7 @@ ESP System
|
||||
----------
|
||||
- The header files ``esp_random.h``, ``esp_mac.h`` and ``esp_chip_info.h``, which were all previously indirectly included via the header file ``esp_system.h``, must now be included directly. These headers are removed from ``esp_system.h``.
|
||||
- The header file ``eh_frame_parser.h`` must now be included with a ``esp_private`` prefix like ``#include "esp_private/eh_frame_parser.h"``.
|
||||
- The header file ``esp_int_wdt.h`` must now be included with a ``esp_private`` prefix like ``#include "esp_private/esp_int_wdt.h"``.
|
||||
|
||||
SOC dependency
|
||||
--------------
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user