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Merge branch 'bugfix/spi_clk_rc_fast_enable_disable' into 'master'
spi_master: fix clock source RC_FAST usage See merge request espressif/esp-idf!22160
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commit
a49164b5ec
@ -175,6 +175,7 @@ typedef struct spi_device_t *spi_device_handle_t; ///< Handle for a device on a
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* @return
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* - ESP_ERR_INVALID_ARG if parameter is invalid or configuration combination is not supported (e.g.
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* `dev_config->post_cb` isn't set while flag `SPI_DEVICE_NO_RETURN_RESULT` is enabled)
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* - ESP_ERR_INVALID_STATE if selected clock source is unavailable or spi bus not initialized
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* - ESP_ERR_NOT_FOUND if host doesn't have any free CS slots
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* - ESP_ERR_NO_MEM if out of memory
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* - ESP_OK on success
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@ -75,3 +75,8 @@ esp_err_t spi_slave_queue_reset_isr(spi_host_device_t host);
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* - ESP_OK on success
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*/
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esp_err_t spi_slave_queue_trans_isr(spi_host_device_t host, const spi_slave_transaction_t *trans_desc);
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#ifdef __cplusplus
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}
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#endif
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@ -114,6 +114,7 @@ We have two bits to control the interrupt:
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#include "esp_private/spi_common_internal.h"
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#include "driver/spi_master.h"
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#include "clk_tree.h"
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#include "clk_ctrl_os.h"
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#include "esp_log.h"
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#include "esp_ipc.h"
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#include "freertos/task.h"
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@ -355,6 +356,11 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
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spi_host_t *host = bus_driver_ctx[host_id];
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const spi_bus_attr_t* bus_attr = host->bus_attr;
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SPI_CHECK(dev_config->spics_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(dev_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG);
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#if SOC_SPI_SUPPORT_CLK_RC_FAST
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if (dev_config->clock_source == SPI_CLK_SRC_RC_FAST) {
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SPI_CHECK(periph_rtc_dig_clk8m_enable(), "the selected clock not available", ESP_ERR_INVALID_STATE);
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}
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#endif
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spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
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uint32_t clock_source_hz = 0;
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if (dev_config->clock_source) {
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@ -495,6 +501,12 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
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SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
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}
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#if SOC_SPI_SUPPORT_CLK_RC_FAST
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if (handle->cfg.clock_source == SPI_CLK_SRC_RC_FAST) {
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periph_rtc_dig_clk8m_disable();
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}
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#endif
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//return
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int spics_io_num = handle->cfg.spics_io_num;
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if (spics_io_num >= 0) spicommon_cs_free_io(spics_io_num);
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@ -57,7 +57,9 @@ static void check_spi_pre_n_for(spi_clock_source_t clock_source, int clk, int pr
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spi_dev_t *hw = spi_periph_signal[TEST_SPI_HOST].hw;
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printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre + 1, hw->clock.clkcnt_n + 1);
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int real_freq_khz;
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spi_device_get_actual_freq(handle, &real_freq_khz);
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printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d, real_freq %d kHZ\n", clk, pre, n, hw->clock.clkdiv_pre + 1, hw->clock.clkcnt_n + 1, real_freq_khz);
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TEST_ASSERT(hw->clock.clkcnt_n + 1 == n);
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TEST_ASSERT(hw->clock.clkdiv_pre + 1 == pre);
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@ -538,7 +538,7 @@ SPI Clock Frequency
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Clock source of the GPSPI peripherals can be selected by setting :cpp:member:`spi_device_handle_t::cfg::clock_source`. You can refer to :cpp:type:`spi_clock_source_t` to know the supported clock sources.
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By default driver will set :cpp:member:`spi_device_handle_t::cfg::clock_source` to `SPI_CLK_SRC_DEFAULT`. This usually stands for the highest frequency among GPSPI clock sources. Its value will be different among chips.
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Actual clock frequency of a device may not be exactly equal to the number you set, it will be re-calculated by the driver to the nearest hardware compatible number, and not larger than the clock frequency of the clock source. You can call :cpp:func:`spi_device_get_actual_freq` or use :cpp:member:`spi_device_handle_t::real_clk_freq_hz` directly to know the actual frequency computed by the driver.
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Actual clock frequency of a device may not be exactly equal to the number you set, it will be re-calculated by the driver to the nearest hardware compatible number, and not larger than the clock frequency of the clock source. You can call :cpp:func:`spi_device_get_actual_freq` to know the actual frequency computed by the driver.
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Theoretical maximum transfer speed of Write or Read phase can be calculated according to the table below:
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