alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'feature/lp_wdt_h2_5.1' into 'release/v5.1'

Browse Source 
LP-WDT: add support for H2 (v5.1)

See merge request espressif/esp-idf!25863
This commit is contained in:
Jiang Jiang Jian 2023-09-11 19:04:00 +08:00
commit a432b1459e
2 changed files with 133 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
components/hal/esp32c6/include/hal/lpwdt_ll.h
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -24,22 +24,42 @@ extern "C" {
#include "esp32c6/rom/ets_sys.h" #include "esp32c6/rom/ets_sys.h"
// TODO: IDF-5717 /* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
// //Type check wdt_stage_action_t #define LP_WDT_WKEY_VALUE 0x50D83AA1
// ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); /* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
// ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); #define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
// ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
// ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
// ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); #define LP_WDT_RESET_LENGTH_100_NS 0
// //Type check wdt_reset_sig_length_t #define LP_WDT_RESET_LENGTH_200_NS 1
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_RESET_LENGTH_300_NS 2
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_RESET_LENGTH_400_NS 3
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_RESET_LENGTH_500_NS 4
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_RESET_LENGTH_800_NS 5
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_RESET_LENGTH_1600_NS 6
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_RESET_LENGTH_3200_NS 7
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
// ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); #define LP_WDT_STG_SEL_OFF 0
#define LP_WDT_STG_SEL_INT 1
#define LP_WDT_STG_SEL_RESET_CPU 2
#define LP_WDT_STG_SEL_RESET_SYSTEM 3
#define LP_WDT_STG_SEL_RESET_RTC 4
//Type check wdt_stage_action_t
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
//Type check wdt_reset_sig_length_t
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
/** /**
* @brief Enable the RWDT * @brief Enable the RWDT
@ -268,7 +288,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
{ {
hw->wprotect.val = RTC_CNTL_WDT_WKEY_VALUE; hw->wprotect.val = LP_WDT_WKEY_VALUE;
} }
/** /**

160
components/hal/esp32h2/include/hal/lpwdt_ll.h
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -23,6 +23,43 @@ extern "C" {
#include "esp32h2/rom/ets_sys.h" #include "esp32h2/rom/ets_sys.h"
/* The value that needs to be written to LP_WDT_WKEY to write-enable the wdt registers */
#define LP_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
/* Possible values for LP_WDT_CPU_RESET_LENGTH and LP_WDT_SYS_RESET_LENGTH */
#define LP_WDT_RESET_LENGTH_100_NS 0
#define LP_WDT_RESET_LENGTH_200_NS 1
#define LP_WDT_RESET_LENGTH_300_NS 2
#define LP_WDT_RESET_LENGTH_400_NS 3
#define LP_WDT_RESET_LENGTH_500_NS 4
#define LP_WDT_RESET_LENGTH_800_NS 5
#define LP_WDT_RESET_LENGTH_1600_NS 6
#define LP_WDT_RESET_LENGTH_3200_NS 7
#define LP_WDT_STG_SEL_OFF 0
#define LP_WDT_STG_SEL_INT 1
#define LP_WDT_STG_SEL_RESET_CPU 2
#define LP_WDT_STG_SEL_RESET_SYSTEM 3
#define LP_WDT_STG_SEL_RESET_RTC 4
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
//Type check wdt_reset_sig_length_t
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
/** /**
* @brief Enable the RWDT * @brief Enable the RWDT
* *
@ -30,7 +67,7 @@ extern "C" {
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
{ {
// hw->config0.en = 1; hw->config0.wdt_en = 1;
} }
/** /**
@ -43,7 +80,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
{ {
// hw->config0.en = 0; hw->config0.wdt_en = 0;
} }
/** /**
@ -54,7 +91,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
{ {
return false;//(hw->config0.en) ? true : false; return (hw->config0.wdt_en) ? true : false;
} }
/** /**
@ -77,27 +114,27 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
{ {
// switch (stage) { switch (stage) {
// case WDT_STAGE0: case WDT_STAGE0:
// hw->config0.stg0 = behavior; hw->config0.wdt_stg0 = behavior;
// //Account of implicty multiplier applied to stage 0 timeout tick config value //Account of implicty multiplier applied to stage 0 timeout tick config value
// hw->config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
// break; break;
// case WDT_STAGE1: case WDT_STAGE1:
// hw->config0.stg1 = behavior; hw->config0.wdt_stg1 = behavior;
// hw->config2 = timeout_ticks; hw->config2.val = timeout_ticks;
// break; break;
// case WDT_STAGE2: case WDT_STAGE2:
// hw->config0.stg2 = behavior; hw->config0.wdt_stg2 = behavior;
// hw->config3 = timeout_ticks; hw->config3.val = timeout_ticks;
// break; break;
// case WDT_STAGE3: case WDT_STAGE3:
// hw->config0.stg3 = behavior; hw->config0.wdt_stg3 = behavior;
// hw->config4 = timeout_ticks; hw->config4.val = timeout_ticks;
// break; break;
// default: default:
// abort(); abort();
// } }
} }
/** /**
@ -108,22 +145,22 @@ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage) FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
{ {
// switch (stage) { switch (stage) {
// case WDT_STAGE0: case WDT_STAGE0:
// hw->config0.stg0 = WDT_STAGE_ACTION_OFF; hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
// break; break;
// case WDT_STAGE1: case WDT_STAGE1:
// hw->config0.stg1 = WDT_STAGE_ACTION_OFF; hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
// break; break;
// case WDT_STAGE2: case WDT_STAGE2:
// hw->config0.stg2 = WDT_STAGE_ACTION_OFF; hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
// break; break;
// case WDT_STAGE3: case WDT_STAGE3:
// hw->config0.stg3 = WDT_STAGE_ACTION_OFF; hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
// break; break;
// default: default:
// abort(); abort();
// } }
} }
/** /**
@ -134,7 +171,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stag
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{ {
// hw->config0.cpu_reset_length = length; hw->config0.wdt_cpu_reset_length = length;
} }
/** /**
@ -145,7 +182,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{ {
// hw->config0.sys_reset_length = length; hw->config0.wdt_sys_reset_length = length;
} }
/** /**
@ -160,7 +197,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
{ {
// hw->config0.flashboot_mod_en = (enable) ? 1 : 0; hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
} }
/** /**
@ -171,7 +208,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable) FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{ {
// hw->config0.procpu_reset_en = (enable) ? 1 : 0; hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
} }
/** /**
@ -182,7 +219,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enabl
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable) FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{ {
// hw->config0.appcpu_reset_en = (enable) ? 1 : 0; hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
} }
/** /**
@ -193,7 +230,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enabl
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable) FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
{ {
// hw->config0.pause_in_slp = (enable) ? 1 : 0; hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
} }
/** /**
@ -207,19 +244,17 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool ena
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
{ {
// hw->config5.chip_reset_en = (enable) ? 1 : 0; hw->config5.chip_reset_en = (enable) ? 1 : 0;
} }
/** /**
* @brief Set width of chip reset signal * @brief No register for setting reset width on H2, we keep an empty function to
* * provide the same HAL interface as other targets.
* @param hw Start address of the peripheral registers.
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width) FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
{ {
// ESP32H2-TODO: IDF-6402 (void)hw;
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, chip_reset_width, width); (void)width;
} }
/** /**
@ -231,8 +266,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
{ {
// ESP32H2-TODO: IDF-6402 hw->feed.rtc_wdt_feed = 1;
// hw->feed.rtc_wdt_feed = 1;
} }
/** /**
@ -242,8 +276,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
{ {
// ESP32H2-TODO: IDF-6402 hw->wprotect.val = 0;
// hw->wprotect = 0;
} }
/** /**
@ -253,8 +286,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
{ {
// ESP32H2-TODO: IDF-6402 hw->wprotect.val = LP_WDT_WKEY_VALUE;
// hw->wprotect = RTC_CNTL_WDT_WKEY_VALUE;
} }
/** /**
@ -265,8 +297,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
{ {
// ESP32H2-TODO: IDF-6402 hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
// hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
} }
/** /**
@ -277,7 +308,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
*/ */
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
{ {
return false;//(hw->int_st.lp_wdt_int_st) ? true : false; // ESP32H2-TODO: IDF-6402 return (hw->int_st.lp_wdt_int_st) ? true : false;
} }
/** /**
@ -287,8 +318,7 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
*/ */
FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw) FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
{ {
// ESP32H2-TODO: IDF-6402 hw->int_clr.lp_wdt_int_clr = 1;
// hw->int_clr.lp_wdt_int_clr = 1;
} }
#ifdef __cplusplus #ifdef __cplusplus