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Merge branch 'feature/watchpoint_on_stack_canary' into 'master'
Add option to automatically set a watchpoint at the end of the swapped-in task This should make stack overflows easier to debug because it triggers a debug exception as soon as the stack is overwritten, not later when a context switch happens. Marked as a FreeRTOS debug feature because it doesn't give a nice error message and uses up a watchpoint. See merge request !389
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a3f6728797
@ -14,8 +14,49 @@
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#ifndef __ASSEMBLER__
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#include "esp_err.h"
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/**
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* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
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* address. Do nothing otherwise.
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* @param data Pointer to the target breakpoint position
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*/
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void esp_set_breakpoint_if_jtag(void *fn);
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#define ESP_WATCHPOINT_LOAD 0x40000000
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#define ESP_WATCHPOINT_STORE 0x80000000
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#define ESP_WATCHPOINT_ACCESS 0xC0000000
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/**
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* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
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*
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* @param no Watchpoint number. On the ESP32, this can be 0 or 1.
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* @param adr Base address to watch
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* @param size Size of the region, starting at the base address, to watch. Must
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* be one of 2^n, with n in [0..6].
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* @param flags One of ESP_WATCHPOINT_* flags
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*
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* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
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*
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* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
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* masking away the lower n bits for a region with size 2^n. If adr does
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* not have zero for these lower n bits, you may not be watching the
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* region you intended.
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*/
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esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
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/**
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* @brief Clear a watchpoint
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*
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* @param no Watchpoint to clear
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*
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*/
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void esp_clear_watchpoint(int no);
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#endif
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#endif
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#endif
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@ -32,6 +32,7 @@
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#include "esp_gdbstub.h"
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#include "esp_panic.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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/*
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Panic handlers; these get called when an unhandled exception occurs or the assembly-level
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@ -163,8 +164,37 @@ void panicHandler(XtExcFrame *frame)
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panicPutStr("Guru Meditation Error: Core ");
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panicPutDec(xPortGetCoreID());
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panicPutStr(" panic'ed (");
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panicPutStr(reason);
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panicPutStr(")\r\n");
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if (!abort_called) {
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panicPutStr(reason);
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panicPutStr(")\r\n");
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if (regs[20]==PANIC_RSN_DEBUGEXCEPTION) {
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int debugRsn;
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asm("rsr.debugcause %0":"=r"(debugRsn));
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panicPutStr("Debug exception reason: ");
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if (debugRsn&XCHAL_DEBUGCAUSE_ICOUNT_MASK) panicPutStr("SingleStep ");
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if (debugRsn&XCHAL_DEBUGCAUSE_IBREAK_MASK) panicPutStr("HwBreakpoint ");
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if (debugRsn&XCHAL_DEBUGCAUSE_DBREAK_MASK) {
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//Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
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//reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
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//debugcause if the cause is watchdog 1 and clearing it if it's watchdog 0.
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if (debugRsn&(1<<8)) {
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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panicPutStr("Stack canary watchpoint triggered ");
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#else
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panicPutStr("Watchpoint 1 triggered ");
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#endif
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} else {
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panicPutStr("Watchpoint 0 triggered ");
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}
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}
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if (debugRsn&XCHAL_DEBUGCAUSE_BREAK_MASK) panicPutStr("BREAK instr ");
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if (debugRsn&XCHAL_DEBUGCAUSE_BREAKN_MASK) panicPutStr("BREAKN instr ");
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if (debugRsn&XCHAL_DEBUGCAUSE_DEBUGINT_MASK) panicPutStr("DebugIntr ");
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panicPutStr("\r\n");
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}
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} else {
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panicPutStr("abort)\r\n");
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}
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if (esp_cpu_in_ocd_debug_mode()) {
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asm("break.n 1");
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@ -353,3 +383,50 @@ void esp_set_breakpoint_if_jtag(void *fn)
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setFirstBreakpoint((uint32_t)fn);
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}
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}
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esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags)
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{
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int x;
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if (no<0 || no>1) return ESP_ERR_INVALID_ARG;
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if (flags&(~0xC0000000)) return ESP_ERR_INVALID_ARG;
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int dbreakc=0x3F;
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//We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
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for (x=0; x<7; x++) {
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if (size==(1<<x)) break;
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dbreakc<<=1;
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}
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if (x==7) return ESP_ERR_INVALID_ARG;
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//Mask mask and add in flags.
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dbreakc=(dbreakc&0x3f)|flags;
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if (no==0) {
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asm volatile(
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"wsr.dbreaka0 %0\n" \
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"wsr.dbreakc0 %1\n" \
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::"r"(adr),"r"(dbreakc));
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} else {
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asm volatile(
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"wsr.dbreaka1 %0\n" \
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"wsr.dbreakc1 %1\n" \
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::"r"(adr),"r"(dbreakc));
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}
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return ESP_OK;
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}
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void esp_clear_watchpoint(int no)
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{
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//Setting a dbreakc register to 0 makes it trigger on neither load nor store, effectively disabling it.
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int dbreakc=0;
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if (no==0) {
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asm volatile(
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"wsr.dbreakc0 %0\n" \
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::"r"(dbreakc));
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} else {
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asm volatile(
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"wsr.dbreakc1 %0\n" \
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::"r"(dbreakc));
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}
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}
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@ -197,6 +197,22 @@ config FREERTOS_PORTMUX_DEBUG_RECURSIVE
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portMUX usage.
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endif #FREERTOS_UNICORE
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config FREERTOS_WATCHPOINT_END_OF_STACK
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bool "Set a debug watchpoint at the end of each stack"
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default n
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help
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FreeRTOS can check if a stack has overflown its bounds by checking either the value of
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the stack pointer or by checking the integrity of canary bytes. (See FREERTOS_CHECK_STACKOVERFLOW
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for more information.) These checks only happen on a context switch, and the situation that caused
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the stack overflow may already be long gone by then. This option will use the debug memory
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watchpoint 1 (the second one) to allow breaking into the debugger (or panic'ing) as soon as any
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of the last 32 bytes on the stack of a task are overwritten. The side effect is that using gdb, you
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effectively only have one watchpoint; the 2nd one is overwritten as soon as a task switch happens.
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When this watchpoint is hit, gdb will stop with a SIGTRAP message. When no OCD is attached, esp-idf
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will panic on an unhandled debug exception.
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endif # FREERTOS_DEBUG_INTERNALS
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endmenu
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@ -187,6 +187,13 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
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void vPortYieldOtherCore( BaseType_t coreid) PRIVILEGED_FUNCTION;
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/*
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Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
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watchpoint around.
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*/
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void vPortSetStackWatchpoint( void* pxStackStart );
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/*
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* The structures and methods of manipulating the MPU are contained within the
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* port layer.
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@ -394,3 +394,19 @@ void vPortFirstTaskHook(TaskFunction_t function) {
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#endif
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void vPortSetStackWatchpoint( void* pxStackStart ) {
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//Set watchpoint 1 to watch the last 32 bytes of the stack.
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//Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because
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//the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32
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//bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most
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//28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes.
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//This way, we make sure we trigger before/when the stack canary is corrupted, not after.
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int addr=(int)pxStackStart;
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addr=(addr+31)&(~31);
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esp_set_watchpoint(1, (char*)addr, 32, ESP_WATCHPOINT_STORE);
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}
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@ -78,6 +78,7 @@ task.h is included from an application file. */
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#include "rom/ets_sys.h"
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#include "esp_newlib.h"
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#include "esp_panic.h"
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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@ -2809,6 +2810,11 @@ void vTaskSwitchContext( void )
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traceTASK_SWITCHED_IN();
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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vPortSetStackWatchpoint(pxCurrentTCB[xPortGetCoreID()]->pxStack);
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#endif
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}
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portEXIT_CRITICAL_NESTED(irqstate);
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}
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