diff --git a/components/driver/gpio.c b/components/driver/gpio.c index 50865d8cc7..e53215c105 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -11,6 +11,7 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #include #include "esp_err.h" #include "freertos/FreeRTOS.h" @@ -19,13 +20,16 @@ #include "driver/rtc_io.h" #include "soc/soc.h" #include "soc/periph_defs.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/gpio_periph.h" -#include "esp_log.h" #if !CONFIG_FREERTOS_UNICORE #include "esp_ipc.h" #endif +#include "soc/gpio_caps.h" +#include "soc/gpio_periph.h" +#include "esp_log.h" +#include "hal/gpio_hal.h" + +static const char *GPIO_TAG = "gpio"; #define GPIO_CHECK(a, str, ret_val) \ if (!(a)) { \ ESP_LOGE(GPIO_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \ @@ -35,7 +39,7 @@ typedef struct { gpio_isr_t fn; /*!< isr function */ - void* args; /*!< isr function args */ + void *args; /*!< isr function args */ } gpio_isr_func_t; // Used by the IPC call to register the interrupt service routine. @@ -48,69 +52,82 @@ typedef struct { esp_err_t ret; } gpio_isr_alloc_t; -static const char* GPIO_TAG = "gpio"; -static gpio_isr_func_t* gpio_isr_func = NULL; -static gpio_isr_handle_t gpio_isr_handle; -static uint32_t isr_core_id = GPIO_ISR_CORE_ID_UNINIT; -static portMUX_TYPE gpio_spinlock = portMUX_INITIALIZER_UNLOCKED; +typedef struct { + gpio_hal_context_t *gpio_hal; + portMUX_TYPE gpio_spinlock; + uint32_t isr_core_id; + gpio_isr_func_t *gpio_isr_func; + gpio_isr_handle_t gpio_isr_handle; +} gpio_context_t; + +static gpio_hal_context_t _gpio_hal = { + .dev = GPIO_HAL_GET_HW(GPIO_PORT_0) +}; + +static gpio_context_t gpio_context = { + .gpio_hal = &_gpio_hal, + .gpio_spinlock = portMUX_INITIALIZER_UNLOCKED, + .isr_core_id = GPIO_ISR_CORE_ID_UNINIT, + .gpio_isr_func = NULL, +}; esp_err_t gpio_pullup_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { + + if (rtc_gpio_is_valid_gpio(gpio_num)) { rtc_gpio_pullup_en(gpio_num); } else { - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); -#endif + return ESP_OK; } esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { + + if (rtc_gpio_is_valid_gpio(gpio_num)) { rtc_gpio_pullup_dis(gpio_num); } else { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); -#endif + return ESP_OK; } esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { + + if (rtc_gpio_is_valid_gpio(gpio_num)) { rtc_gpio_pulldown_en(gpio_num); } else { - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); -#endif + return ESP_OK; } esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { + + if (rtc_gpio_is_valid_gpio(gpio_num)) { rtc_gpio_pulldown_dis(gpio_num); } else { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); -#endif + return ESP_OK; } @@ -118,109 +135,91 @@ esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); GPIO_CHECK(intr_type < GPIO_INTR_MAX, "GPIO interrupt type error", ESP_ERR_INVALID_ARG); - GPIO.pin[gpio_num].int_type = intr_type; + + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_set_intr_type(gpio_context.gpio_hal, gpio_num, intr_type); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } -static void gpio_intr_status_clr(gpio_num_t gpio_num) +static esp_err_t gpio_intr_enable_on_core(gpio_num_t gpio_num, uint32_t core_id) { - if (gpio_num < 32) { - GPIO.status_w1tc = BIT(gpio_num); - } else { - GPIO.status1_w1tc.intr_st = BIT(gpio_num - 32); - } -} - -static esp_err_t gpio_intr_enable_on_core (gpio_num_t gpio_num, uint32_t core_id) -{ - gpio_intr_status_clr(gpio_num); -#if CONFIG_IDF_TARGET_ESP32 - if (core_id == 0) { - GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr - } else { - GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr - } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - if (core_id == 0) { - GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr - } -#endif + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_intr_enable_on_core(gpio_context.gpio_hal, gpio_num, core_id); return ESP_OK; } esp_err_t gpio_intr_enable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&gpio_spinlock); - if(isr_core_id == GPIO_ISR_CORE_ID_UNINIT) { - isr_core_id = xPortGetCoreID(); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + if(gpio_context.isr_core_id == GPIO_ISR_CORE_ID_UNINIT) { + gpio_context.isr_core_id = xPortGetCoreID(); } - portEXIT_CRITICAL(&gpio_spinlock); - return gpio_intr_enable_on_core (gpio_num, isr_core_id); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); + return gpio_intr_enable_on_core (gpio_num, gpio_context.isr_core_id); } esp_err_t gpio_intr_disable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr - gpio_intr_status_clr(gpio_num); + gpio_hal_intr_disable(gpio_context.gpio_hal, gpio_num); + return ESP_OK; +} + +static esp_err_t gpio_input_disable(gpio_num_t gpio_num) +{ + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_input_disable(gpio_context.gpio_hal, gpio_num); + return ESP_OK; +} + +static esp_err_t gpio_input_enable(gpio_num_t gpio_num) +{ + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_input_enable(gpio_context.gpio_hal, gpio_num); return ESP_OK; } static esp_err_t gpio_output_disable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - if (gpio_num < 32) { - GPIO.enable_w1tc = (0x1 << gpio_num); - } else { - GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32)); - } - - // Ensure no other output signal is routed via GPIO matrix to this pin - REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), - SIG_GPIO_OUT_IDX); - + gpio_hal_output_disable(gpio_context.gpio_hal, gpio_num); return ESP_OK; } static esp_err_t gpio_output_enable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG); - if (gpio_num < 32) { - GPIO.enable_w1ts = (0x1 << gpio_num); - } else { - GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32)); - } + gpio_hal_output_enable(gpio_context.gpio_hal, gpio_num); gpio_matrix_out(gpio_num, SIG_GPIO_OUT_IDX, false, false); return ESP_OK; } +static esp_err_t gpio_od_disable(gpio_num_t gpio_num) +{ + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_od_disable(gpio_context.gpio_hal, gpio_num); + return ESP_OK; +} + +static esp_err_t gpio_od_enable(gpio_num_t gpio_num) +{ + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_od_enable(gpio_context.gpio_hal, gpio_num); + return ESP_OK; +} + esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG); - if (level) { - if (gpio_num < 32) { - GPIO.out_w1ts = (1 << gpio_num); - } else { - GPIO.out1_w1ts.data = (1 << (gpio_num - 32)); - } - } else { - if (gpio_num < 32) { - GPIO.out_w1tc = (1 << gpio_num); - } else { - GPIO.out1_w1tc.data = (1 << (gpio_num - 32)); - } - } + gpio_hal_set_level(gpio_context.gpio_hal, gpio_num, level); return ESP_OK; } int gpio_get_level(gpio_num_t gpio_num) { - if (gpio_num < 32) { - return (GPIO.in >> gpio_num) & 0x1; - } else { - return (GPIO.in1.data >> (gpio_num - 32)) & 0x1; - } + return gpio_hal_get_level(gpio_context.gpio_hal, gpio_num); } esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) @@ -228,58 +227,66 @@ esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); GPIO_CHECK(pull <= GPIO_FLOATING, "GPIO pull mode error", ESP_ERR_INVALID_ARG); esp_err_t ret = ESP_OK; + switch (pull) { - case GPIO_PULLUP_ONLY: - gpio_pulldown_dis(gpio_num); - gpio_pullup_en(gpio_num); - break; - case GPIO_PULLDOWN_ONLY: - gpio_pulldown_en(gpio_num); - gpio_pullup_dis(gpio_num); - break; - case GPIO_PULLUP_PULLDOWN: - gpio_pulldown_en(gpio_num); - gpio_pullup_en(gpio_num); - break; - case GPIO_FLOATING: - gpio_pulldown_dis(gpio_num); - gpio_pullup_dis(gpio_num); - break; - default: - ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u", gpio_num, pull); - ret = ESP_ERR_INVALID_ARG; - break; + case GPIO_PULLUP_ONLY: + gpio_pulldown_dis(gpio_num); + gpio_pullup_en(gpio_num); + break; + + case GPIO_PULLDOWN_ONLY: + gpio_pulldown_en(gpio_num); + gpio_pullup_dis(gpio_num); + break; + + case GPIO_PULLUP_PULLDOWN: + gpio_pulldown_en(gpio_num); + gpio_pullup_en(gpio_num); + break; + + case GPIO_FLOATING: + gpio_pulldown_dis(gpio_num); + gpio_pullup_dis(gpio_num); + break; + + default: + ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u", gpio_num, pull); + ret = ESP_ERR_INVALID_ARG; + break; } + return ret; } esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (gpio_num >= 34 && (mode & GPIO_MODE_DEF_OUTPUT)) { -#elif CONFIG_IDF_TARGET_ESP32S2BETA - if (gpio_num >= 46 && (mode & GPIO_MODE_DEF_OUTPUT)) { -#endif + + if ((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) != true) && (mode & GPIO_MODE_DEF_OUTPUT)) { ESP_LOGE(GPIO_TAG, "io_num=%d can only be input", gpio_num); return ESP_ERR_INVALID_ARG; } + esp_err_t ret = ESP_OK; + if (mode & GPIO_MODE_DEF_INPUT) { - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + gpio_input_enable(gpio_num); } else { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + gpio_input_disable(gpio_num); } + if (mode & GPIO_MODE_DEF_OUTPUT) { gpio_output_enable(gpio_num); } else { gpio_output_disable(gpio_num); } + if (mode & GPIO_MODE_DEF_OD) { - GPIO.pin[gpio_num].pad_driver = 1; + gpio_od_enable(gpio_num); } else { - GPIO.pin[gpio_num].pad_driver = 0; + gpio_od_disable(gpio_num); } + return ret; } @@ -293,75 +300,82 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig) uint8_t od_en = 0; uint8_t pu_en = 0; uint8_t pd_en = 0; + if (pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) { ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error "); return ESP_ERR_INVALID_ARG; } -#if CONFIG_IDF_TARGET_ESP32 + if ((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) { - //GPIO 34/35/36/37/38/39 can only be used as input mode; - if ((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) { - ESP_LOGE(GPIO_TAG, "GPIO34-39 can only be used as input mode"); + if(GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_pin_mask)) { + ESP_LOGE(GPIO_TAG, "GPIO can only be used as input mode"); return ESP_ERR_INVALID_ARG; } } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - if ( (pGPIOConfig->mode & GPIO_MODE_DEF_OUTPUT) && (gpio_pin_mask & GPIO_SEL_46) ) { - ESP_LOGE(GPIO_TAG, "GPIO46 can only be used as input mode"); - return ESP_ERR_INVALID_ARG; - } -#endif + do { io_reg = GPIO_PIN_MUX_REG[io_num]; + if (((gpio_pin_mask >> io_num) & BIT(0))) { if (!io_reg) { - ESP_LOGE(GPIO_TAG, "IO%d is not a valid GPIO",io_num); + ESP_LOGE(GPIO_TAG, "IO%d is not a valid GPIO", io_num); return ESP_ERR_INVALID_ARG; } - if(RTC_GPIO_IS_VALID_GPIO(io_num)){ + + if (rtc_gpio_is_valid_gpio(io_num)) { rtc_gpio_deinit(io_num); } + if ((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) { input_en = 1; - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]); + gpio_input_enable(io_num); } else { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]); + gpio_input_disable(io_num); } + if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) { od_en = 1; - GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */ + gpio_od_enable(io_num); } else { - GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */ + gpio_od_disable(io_num); } + if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) { output_en = 1; gpio_output_enable(io_num); } else { gpio_output_disable(io_num); } + if (pGPIOConfig->pull_up_en) { pu_en = 1; gpio_pullup_en(io_num); } else { gpio_pullup_dis(io_num); } + if (pGPIOConfig->pull_down_en) { pd_en = 1; gpio_pulldown_en(io_num); } else { gpio_pulldown_dis(io_num); } + ESP_LOGI(GPIO_TAG, "GPIO[%d]| InputEn: %d| OutputEn: %d| OpenDrain: %d| Pullup: %d| Pulldown: %d| Intr:%d ", io_num, input_en, output_en, od_en, pu_en, pd_en, pGPIOConfig->intr_type); gpio_set_intr_type(io_num, pGPIOConfig->intr_type); + if (pGPIOConfig->intr_type) { gpio_intr_enable(io_num); } else { gpio_intr_disable(io_num); } + PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */ } + io_num++; } while (io_num < GPIO_PIN_COUNT); + return ESP_OK; } @@ -380,106 +394,105 @@ esp_err_t gpio_reset_pin(gpio_num_t gpio_num) return ESP_OK; } -static inline void IRAM_ATTR gpio_isr_loop(uint32_t status, const uint32_t gpio_num_start) { +static inline void IRAM_ATTR gpio_isr_loop(uint32_t status, const uint32_t gpio_num_start) +{ while (status) { int nbit = __builtin_ffs(status) - 1; status &= ~(1 << nbit); int gpio_num = gpio_num_start + nbit; - if (gpio_isr_func[gpio_num].fn != NULL) { - gpio_isr_func[gpio_num].fn(gpio_isr_func[gpio_num].args); + + if (gpio_context.gpio_isr_func[gpio_num].fn != NULL) { + gpio_context.gpio_isr_func[gpio_num].fn(gpio_context.gpio_isr_func[gpio_num].args); } } } -static void IRAM_ATTR gpio_intr_service(void* arg) +static void IRAM_ATTR gpio_intr_service(void *arg) { //GPIO intr process - if (gpio_isr_func == NULL) { + if (gpio_context.gpio_isr_func == NULL) { return; } + //read status to get interrupt status for GPIO0-31 uint32_t gpio_intr_status; -#ifdef CONFIG_IDF_TARGET_ESP32 - gpio_intr_status = (isr_core_id == 0) ? GPIO.pcpu_int : GPIO.acpu_int; -#else - gpio_intr_status = GPIO.pcpu_int; -#endif + gpio_hal_get_intr_status(gpio_context.gpio_hal, gpio_context.isr_core_id, &gpio_intr_status); + if (gpio_intr_status) { gpio_isr_loop(gpio_intr_status, 0); - GPIO.status_w1tc = gpio_intr_status; + gpio_hal_clear_intr_status(gpio_context.gpio_hal, gpio_intr_status); } //read status1 to get interrupt status for GPIO32-39 uint32_t gpio_intr_status_h; -#ifdef CONFIG_IDF_TARGET_ESP32 - gpio_intr_status_h = (isr_core_id == 0) ? GPIO.pcpu_int1.intr : GPIO.acpu_int1.intr; -#else - gpio_intr_status_h = GPIO.pcpu_int1.intr; -#endif + gpio_hal_get_intr_status_high(gpio_context.gpio_hal, gpio_context.isr_core_id, &gpio_intr_status_h); + if (gpio_intr_status_h) { gpio_isr_loop(gpio_intr_status_h, 32); - GPIO.status1_w1tc.intr_st = gpio_intr_status_h; + gpio_hal_clear_intr_status_high(gpio_context.gpio_hal, gpio_intr_status); } } -esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void* args) +esp_err_t gpio_install_isr_service(int intr_alloc_flags) { - GPIO_CHECK(gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE); - GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&gpio_spinlock); - gpio_intr_disable(gpio_num); - if (gpio_isr_func) { - gpio_isr_func[gpio_num].fn = isr_handler; - gpio_isr_func[gpio_num].args = args; + GPIO_CHECK(gpio_context.gpio_isr_func == NULL, "GPIO isr service already installed", ESP_ERR_INVALID_STATE); + esp_err_t ret; + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_context.gpio_isr_func = (gpio_isr_func_t *) calloc(GPIO_NUM_MAX, sizeof(gpio_isr_func_t)); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); + if (gpio_context.gpio_isr_func == NULL) { + ret = ESP_ERR_NO_MEM; + } else { + ret = gpio_isr_register(gpio_intr_service, NULL, intr_alloc_flags, &gpio_context.gpio_isr_handle); } - gpio_intr_enable_on_core (gpio_num, esp_intr_get_cpu(gpio_isr_handle)); - portEXIT_CRITICAL(&gpio_spinlock); + + return ret; +} + +esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void *args) +{ + GPIO_CHECK(gpio_context.gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE); + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_intr_disable(gpio_num); + if (gpio_context.gpio_isr_func) { + gpio_context.gpio_isr_func[gpio_num].fn = isr_handler; + gpio_context.gpio_isr_func[gpio_num].args = args; + } + gpio_intr_enable_on_core (gpio_num, esp_intr_get_cpu(gpio_context.gpio_isr_handle)); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } esp_err_t gpio_isr_handler_remove(gpio_num_t gpio_num) { - GPIO_CHECK(gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE); + GPIO_CHECK(gpio_context.gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE); GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - portENTER_CRITICAL(&gpio_spinlock); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_intr_disable(gpio_num); - if (gpio_isr_func) { - gpio_isr_func[gpio_num].fn = NULL; - gpio_isr_func[gpio_num].args = NULL; + if (gpio_context.gpio_isr_func) { + gpio_context.gpio_isr_func[gpio_num].fn = NULL; + gpio_context.gpio_isr_func[gpio_num].args = NULL; } - portEXIT_CRITICAL(&gpio_spinlock); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } -esp_err_t gpio_install_isr_service(int intr_alloc_flags) -{ - GPIO_CHECK(gpio_isr_func == NULL, "GPIO isr service already installed", ESP_ERR_INVALID_STATE); - esp_err_t ret; - portENTER_CRITICAL(&gpio_spinlock); - gpio_isr_func = (gpio_isr_func_t*) calloc(GPIO_NUM_MAX, sizeof(gpio_isr_func_t)); - portEXIT_CRITICAL(&gpio_spinlock); - if (gpio_isr_func == NULL) { - ret = ESP_ERR_NO_MEM; - } else { - ret = gpio_isr_register(gpio_intr_service, NULL, intr_alloc_flags, &gpio_isr_handle); - } - return ret; -} - void gpio_uninstall_isr_service(void) { - if (gpio_isr_func == NULL) { + if (gpio_context.gpio_isr_func == NULL) { return; } - portENTER_CRITICAL(&gpio_spinlock); - esp_intr_free(gpio_isr_handle); - free(gpio_isr_func); - gpio_isr_func = NULL; - isr_core_id = GPIO_ISR_CORE_ID_UNINIT; - portEXIT_CRITICAL(&gpio_spinlock); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + esp_intr_free(gpio_context.gpio_isr_handle); + free(gpio_context.gpio_isr_func); + gpio_context.gpio_isr_func = NULL; + gpio_context.isr_core_id = GPIO_ISR_CORE_ID_UNINIT; + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return; } + static void gpio_isr_register_on_core_static(void *param) { gpio_isr_alloc_t *p = (gpio_isr_alloc_t *)param; @@ -487,7 +500,7 @@ static void gpio_isr_register_on_core_static(void *param) p->ret = esp_intr_alloc(p->source, p->intr_alloc_flags, p->fn, p->arg, p->handle); } -esp_err_t gpio_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, gpio_isr_handle_t *handle) +esp_err_t gpio_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, gpio_isr_handle_t *handle) { GPIO_CHECK(fn, "GPIO ISR null", ESP_ERR_INVALID_ARG); gpio_isr_alloc_t p; @@ -496,17 +509,17 @@ esp_err_t gpio_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, p.fn = fn; p.arg = arg; p.handle = handle; - portENTER_CRITICAL(&gpio_spinlock); - if(isr_core_id == GPIO_ISR_CORE_ID_UNINIT) { - isr_core_id = xPortGetCoreID(); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + if(gpio_context.isr_core_id == GPIO_ISR_CORE_ID_UNINIT) { + gpio_context.isr_core_id = xPortGetCoreID(); } - portEXIT_CRITICAL(&gpio_spinlock); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); esp_err_t ret; #if CONFIG_FREERTOS_UNICORE gpio_isr_register_on_core_static(&p); ret = ESP_OK; #else /* CONFIG_FREERTOS_UNICORE */ - ret = esp_ipc_call_blocking(isr_core_id, gpio_isr_register_on_core_static, (void *)&p); + ret = esp_ipc_call_blocking(gpio_context.isr_core_id, gpio_isr_register_on_core_static, (void *)&p); #endif /* !CONFIG_FREERTOS_UNICORE */ if(ret != ESP_OK || p.ret != ESP_OK) { return ESP_ERR_NOT_FOUND; @@ -518,154 +531,118 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); esp_err_t ret = ESP_OK; - if (( intr_type == GPIO_INTR_LOW_LEVEL ) || ( intr_type == GPIO_INTR_HIGH_LEVEL )) { - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { + + if ((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) { + if (rtc_gpio_is_valid_gpio(gpio_num)) { ret = rtc_gpio_wakeup_enable(gpio_num, intr_type); } else { - GPIO.pin[gpio_num].int_type = intr_type; - GPIO.pin[gpio_num].wakeup_enable = 0x1; + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } } else { ESP_LOGE(GPIO_TAG, "GPIO wakeup only supports level mode, but edge mode set. gpio_num:%u", gpio_num); ret = ESP_ERR_INVALID_ARG; } + return ret; } esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - GPIO.pin[gpio_num].wakeup_enable = 0; - return ESP_OK; + esp_err_t ret = ESP_OK; + + if (rtc_gpio_is_valid_gpio(gpio_num)) { + ret = rtc_gpio_wakeup_disable(gpio_num); + } else { + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_wakeup_disable(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); + } + return ret; } esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { - rtc_gpio_set_drive_capability(gpio_num, strength); + esp_err_t ret = ESP_OK; + + if (rtc_gpio_is_valid_gpio(gpio_num)) { + ret = rtc_gpio_set_drive_capability(gpio_num, strength); } else { - SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); -#endif - return ESP_OK; + return ret; } -esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength) +esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *strength) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG); -#if CONFIG_IDF_TARGET_ESP32 - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { - return rtc_gpio_get_drive_capability(gpio_num, strength); - } else { - *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); - } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); -#endif - return ESP_OK; -} + esp_err_t ret = ESP_OK; -#if CONFIG_IDF_TARGET_ESP32 -static const uint32_t GPIO_HOLD_MASK[34] = { - 0, - GPIO_SEL_1, - 0, - GPIO_SEL_0, - 0, - GPIO_SEL_8, - GPIO_SEL_2, - GPIO_SEL_3, - GPIO_SEL_4, - GPIO_SEL_5, - GPIO_SEL_6, - GPIO_SEL_7, - 0, - 0, - 0, - 0, - GPIO_SEL_9, - GPIO_SEL_10, - GPIO_SEL_11, - GPIO_SEL_12, - 0, - GPIO_SEL_14, - GPIO_SEL_15, - GPIO_SEL_16, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, -}; -#endif + if (rtc_gpio_is_valid_gpio(gpio_num)) { + ret = rtc_gpio_get_drive_capability(gpio_num, strength); + } else { + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); + } + return ret; +} esp_err_t gpio_hold_en(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED); - esp_err_t r = ESP_OK; - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { - r = rtc_gpio_hold_en(gpio_num); -#if CONFIG_IDF_TARGET_ESP32 + int ret = ESP_OK; + + if (rtc_gpio_is_valid_gpio(gpio_num)) { + ret = rtc_gpio_hold_en(gpio_num); } else if (GPIO_HOLD_MASK[gpio_num]) { - SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_hold_en(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } else { - r = ESP_ERR_NOT_SUPPORTED; + ret = ESP_ERR_NOT_SUPPORTED; } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - } else { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - RTC_GPIO_NUMBER)); - } -#endif - return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED; + + return ret; } esp_err_t gpio_hold_dis(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED); - esp_err_t r = ESP_OK; - if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) { - r = rtc_gpio_hold_dis(gpio_num); -#if CONFIG_IDF_TARGET_ESP32 + int ret = ESP_OK; + + if (rtc_gpio_is_valid_gpio(gpio_num)) { + ret = rtc_gpio_hold_dis(gpio_num); }else if (GPIO_HOLD_MASK[gpio_num]) { - CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_hold_dis(gpio_context.gpio_hal, gpio_num); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } else { - r = ESP_ERR_NOT_SUPPORTED; + ret = ESP_ERR_NOT_SUPPORTED; } -#elif CONFIG_IDF_TARGET_ESP32S2BETA - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - RTC_GPIO_NUMBER)); - } -#endif - return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED; + + return ret; } void gpio_deep_sleep_hold_en(void) { - portENTER_CRITICAL(&gpio_spinlock); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); - portEXIT_CRITICAL(&gpio_spinlock); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_deep_sleep_hold_en(gpio_context.gpio_hal); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } void gpio_deep_sleep_hold_dis(void) { - portENTER_CRITICAL(&gpio_spinlock); -#if CONFIG_IDF_TARGET_ESP32 - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); -#endif - portEXIT_CRITICAL(&gpio_spinlock); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } #if CONFIG_IDF_TARGET_ESP32S2BETA @@ -673,30 +650,31 @@ void gpio_deep_sleep_hold_dis(void) esp_err_t gpio_force_hold_all() { rtc_gpio_force_hold_all(); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } esp_err_t gpio_force_unhold_all() { rtc_gpio_force_hold_dis_all(); + portENTER_CRITICAL(&gpio_context.gpio_spinlock); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } #endif void gpio_iomux_in(uint32_t gpio, uint32_t signal_idx) { - GPIO.func_in_sel_cfg[signal_idx].sig_in_sel = 0; - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); + gpio_hal_iomux_in(gpio_context.gpio_hal, gpio, signal_idx); } void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv) { - GPIO.func_out_sel_cfg[gpio_num].oen_sel = 0; - GPIO.func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_hal_iomux_out(gpio_context.gpio_hal, gpio_num, func, (uint32_t)oen_inv); } diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index 1e923ec5ec..7509118909 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -12,8 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _DRIVER_GPIO_H_ -#define _DRIVER_GPIO_H_ +#pragma once #include "esp_err.h" #include #include @@ -33,268 +32,6 @@ extern "C" { #endif -#if CONFIG_IDF_TARGET_ESP32 -#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ -#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ -#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected - @note There are more macros - like that up to pin 39, - excluding pins 20, 24 and 28..31. - They are not shown here - to reduce redundant information. */ -/** @cond */ -#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */ -#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */ -#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */ -#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */ -#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */ -#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */ -#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */ -#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */ -#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */ -#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */ -#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */ -#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */ -#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */ -#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */ -#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */ -#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */ -#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */ - -#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */ -#define GPIO_SEL_22 (BIT(22)) /*!< Pin 22 selected */ -#define GPIO_SEL_23 (BIT(23)) /*!< Pin 23 selected */ - -#define GPIO_SEL_25 (BIT(25)) /*!< Pin 25 selected */ -#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */ -#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */ - -#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */ -#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */ -#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */ -#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */ -#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */ -#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */ -#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ -#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ - -#elif CONFIG_IDF_TARGET_ESP32S2BETA -#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ -#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ -#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */ -#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */ -#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */ -#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */ -#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */ -#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */ -#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */ -#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */ -#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */ -#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */ -#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */ -#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */ -#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */ -#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */ -#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */ -#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */ -#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */ -#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */ -#define GPIO_SEL_20 (BIT(20)) /*!< Pin 20 selected */ -#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */ - -#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */ -#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */ -#define GPIO_SEL_28 (BIT(28)) /*!< Pin 28 selected */ -#define GPIO_SEL_29 (BIT(29)) /*!< Pin 29 selected */ -#define GPIO_SEL_30 (BIT(30)) /*!< Pin 30 selected */ -#define GPIO_SEL_31 (BIT(31)) /*!< Pin 31 selected */ -#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */ -#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */ -#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */ -#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */ -#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */ -#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */ -#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ -#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ -#define GPIO_SEL_40 ((uint64_t)(((uint64_t)1)<<40)) /*!< Pin 40 selected */ -#define GPIO_SEL_41 ((uint64_t)(((uint64_t)1)<<41)) /*!< Pin 41 selected */ -#define GPIO_SEL_42 ((uint64_t)(((uint64_t)1)<<42)) /*!< Pin 42 selected */ -#define GPIO_SEL_43 ((uint64_t)(((uint64_t)1)<<43)) /*!< Pin 43 selected */ -#define GPIO_SEL_44 ((uint64_t)(((uint64_t)1)<<44)) /*!< Pin 44 selected */ -#define GPIO_SEL_45 ((uint64_t)(((uint64_t)1)<<45)) /*!< Pin 45 selected */ -#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */ -#endif - -#if CONFIG_IDF_TARGET_ESP32 -#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG -#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG -#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG -#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG -#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG -#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG -#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG -#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG -#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG -#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG -#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG -#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG -#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG -#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG -#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG -#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG -#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG -#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG -#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG -#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG -#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG -#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG -#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG -#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG -#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG -#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG -#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG -#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG -#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG -#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG -#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG -#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG -#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG -#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG -#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG -#elif CONFIG_IDF_TARGET_ESP32S2BETA -#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG -#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG -#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG -#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG -#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG -#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG -#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG -#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG -#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG -#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG -#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG -#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG -#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG -#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG -#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG -#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG -#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG -#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG -#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG -#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG -#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG -#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG -#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG -#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG -#define GPIO_PIN_REG_24 IO_MUX_GPIO24_REG -#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG -#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG -#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG -#define GPIO_PIN_REG_28 IO_MUX_GPIO28_REG -#define GPIO_PIN_REG_29 IO_MUX_GPIO29_REG -#define GPIO_PIN_REG_30 IO_MUX_GPIO30_REG -#define GPIO_PIN_REG_31 IO_MUX_GPIO31_REG -#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG -#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG -#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG -#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG -#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG -#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG -#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG -#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG -#define GPIO_PIN_REG_40 IO_MUX_GPIO40_REG -#define GPIO_PIN_REG_41 IO_MUX_GPIO41_REG -#define GPIO_PIN_REG_42 IO_MUX_GPIO42_REG -#define GPIO_PIN_REG_43 IO_MUX_GPIO43_REG -#define GPIO_PIN_REG_44 IO_MUX_GPIO44_REG -#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG -#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG -#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG -#endif - -#if CONFIG_IDF_TARGET_ESP32 -#define GPIO_APP_CPU_INTR_ENA (BIT(0)) -#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1)) -#define GPIO_PRO_CPU_INTR_ENA (BIT(2)) -#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3)) -#define GPIO_SDIO_EXT_INTR_ENA (BIT(4)) -#elif CONFIG_IDF_TARGET_ESP32S2BETA -#define GPIO_PRO_CPU_INTR_ENA (BIT(0)) -#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1)) -#endif - -#define GPIO_MODE_DEF_DISABLE (0) -#define GPIO_MODE_DEF_INPUT (BIT0) -#define GPIO_MODE_DEF_OUTPUT (BIT1) -#define GPIO_MODE_DEF_OD (BIT2) - - -/** @endcond */ - -#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */ -#if CONFIG_IDF_TARGET_ESP32 -#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) /*!< Check whether it can be a valid GPIO number of output mode */ -#elif CONFIG_IDF_TARGET_ESP32S2BETA -#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */ -#endif - -typedef enum { - GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ - GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */ - GPIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */ - GPIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */ - GPIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */ - GPIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */ - GPIO_INTR_MAX, -} gpio_int_type_t; - -typedef enum { - GPIO_MODE_DISABLE = GPIO_MODE_DEF_DISABLE, /*!< GPIO mode : disable input and output */ - GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT, /*!< GPIO mode : input only */ - GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT, /*!< GPIO mode : output only mode */ - GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /*!< GPIO mode : output only with open-drain mode */ - GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /*!< GPIO mode : output and input with open-drain mode*/ - GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)), /*!< GPIO mode : output and input mode */ -} gpio_mode_t; - -typedef enum { - GPIO_PULLUP_DISABLE = 0x0, /*!< Disable GPIO pull-up resistor */ - GPIO_PULLUP_ENABLE = 0x1, /*!< Enable GPIO pull-up resistor */ -} gpio_pullup_t; - -typedef enum { - GPIO_PULLDOWN_DISABLE = 0x0, /*!< Disable GPIO pull-down resistor */ - GPIO_PULLDOWN_ENABLE = 0x1, /*!< Enable GPIO pull-down resistor */ -} gpio_pulldown_t; - -/** - * @brief Configuration parameters of GPIO pad for gpio_config function - */ -typedef struct { - uint64_t pin_bit_mask; /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */ - gpio_mode_t mode; /*!< GPIO mode: set input/output mode */ - gpio_pullup_t pull_up_en; /*!< GPIO pull-up */ - gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */ - gpio_int_type_t intr_type; /*!< GPIO interrupt type */ -} gpio_config_t; - -typedef enum { - GPIO_PULLUP_ONLY, /*!< Pad pull up */ - GPIO_PULLDOWN_ONLY, /*!< Pad pull down */ - GPIO_PULLUP_PULLDOWN, /*!< Pad pull up + pull down*/ - GPIO_FLOATING, /*!< Pad floating */ -} gpio_pull_mode_t; - -typedef enum { - GPIO_DRIVE_CAP_0 = 0, /*!< Pad drive capability: weak */ - GPIO_DRIVE_CAP_1 = 1, /*!< Pad drive capability: stronger */ - GPIO_DRIVE_CAP_2 = 2, /*!< Pad drive capability: default value */ - GPIO_DRIVE_CAP_DEFAULT = 2, /*!< Pad drive capability: default value */ - GPIO_DRIVE_CAP_3 = 3, /*!< Pad drive capability: strongest */ - GPIO_DRIVE_CAP_MAX, -} gpio_drive_cap_t; - -typedef void (*gpio_isr_t)(void*); typedef intr_handle_t gpio_isr_handle_t; /** @@ -470,7 +207,7 @@ esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num); * - ESP_ERR_INVALID_ARG GPIO error * - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags */ -esp_err_t gpio_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, gpio_isr_handle_t *handle); +esp_err_t gpio_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, gpio_isr_handle_t *handle); /** * @brief Enable pull-up on GPIO. @@ -562,7 +299,7 @@ void gpio_uninstall_isr_service(void); * - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized. * - ESP_ERR_INVALID_ARG Parameter error */ -esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void* args); +esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void *args); /** * @brief Remove ISR handler for the corresponding GPIO pin. @@ -598,7 +335,7 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error */ -esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength); +esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *strength); /** * @brief Enable gpio pad hold function. @@ -626,7 +363,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num); * @brief Disable gpio pad hold function. * * When the chip is woken up from Deep-sleep, the gpio will be set to the default mode, so, the gpio will output - * the default level if this function is called. If you dont't want the level changes, the gpio should be configured to + * the default level if this function is called. If you don't want the level changes, the gpio should be configured to * a known state before this function is called. * e.g. * If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called, @@ -670,7 +407,7 @@ void gpio_iomux_in(uint32_t gpio_num, uint32_t signal_idx); * @param gpio_num gpio_num GPIO number of the pad. * @param func The function number of the peripheral pin to output pin. * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. - * @param oen_inv True if the output enable needs to be inversed, otherwise False. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. */ void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv); @@ -692,4 +429,3 @@ esp_err_t gpio_force_unhold_all(void); } #endif -#endif /* _DRIVER_GPIO_H_ */ diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index b8436c984c..f90e483e80 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -28,6 +28,7 @@ list(APPEND srcs "src/hal/ledc_hal_iram.c" "src/hal/i2c_hal.c" "src/hal/i2c_hal_iram.c" + "src/hal/gpio_hal.c" ) # TODO: SPI Flash HAL for ESP32S2Beta also diff --git a/components/soc/esp32/gpio_periph.c b/components/soc/esp32/gpio_periph.c index 3534b7b3e5..d8a30b0af5 100644 --- a/components/soc/esp32/gpio_periph.c +++ b/components/soc/esp32/gpio_periph.c @@ -56,3 +56,46 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { IO_MUX_GPIO38_REG, IO_MUX_GPIO39_REG, }; + +const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = { + 0, + BIT(1), + 0, + BIT(0), + 0, + BIT(8), + BIT(2), + BIT(3), + BIT(4), + BIT(5), + BIT(6), + BIT(7), + 0, + 0, + 0, + 0, + BIT(9), + BIT(10), + BIT(11), + BIT(12), + 0, + BIT(14), + BIT(15), + BIT(16), + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; diff --git a/components/soc/esp32/include/hal/gpio_ll.h b/components/soc/esp32/include/hal/gpio_ll.h new file mode 100644 index 0000000000..5fa8f5e680 --- /dev/null +++ b/components/soc/esp32/include/hal/gpio_ll.h @@ -0,0 +1,411 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32 GPIO register operations + +#pragma once + +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/rtc_io_reg.h" +#include "hal/gpio_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get GPIO hardware instance with giving gpio num +#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) + +/** + * @brief Enable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Disable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Enable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief Disable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief GPIO set interrupt trigger type + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; +} + +/** + * @brief Get GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status + */ +static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = (core_id == 0) ? hw->pcpu_int : hw->acpu_int; +} + +/** + * @brief Get GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status high + */ +static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = (core_id == 0) ? hw->pcpu_int1.intr : hw->acpu_int1.intr; +} + +/** + * @brief Clear GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status clear mask + */ +static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) +{ + hw->status_w1tc = mask; +} + +/** + * @brief Clear GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status high clear mask + */ +static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) +{ + hw->status1_w1tc.intr_st = mask; +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id Interrupt enabled CPU to corresponding ID + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num) +{ + if (core_id == 0) { + hw->pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr + } else { + hw->pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr + } +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].int_ena = 0; //disable GPIO intr +} + +/** + * @brief Disable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + hw->enable_w1tc = (0x1 << gpio_num); + } else { + hw->enable1_w1tc.data = (0x1 << (gpio_num - 32)); + } + + // Ensure no other output signal is routed via GPIO matrix to this pin + REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), + SIG_GPIO_OUT_IDX); +} + +/** + * @brief Enable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + hw->enable_w1ts = (0x1 << gpio_num); + } else { + hw->enable1_w1ts.data = (0x1 << (gpio_num - 32)); + } +} + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 0; +} + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 1; +} + +/** + * @brief GPIO set output level + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level) +{ + if (level) { + if (gpio_num < 32) { + hw->out_w1ts = (1 << gpio_num); + } else { + hw->out1_w1ts.data = (1 << (gpio_num - 32)); + } + } else { + if (gpio_num < 32) { + hw->out_w1tc = (1 << gpio_num); + } else { + hw->out1_w1tc.data = (1 << (gpio_num - 32)); + } + } +} + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + return (hw->in >> gpio_num) & 0x1; + } else { + return (hw->in1.data >> (gpio_num - 32)) & 0x1; + } +} + +/** + * @brief Enable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; + hw->pin[gpio_num].wakeup_enable = 0x1; +} + +/** + * @brief Disable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].wakeup_enable = 0; +} + +/** + * @brief Set GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength) +{ + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); +} + +/** + * @brief Get GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength) +{ + *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); +} + +/** + * @brief Enable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Disable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Enable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); +} + +/** + * @brief Disable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); +} + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) +{ + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); +} + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) +{ + hw->func_out_sel_cfg[gpio_num].oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/soc/esp32/include/soc/gpio_caps.h b/components/soc/esp32/include/soc/gpio_caps.h new file mode 100644 index 0000000000..8ad1bd5526 --- /dev/null +++ b/components/soc/esp32/include/soc/gpio_caps.h @@ -0,0 +1,172 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32 has 1 GPIO peripheral +#define GPIO_PORT_0 (0) /*!< GPIO port 0 */ +#define GPIO_PORT_MAX (1) /*!< GPIO port max */ +#define SOC_GPIO_PORT (GPIO_PORT_MAX) +#define GPIO_PIN_COUNT (40) + +#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ +#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ +#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected + @note There are more macros + like that up to pin 39, + excluding pins 20, 24 and 28..31. + They are not shown here + to reduce redundant information. */ +/** @cond */ +#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */ +#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */ +#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */ +#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */ +#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */ +#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */ +#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */ +#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */ +#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */ +#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */ +#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */ +#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */ +#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */ +#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */ +#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */ +#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */ +#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */ + +#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */ +#define GPIO_SEL_22 (BIT(22)) /*!< Pin 22 selected */ +#define GPIO_SEL_23 (BIT(23)) /*!< Pin 23 selected */ + +#define GPIO_SEL_25 (BIT(25)) /*!< Pin 25 selected */ +#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */ +#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */ + +#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */ +#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */ +#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */ +#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */ +#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */ +#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */ +#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ +#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ + +#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG +#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG +#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG +#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG +#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG +#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG +#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG +#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG +#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG +#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG +#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG +#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG +#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG +#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG +#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG +#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG +#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG +#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG +#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG +#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG +#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG +#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG +#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG +#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG +#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG +#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG +#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG +#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG +#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG +#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG +#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG +#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG +#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG +#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG +#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG + +#define GPIO_APP_CPU_INTR_ENA (BIT(0)) +#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1)) +#define GPIO_PRO_CPU_INTR_ENA (BIT(2)) +#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3)) +#define GPIO_SDIO_EXT_INTR_ENA (BIT(4)) + +#define GPIO_MODE_DEF_DISABLE (0) +#define GPIO_MODE_DEF_INPUT (BIT0) +#define GPIO_MODE_DEF_OUTPUT (BIT1) +#define GPIO_MODE_DEF_OD (BIT2) + +/** @endcond */ + +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */ +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) /*!< Check whether it can be a valid GPIO number of output mode */ +#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) /*!< Check whether it contains input io */ + +#define GPIO_NUM_NC (-1) /*!< Use to signal not connected to S/W */ +#define GPIO_NUM_0 (0) /*!< GPIO0, input and output */ +#define GPIO_NUM_1 (1) /*!< GPIO1, input and output */ +#define GPIO_NUM_2 (2) /*!< GPIO2, input and output + @note There are more enumerations like that + up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31. + They are not shown here to reduce redundant information. + @note GPIO34..39 are input mode only. */ + /** @cond */ +#define GPIO_NUM_3 (3) /*!< GPIO3, input and output */ +#define GPIO_NUM_4 (4) /*!< GPIO4, input and output */ +#define GPIO_NUM_5 (5) /*!< GPIO5, input and output */ +#define GPIO_NUM_6 (6) /*!< GPIO6, input and output */ +#define GPIO_NUM_7 (7) /*!< GPIO7, input and output */ +#define GPIO_NUM_8 (8) /*!< GPIO8, input and output */ +#define GPIO_NUM_9 (9) /*!< GPIO9, input and output */ +#define GPIO_NUM_10 (10) /*!< GPIO10, input and output */ +#define GPIO_NUM_11 (11) /*!< GPIO11, input and output */ +#define GPIO_NUM_12 (12) /*!< GPIO12, input and output */ +#define GPIO_NUM_13 (13) /*!< GPIO13, input and output */ +#define GPIO_NUM_14 (14) /*!< GPIO14, input and output */ +#define GPIO_NUM_15 (15) /*!< GPIO15, input and output */ +#define GPIO_NUM_16 (16) /*!< GPIO16, input and output */ +#define GPIO_NUM_17 (17) /*!< GPIO17, input and output */ +#define GPIO_NUM_18 (18) /*!< GPIO18, input and output */ +#define GPIO_NUM_19 (19) /*!< GPIO19, input and output */ + +#define GPIO_NUM_21 (21) /*!< GPIO21, input and output */ +#define GPIO_NUM_22 (22) /*!< GPIO22, input and output */ +#define GPIO_NUM_23 (23) /*!< GPIO23, input and output */ + +#define GPIO_NUM_25 (25) /*!< GPIO25, input and output */ +#define GPIO_NUM_26 (26) /*!< GPIO26, input and output */ +#define GPIO_NUM_27 (27) /*!< GPIO27, input and output */ + +#define GPIO_NUM_32 (32) /*!< GPIO32, input and output */ +#define GPIO_NUM_33 (33) /*!< GPIO33, input and output */ +#define GPIO_NUM_34 (34) /*!< GPIO34, input mode only */ +#define GPIO_NUM_35 (35) /*!< GPIO35, input mode only */ +#define GPIO_NUM_36 (36) /*!< GPIO36, input mode only */ +#define GPIO_NUM_37 (37) /*!< GPIO37, input mode only */ +#define GPIO_NUM_38 (38) /*!< GPIO38, input mode only */ +#define GPIO_NUM_39 (39) /*!< GPIO39, input mode only */ +#define GPIO_NUM_MAX (40) + /** @endcond */ + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/gpio_pins.h b/components/soc/esp32/include/soc/gpio_pins.h deleted file mode 100644 index 6c2bfb7418..0000000000 --- a/components/soc/esp32/include/soc/gpio_pins.h +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _GPIO_PINS_H -#define _GPIO_PINS_H -#ifdef __cplusplus -extern "C" -{ -#endif - -#define GPIO_PIN_COUNT 40 - -#ifdef __cplusplus -} -#endif - -#endif // _GPIO_PINS_H diff --git a/components/soc/esp32s2beta/gpio_periph.c b/components/soc/esp32s2beta/gpio_periph.c index 79e5c87c8e..03ef9143b1 100644 --- a/components/soc/esp32s2beta/gpio_periph.c +++ b/components/soc/esp32s2beta/gpio_periph.c @@ -64,3 +64,54 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { IO_MUX_GPIO46_REG, 0, }; + +const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + BIT(1), + BIT(2), + BIT(3), + BIT(4), + BIT(5), + BIT(6), + BIT(7), + BIT(8), + BIT(9), + BIT(10), + BIT(11), + BIT(12), + BIT(13), + BIT(14), + BIT(15), + BIT(16), + BIT(17), + BIT(18), + BIT(19), + BIT(20), + BIT(21), + BIT(22), + BIT(23), + BIT(24), + BIT(25), + BIT(26), +}; diff --git a/components/soc/esp32s2beta/include/hal/gpio_ll.h b/components/soc/esp32s2beta/include/hal/gpio_ll.h new file mode 100644 index 0000000000..cd1f43ee9a --- /dev/null +++ b/components/soc/esp32s2beta/include/hal/gpio_ll.h @@ -0,0 +1,409 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32 GPIO register operations + +#pragma once + +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/rtc_io_reg.h" +#include "hal/gpio_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get GPIO hardware instance with giving gpio num +#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) + +/** + * @brief Enable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Disable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Enable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief Disable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief GPIO set interrupt trigger type + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; +} + +/** + * @brief Get GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status + */ +static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = hw->pcpu_int; +} + +/** + * @brief Get GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status high + */ +static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = hw->pcpu_int1.intr; +} + +/** + * @brief Clear GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status clear mask + */ +static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) +{ + hw->status_w1tc = mask; +} + +/** + * @brief Clear GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status high clear mask + */ +static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) +{ + hw->status1_w1tc.intr_st = mask; +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id Interrupt enabled CPU to corresponding ID + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num) +{ + if (core_id == 0) { + GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr + } +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].int_ena = 0; //disable GPIO intr +} + +/** + * @brief Disable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + hw->enable_w1tc = (0x1 << gpio_num); + } else { + hw->enable1_w1tc.data = (0x1 << (gpio_num - 32)); + } + + // Ensure no other output signal is routed via GPIO matrix to this pin + REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), + SIG_GPIO_OUT_IDX); +} + +/** + * @brief Enable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + hw->enable_w1ts = (0x1 << gpio_num); + } else { + hw->enable1_w1ts.data = (0x1 << (gpio_num - 32)); + } +} + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 0; +} + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 1; +} + +/** + * @brief GPIO set output level + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level) +{ + if (level) { + if (gpio_num < 32) { + hw->out_w1ts = (1 << gpio_num); + } else { + hw->out1_w1ts.data = (1 << (gpio_num - 32)); + } + } else { + if (gpio_num < 32) { + hw->out_w1tc = (1 << gpio_num); + } else { + hw->out1_w1tc.data = (1 << (gpio_num - 32)); + } + } +} + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + return (hw->in >> gpio_num) & 0x1; + } else { + return (hw->in1.data >> (gpio_num - 32)) & 0x1; + } +} + +/** + * @brief Enable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; + hw->pin[gpio_num].wakeup_enable = 0x1; +} + +/** + * @brief Disable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].wakeup_enable = 0; +} + +/** + * @brief Set GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength) +{ + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); +} + +/** + * @brief Get GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength) +{ + *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); +} + +/** + * @brief Enable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Disable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); +} + +/** + * @brief Enable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); +} + +/** + * @brief Disable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); +} + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) +{ + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); +} + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) +{ + hw->func_out_sel_cfg[gpio_num].oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/soc/esp32s2beta/include/soc/gpio_caps.h b/components/soc/esp32s2beta/include/soc/gpio_caps.h new file mode 100644 index 0000000000..f525d81eea --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/gpio_caps.h @@ -0,0 +1,189 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32-S2 has 1 GPIO peripheral +#define GPIO_PORT_0 (0) /*!< GPIO port 0 */ +#define GPIO_PORT_MAX (1) /*!< GPIO port max */ +#define SOC_GPIO_PORT (GPIO_PORT_MAX) +#define GPIO_PIN_COUNT (48) + +#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ +#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ +#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */ +#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */ +#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */ +#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */ +#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */ +#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */ +#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */ +#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */ +#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */ +#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */ +#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */ +#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */ +#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */ +#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */ +#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */ +#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */ +#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */ +#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */ +#define GPIO_SEL_20 (BIT(20)) /*!< Pin 20 selected */ +#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */ + +#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */ +#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */ +#define GPIO_SEL_28 (BIT(28)) /*!< Pin 28 selected */ +#define GPIO_SEL_29 (BIT(29)) /*!< Pin 29 selected */ +#define GPIO_SEL_30 (BIT(30)) /*!< Pin 30 selected */ +#define GPIO_SEL_31 (BIT(31)) /*!< Pin 31 selected */ +#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */ +#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */ +#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */ +#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */ +#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */ +#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */ +#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ +#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ +#define GPIO_SEL_40 ((uint64_t)(((uint64_t)1)<<40)) /*!< Pin 40 selected */ +#define GPIO_SEL_41 ((uint64_t)(((uint64_t)1)<<41)) /*!< Pin 41 selected */ +#define GPIO_SEL_42 ((uint64_t)(((uint64_t)1)<<42)) /*!< Pin 42 selected */ +#define GPIO_SEL_43 ((uint64_t)(((uint64_t)1)<<43)) /*!< Pin 43 selected */ +#define GPIO_SEL_44 ((uint64_t)(((uint64_t)1)<<44)) /*!< Pin 44 selected */ +#define GPIO_SEL_45 ((uint64_t)(((uint64_t)1)<<45)) /*!< Pin 45 selected */ +#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */ + +#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG +#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG +#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG +#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG +#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG +#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG +#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG +#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG +#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG +#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG +#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG +#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG +#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG +#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG +#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG +#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG +#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG +#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG +#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG +#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG +#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG +#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG +#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG +#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG +#define GPIO_PIN_REG_24 IO_MUX_GPIO24_REG +#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG +#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG +#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG +#define GPIO_PIN_REG_28 IO_MUX_GPIO28_REG +#define GPIO_PIN_REG_29 IO_MUX_GPIO29_REG +#define GPIO_PIN_REG_30 IO_MUX_GPIO30_REG +#define GPIO_PIN_REG_31 IO_MUX_GPIO31_REG +#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG +#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG +#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG +#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG +#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG +#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG +#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG +#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG +#define GPIO_PIN_REG_40 IO_MUX_GPIO40_REG +#define GPIO_PIN_REG_41 IO_MUX_GPIO41_REG +#define GPIO_PIN_REG_42 IO_MUX_GPIO42_REG +#define GPIO_PIN_REG_43 IO_MUX_GPIO43_REG +#define GPIO_PIN_REG_44 IO_MUX_GPIO44_REG +#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG +#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG +#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG + +#define GPIO_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1)) + +#define GPIO_MODE_DEF_DISABLE (0) +#define GPIO_MODE_DEF_INPUT (BIT0) +#define GPIO_MODE_DEF_OUTPUT (BIT1) +#define GPIO_MODE_DEF_OD (BIT2) + + +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */ +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */ +#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */ + +#define GPIO_NUM_NC (-1) /*!< Use to signal not connected to S/W */ +#define GPIO_NUM_0 (0) /*!< GPIO0, input and output */ +#define GPIO_NUM_1 (1) /*!< GPIO1, input and output */ +#define GPIO_NUM_2 (2) /*!< GPIO2, input and output + @note There are more enumerations like that + up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31. + They are not shown here to reduce redundant information. + @note GPIO34..39 are input mode only. */ + /** @cond */ +#define GPIO_NUM_3 (3) /*!< GPIO3, input and output */ +#define GPIO_NUM_4 (4) /*!< GPIO4, input and output */ +#define GPIO_NUM_5 (5) /*!< GPIO5, input and output */ +#define GPIO_NUM_6 (6) /*!< GPIO6, input and output */ +#define GPIO_NUM_7 (7) /*!< GPIO7, input and output */ +#define GPIO_NUM_8 (8) /*!< GPIO8, input and output */ +#define GPIO_NUM_9 (9) /*!< GPIO9, input and output */ +#define GPIO_NUM_10 (10) /*!< GPIO10, input and output */ +#define GPIO_NUM_11 (11) /*!< GPIO11, input and output */ +#define GPIO_NUM_12 (12) /*!< GPIO12, input and output */ +#define GPIO_NUM_13 (13) /*!< GPIO13, input and output */ +#define GPIO_NUM_14 (14) /*!< GPIO14, input and output */ +#define GPIO_NUM_15 (15) /*!< GPIO15, input and output */ +#define GPIO_NUM_16 (16) /*!< GPIO16, input and output */ +#define GPIO_NUM_17 (17) /*!< GPIO17, input and output */ +#define GPIO_NUM_18 (18) /*!< GPIO18, input and output */ +#define GPIO_NUM_19 (19) /*!< GPIO19, input and output */ + +#define GPIO_NUM_21 (21) /*!< GPIO21, input and output */ +#define GPIO_NUM_22 (22) /*!< GPIO22, input and output */ +#define GPIO_NUM_23 (23) /*!< GPIO23, input and output */ + +#define GPIO_NUM_25 (25) /*!< GPIO25, input and output */ +#define GPIO_NUM_26 (26) /*!< GPIO26, input and output */ +#define GPIO_NUM_27 (27) /*!< GPIO27, input and output */ + +#define GPIO_NUM_32 (32) /*!< GPIO32, input and output */ +#define GPIO_NUM_33 (33) /*!< GPIO33, input and output */ +#define GPIO_NUM_34 (34) /*!< GPIO34, input mode only */ +#define GPIO_NUM_35 (35) /*!< GPIO35, input mode only */ +#define GPIO_NUM_36 (36) /*!< GPIO36, input mode only */ +#define GPIO_NUM_37 (37) /*!< GPIO37, input mode only */ +#define GPIO_NUM_38 (38) /*!< GPIO38, input mode only */ +#define GPIO_NUM_39 (39) /*!< GPIO39, input mode only */ +#define GPIO_NUM_40 (40) /*!< GPIO40, input and output */ +#define GPIO_NUM_41 (41) /*!< GPIO41, input and output */ +#define GPIO_NUM_42 (42) /*!< GPIO42, input and output */ +#define GPIO_NUM_43 (43) /*!< GPIO43, input and output */ +#define GPIO_NUM_44 (44) /*!< GPIO44, input and output */ +#define GPIO_NUM_45 (45) /*!< GPIO45, input and output */ +#define GPIO_NUM_46 (46) /*!< GPIO46, input mode only */ +#define GPIO_NUM_MAX (47) + /** @endcond */ + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2beta/include/soc/gpio_pins.h b/components/soc/esp32s2beta/include/soc/gpio_pins.h deleted file mode 100644 index da8cd2ebe6..0000000000 --- a/components/soc/esp32s2beta/include/soc/gpio_pins.h +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _GPIO_PINS_H -#define _GPIO_PINS_H -#ifdef __cplusplus -extern "C" -{ -#endif - -#define GPIO_PIN_COUNT 48 - -#ifdef __cplusplus -} -#endif - -#endif // _GPIO_PINS_H diff --git a/components/soc/include/hal/gpio_hal.h b/components/soc/include/hal/gpio_hal.h new file mode 100644 index 0000000000..cc948507ff --- /dev/null +++ b/components/soc/include/hal/gpio_hal.h @@ -0,0 +1,324 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The HAL layer for GPIO + +#pragma once + +#include "soc/gpio_periph.h" +#include "hal/gpio_ll.h" +#include "hal/gpio_types.h" + +#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS +#include "soc/rtc_io_reg.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// Get GPIO hardware instance with giving gpio num +#define GPIO_HAL_GET_HW(num) GPIO_LL_GET_HW(num) + +/** + * Context that should be maintained by both the driver and the HAL + */ + +typedef struct { + gpio_dev_t *dev; + uint32_t version; +} gpio_hal_context_t; + +/** + * @brief Enable pull-up on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_pullup_en(hal, gpio_num) gpio_ll_pullup_en((hal)->dev, gpio_num) + +/** + * @brief Disable pull-up on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_pullup_dis(hal, gpio_num) gpio_ll_pullup_dis((hal)->dev, gpio_num) + +/** + * @brief Enable pull-down on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_pulldown_en(hal, gpio_num) gpio_ll_pulldown_en((hal)->dev, gpio_num) + +/** + * @brief Disable pull-down on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_pulldown_dis(hal, gpio_num) gpio_ll_pulldown_dis((hal)->dev, gpio_num) + +/** + * @brief GPIO set interrupt trigger type + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +#define gpio_hal_set_intr_type(hal, gpio_num, intr_type) gpio_ll_set_intr_type((hal)->dev, gpio_num, intr_type) + +/** + * @brief Get GPIO interrupt status + * + * @param hal Context of the HAL layer + * @param core_id interrupt core id + * @param status interrupt status + */ +#define gpio_hal_get_intr_status(hal, core_id, status) gpio_ll_get_intr_status((hal)->dev, core_id, status) + +/** + * @brief Get GPIO interrupt status high + * + * @param hal Context of the HAL layer + * @param core_id interrupt core id + * @param status interrupt status high + */ +#define gpio_hal_get_intr_status_high(hal, core_id, status) gpio_ll_get_intr_status_high((hal)->dev, core_id, status) + +/** + * @brief Clear GPIO interrupt status + * + * @param hal Context of the HAL layer + * @param mask interrupt status clear mask + */ +#define gpio_hal_clear_intr_status(hal, mask) gpio_ll_clear_intr_status((hal)->dev, mask) + +/** + * @brief Clear GPIO interrupt status high + * + * @param hal Context of the HAL layer + * @param mask interrupt status high clear mask + */ +#define gpio_hal_clear_intr_status_high(hal, mask) gpio_ll_clear_intr_status_high((hal)->dev, mask) + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param core_id Interrupt enabled CPU to corresponding ID + */ +void gpio_hal_intr_enable_on_core(gpio_hal_context_t *hal, gpio_num_t gpio_num, uint32_t core_id); + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num); + +/** + * @brief Disable input mode on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_input_disable(hal, gpio_num) gpio_ll_input_disable((hal)->dev, gpio_num) + +/** + * @brief Enable input mode on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_input_enable(hal, gpio_num) gpio_ll_input_enable((hal)->dev, gpio_num) + +/** + * @brief Disable output mode on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_output_disable(hal, gpio_num) gpio_ll_output_disable((hal)->dev, gpio_num) + +/** + * @brief Enable output mode on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_output_enable(hal, gpio_num) gpio_ll_output_enable((hal)->dev, gpio_num) + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_od_disable(hal, gpio_num) gpio_ll_od_disable((hal)->dev, gpio_num) + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_od_enable(hal, gpio_num) gpio_ll_od_enable((hal)->dev, gpio_num) + +/** + * @brief GPIO set output level + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +#define gpio_hal_set_level(hal, gpio_num, level) gpio_ll_set_level((hal)->dev, gpio_num, level) + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +#define gpio_hal_get_level(hal, gpio_num) gpio_ll_get_level((hal)->dev, gpio_num) + +/** + * @brief Enable GPIO wake-up function. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +#define gpio_hal_wakeup_enable(hal, gpio_num, intr_type) gpio_ll_wakeup_enable((hal)->dev, gpio_num, intr_type) + +/** + * @brief Disable GPIO wake-up function. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +#define gpio_hal_wakeup_disable(hal, gpio_num) gpio_ll_wakeup_disable((hal)->dev, gpio_num) + +/** + * @brief Set GPIO pad drive capability + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +#define gpio_hal_set_drive_capability(hal, gpio_num, strength) gpio_ll_set_drive_capability((hal)->dev, gpio_num, strength) + +/** + * @brief Get GPIO pad drive capability + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +#define gpio_hal_get_drive_capability(hal, gpio_num, strength) gpio_ll_get_drive_capability((hal)->dev, gpio_num, strength) + +/** + * @brief Enable gpio pad hold function. + * + * The gpio pad hold function works in both input and output modes, but must be output-capable gpios. + * If pad hold enabled: + * in output mode: the output level of the pad will be force locked and can not be changed. + * in input mode: the input value read will not change, regardless the changes of input signal. + * + * The state of digital gpio cannot be held during Deep-sleep, and it will resume the hold function + * when the chip wakes up from Deep-sleep. If the digital gpio also needs to be held during Deep-sleep, + * `gpio_deep_sleep_hold_en` should also be called. + * + * Power down or call gpio_hold_dis will disable this function. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number, only support output GPIOs + */ +#define gpio_hal_hold_en(hal, gpio_num) gpio_ll_hold_en((hal)->dev, gpio_num) + +/** + * @brief Disable gpio pad hold function. + * + * When the chip is woken up from Deep-sleep, the gpio will be set to the default mode, so, the gpio will output + * the default level if this function is called. If you don't want the level changes, the gpio should be configured to + * a known state before this function is called. + * e.g. + * If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called, + * gpio18 will output low level(because gpio18 is input mode by default). If you don't want this behavior, + * you should configure gpio18 as output mode and set it to hight level before calling `gpio_hold_dis`. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number, only support output GPIOs + */ +#define gpio_hal_hold_dis(hal, gpio_num) gpio_ll_hold_dis((hal)->dev, gpio_num) + +/** + * @brief Enable all digital gpio pad hold function during Deep-sleep. + * + * When the chip is in Deep-sleep mode, all digital gpio will hold the state before sleep, and when the chip is woken up, + * the status of digital gpio will not be held. Note that the pad hold feature only works when the chip is in Deep-sleep mode, + * when not in sleep mode, the digital gpio state can be changed even you have called this function. + * + * Power down or call gpio_hold_dis will disable this function, otherwise, the digital gpio hold feature works as long as the chip enter Deep-sleep. + * + * @param hal Context of the HAL layer + */ +#define gpio_hal_deep_sleep_hold_en(hal) gpio_ll_deep_sleep_hold_en((hal)->dev) + +/** + * @brief Disable all digital gpio pad hold function during Deep-sleep. + * + * @param hal Context of the HAL layer + */ +#define gpio_hal_deep_sleep_hold_dis(hal) gpio_ll_deep_sleep_hold_dis((hal)->dev) + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +#define gpio_hal_iomux_in(hal, gpio_num, signal_idx) gpio_ll_iomux_in((hal)->dev, gpio_num, signal_idx) + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hal Context of the HAL layer + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +#define gpio_hal_iomux_out(hal, gpio_num, func, oen_inv) gpio_ll_iomux_out((hal)->dev, gpio_num, func, oen_inv) + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/soc/include/hal/gpio_types.h b/components/soc/include/hal/gpio_types.h index 1b0c46c143..bf8ac7f7e3 100644 --- a/components/soc/include/hal/gpio_types.h +++ b/components/soc/include/hal/gpio_types.h @@ -1,51 +1,86 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #pragma once -#include "soc/gpio_pins.h" +#include "soc/gpio_periph.h" +#include "soc/gpio_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int gpio_num_t; typedef enum { - GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ - GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ - GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ - GPIO_NUM_2 = 2, /*!< GPIO2, input and output - @note There are more enumerations like that - up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31. - They are not shown here to reduce redundant information. - @note GPIO34..39 are input mode only. */ -/** @cond */ - GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ - GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ - GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ - GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ - GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ - GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ - GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ - GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ - GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ - GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ - GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ - GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ - GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ - GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ - GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ - GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ - GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ + GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */ + GPIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */ + GPIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */ + GPIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */ + GPIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */ + GPIO_INTR_MAX, +} gpio_int_type_t; - GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ - GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ +typedef enum { + GPIO_MODE_DISABLE = GPIO_MODE_DEF_DISABLE, /*!< GPIO mode : disable input and output */ + GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT, /*!< GPIO mode : input only */ + GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT, /*!< GPIO mode : output only mode */ + GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD)), /*!< GPIO mode : output only with open-drain mode */ + GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT) | (GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD)), /*!< GPIO mode : output and input with open-drain mode*/ + GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT) | (GPIO_MODE_DEF_OUTPUT)), /*!< GPIO mode : output and input mode */ +} gpio_mode_t; - GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ - GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ - GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ +typedef enum { + GPIO_PULLUP_DISABLE = 0x0, /*!< Disable GPIO pull-up resistor */ + GPIO_PULLUP_ENABLE = 0x1, /*!< Enable GPIO pull-up resistor */ +} gpio_pullup_t; - GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ - GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ - GPIO_NUM_34 = 34, /*!< GPIO34, input mode only */ - GPIO_NUM_35 = 35, /*!< GPIO35, input mode only */ - GPIO_NUM_36 = 36, /*!< GPIO36, input mode only */ - GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */ - GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */ - GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */ - GPIO_NUM_MAX = 40, -/** @endcond */ -} gpio_num_t; \ No newline at end of file +typedef enum { + GPIO_PULLDOWN_DISABLE = 0x0, /*!< Disable GPIO pull-down resistor */ + GPIO_PULLDOWN_ENABLE = 0x1, /*!< Enable GPIO pull-down resistor */ +} gpio_pulldown_t; + +/** + * @brief Configuration parameters of GPIO pad for gpio_config function + */ +typedef struct { + uint64_t pin_bit_mask; /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */ + gpio_mode_t mode; /*!< GPIO mode: set input/output mode */ + gpio_pullup_t pull_up_en; /*!< GPIO pull-up */ + gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */ + gpio_int_type_t intr_type; /*!< GPIO interrupt type */ +} gpio_config_t; + +typedef enum { + GPIO_PULLUP_ONLY, /*!< Pad pull up */ + GPIO_PULLDOWN_ONLY, /*!< Pad pull down */ + GPIO_PULLUP_PULLDOWN, /*!< Pad pull up + pull down*/ + GPIO_FLOATING, /*!< Pad floating */ +} gpio_pull_mode_t; + +typedef enum { + GPIO_DRIVE_CAP_0 = 0, /*!< Pad drive capability: weak */ + GPIO_DRIVE_CAP_1 = 1, /*!< Pad drive capability: stronger */ + GPIO_DRIVE_CAP_2 = 2, /*!< Pad drive capability: medium */ + GPIO_DRIVE_CAP_DEFAULT = 2, /*!< Pad drive capability: medium */ + GPIO_DRIVE_CAP_3 = 3, /*!< Pad drive capability: strongest */ + GPIO_DRIVE_CAP_MAX, +} gpio_drive_cap_t; + +typedef void (*gpio_isr_t)(void *); + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/include/soc/gpio_periph.h b/components/soc/include/soc/gpio_periph.h index 306814557d..ee5d7c36ed 100644 --- a/components/soc/include/soc/gpio_periph.h +++ b/components/soc/include/soc/gpio_periph.h @@ -3,7 +3,7 @@ // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -14,10 +14,10 @@ #pragma once #include "stdint.h" -#include "soc/gpio_pins.h" #include "soc/io_mux_reg.h" #include "soc/gpio_struct.h" #include "soc/gpio_reg.h" +#include "soc/gpio_caps.h" #include "soc/gpio_sig_map.h" #ifdef __cplusplus @@ -27,6 +27,8 @@ extern "C" extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT]; +extern const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT]; + #ifdef __cplusplus } #endif diff --git a/components/soc/include/soc/rtc_periph.h b/components/soc/include/soc/rtc_periph.h index ace5489908..535245224d 100644 --- a/components/soc/include/soc/rtc_periph.h +++ b/components/soc/include/soc/rtc_periph.h @@ -15,7 +15,7 @@ #pragma once #include #include "rtc_io_periph.h" -#include "soc/gpio_pins.h" +#include "soc/gpio_caps.h" #ifdef __cplusplus extern "C" diff --git a/components/soc/src/hal/gpio_hal.c b/components/soc/src/hal/gpio_hal.c new file mode 100644 index 0000000000..4ce7d163a8 --- /dev/null +++ b/components/soc/src/hal/gpio_hal.c @@ -0,0 +1,40 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The HAL layer for GPIO (common part) + +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "hal/gpio_hal.h" +#include "esp32/rom/gpio.h" + +void gpio_hal_intr_enable_on_core(gpio_hal_context_t *hal, gpio_num_t gpio_num, uint32_t core_id) +{ + if (gpio_num < 32) { + gpio_ll_clear_intr_status(hal->dev, BIT(gpio_num)); + } else { + gpio_ll_clear_intr_status_high(hal->dev, BIT(gpio_num - 32)); + } + gpio_ll_intr_enable_on_core(hal->dev, core_id, gpio_num); +} + +void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num) +{ + gpio_ll_intr_disable(hal->dev, gpio_num); + if (gpio_num < 32) { + gpio_ll_clear_intr_status(hal->dev, BIT(gpio_num)); + } else { + gpio_ll_clear_intr_status_high(hal->dev, BIT(gpio_num - 32)); + } +} \ No newline at end of file diff --git a/docs/Doxyfile b/docs/Doxyfile index 4b22164cac..29018c521c 100644 --- a/docs/Doxyfile +++ b/docs/Doxyfile @@ -113,6 +113,7 @@ INPUT = \ ../../components/soc/include/hal/ledc_types.h \ ../../components/soc/include/hal/i2c_types.h \ ../../components/soc/include/hal/dac_types.h \ + ../../components/soc/include/hal/gpio_types.h \ ../../components/soc/esp32/include/soc/adc_channel.h \ ../../components/soc/esp32/include/soc/dac_channel.h \ ../../components/soc/esp32/include/soc/touch_channel.h \