alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'bugfix/fixed_some_wifi_bugs_240222_v5.2' into 'release/v5.2'

Browse Source 
fix(wifi): fixed some wifi bugs 240222 v5.2 (Backport v5.2)

See merge request espressif/esp-idf!29185
This commit is contained in:
Jiang Jiang Jian 2024-02-23 00:18:45 +08:00
commit a328e1a08f
14 changed files with 22 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -1635,9 +1635,9 @@ hal_mac_set_txq_invalid = 0x40001d60;
hal_mac_txq_disable = 0x40001d64; hal_mac_txq_disable = 0x40001d64;
hal_mac_is_txq_enabled = 0x40001d68; hal_mac_is_txq_enabled = 0x40001d68;
hal_mac_get_txq_pmd = 0x40001d6c; hal_mac_get_txq_pmd = 0x40001d6c;
lmacDiscardFrameExchangeSequence = 0x40001d70; /*lmacDiscardFrameExchangeSequence = 0x40001d70;*/
lmacDisableTransmit = 0x40001d74; /*lmacDisableTransmit = 0x40001d74;*/
lmacProcessTxTimeout = 0x40001d78; /*lmacProcessTxTimeout = 0x40001d78;*/
/*lmacProcessTxSuccess = 0x40001d7c;*/ /*lmacProcessTxSuccess = 0x40001d7c;*/
lmacProcessCollision = 0x40001d80; lmacProcessCollision = 0x40001d80;
lmacProcessTxRtsError = 0x40001d84; lmacProcessTxRtsError = 0x40001d84;
@ -1669,7 +1669,7 @@ mac_last_rxbuf_init = 0x40001de8;
hal_attenna_init = 0x40001dec; hal_attenna_init = 0x40001dec;
hal_timer_update_by_rtc = 0x40001df0; hal_timer_update_by_rtc = 0x40001df0;
hal_coex_pti_init = 0x40001df4; hal_coex_pti_init = 0x40001df4;
lmac_stop_hw_txq = 0x40001df8; /*lmac_stop_hw_txq = 0x40001df8;*/
ppDirectRecycleAmpdu = 0x40001dfc; ppDirectRecycleAmpdu = 0x40001dfc;
esp_wifi_internal_set_rts = 0x40001e00; esp_wifi_internal_set_rts = 0x40001e00;
esp_wifi_internal_get_rts = 0x40001e04; esp_wifi_internal_get_rts = 0x40001e04;
@ -1850,7 +1850,7 @@ ic_reset_rx_ba = 0x40001fa8;
ieee80211_align_eb = 0x40001fac; ieee80211_align_eb = 0x40001fac;
ieee80211_ampdu_reorder = 0x40001fb0; ieee80211_ampdu_reorder = 0x40001fb0;
ieee80211_ampdu_start_age_timer = 0x40001fb4; ieee80211_ampdu_start_age_timer = 0x40001fb4;
ieee80211_encap_esfbuf = 0x40001fb8; /*ieee80211_encap_esfbuf = 0x40001fb8;*/
ieee80211_is_tx_allowed = 0x40001fbc; ieee80211_is_tx_allowed = 0x40001fbc;
ieee80211_output_pending_eb = 0x40001fc0; ieee80211_output_pending_eb = 0x40001fc0;
/* ieee80211_output_process = 0x40001fc4; */ /* ieee80211_output_process = 0x40001fc4; */
@ -1860,7 +1860,7 @@ wifi_get_macaddr = 0x40001fd0;
wifi_rf_phy_disable = 0x40001fd4; wifi_rf_phy_disable = 0x40001fd4;
wifi_rf_phy_enable = 0x40001fd8; wifi_rf_phy_enable = 0x40001fd8;
ic_ebuf_alloc = 0x40001fdc; ic_ebuf_alloc = 0x40001fdc;
ieee80211_classify = 0x40001fe0; /*ieee80211_classify = 0x40001fe0;*/
ieee80211_copy_eb_header = 0x40001fe4; ieee80211_copy_eb_header = 0x40001fe4;
ieee80211_recycle_cache_eb = 0x40001fe8; ieee80211_recycle_cache_eb = 0x40001fe8;
ieee80211_search_node = 0x40001fec; ieee80211_search_node = 0x40001fec;

4
components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
View File

@ -35,8 +35,8 @@ wDev_ProcessRxSucData = 0x400017f4;
/*ppProcTxDone = 0x40001804;*/ /*ppProcTxDone = 0x40001804;*/
pm_tx_data_done_process = 0x40001808; pm_tx_data_done_process = 0x40001808;
ppMapWaitTxq = 0x40001810; ppMapWaitTxq = 0x40001810;
ieee80211_encap_esfbuf = 0x4000185c; /*ieee80211_encap_esfbuf = 0x4000185c;*/
sta_input = 0x40001870; /*sta_input = 0x40001870;*/
ieee80211_crypto_decap = 0x4000189c; ieee80211_crypto_decap = 0x4000189c;
ieee80211_decap = 0x400018a0; ieee80211_decap = 0x400018a0;
coex_core_timer_idx_get = 0x400018d0; coex_core_timer_idx_get = 0x400018d0;

2
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
View File

@ -1729,7 +1729,7 @@ wifi_get_macaddr = 0x40001874;
wifi_rf_phy_disable = 0x40001878; wifi_rf_phy_disable = 0x40001878;
wifi_rf_phy_enable = 0x4000187c; wifi_rf_phy_enable = 0x4000187c;
ic_ebuf_alloc = 0x40001880; ic_ebuf_alloc = 0x40001880;
ieee80211_classify = 0x40001884; /*ieee80211_classify = 0x40001884;*/
ieee80211_copy_eb_header = 0x40001888; ieee80211_copy_eb_header = 0x40001888;
ieee80211_recycle_cache_eb = 0x4000188c; ieee80211_recycle_cache_eb = 0x4000188c;
ieee80211_search_node = 0x40001890; ieee80211_search_node = 0x40001890;

4
components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld
View File

@ -33,7 +33,7 @@ ic_reset_rx_ba = 0x40000b78;
ieee80211_align_eb = 0x40000b7c; ieee80211_align_eb = 0x40000b7c;
ieee80211_ampdu_reorder = 0x40000b80; ieee80211_ampdu_reorder = 0x40000b80;
ieee80211_ampdu_start_age_timer = 0x40000b84; ieee80211_ampdu_start_age_timer = 0x40000b84;
ieee80211_encap_esfbuf = 0x40000b88; /*ieee80211_encap_esfbuf = 0x40000b88;*/
ieee80211_is_tx_allowed = 0x40000b8c; ieee80211_is_tx_allowed = 0x40000b8c;
ieee80211_output_pending_eb = 0x40000b90; ieee80211_output_pending_eb = 0x40000b90;
/*ieee80211_output_process = 0x40000b94;*/ /*ieee80211_output_process = 0x40000b94;*/
@ -43,7 +43,7 @@ wifi_get_macaddr = 0x40000ba0;
wifi_rf_phy_disable = 0x40000ba4; wifi_rf_phy_disable = 0x40000ba4;
wifi_rf_phy_enable = 0x40000ba8; wifi_rf_phy_enable = 0x40000ba8;
ic_ebuf_alloc = 0x40000bac; ic_ebuf_alloc = 0x40000bac;
ieee80211_classify = 0x40000bb0; /*ieee80211_classify = 0x40000bb0;*/
ieee80211_copy_eb_header = 0x40000bb4; ieee80211_copy_eb_header = 0x40000bb4;
ieee80211_recycle_cache_eb = 0x40000bb8; ieee80211_recycle_cache_eb = 0x40000bb8;
ieee80211_search_node = 0x40000bbc; ieee80211_search_node = 0x40000bbc;

2
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
View File

@ -2037,7 +2037,7 @@ wifi_get_macaddr = 0x40005ab4;
wifi_rf_phy_disable = 0x40005ac0; wifi_rf_phy_disable = 0x40005ac0;
wifi_rf_phy_enable = 0x40005acc; wifi_rf_phy_enable = 0x40005acc;
ic_ebuf_alloc = 0x40005ad8; ic_ebuf_alloc = 0x40005ad8;
ieee80211_classify = 0x40005ae4; /*ieee80211_classify = 0x40005ae4;*/
ieee80211_copy_eb_header = 0x40005af0; ieee80211_copy_eb_header = 0x40005af0;
ieee80211_recycle_cache_eb = 0x40005afc; ieee80211_recycle_cache_eb = 0x40005afc;
ieee80211_search_node = 0x40005b08; ieee80211_search_node = 0x40005b08;

2
components/esp_system/port/soc/esp32c2/clk.c
View File

@ -246,7 +246,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -289,7 +289,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32c6/clk.c
View File

@ -286,7 +286,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -280,7 +280,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32p4/clk.c
View File

@ -266,7 +266,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -306,7 +306,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0); DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M); DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL32K | DPORT_LPCLK_SEL_XTAL | DPORT_LPCLK_SEL_8M | DPORT_LPCLK_SEL_RTC_SLOW);
DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW); DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);

2
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -309,7 +309,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit 4457ec627eeabfaf38fa1f3d986917dbdf0849a7 Subproject commit 1334b6d87456cd999e713e645e5dcdc10c527efb

1
examples/protocols/esp_local_ctrl/sdkconfig.defaults
View File

@ -1 +1,2 @@
CONFIG_ESP_HTTPS_SERVER_ENABLE=y CONFIG_ESP_HTTPS_SERVER_ENABLE=y
CONFIG_COMPILER_OPTIMIZATION_SIZE=y