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esp32s2: Always use eFuse config for WP pin

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No reason to override just this pin in software.
This commit is contained in:
Angus Gratton 2020-07-07 14:54:20 +10:00 committed by chenjianqiang
parent c09fdc0b09
commit a2eed7cba6
2 changed files with 0 additions and 24 deletions
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16
components/esp32s2/Kconfig
View File

@ -182,22 +182,6 @@ menu "ESP32S2-specific"
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
endmenu
config SPIRAM_SPIWP_SD3_PIN
int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
range 0 33
default 28
help
This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been
overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
Different from esp32 chip, on esp32s2, the WP pin would also be defined in efuse. This value would only
be used if the WP pin recorded in efuse SPI_PAD_CONFIG_xxx is invalid.
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set as the value configured in
bootloader.
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n

8
components/esp32s2/spiram_psram.c
View File

@ -375,15 +375,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio();
}
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT
// WP/HD already configured in bootloader.
psram_io.psram_spiwp_sd3_io = (psram_io.psram_spiwp_sd3_io <= MAX_PAD_GPIO_NUM ? psram_io.psram_spiwp_sd3_io : CONFIG_BOOTLOADER_SPI_WP_PIN);
#else
psram_io.psram_spiwp_sd3_io = (psram_io.psram_spiwp_sd3_io <= MAX_PAD_GPIO_NUM ? psram_io.psram_spiwp_sd3_io : CONFIG_SPIRAM_SPIWP_SD3_PIN);
esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig);
#endif
}
psram_size_t psram_get_size(void)