test(intr): fix intr dump test on C5

tools/test_apps/system/.build-test-rules.yml

@@ -30,10 +30,6 @@ tools/test_apps/system/eh_frame:
       reason: the other targets are not tested yet
 
 tools/test_apps/system/esp_intr_dump:
-  disable_test:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: target test failed  # TODO [ESP32C5] IDF-10344
 
 tools/test_apps/system/g0_components:
   enable:

tools/test_apps/system/esp_intr_dump/expected_output/esp32c5.txt

@@ -0,0 +1,36 @@
+CPU 0 interrupt status:
+ Int  Level  Type   Status
+  0     1    Level  Used: FROM_CPU_INTR0
+  1     *      *    Reserved
+  2     1    Level  Used: SYSTIMER_TARGET0
+  3     1    Level  Used: TG0_WDT_LEVEL
+  4     1    Level  Used: UART0
+  5     *      *    Free
+  6     *      *    Reserved
+  7     *      *    Free
+  8     *      *    Free
+  9     *      *    Free
+ 10     *      *    Free
+ 11     *      *    Free
+ 12     *      *    Free
+ 13     *      *    Free
+ 14     *      *    Free
+ 15     *      *    Free
+ 16     *      *    Free
+ 17     *      *    Free
+ 18     *      *    Free
+ 19     *      *    Free
+ 20     *      *    Free
+ 21     *      *    Free
+ 22     *      *    Free
+ 23     *      *    Free
+ 24     *      *    Reserved
+ 25     *      *    Reserved
+ 26     *      *    Free
+ 27     *      *    Free
+ 28     *      *    Free
+ 29     *      *    Free
+ 30     *      *    Free
+ 31     *      *    Free
+Interrupts available for general use: 24
+Shared interrupts: 0

tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py

@@ -48,8 +48,6 @@ def test_esp_intr_dump_shared(dut: Dut) -> None:
 
 # TODO: IDF-9512, Update the expected output of dual core RISC-V chips when the issue is resolved
 @pytest.mark.supported_targets
-# TODO: [ESP32C5] IDF-10344
-@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='c5 test failed')
 @pytest.mark.generic
 def test_esp_intr_dump_expected_output(dut: Dut) -> None:
     dut.expect_exact(PROMPT, timeout=30)