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Merge branch 'bugfix/add_kconfig_help_for_eth_gpio0_output_mode_v3.2' into 'release/v3.2'

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ethernet: add kconfig help for GPIO0 output mode (v3.2)

See merge request espressif/esp-idf!6343
This commit is contained in:
Jiang Jiang Jian 2019-10-21 10:48:44 +08:00
commit a1c1175fa7
5 changed files with 42 additions and 28 deletions
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19
components/ethernet/emac_main.c
View File

@ -825,9 +825,9 @@ static void emac_start(void *param)
emac_mac_init();
/* check if enable promiscuous mode */
if(emac_config.promiscuous_enable){
if (emac_config.promiscuous_enable) {
emac_enable_promiscuous();
}else{
} else {
emac_disable_promiscuous();
}
@ -1116,12 +1116,15 @@ esp_err_t esp_eth_init_internal(eth_config_t *config)
if (emac_config.clock_mode != ETH_CLOCK_GPIO0_IN) {
#if CONFIG_SPIRAM_SUPPORT
if (esp_spiram_is_initialized()) {
ESP_LOGE(TAG, "GPIO16 and GPIO17 has been occupied by PSRAM, Only ETH_CLOCK_GPIO_IN is supported!");
ret = ESP_FAIL;
goto _verify_err;
} else {
ESP_LOGW(TAG, "GPIO16/17 is used for clock of EMAC, Please Make Sure you're not using PSRAM.");
// make sure Ethernet won't have conflict with PSRAM
if (emac_config.clock_mode >= ETH_CLOCK_GPIO16_OUT) {
if (esp_spiram_is_initialized()) {
ESP_LOGE(TAG, "GPIO16 and GPIO17 are occupied by PSRAM, please switch to ETH_CLOCK_GPIO_IN or ETH_CLOCK_GPIO_OUT mode");
ret = ESP_FAIL;
goto _verify_err;
} else {
ESP_LOGW(TAG, "Using GPIO16/17 to output Ethernet RMII clock, make sure you don't have PSRAM on board");
}
}
#endif
// 50 MHz = 40MHz * (6 + 4) / (2 * (2 + 2) = 400MHz / 8

14
components/ethernet/eth_phy/phy_lan8720.c
View File

@ -128,11 +128,11 @@ void phy_lan8720_dump_registers()
ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x17));
ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x18));
ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x26));
ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x27));
ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x29));
ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x30));
ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x31));
ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x11));
ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x12));
ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x1A));
ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x1B));
ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x1D));
ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x1E));
ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x1F));
}

18
examples/ethernet/ethernet/main/Kconfig.projbuild
View File

@ -2,7 +2,7 @@ menu "Example Configuration"
choice PHY_MODEL
prompt "Ethernet PHY Device"
default PHY_TLK110
default PHY_IP101
help
Select the PHY driver to use for the example.
config PHY_IP101
@ -24,7 +24,7 @@ menu "Example Configuration"
config PHY_ADDRESS
int "Ethernet PHY Address"
default 31
default 1
range 0 31
help
PHY Address of your PHY device. It dependens on your schematic design.
@ -39,9 +39,15 @@ menu "Example Configuration"
help
Input of 50MHz RMII clock on GPIO0.
config PHY_CLOCK_GPIO0_OUT
bool "GPIO0 Output"
bool "GPIO0 Output(READ HELP)"
help
Output the internal 50MHz RMII clock on GPIO0.
GPIO0 can be set to output a pre-divided PLL clock (test only!).
Enabling this option will configure GPIO0 to output a 50MHz clock.
In fact this clock doesn't have directly relationship with EMAC peripheral.
Sometimes this clock won't work well with your PHY chip. You might need to
add some extra devices after GPIO0 (e.g. inverter).
Note that outputting RMII clock on GPIO0 is an experimental practice.
If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
config PHY_CLOCK_GPIO16_OUT
bool "GPIO16 Output"
help
@ -61,7 +67,7 @@ menu "Example Configuration"
config PHY_USE_POWER_PIN
bool "Use PHY Power (enable / disable) pin"
default n
default y
help
Use a GPIO "power pin" to power the PHY on/off during operation.
When using GPIO0 to input RMII clock, the reset process will be interfered by this clock.
@ -70,7 +76,7 @@ menu "Example Configuration"
if PHY_USE_POWER_PIN
config PHY_POWER_PIN
int "PHY Power GPIO"
default 17
default 5
range 0 33
depends on PHY_USE_POWER_PIN
help

1
examples/ethernet/ethernet/sdkconfig.defaults
View File

@ -1 +0,0 @@

18
examples/ethernet/iperf/main/Kconfig.projbuild
View File

@ -11,7 +11,7 @@ menu "Example Configuration"
menu "Etherent PHY Device"
choice PHY_MODEL
prompt "Ethernet PHY Device"
default PHY_TLK110
default PHY_IP101
help
Select the PHY driver to use for the example.
config PHY_IP101
@ -33,7 +33,7 @@ menu "Example Configuration"
config PHY_ADDRESS
int "Ethernet PHY Address"
default 31
default 1
range 0 31
help
PHY Address of your PHY device. It dependens on your schematic design.
@ -48,9 +48,15 @@ menu "Example Configuration"
help
Input of 50MHz RMII clock on GPIO0.
config PHY_CLOCK_GPIO0_OUT
bool "GPIO0 Output"
bool "GPIO0 Output(READ HELP)"
help
Output the internal 50MHz RMII clock on GPIO0.
GPIO0 can be set to output a pre-divided PLL clock (test only!).
Enabling this option will configure GPIO0 to output a 50MHz clock.
In fact this clock doesn't have directly relationship with EMAC peripheral.
Sometimes this clock won't work well with your PHY chip. You might need to
add some extra devices after GPIO0 (e.g. inverter).
Note that outputting RMII clock on GPIO0 is an experimental practice.
If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
config PHY_CLOCK_GPIO16_OUT
bool "GPIO16 Output"
help
@ -70,7 +76,7 @@ menu "Example Configuration"
config PHY_USE_POWER_PIN
bool "Use PHY Power (enable / disable) pin"
default n
default y
help
Use a GPIO "power pin" to power the PHY on/off during operation.
When using GPIO0 to input RMII clock, the reset process will be interfered by this clock.
@ -79,7 +85,7 @@ menu "Example Configuration"
if PHY_USE_POWER_PIN
config PHY_POWER_PIN
int "PHY Power GPIO"
default 17
default 5
range 0 33
depends on PHY_USE_POWER_PIN
help