diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c
index 4f4d8893c8..9e179e7e65 100644
--- a/components/esp_hw_support/dma/gdma.c
+++ b/components/esp_hw_support/dma/gdma.c
@@ -47,7 +47,7 @@
 #include "esp_private/periph_ctrl.h"
 #include "gdma_priv.h"
 
-#if CONFIG_PM_ENABLE && SOC_PM_SUPPORT_TOP_PD
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
 #include "esp_private/gdma_sleep_retention.h"
 #endif
 
@@ -669,7 +669,7 @@ static void gdma_release_pair_handle(gdma_pair_t *pair)
 
     if (do_deinitialize) {
         free(pair);
-#if CONFIG_PM_ENABLE && SOC_PM_SUPPORT_TOP_PD && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8461
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION
         gdma_sleep_retention_deinit(group->group_id, pair_id);
 #endif
         ESP_LOGD(TAG, "del pair (%d,%d)", group->group_id, pair_id);
@@ -709,7 +709,7 @@ static gdma_pair_t *gdma_acquire_pair_handle(gdma_group_t *group, int pair_id)
         s_platform.group_ref_counts[group->group_id]++;
         portEXIT_CRITICAL(&s_platform.spinlock);
 
-#if CONFIG_PM_ENABLE && SOC_PM_SUPPORT_TOP_PD && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8461
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION
         gdma_sleep_retention_init(group->group_id, pair_id);
 #endif
         ESP_LOGD(TAG, "new pair (%d,%d) at %p", group->group_id, pair_id, pair);
diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
new file mode 100644
index 0000000000..c6c263cd7f
--- /dev/null
+++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
@@ -0,0 +1,97 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_private/sleep_clock.h"
+#include "soc/pcr_reg.h"
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+#include "soc/i2c_ana_mst_reg.h"
+
+static const char *TAG = "sleep_clock";
+
+esp_err_t sleep_clock_system_retention_init(void *arg)
+{
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    const static sleep_retention_entries_config_t pcr_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+    };
+    esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+#endif
+    ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+}
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+esp_err_t sleep_clock_modem_retention_init(void *arg)
+{
+    #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
+
+    const static sleep_retention_entries_config_t modem_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
+    };
+
+    esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
+    ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+
+    #undef N_REGS_SYSCON
+}
+#endif
+
+bool clock_domain_pd_allowed(void)
+{
+    const uint32_t inited_modules = sleep_retention_get_inited_modules();
+    const uint32_t created_modules = sleep_retention_get_created_modules();
+    const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
+
+    /* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
+     * through MODEM_SYSCON, when one or more MODEMs are initialized, it is
+     * necessary to check the state of CLOCK_MODEM to determine MODEM domain on
+     * or off. The clock and reset of digital peripherals are managed through
+     * PCR, with TOP domain similar to MODEM domain. */
+    uint32_t modem_clk_dep_modules = 0;
+#if SOC_WIFI_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
+#endif
+#if SOC_BT_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
+#endif
+#if SOC_IEEE802154_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
+#endif
+
+    uint32_t mask = 0;
+    if (inited_modules & sys_clk_dep_modules) {
+        mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    }
+    if (inited_modules & modem_clk_dep_modules) {
+#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
+        mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+#endif
+    }
+    return ((inited_modules & mask) == (created_modules & mask));
+}
+
+ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
+{
+    sleep_retention_module_init_param_t init_param = {
+        .cbs       = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
+        .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
+    };
+    sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+    init_param = (sleep_retention_module_init_param_t) {
+        .cbs       = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
+        .depends   = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
+        .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
+    };
+    sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
+#endif
+    return ESP_OK;
+}
diff --git a/components/esp_hw_support/port/esp32c5/clock_retention_init.c b/components/esp_hw_support/port/esp32c5/clock_retention_init.c
index a2d0cfc961..eaccddea7a 100644
--- a/components/esp_hw_support/port/esp32c5/clock_retention_init.c
+++ b/components/esp_hw_support/port/esp32c5/clock_retention_init.c
@@ -12,10 +12,12 @@ static __attribute__((unused)) const char *TAG = "sleep_clock";
 
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
-#define N_REGS_PCR()    (((PCR_SRAM_POWER_CONF_1_REG - DR_REG_PCR_BASE) / 4) + 1)
+    #define N_REGS_PCR()    (((PCR_HPCORE_0_PD_CTRL_REG - DR_REG_PCR_BASE) / 4) + 1)
 
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* pcr */
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+#endif
     };
 
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
@@ -27,17 +29,10 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
 #if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
 esp_err_t sleep_clock_modem_retention_init(void *arg)
 {
-#if CONFIG_IDF_TARGET_ESP32C5
     #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
-#else
-    #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
-#endif
 
     const static sleep_retention_entries_config_t modem_regs_retention[] = {
         [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
-#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
-        [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0),  MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) } /* MODEM LPCON */
-#endif
     };
 
     esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
diff --git a/components/esp_hw_support/port/esp32h2/clock_retention_init.c b/components/esp_hw_support/port/esp32h2/clock_retention_init.c
index dd11464b0c..b500111948 100644
--- a/components/esp_hw_support/port/esp32h2/clock_retention_init.c
+++ b/components/esp_hw_support/port/esp32h2/clock_retention_init.c
@@ -24,6 +24,8 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
+
+    #undef N_REGS_PCR
 }
 
 #if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
@@ -41,5 +43,8 @@ esp_err_t sleep_clock_modem_retention_init(void *arg)
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
     ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
+
+    #undef N_REGS_LPCON
+    #undef N_REGS_SYSCON
 }
 #endif
diff --git a/components/esp_hw_support/port/esp32p4/clock_retention_init.c b/components/esp_hw_support/port/esp32p4/clock_retention_init.c
index bd0d66d6a8..07bf98e8f7 100644
--- a/components/esp_hw_support/port/esp32p4/clock_retention_init.c
+++ b/components/esp_hw_support/port/esp32p4/clock_retention_init.c
@@ -25,4 +25,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
+
+    #undef N_REGS_PCR
 }
diff --git a/components/esp_hw_support/sleep_clock.c b/components/esp_hw_support/sleep_clock.c
index 297d8f7083..35117fa438 100644
--- a/components/esp_hw_support/sleep_clock.c
+++ b/components/esp_hw_support/sleep_clock.c
@@ -5,6 +5,44 @@
  */
 
 #include "esp_private/sleep_clock.h"
+#include "soc/pcr_reg.h"
+#include "modem/modem_syscon_reg.h"
+
+static const char *TAG = "sleep_clock";
+
+esp_err_t sleep_clock_system_retention_init(void *arg)
+{
+    #define N_REGS_PCR()    (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
+
+    const static sleep_retention_entries_config_t pcr_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* pcr */
+    };
+
+    esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+    ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+
+    #undef N_REGS_PCR
+}
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+esp_err_t sleep_clock_modem_retention_init(void *arg)
+{
+    #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
+
+    const static sleep_retention_entries_config_t modem_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
+    };
+
+    esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
+    ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+
+    #undef N_REGS_SYSCON
+}
+#endif
 
 bool clock_domain_pd_allowed(void)
 {
diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c
index f3eb153a98..bbec68730e 100644
--- a/components/esp_hw_support/sleep_system_peripheral.c
+++ b/components/esp_hw_support/sleep_system_peripheral.c
@@ -81,7 +81,9 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_flash_spimem_retention
     return ESP_OK;
 }
 
-#if CONFIG_SPIRAM
+#if CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32P4
+/* TODO: PM-205, In the ESP32C5, Flash and PSRAM use the same set of SPIMEM hardware, while in P4, Flash and PSRAM each have their own SPIMEM hardware.
+ * It’s necessary to confirm whether the ESP32C5 can independently manage SPIMEM retention for Flash and PSRAM in software. */
 static __attribute__((unused)) esp_err_t sleep_sys_periph_psram_spimem_retention_init(void *arg)
 {
     esp_err_t err = sleep_retention_entries_create(psram_spimem_regs_retention, ARRAY_SIZE(psram_spimem_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_LOW, SLEEP_RETENTION_MODULE_SYS_PERIPH);
@@ -142,7 +144,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
     if(err) goto error;
     err = sleep_sys_periph_flash_spimem_retention_init(arg);
     if(err) goto error;
-#if CONFIG_SPIRAM
+#if CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32P4
     err = sleep_sys_periph_psram_spimem_retention_init(arg);
     if(err) goto error;
 #endif
diff --git a/components/esp_system/int_wdt.c b/components/esp_system/int_wdt.c
index 9a8db626f3..f140fe1edd 100644
--- a/components/esp_system/int_wdt.c
+++ b/components/esp_system/int_wdt.c
@@ -180,7 +180,7 @@ void esp_int_wdt_init(void)
                 "movi   %[IMM], 1\n"
                 "or     %[REG], %[IMM], %[REG]\n"
                 "wer    %[REG], %[ERI]\n"
-                /* Enable Xtensa Debug Module BreakIn signal */
+                /* Enable Xtensa Debug Module Break_In signal */
                 "movi   %[ERI], " SYM2STR(ERI_ADDR(APB_DCRSET)) "\n"
                 "rer    %[REG], %[ERI]\n"
                 "movi   %[IMM], 0x10000\n"
diff --git a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c
index 8b8ed63180..f33665bfa6 100644
--- a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c
+++ b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c
@@ -55,7 +55,7 @@ static esp_err_t sleep_task_wdt_retention_init(void *arg)
                                                    REGDMA_LINK_PRI_SYS_PERIPH_LOW,
                                                    (group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT);
     if (err == ESP_OK) {
-        ESP_LOGD(TAG, "Task watchdog timer retention initialization");
+        ESP_LOGI(TAG, "Task watchdog timer retention initialization");
     }
     ESP_RETURN_ON_ERROR(err, TAG, "Failed to create sleep retention linked list for task watchdog timer");
     return err;
diff --git a/components/hal/esp32c5/include/hal/timer_ll.h b/components/hal/esp32c5/include/hal/timer_ll.h
index 7798f6c7ba..e0994053c8 100644
--- a/components/hal/esp32c5/include/hal/timer_ll.h
+++ b/components/hal/esp32c5/include/hal/timer_ll.h
@@ -24,6 +24,7 @@ extern "C" {
 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
+#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER)
 
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                     \
     (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                          \
diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h
index a3fd804792..afbdab2cf6 100644
--- a/components/hal/esp32c5/include/hal/uart_ll.h
+++ b/components/hal/esp32c5/include/hal/uart_ll.h
@@ -61,6 +61,10 @@ extern "C" {
 #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix)  \
     (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
 
+// UART sleep retention module
+#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
+                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
+
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index fdbc426457..164be99cc6 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -171,10 +171,18 @@ config SOC_PMU_SUPPORTED
     bool
     default y
 
+config SOC_PAU_SUPPORTED
+    bool
+    default y
+
 config SOC_LP_TIMER_SUPPORTED
     bool
     default y
 
+config SOC_LP_AON_SUPPORTED
+    bool
+    default y
+
 config SOC_LP_PERIPHERALS_SUPPORTED
     bool
     default y
@@ -1079,6 +1087,14 @@ config SOC_TIMER_SUPPORT_ETM
     bool
     default y
 
+config SOC_TIMER_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_MWDT_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_EFUSE_ECDSA_KEY
     bool
     default y
@@ -1167,6 +1183,10 @@ config SOC_UART_HAS_LP_UART
     bool
     default y
 
+config SOC_UART_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
     bool
     default y
@@ -1219,6 +1239,10 @@ config SOC_PM_CPU_RETENTION_BY_SW
     bool
     default y
 
+config SOC_PM_MODEM_RETENTION_BY_REGDMA
+    bool
+    default y
+
 config SOC_PM_PAU_LINK_NUM
     int
     default 4
diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h
index 2ef044eb40..ec8442305b 100644
--- a/components/soc/esp32c5/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h
@@ -18,24 +18,31 @@ typedef enum periph_retention_module {
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
+    /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
+     * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
+    SLEEP_RETENTION_MODULE_SYS_PERIPH   = 3,
+    /* Timer Group by target*/
+    SLEEP_RETENTION_MODULE_TG0_WDT      = 4,
+    SLEEP_RETENTION_MODULE_TG1_WDT      = 5,
+    SLEEP_RETENTION_MODULE_TG0_TIMER    = 6,
+    SLEEP_RETENTION_MODULE_TG1_TIMER    = 7,
+    /* GDMA by channel */
+    SLEEP_RETENTION_MODULE_GDMA_CH0     = 8,
+    SLEEP_RETENTION_MODULE_GDMA_CH1     = 9,
+    SLEEP_RETENTION_MODULE_GDMA_CH2     = 10,
+    /* MISC Peripherals */
+    SLEEP_RETENTION_MODULE_ADC          = 11,
+    SLEEP_RETENTION_MODULE_I2C0         = 12,
+    SLEEP_RETENTION_MODULE_RMT0         = 13,
+    SLEEP_RETENTION_MODULE_UART0        = 14,
+    SLEEP_RETENTION_MODULE_UART1        = 15,
 
     /* modem module, which includes WiFi, BLE and 802.15.4 */
-    SLEEP_RETENTION_MODULE_WIFI_MAC     = 10,
-    SLEEP_RETENTION_MODULE_WIFI_BB      = 11,
-    SLEEP_RETENTION_MODULE_BLE_MAC      = 12,
-    SLEEP_RETENTION_MODULE_BT_BB        = 13,
-    SLEEP_RETENTION_MODULE_802154_MAC   = 14,
-
-    /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
-    SLEEP_RETENTION_MODULE_SYS_PERIPH   = 16,
-
-    SLEEP_RETENTION_MODULE_ADC          = 17,
-
-    SLEEP_RETENTION_MODULE_GDMA_CH0     = 24,
-    SLEEP_RETENTION_MODULE_GDMA_CH1     = 25,
-    SLEEP_RETENTION_MODULE_GDMA_CH2     = 26,
-
+    SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
+    SLEEP_RETENTION_MODULE_WIFI_BB      = 27,
+    SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
+    SLEEP_RETENTION_MODULE_BT_BB        = 29,
+    SLEEP_RETENTION_MODULE_802154_MAC   = 30,
     SLEEP_RETENTION_MODULE_MAX          = 31
 } periph_retention_module_t;
 
@@ -52,10 +59,19 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_802154_MAC   = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
 
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
+     * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
     SLEEP_RETENTION_MODULE_BM_SYS_PERIPH   = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
-
+    /* Timer Group by target*/
+    SLEEP_RETENTION_MODULE_BM_TASK_WDT     = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
+    SLEEP_RETENTION_MODULE_BM_INT_WDT      = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
+    SLEEP_RETENTION_MODULE_BM_TG0_TIMER    = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
+    SLEEP_RETENTION_MODULE_BM_TG1_TIMER    = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
+    /* MISC Peripherals */
     SLEEP_RETENTION_MODULE_BM_ADC          = BIT(SLEEP_RETENTION_MODULE_ADC),
+    SLEEP_RETENTION_MODULE_BM_I2C0         = BIT(SLEEP_RETENTION_MODULE_I2C0),
+    SLEEP_RETENTION_MODULE_BM_RMT0         = BIT(SLEEP_RETENTION_MODULE_RMT0),
+    SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
+    SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
 
     SLEEP_RETENTION_MODULE_BM_GDMA_CH0     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
     SLEEP_RETENTION_MODULE_BM_GDMA_CH1     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
@@ -63,6 +79,20 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_ALL          = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 
+#define TOP_DOMAIN_PERIPHERALS_BM ( SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
+                                  | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
+                                  | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
+                                  | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
+                                  | SLEEP_RETENTION_MODULE_BM_ADC         \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C0        \
+                                  | SLEEP_RETENTION_MODULE_BM_RMT0        \
+                                  | SLEEP_RETENTION_MODULE_BM_UART0       \
+                                  | SLEEP_RETENTION_MODULE_BM_UART1       \
+                                  )
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index ac6327f683..75ff3bfa5b 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -60,9 +60,9 @@
 #define SOC_BOD_SUPPORTED               1
 #define SOC_APM_SUPPORTED               1 /*!< Support for APM peripheral */
 #define SOC_PMU_SUPPORTED               1
-// #define SOC_PAU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8638
+#define SOC_PAU_SUPPORTED               1
 #define SOC_LP_TIMER_SUPPORTED          1
-// #define SOC_LP_AON_SUPPORTED            1  // TODO: [ESP32C5] IDF-8638
+#define SOC_LP_AON_SUPPORTED            1
 #define SOC_LP_PERIPHERALS_SUPPORTED    1
 #define SOC_LP_I2C_SUPPORTED            1
 #define SOC_ULP_LP_UART_SUPPORTED       1
@@ -463,10 +463,11 @@
 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 #define SOC_TIMER_SUPPORT_ETM             (1)
-// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
+#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
 
 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/
 // #define SOC_MWDT_SUPPORT_XTAL              (1)
+#define SOC_MWDT_SUPPORT_SLEEP_RETENTION   (1)
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
 // #define SOC_TWAI_CONTROLLER_NUM         2
@@ -504,17 +505,18 @@
 
 /*-------------------------- UART CAPS ---------------------------------------*/
 // ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
-#define SOC_UART_NUM                    (3)
-#define SOC_UART_HP_NUM                 (2)
-#define SOC_UART_LP_NUM                 (1U)
-#define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
-#define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
-#define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
-#define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
-#define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
-#define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
-#define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
-#define SOC_UART_HAS_LP_UART            (1)         /*!< Support LP UART */
+#define SOC_UART_NUM                       (3)
+#define SOC_UART_HP_NUM                    (2)
+#define SOC_UART_LP_NUM                    (1U)
+#define SOC_UART_FIFO_LEN                  (128)       /*!< The UART hardware FIFO length */
+#define SOC_LP_UART_FIFO_LEN               (16)        /*!< The LP UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX               (5000000)   /*!< Max bit rate supported by UART */
+#define SOC_UART_SUPPORT_PLL_F80M_CLK      (1)         /*!< Support PLL_F80M as the clock source */
+#define SOC_UART_SUPPORT_RTC_CLK           (1)         /*!< Support RTC clock as the clock source */
+#define SOC_UART_SUPPORT_XTAL_CLK          (1)         /*!< Support XTAL clock as the clock source */
+#define SOC_UART_SUPPORT_WAKEUP_INT        (1)         /*!< Support UART wakeup interrupt */
+#define SOC_UART_HAS_LP_UART               (1)         /*!< Support LP UART */
+#define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
 
 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
@@ -556,7 +558,7 @@
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
 #define SOC_PM_CPU_RETENTION_BY_SW          (1)
-// #define SOC_PM_MODEM_RETENTION_BY_REGDMA    (1)
+#define SOC_PM_MODEM_RETENTION_BY_REGDMA    (1)
 // #define SOC_PM_RETENTION_HAS_CLOCK_BUG      (1)
 
 #define SOC_PM_PAU_LINK_NUM                 (4)
diff --git a/components/soc/esp32c5/include/soc/system_periph_retention.h b/components/soc/esp32c5/include/soc/system_periph_retention.h
new file mode 100644
index 0000000000..dac1f0414d
--- /dev/null
+++ b/components/soc/esp32c5/include/soc/system_periph_retention.h
@@ -0,0 +1,82 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+#include "soc/regdma.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @brief Provide access to interrupt matrix configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define INT_MTX_RETENTION_LINK_LEN   1
+extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to hp_system configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define HP_SYSTEM_RETENTION_LINK_LEN 3
+extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to TEE_APM configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define TEE_APM_RETENTION_LINK_LEN   2
+extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN];
+#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN   1
+extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to IOMUX configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define IOMUX_RETENTION_LINK_LEN    5
+extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to spimem configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define SPIMEM_RETENTION_LINK_LEN   8
+extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to systimer configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define SYSTIMER_RETENTION_LINK_LEN   19
+extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/system_retention_periph.c b/components/soc/esp32c5/system_retention_periph.c
new file mode 100644
index 0000000000..fbface5460
--- /dev/null
+++ b/components/soc/esp32c5/system_retention_periph.c
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/regdma.h"
+#include "soc/system_periph_retention.h"
+#include "soc/timer_periph.h"
+#include "soc/uart_reg.h"
+#include "soc/systimer_reg.h"
+#include "soc/timer_group_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/hp_system_reg.h"
+#include "soc/tee_reg.h"
+#include "soc/hp_apm_reg.h"
+#include "soc/gpio_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/interrupt_matrix_reg.h"
+
+/* Interrupt Matrix Registers Context */
+#define N_REGS_INTR_MATRIX()    (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1)
+const regdma_entries_config_t intr_matrix_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* intr matrix */
+};
+_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
+
+/* HP System Registers Context */
+#define N_REGS_HP_SYSTEM_0()      (((HP_SYSTEM_SDIO_CTRL_REG - DR_REG_HP_SYSTEM_BASE) / 4) + 1)
+#define N_REGS_HP_SYSTEM_1()      (((HP_SYSTEM_MEM_TEST_CONF_REG - HP_SYSTEM_ROM_TABLE_LOCK_REG) / 4) + 1)
+#define N_REGS_HP_SYSTEM_2()      (((HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG - HP_SYSTEM_SPROM_CTRL_REG) / 4) + 1)
+const regdma_entries_config_t hp_system_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0x0), DR_REG_HP_SYSTEM_BASE,        DR_REG_HP_SYSTEM_BASE,        N_REGS_HP_SYSTEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* hp system */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0x1), HP_SYSTEM_ROM_TABLE_LOCK_REG, HP_SYSTEM_ROM_TABLE_LOCK_REG, N_REGS_HP_SYSTEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0x2), HP_SYSTEM_SPROM_CTRL_REG,     HP_SYSTEM_SPROM_CTRL_REG,     N_REGS_HP_SYSTEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
+
+/* TEE/APM Registers Context */
+#define N_REGS_TEE()    (((TEE_CLOCK_GATE_REG - DR_REG_TEE_BASE) / 4) + 1)
+#define N_REGS_APM()    (((HP_APM_INT_EN_REG - DR_REG_HP_APM_BASE) / 4) + 1)
+const regdma_entries_config_t tee_apm_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0), DR_REG_HP_APM_BASE, DR_REG_HP_APM_BASE, N_REGS_APM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* apm */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(1), DR_REG_TEE_BASE,    DR_REG_TEE_BASE,    N_REGS_TEE(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* tee */
+};
+const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TEEAPM_LINK(2), TEE_M4_MODE_CTRL_REG, 0x0, 0xffffffff, 1, 0), .owner = ENTRY(2) }
+};
+_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
+
+/* IO MUX Registers Context */
+#define N_REGS_IOMUX_0()    (((PERIPHS_IO_MUX_U_PAD_GPIO28 - REG_IO_MUX_BASE) / 4) + 1)
+#define N_REGS_IOMUX_1()    (((GPIO_FUNC32_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
+#define N_REGS_IOMUX_2()    (((GPIO_FUNC116_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1)
+#define N_REGS_IOMUX_3()    (((GPIO_PIN32_REG - GPIO_PIN0_REG) / 4) + 1)
+
+#define GPIO_RETENTION_REGS_CNT  6
+#define GPIO_RETENTION_MAP_BASE  GPIO_OUT_REG
+static const uint32_t gpio_regs_map[4] = {0x90009009, 0, 0, 0};
+
+const regdma_entries_config_t iomux_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE,            REG_IO_MUX_BASE,            N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG,  GPIO_FUNC0_IN_SEL_CFG_REG,  N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG,              GPIO_PIN0_REG,              N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_REGS_CNT, 0, 0,
+            gpio_regs_map[0], gpio_regs_map[1], gpio_regs_map[2], gpio_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, \
+};
+_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions");
+
+/* Memory SPI Registers Context */
+#define N_REGS_SPI1_MEM_0()     (((SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
+#define N_REGS_SPI1_MEM_1()     (1)
+#define N_REGS_SPI1_MEM_2()     (1)
+
+#define N_REGS_SPI0_MEM_0()     (((SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
+#define N_REGS_SPI0_MEM_1()     (((SPI_SMEM_AC_REG(0) - SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
+#define N_REGS_SPI0_MEM_2()     (1)
+#define N_REGS_SPI0_MEM_3()     (((SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0) - SPI_MEM_MMU_POWER_CTRL_REG(0)) / 4) + 1)
+
+const regdma_entries_config_t flash_spimem_regs_retention[] = {
+    /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1),           REG_SPI_MEM_BASE(1),           N_REGS_SPI1_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_TIMING_CALI_REG(1),    SPI_MEM_TIMING_CALI_REG(1),    N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI_MEM_CLOCK_GATE_REG(1),     SPI_MEM_CLOCK_GATE_REG(1),     N_REGS_SPI1_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
+    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), REG_SPI_MEM_BASE(0),           REG_SPI_MEM_BASE(0),           N_REGS_SPI0_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI_FMEM_PMS0_ATTR_REG(0),     SPI_FMEM_PMS0_ATTR_REG(0),     N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_CLOCK_GATE_REG(0),     SPI_MEM_CLOCK_GATE_REG(0),     N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_POWER_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    /* Note: spimem register should set update reg to make the configuration take effect */
+    [7] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0),    SPI_MEM_TIMING_CALI_UPDATE,    SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+_Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_RETENTION_LINK_LEN, "Inconsistent SPI Mem retention link length definitions");
+
+/* Systimer Registers Context */
+#define N_REGS_SYSTIMER_0()     (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1)
+const regdma_entries_config_t systimer_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG,       SYSTIMER_TIMER_UNIT0_UPDATE_M,    SYSTIMER_TIMER_UNIT0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */
+    [1]  = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG,       SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
+    [2]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG,       2,                                0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG,     SYSTIMER_TIMER_UNIT0_LOAD_M,      SYSTIMER_TIMER_UNIT0_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [4]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG,       SYSTIMER_TIMER_UNIT1_UPDATE_M,    SYSTIMER_TIMER_UNIT1_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
+    [5]  = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG,       SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
+    [6]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG,       2,                                0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [7]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG,     SYSTIMER_TIMER_UNIT1_LOAD_M,      SYSTIMER_TIMER_UNIT1_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [8]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG,     SYSTIMER_TARGET0_HI_REG,          N_REGS_SYSTIMER_0(),              0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */
+
+    [9]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG,     SYSTIMER_TIMER_COMP0_LOAD,        SYSTIMER_TIMER_COMP0_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [10] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG,     SYSTIMER_TIMER_COMP1_LOAD,        SYSTIMER_TIMER_COMP1_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [11] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG,     SYSTIMER_TIMER_COMP2_LOAD,        SYSTIMER_TIMER_COMP2_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [12] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG,   0,                                SYSTIMER_TARGET0_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [13] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG,   SYSTIMER_TARGET0_PERIOD_MODE_M,   SYSTIMER_TARGET0_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [14] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG,   0,                                SYSTIMER_TARGET1_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [15] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG,   SYSTIMER_TARGET1_PERIOD_MODE_M,   SYSTIMER_TARGET1_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [16] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG,   0,                                SYSTIMER_TARGET2_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG,           SYSTIMER_CONF_REG,                1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */
+    [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG,        SYSTIMER_INT_ENA_REG,             1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* Systimer intr enable */
+};
+_Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");
diff --git a/components/soc/esp32c5/timer_periph.c b/components/soc/esp32c5/timer_periph.c
index 6e407b5eb6..916d7719eb 100644
--- a/components/soc/esp32c5/timer_periph.c
+++ b/components/soc/esp32c5/timer_periph.c
@@ -1,3 +1,4 @@
+
 /*
  * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
@@ -23,70 +24,111 @@ const timer_group_signal_conn_t timer_group_periph_signals = {
     }
 };
 
-#if SOC_TIMER_SUPPORT_SLEEP_RETENTION
-#define N_REGS_TGWDT          6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
-
-static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
-    /*Timer group backup. should get of write project firstly. wdt used by RTOS.*/
-    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = TIMG_RETENTION_ENTRY },
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0),    TIMG_WDTCONFIG0_REG(0),  N_REGS_TGWDT,              0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [2] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(0),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = TIMG_RETENTION_ENTRY },
-    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = TIMG_RETENTION_ENTRY },
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1,                      0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(0),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = TIMG_RETENTION_ENTRY },
-};
-
-static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
-    /*Timer group0 backup. T0_wdt should get of write project firstly. wdt used by RTOS.*/
-    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = TIMG_RETENTION_ENTRY },
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1,                      0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(1),    TIMG_WDTCONFIG0_REG(1),  N_REGS_TGWDT,              0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = TIMG_RETENTION_ENTRY },
-    [4] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(1),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = TIMG_RETENTION_ENTRY },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = TIMG_RETENTION_ENTRY },
-};
-
 /*  Registers in retention context:
  *      TIMG_T0CONFIG_REG
  *      TIMG_T0ALARMLO_REG
  *      TIMG_T0ALARMHI_REG
+ *      TIMG_T0LOADLO_REG
+ *      TIMG_T0LOADHI_REG
  *      TIMG_INT_ENA_TIMERS_REG
  *      TIMG_REGCLK_REG
  */
-#define N_REGS_TG_TIMER_CFG            5
-static const uint32_t tg_timer_regs_map[4] = {0x10000031, 0x80000000, 0, 0};
+#define TG_TIMER_RETENTION_REGS_CNT 7
+static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0};
 
-const regdma_entries_config_t tg0_timer_regs_retention[] = {
+const regdma_entries_config_t tg0_timer_regdma_entries[] = {
+    // backup stage: trigger a soft capture
     [0] = {
-        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x00),         TIMG_T0CONFIG_REG(0),   TIMG_T0CONFIG_REG(0),   N_REGS_TG_TIMER_CFG, 0, 0, \
-                                            tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]),  .owner = TIMG_RETENTION_ENTRY
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00),
+        TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // backup stage: wait for the capture done
+    [1] = {
+        .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01),
+        TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // backup stage: save the captured counter value
+    // restore stage: store the captured counter value to the loader register
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02),
+        TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    [3] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03),
+        TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // restore stage: trigger a soft reload, so the timer can continue from where it was backed up
+    [4] = {
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x04),
+        TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // backup stage: save other configuration and status registers
+    // restore stage: restore the configuration and status registers
+    [5] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x05),
+        TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0),
+        TG_TIMER_RETENTION_REGS_CNT, 0, 0,
+        tg_timer_regs_map[0], tg_timer_regs_map[1],
+        tg_timer_regs_map[2], tg_timer_regs_map[3]),
+        .owner = TIMG_RETENTION_ENTRY
     },
-    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01),        TIMG_T0UPDATE_REG(0),   TIMG_T0_UPDATE,         TIMG_T0_UPDATE_M,    0, 1), .owner = TIMG_RETENTION_ENTRY },
-    [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02),         TIMG_T0UPDATE_REG(0),   0x0,                    TIMG_T0_UPDATE_M,    0, 1), .owner = TIMG_RETENTION_ENTRY },
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03),   TIMG_T0LO_REG(0),       TIMG_T0LOADLO_REG(0),   2,                   0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04),   TIMG_T0HI_REG(0),       TIMG_T0LOADHI_REG(0),   2,                   0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05),        TIMG_T0LOAD_REG(0),     0x1,                    TIMG_T0_LOAD_M,      1, 0), .owner = TIMG_RETENTION_ENTRY },
 };
 
-const regdma_entries_config_t tg1_timer_regs_retention[] = {
+const regdma_entries_config_t tg1_timer_regdma_entries[] = {
+    // backup stage: trigger a soft capture
     [0] = {
-        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x00),         TIMG_T0CONFIG_REG(1),   TIMG_T0CONFIG_REG(1),   N_REGS_TG_TIMER_CFG, 0, 0, \
-                                            tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]),  .owner = TIMG_RETENTION_ENTRY
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00),
+        TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // backup stage: wait for the capture done
+    [1] = {
+        .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01),
+        TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // backup stage: save the captured counter value
+    // restore stage: store the captured counter value to the loader register
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02),
+        TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    [3] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03),
+        TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // restore stage: trigger a soft reload, so the timer can continue from where it was backed up
+    [4] = {
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x04),
+        TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
+        .owner = ENTRY(0) | ENTRY(2)
+    },
+    // backup stage: save other configuration and status registers
+    // restore stage: restore the configuration and status registers
+    [5] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x05),
+        TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1),
+        TG_TIMER_RETENTION_REGS_CNT, 0, 0,
+        tg_timer_regs_map[0], tg_timer_regs_map[1],
+        tg_timer_regs_map[2], tg_timer_regs_map[3]),
+        .owner = TIMG_RETENTION_ENTRY
     },
-    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01),        TIMG_T0UPDATE_REG(1),   TIMG_T0_UPDATE,         TIMG_T0_UPDATE_M,    0, 1), .owner = TIMG_RETENTION_ENTRY },
-    [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02),         TIMG_T0UPDATE_REG(0),   0x0,                    TIMG_T0_UPDATE_M,    0, 1), .owner = TIMG_RETENTION_ENTRY },
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03),   TIMG_T0LO_REG(1),       TIMG_T0LOADLO_REG(1),   2,                   0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04),   TIMG_T0HI_REG(1),       TIMG_T0LOADHI_REG(1),   2,                   0, 0), .owner = TIMG_RETENTION_ENTRY },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05),        TIMG_T0LOAD_REG(1),     0x1,                    TIMG_T0_LOAD_M,      1, 0), .owner = TIMG_RETENTION_ENTRY },
 };
 
-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
-    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
-    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
+const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = tg0_timer_regdma_entries,
+        .array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
+    },
+    [1] = {
+        .regdma_entry_array = tg1_timer_regdma_entries,
+        .array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
+    },
 };
-
-const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = {
-    [0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)},
-    [1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)},
-};
-#endif
diff --git a/components/soc/esp32c5/uart_periph.c b/components/soc/esp32c5/uart_periph.c
index 13a83fce13..733cde884b 100644
--- a/components/soc/esp32c5/uart_periph.c
+++ b/components/soc/esp32c5/uart_periph.c
@@ -109,3 +109,52 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
         .irq = ETS_LP_UART_INTR_SOURCE,
     },
 };
+
+/**
+ * UART registers to be saved during sleep retention
+ *
+ * Reset TXFIFO and RXFIFO
+ * UART registers require set the reg_update bit to make the configuration take effect
+ *
+ * UART_INT_ENA_REG, UART_CLKDIV_SYNC_REG, UART_RX_FILT_REG, UART_CONF0_SYNC_REG, UART_CONF1_REG,
+ * UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
+ * UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
+ * UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
+ * UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_CLK_CONF_REG, UART_ID_REG
+ */
+#define UART_RETENTION_ADDR_MAP_REGS_CNT 22
+#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
+static const uint32_t uart_regs_map[4] = {0x807FFF6D, 0x10, 0x0, 0x0};
+#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
+                                               UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \
+                                               UART_RETENTION_ADDR_MAP_REGS_CNT, 0, 0, \
+                                               uart_regs_map[0], uart_regs_map[1], \
+                                               uart_regs_map[2], uart_regs_map[3] \
+                                              ), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
+                                            UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
+                                            UART_REG_UPDATE_M, 1, 0 \
+                                           ), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
+                                           UART_REG_UPDATE_REG(uart_num), 0x0, \
+                                           UART_REG_UPDATE_M, 1, 0 \
+                                          ), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
+
+const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
+    [0] = {
+        .regdma_entry_array = uart0_regdma_entries,
+        .array_size = ARRAY_SIZE(uart0_regdma_entries),
+    },
+    [1] = {
+        .regdma_entry_array = uart1_regdma_entries,
+        .array_size = ARRAY_SIZE(uart1_regdma_entries),
+    },
+};
diff --git a/components/soc/esp32c5/wdt_periph.c b/components/soc/esp32c5/wdt_periph.c
index 58f1349d3d..f615401cfa 100644
--- a/components/soc/esp32c5/wdt_periph.c
+++ b/components/soc/esp32c5/wdt_periph.c
@@ -5,3 +5,28 @@
  */
 
 #include "soc/wdt_periph.h"
+
+#define N_REGS_TGWDT          6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
+
+static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0),    TIMG_WDTCONFIG0_REG(0),  N_REGS_TGWDT,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1,                      0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+
+static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1,                      0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1),    TIMG_WDTCONFIG0_REG(1),  N_REGS_TGWDT,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [4] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
+    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
+};
diff --git a/components/soc/esp32c6/include/soc/retention_periph_defs.h b/components/soc/esp32c6/include/soc/retention_periph_defs.h
index e0d6c4da4c..a1dee8299a 100644
--- a/components/soc/esp32c6/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c6/include/soc/retention_periph_defs.h
@@ -19,10 +19,10 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
+     * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
     SLEEP_RETENTION_MODULE_SYS_PERIPH   = 3,
     /* Timer Group by target*/
-    SLEEP_RETENTION_MODULE_TG0_WDT     = 4,
+    SLEEP_RETENTION_MODULE_TG0_WDT      = 4,
     SLEEP_RETENTION_MODULE_TG1_WDT      = 5,
     SLEEP_RETENTION_MODULE_TG0_TIMER    = 6,
     SLEEP_RETENTION_MODULE_TG1_TIMER    = 7,
@@ -51,7 +51,7 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
+     * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
     SLEEP_RETENTION_MODULE_BM_SYS_PERIPH   = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
     /* Timer Group by target*/
     SLEEP_RETENTION_MODULE_BM_TASK_WDT     = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
@@ -77,22 +77,20 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_ALL          = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 
-#define TOP_DOMAIN_PERIPHERALS_BM  (SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM  \
-                                    | SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM \
-                                    | SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
-                                    | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
-                                    | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
-                                    | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
-                                    | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
-                                    | SLEEP_RETENTION_MODULE_BM_ADC         \
-                                    | SLEEP_RETENTION_MODULE_BM_I2C0        \
-                                    | SLEEP_RETENTION_MODULE_BM_RMT0        \
-                                    | SLEEP_RETENTION_MODULE_BM_UART0       \
-                                    | SLEEP_RETENTION_MODULE_BM_UART1       \
-                                   )
+#define TOP_DOMAIN_PERIPHERALS_BM ( SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
+                                  | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
+                                  | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
+                                  | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
+                                  | SLEEP_RETENTION_MODULE_BM_ADC         \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C0        \
+                                  | SLEEP_RETENTION_MODULE_BM_RMT0        \
+                                  | SLEEP_RETENTION_MODULE_BM_UART0       \
+                                  | SLEEP_RETENTION_MODULE_BM_UART1       \
+                                  )
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32c6/include/soc/system_periph_retention.h b/components/soc/esp32c6/include/soc/system_periph_retention.h
index 54f7c3e205..fa93faf4e0 100644
--- a/components/soc/esp32c6/include/soc/system_periph_retention.h
+++ b/components/soc/esp32c6/include/soc/system_periph_retention.h
@@ -47,16 +47,6 @@ extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LI
 #define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN   1
 extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
 
-/**
- * @brief Provide access to timer group configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define TIMG_RETENTION_LINK_LEN     8
-extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN];
-
 /**
  * @brief Provide access to IOMUX configuration registers retention
  * context definition.
diff --git a/components/soc/esp32h2/include/soc/retention_periph_defs.h b/components/soc/esp32h2/include/soc/retention_periph_defs.h
index bcc1b96931..9c8ea0ea05 100644
--- a/components/soc/esp32h2/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32h2/include/soc/retention_periph_defs.h
@@ -75,23 +75,21 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_ALL          = (uint32_t) -1
 } periph_retention_module_bitmap_t;
 
-#define TOP_DOMAIN_PERIPHERALS_BM  (SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM  \
-                                    | SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM \
-                                    | SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
-                                    | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
-                                    | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
-                                    | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
-                                    | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
-                                    | SLEEP_RETENTION_MODULE_BM_ADC         \
-                                    | SLEEP_RETENTION_MODULE_BM_I2C0        \
-                                    | SLEEP_RETENTION_MODULE_BM_I2C1        \
-                                    | SLEEP_RETENTION_MODULE_BM_RMT0        \
-                                    | SLEEP_RETENTION_MODULE_BM_UART0       \
-                                    | SLEEP_RETENTION_MODULE_BM_UART1       \
-                                   )
+#define TOP_DOMAIN_PERIPHERALS_BM ( SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
+                                  | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
+                                  | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
+                                  | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
+                                  | SLEEP_RETENTION_MODULE_BM_ADC         \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C0        \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C1        \
+                                  | SLEEP_RETENTION_MODULE_BM_RMT0        \
+                                  | SLEEP_RETENTION_MODULE_BM_UART0       \
+                                  | SLEEP_RETENTION_MODULE_BM_UART1       \
+                                  )
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32h2/include/soc/system_periph_retention.h b/components/soc/esp32h2/include/soc/system_periph_retention.h
index 54f7c3e205..fa93faf4e0 100644
--- a/components/soc/esp32h2/include/soc/system_periph_retention.h
+++ b/components/soc/esp32h2/include/soc/system_periph_retention.h
@@ -47,16 +47,6 @@ extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LI
 #define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN   1
 extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
 
-/**
- * @brief Provide access to timer group configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define TIMG_RETENTION_LINK_LEN     8
-extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN];
-
 /**
  * @brief Provide access to IOMUX configuration registers retention
  * context definition.
diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h
index 3103933edb..4d6c8eb19f 100644
--- a/components/soc/esp32p4/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h
@@ -58,19 +58,18 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 
-#define TOP_DOMAIN_PERIPHERALS_BM  (SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM \
-                                    | SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
-                                    | SLEEP_RETENTION_MODULE_BM_TG0_WDT    \
-                                    | SLEEP_RETENTION_MODULE_BM_TG1_WDT    \
-                                    | SLEEP_RETENTION_MODULE_BM_TG0_TIMER  \
-                                    | SLEEP_RETENTION_MODULE_BM_TG1_TIMER  \
-                                    | SLEEP_RETENTION_MODULE_BM_UART0      \
-                                    | SLEEP_RETENTION_MODULE_BM_UART1      \
-                                    | SLEEP_RETENTION_MODULE_BM_UART2      \
-                                    | SLEEP_RETENTION_MODULE_BM_UART3      \
-                                    | SLEEP_RETENTION_MODULE_BM_UART4      \
-                                    | SLEEP_RETENTION_MODULE_BM_RMT0       \
-                                   )
+#define TOP_DOMAIN_PERIPHERALS_BM ( SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
+                                  | SLEEP_RETENTION_MODULE_BM_TG0_WDT    \
+                                  | SLEEP_RETENTION_MODULE_BM_TG1_WDT    \
+                                  | SLEEP_RETENTION_MODULE_BM_TG0_TIMER  \
+                                  | SLEEP_RETENTION_MODULE_BM_TG1_TIMER  \
+                                  | SLEEP_RETENTION_MODULE_BM_UART0      \
+                                  | SLEEP_RETENTION_MODULE_BM_UART1      \
+                                  | SLEEP_RETENTION_MODULE_BM_UART2      \
+                                  | SLEEP_RETENTION_MODULE_BM_UART3      \
+                                  | SLEEP_RETENTION_MODULE_BM_UART4      \
+                                  | SLEEP_RETENTION_MODULE_BM_RMT0       \
+                                  )
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/system_periph_retention.h b/components/soc/esp32p4/include/soc/system_periph_retention.h
index 45041ad49b..7e4c9fa3b8 100644
--- a/components/soc/esp32p4/include/soc/system_periph_retention.h
+++ b/components/soc/esp32p4/include/soc/system_periph_retention.h
@@ -45,16 +45,6 @@ extern const regdma_entries_config_t l2_cache_regs_retention[L2_CACHE_RETENTION_
 #define HP_SYSTEM_RETENTION_LINK_LEN 1
 extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
 
-/**
- * @brief Provide access to timer group configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define TIMG_RETENTION_LINK_LEN     8
-extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN];
-
 /**
  * @brief Provide access to IOMUX configuration registers retention
  * context definition.