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Merge branch 'bugfix/coredump_data_section' into 'master'
espcoredump: fix a bug where tracked DRAM data were not dumped Closes IDFGH-6498 See merge request espressif/esp-idf!16573
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commit
a07b3acf9a
@ -1,6 +1,6 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -25,17 +25,24 @@ extern "C" {
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// Forces data into DRAM instead of flash
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// Forces data into DRAM instead of flash
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#define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
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#define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
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#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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// IRAM can only be accessed as an 8-bit memory on ESP32, when CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY is set
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#define IRAM_8BIT_ACCESSIBLE (CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
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// Make sure that IRAM is accessible as an 8-bit memory on ESP32.
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// If that's not the case, coredump cannot dump data from IRAM.
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#if IRAM_8BIT_ACCESSIBLE
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// Forces data into IRAM instead of DRAM
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// Forces data into IRAM instead of DRAM
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#define IRAM_DATA_ATTR __attribute__((section(".iram.data")))
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#define IRAM_DATA_ATTR __attribute__((section(".iram.data")))
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// Forces data into IRAM instead of DRAM and map it to coredump
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// Forces data into IRAM instead of DRAM and map it to coredump
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#define COREDUMP_IRAM_DATA_ATTR _SECTION_ATTR_IMPL(".iram.data.coredump", __COUNTER__)
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#define COREDUMP_IRAM_DATA_ATTR _SECTION_ATTR_IMPL(".iram2.coredump", __COUNTER__)
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// Forces bss into IRAM instead of DRAM
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// Forces bss into IRAM instead of DRAM
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#define IRAM_BSS_ATTR __attribute__((section(".iram.bss")))
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#define IRAM_BSS_ATTR __attribute__((section(".iram.bss")))
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#else
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#else
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#define COREDUMP_IRAM_DATA_ATTR
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// IRAM is not accessible as an 8-bit memory, put IRAM coredump variables in DRAM
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#define COREDUMP_IRAM_DATA_ATTR COREDUMP_DRAM_ATTR
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#define IRAM_DATA_ATTR
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#define IRAM_DATA_ATTR
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#define IRAM_BSS_ATTR
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#define IRAM_BSS_ATTR
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@ -95,7 +102,9 @@ extern "C" {
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#define RTC_NOINIT_ATTR _SECTION_ATTR_IMPL(".rtc_noinit", __COUNTER__)
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#define RTC_NOINIT_ATTR _SECTION_ATTR_IMPL(".rtc_noinit", __COUNTER__)
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// Forces code into DRAM instead of flash and map it to coredump
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// Forces code into DRAM instead of flash and map it to coredump
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#define COREDUMP_DRAM_ATTR _SECTION_ATTR_IMPL(".dram1.coredump", __COUNTER__)
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// Use dram2 instead of dram1 to make sure this section will not be included
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// by dram1 section in the linker script
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#define COREDUMP_DRAM_ATTR _SECTION_ATTR_IMPL(".dram2.coredump", __COUNTER__)
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// Forces data into RTC memory and map it to coredump
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// Forces data into RTC memory and map it to coredump
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#define COREDUMP_RTC_DATA_ATTR _SECTION_ATTR_IMPL(".rtc.coredump", __COUNTER__)
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#define COREDUMP_RTC_DATA_ATTR _SECTION_ATTR_IMPL(".rtc.coredump", __COUNTER__)
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@ -178,7 +178,8 @@ SECTIONS
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mapping[iram0_text]
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mapping[iram0_text]
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/* added to maintain compability */
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/* Added to maintain compability, there are no iram0 data section to put
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* sections:iram_coredump entry defined in espcoredump's linker.lf file */
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_coredump_iram_start = 0;
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_coredump_iram_start = 0;
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_coredump_iram_end = 0;
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_coredump_iram_end = 0;
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@ -8,20 +8,21 @@ entries:
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[sections:dram_coredump]
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[sections:dram_coredump]
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entries:
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entries:
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.dram1.coredump+
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.dram2.coredump+
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if IDF_TARGET_ESP32S2 = n:
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# Always include .iram2.coredump section in the final linker script file,
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[sections:iram_coredump]
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# even though it may be empty. The coredump component will ignore empty
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entries:
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# sections when generating the ELF dump.
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.iram.data.coredump+
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[sections:iram_coredump]
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entries:
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.iram2.coredump+
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[scheme:coredump_default]
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[scheme:coredump_default]
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entries:
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entries:
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dram_coredump -> dram0_data
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dram_coredump -> dram0_data
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rtc_coredump -> rtc_data
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rtc_coredump -> rtc_data
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rtc_fast_coredump -> rtc_force_fast
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rtc_fast_coredump -> rtc_force_fast
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if IDF_TARGET_ESP32S2 = n:
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iram_coredump -> iram0_data
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iram_coredump -> iram0_data
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[mapping:coredump_default]
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[mapping:coredump_default]
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archive: *
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archive: *
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@ -29,10 +30,8 @@ entries:
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* (coredump_default);
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* (coredump_default);
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rtc_fast_coredump -> rtc_force_fast SURROUND(coredump_rtc_fast),
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rtc_fast_coredump -> rtc_force_fast SURROUND(coredump_rtc_fast),
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rtc_coredump -> rtc_data SURROUND(coredump_rtc),
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rtc_coredump -> rtc_data SURROUND(coredump_rtc),
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dram_coredump -> dram0_data SURROUND(coredump_dram)
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dram_coredump -> dram0_data SURROUND(coredump_dram),
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if IDF_TARGET_ESP32S2 = n:
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iram_coredump -> iram0_data SURROUND(coredump_iram)
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* (coredump_default);
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iram_coredump -> iram0_data SURROUND(coredump_iram)
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[mapping:espcoredump]
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[mapping:espcoredump]
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archive: libespcoredump.a
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archive: libespcoredump.a
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60
components/espcoredump/test/test_sections.c
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60
components/espcoredump/test/test_sections.c
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@ -0,0 +1,60 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "unity.h"
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#include "esp_attr.h"
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/* Global variables that should be part of the coredump */
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COREDUMP_IRAM_DATA_ATTR uint32_t var_iram = 0x42;
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COREDUMP_DRAM_ATTR uint32_t var_dram = 0x43;
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COREDUMP_RTC_DATA_ATTR uint32_t var_rtc = 0x44;
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COREDUMP_RTC_FAST_ATTR uint32_t var_rtcfast = 0x45;
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/* Memory regions to dump, defined at compile time. */
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extern int _coredump_dram_start;
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extern int _coredump_dram_end;
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extern int _coredump_iram_start;
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extern int _coredump_iram_end;
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extern int _coredump_rtc_start;
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extern int _coredump_rtc_end;
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extern int _coredump_rtc_fast_start;
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extern int _coredump_rtc_fast_end;
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static inline bool is_addr_in_region(void* addr, uint8_t* region, int region_size)
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{
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const void* start = (void*) region;
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const void* end = (void*) (region + region_size);
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return addr >= start && addr < end;
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}
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TEST_CASE("test variables presence in core dump sections", "[espcoredump]")
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{
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uint32_t section_start = 0;
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uint32_t section_size = 0;
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/* Check DRAM coredump section */
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section_start = (uint32_t)&_coredump_dram_start;
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section_size = (uint8_t *)&_coredump_dram_end - (uint8_t *)&_coredump_dram_start;
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TEST_ASSERT(section_size > 0);
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TEST_ASSERT(is_addr_in_region(&var_dram, (uint8_t*) section_start, section_size));
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#if IRAM_8BIT_ACCESSIBLE
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/* Check IRAM coredump section */
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section_start = (uint32_t)&_coredump_iram_start;
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section_size = (uint8_t *)&_coredump_iram_end - (uint8_t *)&_coredump_iram_start;
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TEST_ASSERT(section_size > 0);
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TEST_ASSERT(is_addr_in_region(&var_iram, (uint8_t*) section_start, section_size));
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#endif
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/* Check RTC coredump section */
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section_start = (uint32_t)&_coredump_rtc_start;
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section_size = (uint8_t *)&_coredump_rtc_end - (uint8_t *)&_coredump_rtc_start;
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TEST_ASSERT(section_size > 0);
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TEST_ASSERT(is_addr_in_region(&var_rtc, (uint8_t*) section_start, section_size));
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/* Check RTC Fast coredump section */
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section_start = (uint32_t)&_coredump_rtc_fast_start;
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section_size = (uint8_t *)&_coredump_rtc_fast_end - (uint8_t *)&_coredump_rtc_fast_start;
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TEST_ASSERT(section_size > 0);
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TEST_ASSERT(is_addr_in_region(&var_rtcfast, (uint8_t*) section_start, section_size));
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}
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