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refactor(soc): sort esp32 soc headers

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This commit is contained in:
laokaiyao 2024-09-03 16:20:04 +08:00
parent 0fb74b17ab
commit a02b0c52e5
59 changed files with 313 additions and 560 deletions
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2
.codespellrc
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@ -1,4 +1,4 @@
[codespell]
skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*,*.pem
ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr
ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr,oen
write-changes = true

20
components/soc/esp32/include/soc/hwcrypto_reg.h
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@ -1,20 +1,12 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc.h"
#include "soc/soc.h"
/* registers for RSA acceleration via Multiple Precision Integer ops */
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)

18
components/soc/esp32/include/soc/nrx_reg.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

2
components/soc/esp32/include/soc/soc.h
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@ -14,7 +14,7 @@
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#include "soc/reg_base.h"
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)

0
components/soc/esp32/register/soc/.gitkeep
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2
components/soc/esp32/include/soc/apb_ctrl_reg.h → components/soc/esp32/register/soc/apb_ctrl_reg.h
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@ -8,7 +8,7 @@
#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
#include "soc.h"
#include "soc/soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: */

0
components/soc/esp32/include/soc/apb_ctrl_struct.h → components/soc/esp32/register/soc/apb_ctrl_struct.h
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15
components/soc/esp32/include/soc/dport_reg.h → components/soc/esp32/register/soc/dport_reg.h
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@ -1,15 +1,14 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
#pragma once
#include "soc.h"
#include "soc/soc.h"
#ifndef __ASSEMBLER__
#include "dport_access.h"
#include "soc/dport_access.h"
#endif
/* Registers defined in this header file must be accessed using special macros,
@ -3210,8 +3209,8 @@
#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF
#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0
/* register layout:
* BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
* INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
* BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
* INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
*/
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F
@ -4287,5 +4286,3 @@
#define TRACEMEM_MUX_BLK0_ONLY 1
#define TRACEMEM_MUX_BLK1_ONLY 2
#define TRACEMEM_MUX_PROBLK1_APPBLK0 3
#endif /*_SOC_DPORT_REG_H_ */

2
components/soc/esp32/include/soc/efuse_reg.h → components/soc/esp32/register/soc/efuse_reg.h
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@ -7,7 +7,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "efuse_defs.h"
#include "soc/efuse_defs.h"
#ifdef __cplusplus
extern "C" {
#endif

0
components/soc/esp32/include/soc/efuse_struct.h → components/soc/esp32/register/soc/efuse_struct.h
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0
components/soc/esp32/include/soc/emac_dma_struct.h → components/soc/esp32/register/soc/emac_dma_struct.h
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0
components/soc/esp32/include/soc/emac_ext_struct.h → components/soc/esp32/register/soc/emac_ext_struct.h
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0
components/soc/esp32/include/soc/emac_mac_struct.h → components/soc/esp32/register/soc/emac_mac_struct.h
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20
components/soc/esp32/include/soc/gpio_reg.h → components/soc/esp32/register/soc/gpio_reg.h
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@ -1,20 +1,12 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_REG_H_
#define _SOC_GPIO_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000)
/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */
/*description: NA*/

2
components/soc/esp32/include/soc/gpio_sd_reg.h → components/soc/esp32/register/soc/gpio_sd_reg.h
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@ -6,7 +6,7 @@
#pragma once
#include "soc.h"
#include "soc/soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */

0
components/soc/esp32/include/soc/gpio_sd_struct.h → components/soc/esp32/register/soc/gpio_sd_struct.h
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20
components/soc/esp32/include/soc/gpio_struct.h → components/soc/esp32/register/soc/gpio_struct.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_STRUCT_H_
#define _SOC_GPIO_STRUCT_H_
@ -200,7 +192,7 @@ typedef volatile struct gpio_dev_s {
struct {
uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/
uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/
uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/
uint32_t oen_sel: 1; /*weather using the logical output enable signal or not using the value setting by the register*/
uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/
uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
};

20
components/soc/esp32/include/soc/hinf_reg.h → components/soc/esp32/register/soc/hinf_reg.h
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@ -1,21 +1,13 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HINF_REG_H_
#define _SOC_HINF_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
/*description: */

18
components/soc/esp32/include/soc/hinf_struct.h → components/soc/esp32/register/soc/hinf_struct.h
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@ -1,16 +1,8 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HINF_STRUCT_H_
#define _SOC_HINF_STRUCT_H_

20
components/soc/esp32/include/soc/host_reg.h → components/soc/esp32/register/soc/host_reg.h
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@ -1,21 +1,13 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HOST_REG_H_
#define _SOC_HOST_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define HOST_SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
/* HOST_SLC_FUNC2_INT : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: */

22
components/soc/esp32/include/soc/host_struct.h → components/soc/esp32/register/soc/host_struct.h
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@ -1,16 +1,8 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HOST_STRUCT_H_
#define _SOC_HOST_STRUCT_H_
@ -703,14 +695,14 @@ typedef volatile struct host_dev_s {
} slc1_int_ena;
union {
struct {
uint32_t infor: 20;
uint32_t infor: 20; // codespell:ignore infor
uint32_t reserved20: 12;
};
uint32_t val;
} slc0_rx_infor;
union {
struct {
uint32_t infor: 20;
uint32_t infor: 20; // codespell:ignore infor
uint32_t reserved20: 12;
};
uint32_t val;

28
components/soc/esp32/include/soc/i2c_reg.h → components/soc/esp32/register/soc/i2c_reg.h
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@ -1,21 +1,13 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2C_REG_H_
#define _SOC_I2C_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
@ -35,7 +27,7 @@
#define I2C_CLK_EN_V 0x1
#define I2C_CLK_EN_S 8
/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: This bit is used to control the storage mode for received datas.
/*description: This bit is used to control the storage mode for received data.
1: receive data from most significant bit 0: receive data from least significant bit*/
#define I2C_RX_LSB_FIRST (BIT(7))
#define I2C_RX_LSB_FIRST_M (BIT(7))
@ -69,14 +61,14 @@
#define I2C_SAMPLE_SCL_LEVEL_V 0x1
#define I2C_SAMPLE_SCL_LEVEL_S 2
/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1: normally ouput scl clock 0: exchange the function of scl_o
/*description: 1: normally output scl clock 0: exchange the function of scl_o
and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
#define I2C_SCL_FORCE_OUT (BIT(1))
#define I2C_SCL_FORCE_OUT_M (BIT(1))
#define I2C_SCL_FORCE_OUT_V 0x1
#define I2C_SCL_FORCE_OUT_S 1
/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: 1: normally ouput sda data 0: exchange the function of sda_o
/*description: 1: normally output sda data 0: exchange the function of sda_o
and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
#define I2C_SDA_FORCE_OUT (BIT(0))
#define I2C_SDA_FORCE_OUT_M (BIT(0))
@ -243,7 +235,7 @@
#define I2C_FIFO_ADDR_CFG_EN_V 0x1
#define I2C_FIFO_ADDR_CFG_EN_S 11
/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to enble apb nonfifo access.*/
/*description: Set this bit to enable apb nonfifo access.*/
#define I2C_NONFIFO_EN (BIT(10))
#define I2C_NONFIFO_EN_M (BIT(10))
#define I2C_NONFIFO_EN_V 0x1

20
components/soc/esp32/include/soc/i2c_struct.h → components/soc/esp32/register/soc/i2c_struct.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2C_STRUCT_H_
#define _SOC_I2C_STRUCT_H_
@ -92,7 +84,7 @@ typedef volatile struct i2c_dev_s {
struct {
uint32_t rx_fifo_full_thrhd: 5;
uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/
uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/
uint32_t nonfifo_en: 1; /*Set this bit to enable apb nonfifo access.*/
uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/
uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/

2
components/soc/esp32/include/soc/i2s_reg.h → components/soc/esp32/register/soc/i2s_reg.h
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@ -6,7 +6,7 @@
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))

0
components/soc/esp32/include/soc/i2s_struct.h → components/soc/esp32/register/soc/i2s_struct.h
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2
components/soc/esp32/include/soc/io_mux_reg.h → components/soc/esp32/register/soc/io_mux_reg.h
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@ -6,7 +6,7 @@
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#include "soc.h"
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */

52
components/soc/esp32/include/soc/ledc_reg.h → components/soc/esp32/register/soc/ledc_reg.h
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@ -1,21 +1,13 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LEDC_REG_H_
#define _SOC_LEDC_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: This bit is clock gating control signal. when software config
@ -56,7 +48,7 @@
#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)
/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH0 0x01FFFFFF
#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
#define LEDC_DUTY_HSCH0_V 0x1FFFFFF
@ -141,7 +133,7 @@
#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)
/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH1 0x01FFFFFF
#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
#define LEDC_DUTY_HSCH1_V 0x1FFFFFF
@ -226,7 +218,7 @@
#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)
/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH2 0x01FFFFFF
#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
#define LEDC_DUTY_HSCH2_V 0x1FFFFFF
@ -311,7 +303,7 @@
#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)
/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH3 0x01FFFFFF
#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
#define LEDC_DUTY_HSCH3_V 0x1FFFFFF
@ -396,7 +388,7 @@
#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)
/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH4 0x01FFFFFF
#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
#define LEDC_DUTY_HSCH4_V 0x1FFFFFF
@ -481,7 +473,7 @@
#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)
/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH5 0x01FFFFFF
#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
#define LEDC_DUTY_HSCH5_V 0x1FFFFFF
@ -566,7 +558,7 @@
#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)
/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH6 0x01FFFFFF
#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
#define LEDC_DUTY_HSCH6_V 0x1FFFFFF
@ -651,7 +643,7 @@
#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)
/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When hstimerx(x=[0
3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH7 0x01FFFFFF
#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
#define LEDC_DUTY_HSCH7_V 0x1FFFFFF
@ -743,7 +735,7 @@
#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8)
/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH0 0x01FFFFFF
#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
#define LEDC_DUTY_LSCH0_V 0x1FFFFFF
@ -835,7 +827,7 @@
#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC)
/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH1 0x01FFFFFF
#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
#define LEDC_DUTY_LSCH1_V 0x1FFFFFF
@ -927,7 +919,7 @@
#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0)
/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH2 0x01FFFFFF
#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
#define LEDC_DUTY_LSCH2_V 0x1FFFFFF
@ -1019,7 +1011,7 @@
#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4)
/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH3 0x01FFFFFF
#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
#define LEDC_DUTY_LSCH3_V 0x1FFFFFF
@ -1111,7 +1103,7 @@
#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8)
/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH4 0x01FFFFFF
#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
#define LEDC_DUTY_LSCH4_V 0x1FFFFFF
@ -1203,7 +1195,7 @@
#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C)
/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH5 0x01FFFFFF
#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
#define LEDC_DUTY_LSCH5_V 0x1FFFFFF
@ -1295,7 +1287,7 @@
#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120)
/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH6 0x01FFFFFF
#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
#define LEDC_DUTY_LSCH6_V 0x1FFFFFF
@ -1387,7 +1379,7 @@
#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134)
/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: The register is used to control output duty. When lstimerx(x=[0
3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
3]) chosen by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_LSCH7 0x01FFFFFF
#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
#define LEDC_DUTY_LSCH7_V 0x1FFFFFF

18
components/soc/esp32/include/soc/ledc_struct.h → components/soc/esp32/register/soc/ledc_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_

14
components/soc/esp32/include/soc/mcpwm_reg.h → components/soc/esp32/register/soc/mcpwm_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -921,7 +921,7 @@ extern "C" {
#define MCPWM_DT0_RED_S 0
/** MCPWM_CARRIER0_CFG_REG register
* PWM generator 0 carrier enable and configuratoin
* PWM generator 0 carrier enable and configuration
*/
#define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64)
/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0;
@ -1625,7 +1625,7 @@ extern "C" {
#define MCPWM_DT1_RED_S 0
/** MCPWM_CARRIER1_CFG_REG register
* PWM generator 1 carrier enable and configuratoin
* PWM generator 1 carrier enable and configuration
*/
#define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c)
/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0;
@ -2328,7 +2328,7 @@ extern "C" {
#define MCPWM_DT2_RED_S 0
/** MCPWM_CARRIER2_CFG_REG register
* PWM generator 2 carrier enable and configuratoin
* PWM generator 2 carrier enable and configuration
*/
#define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4)
/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0;
@ -2693,7 +2693,7 @@ extern "C" {
#define MCPWM_CAP0_MODE_V 0x00000003U
#define MCPWM_CAP0_MODE_S 1
/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
* Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
* 1
*/
#define MCPWM_CAP0_PRESCALE 0x000000FFU
@ -2736,7 +2736,7 @@ extern "C" {
#define MCPWM_CAP1_MODE_V 0x00000003U
#define MCPWM_CAP1_MODE_S 1
/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
* Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
* 1
*/
#define MCPWM_CAP1_PRESCALE 0x000000FFU
@ -2779,7 +2779,7 @@ extern "C" {
#define MCPWM_CAP2_MODE_V 0x00000003U
#define MCPWM_CAP2_MODE_S 1
/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
* Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
* 1
*/
#define MCPWM_CAP2_PRESCALE 0x000000FFU

4
components/soc/esp32/include/soc/mcpwm_struct.h → components/soc/esp32/register/soc/mcpwm_struct.h
View File

@ -474,7 +474,7 @@ typedef union {
} mcpwm_dt_red_cfg_reg_t;
/** Type of carrier_cfg register
* PWM generator carrier enable and configuratoin
* PWM generator carrier enable and configuration
*/
typedef union {
struct {
@ -746,7 +746,7 @@ typedef union {
*/
uint32_t capn_mode: 2;
/** capn_prescale : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE +
* Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE +
* 1
*/
uint32_t capn_prescale: 8;

32
components/soc/esp32/include/soc/pcnt_reg.h → components/soc/esp32/register/soc/pcnt_reg.h
View File

@ -102,7 +102,7 @@
#define PCNT_FILTER_EN_U0_V 0x1
#define PCNT_FILTER_EN_U0_S 10
/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit0.*/
#define PCNT_FILTER_THRES_U0 0x000003FF
#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))
@ -125,7 +125,7 @@
#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008)
/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit0.*/
/*description: This register is used to configure thr_l_lim value for unit0.*/
#define PCNT_CNT_L_LIM_U0 0x0000FFFF
#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))
#define PCNT_CNT_L_LIM_U0_V 0xFFFF
@ -231,7 +231,7 @@
#define PCNT_FILTER_EN_U1_V 0x1
#define PCNT_FILTER_EN_U1_S 10
/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit1.*/
#define PCNT_FILTER_THRES_U1 0x000003FF
#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))
@ -254,7 +254,7 @@
#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014)
/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit1.*/
/*description: This register is used to configure thr_l_lim value for unit1.*/
#define PCNT_CNT_L_LIM_U1 0x0000FFFF
#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))
#define PCNT_CNT_L_LIM_U1_V 0xFFFF
@ -360,7 +360,7 @@
#define PCNT_FILTER_EN_U2_V 0x1
#define PCNT_FILTER_EN_U2_S 10
/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit2.*/
#define PCNT_FILTER_THRES_U2 0x000003FF
#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))
@ -383,7 +383,7 @@
#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020)
/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit2.*/
/*description: This register is used to configure thr_l_lim value for unit2.*/
#define PCNT_CNT_L_LIM_U2 0x0000FFFF
#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))
#define PCNT_CNT_L_LIM_U2_V 0xFFFF
@ -489,7 +489,7 @@
#define PCNT_FILTER_EN_U3_V 0x1
#define PCNT_FILTER_EN_U3_S 10
/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit3.*/
#define PCNT_FILTER_THRES_U3 0x000003FF
#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))
@ -512,7 +512,7 @@
#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c)
/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit3.*/
/*description: This register is used to configure thr_l_lim value for unit3.*/
#define PCNT_CNT_L_LIM_U3 0x0000FFFF
#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))
#define PCNT_CNT_L_LIM_U3_V 0xFFFF
@ -618,7 +618,7 @@
#define PCNT_FILTER_EN_U4_V 0x1
#define PCNT_FILTER_EN_U4_S 10
/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit4.*/
#define PCNT_FILTER_THRES_U4 0x000003FF
#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S))
@ -641,7 +641,7 @@
#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038)
/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit4.*/
/*description: This register is used to configure thr_l_lim value for unit4.*/
#define PCNT_CNT_L_LIM_U4 0x0000FFFF
#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S))
#define PCNT_CNT_L_LIM_U4_V 0xFFFF
@ -747,7 +747,7 @@
#define PCNT_FILTER_EN_U5_V 0x1
#define PCNT_FILTER_EN_U5_S 10
/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit5.*/
#define PCNT_FILTER_THRES_U5 0x000003FF
#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S))
@ -770,7 +770,7 @@
#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044)
/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit5.*/
/*description: This register is used to configure thr_l_lim value for unit5.*/
#define PCNT_CNT_L_LIM_U5 0x0000FFFF
#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S))
#define PCNT_CNT_L_LIM_U5_V 0xFFFF
@ -876,7 +876,7 @@
#define PCNT_FILTER_EN_U6_V 0x1
#define PCNT_FILTER_EN_U6_S 10
/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit6.*/
#define PCNT_FILTER_THRES_U6 0x000003FF
#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S))
@ -899,7 +899,7 @@
#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050)
/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit6.*/
/*description: This register is used to configure thr_l_lim value for unit6.*/
#define PCNT_CNT_L_LIM_U6 0x0000FFFF
#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S))
#define PCNT_CNT_L_LIM_U6_V 0xFFFF
@ -1005,7 +1005,7 @@
#define PCNT_FILTER_EN_U7_V 0x1
#define PCNT_FILTER_EN_U7_S 10
/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
/*description: This register is used to filter pluse whose width is smaller
/*description: This register is used to filter pulse whose width is smaller
than this value for unit7.*/
#define PCNT_FILTER_THRES_U7 0x000003FF
#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S))
@ -1028,7 +1028,7 @@
#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c)
/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
/*description: This register is used to confiugre thr_l_lim value for unit7.*/
/*description: This register is used to configure thr_l_lim value for unit7.*/
#define PCNT_CNT_L_LIM_U7 0x0000FFFF
#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S))
#define PCNT_CNT_L_LIM_U7_V 0xFFFF

0
components/soc/esp32/include/soc/pcnt_struct.h → components/soc/esp32/register/soc/pcnt_struct.h
View File

0
components/soc/esp32/include/soc/reg_base.h → components/soc/esp32/register/soc/reg_base.h
View File

68
components/soc/esp32/include/soc/rmt_reg.h → components/soc/esp32/register/soc/rmt_reg.h
View File

@ -5,7 +5,7 @@
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
@ -146,7 +146,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH0_V 0x1
#define RMT_MEM_WR_RST_CH0_S 2
/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel0.*/
/*description: Set this bit to enable receiving data for channel0.*/
#define RMT_RX_EN_CH0 (BIT(1))
#define RMT_RX_EN_CH0_M (BIT(1))
#define RMT_RX_EN_CH0_V 0x1
@ -264,7 +264,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH1_V 0x1
#define RMT_MEM_WR_RST_CH1_S 2
/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel1.*/
/*description: Set this bit to enable receiving data for channel1.*/
#define RMT_RX_EN_CH1 (BIT(1))
#define RMT_RX_EN_CH1_M (BIT(1))
#define RMT_RX_EN_CH1_V 0x1
@ -382,7 +382,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH2_V 0x1
#define RMT_MEM_WR_RST_CH2_S 2
/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel2.*/
/*description: Set this bit to enable receiving data for channel2.*/
#define RMT_RX_EN_CH2 (BIT(1))
#define RMT_RX_EN_CH2_M (BIT(1))
#define RMT_RX_EN_CH2_V 0x1
@ -500,7 +500,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH3_V 0x1
#define RMT_MEM_WR_RST_CH3_S 2
/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel3.*/
/*description: Set this bit to enable receiving data for channel3.*/
#define RMT_RX_EN_CH3 (BIT(1))
#define RMT_RX_EN_CH3_M (BIT(1))
#define RMT_RX_EN_CH3_V 0x1
@ -618,7 +618,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH4_V 0x1
#define RMT_MEM_WR_RST_CH4_S 2
/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel4.*/
/*description: Set this bit to enable receiving data for channel4.*/
#define RMT_RX_EN_CH4 (BIT(1))
#define RMT_RX_EN_CH4_M (BIT(1))
#define RMT_RX_EN_CH4_V 0x1
@ -736,7 +736,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH5_V 0x1
#define RMT_MEM_WR_RST_CH5_S 2
/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel5.*/
/*description: Set this bit to enable receiving data for channel5.*/
#define RMT_RX_EN_CH5 (BIT(1))
#define RMT_RX_EN_CH5_M (BIT(1))
#define RMT_RX_EN_CH5_V 0x1
@ -854,7 +854,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH6_V 0x1
#define RMT_MEM_WR_RST_CH6_S 2
/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel6.*/
/*description: Set this bit to enable receiving data for channel6.*/
#define RMT_RX_EN_CH6 (BIT(1))
#define RMT_RX_EN_CH6_M (BIT(1))
#define RMT_RX_EN_CH6_V 0x1
@ -972,7 +972,7 @@ extern "C" {
#define RMT_MEM_WR_RST_CH7_V 0x1
#define RMT_MEM_WR_RST_CH7_S 2
/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enbale receving data for channel7.*/
/*description: Set this bit to enable receiving data for channel7.*/
#define RMT_RX_EN_CH7 (BIT(1))
#define RMT_RX_EN_CH7_M (BIT(1))
#define RMT_RX_EN_CH7_V 0x1
@ -1547,63 +1547,63 @@ extern "C" {
#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0)
/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel7 turns to high level when
transmitter in channle 7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channel 7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31))
#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31))
#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31
/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 6 turns to high level when
transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30))
#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30))
#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30
/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 5 turns to high level when
transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29))
#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29))
#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29
/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 4 turns to high level when
transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28))
#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28))
#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28
/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 3 turns to high level when
transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27))
#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27))
#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27
/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 2 turns to high level when
transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26))
#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26))
#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26
/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 1 turns to high level when
transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25))
#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25))
#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25
/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 0 turns to high level when
transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/
transmitter in channle0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24))
#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24))
#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24
/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 7 turns to high level when
channle 7 detects some errors.*/
channel 7 detects some errors.*/
#define RMT_CH7_ERR_INT_RAW (BIT(23))
#define RMT_CH7_ERR_INT_RAW_M (BIT(23))
#define RMT_CH7_ERR_INT_RAW_V 0x1
@ -1624,7 +1624,7 @@ extern "C" {
#define RMT_CH7_TX_END_INT_RAW_S 21
/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 6 turns to high level when
channle 6 detects some errors.*/
channel 6 detects some errors.*/
#define RMT_CH6_ERR_INT_RAW (BIT(20))
#define RMT_CH6_ERR_INT_RAW_M (BIT(20))
#define RMT_CH6_ERR_INT_RAW_V 0x1
@ -1645,7 +1645,7 @@ extern "C" {
#define RMT_CH6_TX_END_INT_RAW_S 18
/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 5 turns to high level when
channle 5 detects some errors.*/
channel 5 detects some errors.*/
#define RMT_CH5_ERR_INT_RAW (BIT(17))
#define RMT_CH5_ERR_INT_RAW_M (BIT(17))
#define RMT_CH5_ERR_INT_RAW_V 0x1
@ -1666,7 +1666,7 @@ extern "C" {
#define RMT_CH5_TX_END_INT_RAW_S 15
/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 4 turns to high level when
channle 4 detects some errors.*/
channel 4 detects some errors.*/
#define RMT_CH4_ERR_INT_RAW (BIT(14))
#define RMT_CH4_ERR_INT_RAW_M (BIT(14))
#define RMT_CH4_ERR_INT_RAW_V 0x1
@ -1687,7 +1687,7 @@ extern "C" {
#define RMT_CH4_TX_END_INT_RAW_S 12
/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 3 turns to high level when
channle 3 detects some errors.*/
channel 3 detects some errors.*/
#define RMT_CH3_ERR_INT_RAW (BIT(11))
#define RMT_CH3_ERR_INT_RAW_M (BIT(11))
#define RMT_CH3_ERR_INT_RAW_V 0x1
@ -1708,7 +1708,7 @@ extern "C" {
#define RMT_CH3_TX_END_INT_RAW_S 9
/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 2 turns to high level when
channle 2 detects some errors.*/
channel 2 detects some errors.*/
#define RMT_CH2_ERR_INT_RAW (BIT(8))
#define RMT_CH2_ERR_INT_RAW_M (BIT(8))
#define RMT_CH2_ERR_INT_RAW_V 0x1
@ -1729,7 +1729,7 @@ extern "C" {
#define RMT_CH2_TX_END_INT_RAW_S 6
/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 1 turns to high level when
channle 1 detects some errors.*/
channel 1 detects some errors.*/
#define RMT_CH1_ERR_INT_RAW (BIT(5))
#define RMT_CH1_ERR_INT_RAW_M (BIT(5))
#define RMT_CH1_ERR_INT_RAW_V 0x1
@ -1750,7 +1750,7 @@ extern "C" {
#define RMT_CH1_TX_END_INT_RAW_S 3
/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The interrupt raw bit for channel 0 turns to high level when
channle 0 detects some errors.*/
channel 0 detects some errors.*/
#define RMT_CH0_ERR_INT_RAW (BIT(2))
#define RMT_CH0_ERR_INT_RAW_M (BIT(2))
#define RMT_CH0_ERR_INT_RAW_V 0x1
@ -2498,7 +2498,7 @@ extern "C" {
#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0)
/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0
/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 data then channel0
produce the relative interrupt.*/
#define RMT_TX_LIM_CH0 0x000001FF
#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))
@ -2507,7 +2507,7 @@ extern "C" {
#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4)
/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1
/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 data then channel1
produce the relative interrupt.*/
#define RMT_TX_LIM_CH1 0x000001FF
#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))
@ -2516,7 +2516,7 @@ extern "C" {
#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8)
/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2
/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 data then channel2
produce the relative interrupt.*/
#define RMT_TX_LIM_CH2 0x000001FF
#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S))
@ -2525,7 +2525,7 @@ extern "C" {
#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc)
/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3
/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 data then channel3
produce the relative interrupt.*/
#define RMT_TX_LIM_CH3 0x000001FF
#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S))
@ -2534,7 +2534,7 @@ extern "C" {
#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0)
/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4
/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 data then channel4
produce the relative interrupt.*/
#define RMT_TX_LIM_CH4 0x000001FF
#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S))
@ -2543,7 +2543,7 @@ extern "C" {
#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4)
/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5
/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 data then channel5
produce the relative interrupt.*/
#define RMT_TX_LIM_CH5 0x000001FF
#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S))
@ -2552,7 +2552,7 @@ extern "C" {
#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8)
/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6
/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 data then channel6
produce the relative interrupt.*/
#define RMT_TX_LIM_CH6 0x000001FF
#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S))
@ -2561,7 +2561,7 @@ extern "C" {
#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec)
/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7
/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 data then channel7
produce the relative interrupt.*/
#define RMT_TX_LIM_CH7 0x000001FF
#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S))
@ -2570,7 +2570,7 @@ extern "C" {
#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0)
/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: when datas need to be send is more than channel's mem can store
/*description: when data need to be send is more than channel's mem can store
then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/
#define RMT_MEM_TX_WRAP_EN (BIT(1))
#define RMT_MEM_TX_WRAP_EN_M (BIT(1))

0
components/soc/esp32/include/soc/rmt_struct.h → components/soc/esp32/register/soc/rmt_struct.h
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2
components/soc/esp32/include/soc/rtc_cntl_reg.h → components/soc/esp32/register/soc/rtc_cntl_reg.h
View File

@ -6,7 +6,7 @@
#ifndef _SOC_RTC_CNTL_REG_H_
#define _SOC_RTC_CNTL_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
/*description: SW system reset*/

18
components/soc/esp32/include/soc/rtc_cntl_struct.h → components/soc/esp32/register/soc/rtc_cntl_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_

20
components/soc/esp32/include/soc/rtc_i2c_reg.h → components/soc/esp32/register/soc/rtc_i2c_reg.h
View File

@ -1,20 +1,12 @@
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
/**
* This file lists peripheral registers of an I2C controller which is part of the RTC.

40
components/soc/esp32/include/soc/rtc_io_reg.h → components/soc/esp32/register/soc/rtc_io_reg.h
View File

@ -1,21 +1,13 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_IO_REG_H_
#define _SOC_RTC_IO_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0)
/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */
/*description: GPIO0~17 output value*/
@ -1186,7 +1178,7 @@
#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available GPIO4*/
#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1
@ -1278,7 +1270,7 @@
#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.GPIO0*/
#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1
@ -1370,7 +1362,7 @@
#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.GPIO2*/
#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1
@ -1462,7 +1454,7 @@
#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.MTDO*/
#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1
@ -1554,7 +1546,7 @@
#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.MTCK*/
#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1
@ -1646,7 +1638,7 @@
#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.MTDI*/
#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1
@ -1738,7 +1730,7 @@
#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.MTMS*/
#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1
@ -1830,7 +1822,7 @@
#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available.GPIO27*/
#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12))
#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1
@ -1862,7 +1854,7 @@
#define RTC_IO_TOUCH_PAD8_XPD_V 0x1
#define RTC_IO_TOUCH_PAD8_XPD_S 20
/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available*/
#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))
#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19))
#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1
@ -1894,7 +1886,7 @@
#define RTC_IO_TOUCH_PAD9_XPD_V 0x1
#define RTC_IO_TOUCH_PAD9_XPD_S 20
/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
/*description: connect the rtc pad input to digital pad input Ó0Ó is available*/
#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))
#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19))
#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1

68
components/soc/esp32/include/soc/rtc_io_struct.h → components/soc/esp32/register/soc/rtc_io_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_IO_STRUCT_H_
#define _SOC_RTC_IO_STRUCT_H_
@ -142,14 +134,14 @@ typedef volatile struct rtc_io_dev_s {
uint32_t sense1_slp_ie: 1; /*the input enable of the pad in sleep status*/
uint32_t sense1_slp_sel: 1; /*the sleep status selection signal of the pad*/
uint32_t sense1_fun_sel: 2; /*the functional selection signal of the pad*/
uint32_t sense4_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t sense3_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t sense2_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t sense1_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t sense4_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t sense3_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t sense2_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t sense1_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t sense4_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t sense3_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t sense2_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t sense1_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t sense4_hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t sense3_hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t sense2_hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t sense1_hold: 1; /*hold the current value of the output when setting the hold to 1*/
};
uint32_t val;
} sensor_pads;
@ -164,10 +156,10 @@ typedef volatile struct rtc_io_dev_s {
uint32_t adc1_slp_ie: 1; /*the input enable of the pad in sleep status*/
uint32_t adc1_slp_sel: 1; /*the sleep status selection signal of the pad*/
uint32_t adc1_fun_sel: 2; /*the functional selection signal of the pad*/
uint32_t adc2_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t adc1_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t adc2_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t adc1_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t adc2_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t adc1_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t adc2_hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t adc1_hold: 1; /*hold the current value of the output when setting the hold to 1*/
};
uint32_t val;
} adc_pad;
@ -180,12 +172,12 @@ typedef volatile struct rtc_io_dev_s {
uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/
uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/
uint32_t fun_sel: 2; /*the functional selection signal of the pad*/
uint32_t mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t xpd_dac: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
uint32_t dac: 8; /*PAD DAC1 control code.*/
uint32_t rue: 1; /*the pull up enable of the pad*/
uint32_t rde: 1; /*the pull down enable of the pad*/
uint32_t hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t drv: 2; /*the driver strength of the pad*/
};
uint32_t val;
@ -205,17 +197,17 @@ typedef volatile struct rtc_io_dev_s {
uint32_t x32n_slp_ie: 1; /*the input enable of the pad in sleep status*/
uint32_t x32n_slp_sel: 1; /*the sleep status selection signal of the pad*/
uint32_t x32n_fun_sel: 2; /*the functional selection signal of the pad*/
uint32_t x32p_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t x32n_mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t x32p_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t x32n_mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t xpd_xtal_32k: 1; /*Power up 32kHz crystal oscillator*/
uint32_t dac_xtal_32k: 2; /*32K XTAL bias current DAC.*/
uint32_t x32p_rue: 1; /*the pull up enable of the pad*/
uint32_t x32p_rde: 1; /*the pull down enable of the pad*/
uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t x32p_drv: 2; /*the driver strength of the pad*/
uint32_t x32n_rue: 1; /*the pull up enable of the pad*/
uint32_t x32n_rde: 1; /*the pull down enable of the pad*/
uint32_t x32n_hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t x32n_hold: 1; /*hold the current value of the output when setting the hold to 1*/
uint32_t x32n_drv: 2; /*the driver strength of the pad*/
};
uint32_t val;
@ -234,13 +226,13 @@ typedef volatile struct rtc_io_dev_s {
union {
struct {
uint32_t reserved0: 12;
uint32_t to_gpio: 1; /*connect the rtc pad input to digital pad input <EFBFBD>0<EFBFBD> is availbale GPIO4*/
uint32_t to_gpio: 1; /*connect the rtc pad input to digital pad input 0 is available GPIO4*/
uint32_t fun_ie: 1; /*the input enable of the pad*/
uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/
uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/
uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/
uint32_t fun_sel: 2; /*the functional selection signal of the pad*/
uint32_t mux_sel: 1; /*<EFBFBD>1<EFBFBD> select the digital function <20>0<EFBFBD>slection the rtc function*/
uint32_t mux_sel: 1; /*1 select the digital function 0 select the rtc function*/
uint32_t xpd: 1; /*touch sensor power on.*/
uint32_t tie_opt: 1; /*default touch sensor tie option. 0: tie low 1: tie high.*/
uint32_t start: 1; /*start touch sensor.*/
@ -249,21 +241,21 @@ typedef volatile struct rtc_io_dev_s {
uint32_t rue: 1; /*the pull up enable of the pad*/
uint32_t rde: 1; /*the pull down enable of the pad*/
uint32_t drv: 2; /*the driver strength of the pad*/
uint32_t hold: 1; /*hold the current value of the output when setting the hold to <EFBFBD>1<EFBFBD>*/
uint32_t hold: 1; /*hold the current value of the output when setting the hold to 1*/
};
uint32_t val;
} touch_pad[10];
union {
struct {
uint32_t reserved0: 27;
uint32_t sel: 5; /*select the wakeup source <EFBFBD>0<EFBFBD> select GPIO0 <20>1<EFBFBD> select GPIO2 ...<2E>17<31> select GPIO17*/
uint32_t sel: 5; /*select the wakeup source 0 select GPIO0 1 select GPIO2 ...17 select GPIO17*/
};
uint32_t val;
} ext_wakeup0;
union {
struct {
uint32_t reserved0: 27;
uint32_t sel: 5; /*select the external xtl power source <EFBFBD>0<EFBFBD> select GPIO0 <20>1<EFBFBD> select GPIO2 ...<2E>17<31> select GPIO17*/
uint32_t sel: 5; /*select the external xtl power source 0 select GPIO0 1 select GPIO2 ...17 select GPIO17*/
};
uint32_t val;
} xtl_ext_ctr;
@ -271,8 +263,8 @@ typedef volatile struct rtc_io_dev_s {
struct {
uint32_t reserved0: 23;
uint32_t debug_bit_sel: 5;
uint32_t scl_sel: 2; /*<EFBFBD>0<EFBFBD> using TOUCH_PAD[0] as i2c clk <20>1<EFBFBD> using TOUCH_PAD[2] as i2c clk*/
uint32_t sda_sel: 2; /*<EFBFBD>0<EFBFBD> using TOUCH_PAD[1] as i2c sda <20>1<EFBFBD> using TOUCH_PAD[3] as i2c sda*/
uint32_t scl_sel: 2; /*0 using TOUCH_PAD[0] as i2c clk 1 using TOUCH_PAD[2] as i2c clk*/
uint32_t sda_sel: 2; /*0 using TOUCH_PAD[1] as i2c sda 1 using TOUCH_PAD[3] as i2c sda*/
};
uint32_t val;
} sar_i2c_io;

20
components/soc/esp32/include/soc/sdmmc_reg.h → components/soc/esp32/register/soc/sdmmc_reg.h
View File

@ -1,19 +1,11 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SDMMC_REG_H_
#define _SOC_SDMMC_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)

1
components/soc/esp32/include/soc/sdmmc_struct.h → components/soc/esp32/register/soc/sdmmc_struct.h
View File

@ -8,7 +8,6 @@
#include <stdint.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {

20
components/soc/esp32/include/soc/sens_reg.h → components/soc/esp32/register/soc/sens_reg.h
View File

@ -1,21 +1,13 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENS_REG_H_
#define _SOC_SENS_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0000)
/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */
/*description: Invert SAR ADC1 data*/

18
components/soc/esp32/include/soc/sens_struct.h → components/soc/esp32/register/soc/sens_struct.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENS_STRUCT_H_
#define _SOC_SENS_STRUCT_H_

20
components/soc/esp32/include/soc/slc_reg.h → components/soc/esp32/register/soc/slc_reg.h
View File

@ -1,21 +1,13 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SLC_REG_H_
#define _SOC_SLC_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0)
/* SLC_SLC1_TOKEN_SEL : R/W ;bitpos:[31] ;default: 1'h1 ; */
/*description: */

18
components/soc/esp32/include/soc/slc_struct.h → components/soc/esp32/register/soc/slc_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SLC_STRUCT_H_
#define _SOC_SLC_STRUCT_H_

2
components/soc/esp32/include/soc/spi_reg.h → components/soc/esp32/register/soc/spi_reg.h
View File

@ -7,7 +7,7 @@
#define __SPI_REG_H__
#include "soc.h"
#include "soc/soc.h"
#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 )))
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)

0
components/soc/esp32/include/soc/spi_struct.h → components/soc/esp32/register/soc/spi_struct.h
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20
components/soc/esp32/include/soc/syscon_reg.h → components/soc/esp32/register/soc/syscon_reg.h
View File

@ -1,20 +1,12 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* SYSCON_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: */

18
components/soc/esp32/include/soc/syscon_struct.h → components/soc/esp32/register/soc/syscon_struct.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_

2
components/soc/esp32/include/soc/timer_group_reg.h → components/soc/esp32/register/soc/timer_group_reg.h
View File

@ -6,7 +6,7 @@
#pragma once
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {

0
components/soc/esp32/include/soc/timer_group_struct.h → components/soc/esp32/register/soc/timer_group_struct.h
View File

6
components/soc/esp32/include/soc/twai_struct.h → components/soc/esp32/register/soc/twai_struct.h
View File

@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* ---------------------------- Register Layout ------------------------------ */
/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access

58
components/soc/esp32/include/soc/uart_reg.h → components/soc/esp32/register/soc/uart_reg.h
View File

@ -1,21 +1,13 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __UART_REG_H__
#define __UART_REG_H__
#include "soc.h"
#include "soc/soc.h"
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
@ -73,7 +65,7 @@
#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13
/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: This interrupt raw bit turns to high level when transmitter completes
sendding 0 after all the datas in transmitter's fifo are send.*/
sendding 0 after all the data in transmitter's fifo are send.*/
#define UART_TX_BRK_DONE_INT_RAW (BIT(12))
#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12))
#define UART_TX_BRK_DONE_INT_RAW_V 0x1
@ -198,7 +190,7 @@
#define UART_TX_DONE_INT_ST_V 0x1
#define UART_TX_DONE_INT_ST_S 14
/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
is set to 1.*/
#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))
#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))
@ -538,7 +530,7 @@
#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)
/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
/*description: when input pulse width is lower then this value igore this pulse.this
/*description: when input pulse width is lower then this value ignore this pulse.this
register is used in autobaud detect process.*/
#define UART_GLITCH_FILT 0x000000FF
#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
@ -578,7 +570,7 @@
#define UART_ST_UTX_OUT_V 0xF
#define UART_ST_UTX_OUT_S 24
/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in
/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid data in
transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
#define UART_TXFIFO_CNT 0x000000FF
#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
@ -610,7 +602,7 @@
#define UART_ST_URX_OUT_V 0xF
#define UART_ST_URX_OUT_S 8
/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in
/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid data in
receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
#define UART_RXFIFO_CNT 0x000000FF
#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
@ -735,7 +727,7 @@
#define UART_IRDA_DPLX_V 0x1
#define UART_IRDA_DPLX_S 9
/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to enbale transmitter to send 0 when the process
/*description: Set this bit to enable transmitter to send 0 when the process
of sending data is done.*/
#define UART_TXD_BRK (BIT(8))
#define UART_TXD_BRK_M (BIT(8))
@ -762,7 +754,7 @@
#define UART_STOP_BIT_NUM_V 0x3
#define UART_STOP_BIT_NUM_S 4
/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
/*description: This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
#define UART_BIT_NUM 0x00000003
#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
#define UART_BIT_NUM_V 0x3
@ -782,7 +774,7 @@
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: This is the enble bit for uart receiver's timeout function.*/
/*description: This is the enable bit for uart receiver's timeout function.*/
#define UART_RX_TOUT_EN (BIT(31))
#define UART_RX_TOUT_EN_M (BIT(31))
#define UART_RX_TOUT_EN_V 0x1
@ -834,7 +826,7 @@
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)
/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
/*description: This register stores the value of the maxinum duration time
/*description: This register stores the value of the maximum duration time
for the high level pulse. it is used in baudrate-detect process.*/
#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
@ -1015,7 +1007,7 @@
#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)
/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
/*description: This register is used to configure the duration time between
the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/
the at_cmd chars. when the duration time is less than this register value it will not take the data as continuous at_cmd chars.*/
#define UART_RX_GAP_TOUT 0x00FFFFFF
#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
#define UART_RX_GAP_TOUT_V 0xFFFFFF
@ -1023,7 +1015,7 @@
#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54)
/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
/*description: This register is used to configure the num of continous at_cmd
/*description: This register is used to configure the num of continuous at_cmd
chars received by receiver.*/
#define UART_CHAR_NUM 0x000000FF
#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
@ -1038,37 +1030,37 @@
#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58)
/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
/*description: refer to txfifo_empty_thrhd 's describtion.*/
/*description: refer to txfifo_empty_thrhd 's description.*/
#define UART_TX_MEM_EMPTY_THRHD 0x00000007
#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))
#define UART_TX_MEM_EMPTY_THRHD_V 0x7
#define UART_TX_MEM_EMPTY_THRHD_S 28
/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
/*description: refer to the rxfifo_full_thrhd's describtion.*/
/*description: refer to the rxfifo_full_thrhd's description.*/
#define UART_RX_MEM_FULL_THRHD 0x00000007
#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))
#define UART_RX_MEM_FULL_THRHD_V 0x7
#define UART_RX_MEM_FULL_THRHD_S 25
/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
/*description: refer to the uart_xoff_threshold's describtion.*/
/*description: refer to the uart_xoff_threshold's description.*/
#define UART_XOFF_THRESHOLD_H2 0x00000003
#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))
#define UART_XOFF_THRESHOLD_H2_V 0x3
#define UART_XOFF_THRESHOLD_H2_S 23
/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
/*description: refer to the uart_xon_threshold's describtion.*/
/*description: refer to the uart_xon_threshold's description.*/
#define UART_XON_THRESHOLD_H2 0x00000003
#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))
#define UART_XON_THRESHOLD_H2_V 0x3
#define UART_XON_THRESHOLD_H2_S 21
/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: refer to the rx_tout_thrhd's describtion.*/
/*description: refer to the rx_tout_thrhd's description.*/
#define UART_RX_TOUT_THRHD_H3 0x00000007
#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))
#define UART_RX_TOUT_THRHD_H3_V 0x7
#define UART_RX_TOUT_THRHD_H3_S 18
/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
/*description: refer to the rx_flow_thrhd's describtion.*/
/*description: refer to the rx_flow_thrhd's description.*/
#define UART_RX_FLOW_THRHD_H3 0x00000007
#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))
#define UART_RX_FLOW_THRHD_H3_V 0x7
@ -1126,13 +1118,13 @@
#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */
/*description: refer to the txfifo_cnt's describtion.*/
/*description: refer to the txfifo_cnt's description.*/
#define UART_TX_MEM_CNT 0x00000007
#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S))
#define UART_TX_MEM_CNT_V 0x7
#define UART_TX_MEM_CNT_S 3
/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: refer to the rxfifo_cnt's describtion.*/
/*description: refer to the rxfifo_cnt's description.*/
#define UART_RX_MEM_CNT 0x00000007
#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S))
#define UART_RX_MEM_CNT_V 0x7

20
components/soc/esp32/include/soc/uart_struct.h → components/soc/esp32/register/soc/uart_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
@ -294,7 +286,7 @@ typedef volatile struct uart_dev_s {
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continuous at_cmd chars.*/
uint32_t reserved24: 8;
};
uint32_t val;

32
components/soc/esp32/include/soc/uhci_reg.h → components/soc/esp32/register/soc/uhci_reg.h
View File

@ -1,21 +1,13 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UHCI_REG_H_
#define _SOC_UHCI_REG_H_
#include "soc.h"
#include "soc/soc.h"
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
@ -859,7 +851,7 @@
#define UHCI_AHB_TESTADDR_V 0x3
#define UHCI_AHB_TESTADDR_S 4
/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1)
/*description: bit2 is ahb bus test enable ,bit1 is used to choose write(1)
or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
#define UHCI_AHB_TESTMODE 0x00000007
#define UHCI_AHB_TESTMODE_M ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S))
@ -1154,21 +1146,21 @@
#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0xB0)
/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
/*description: This register stores the second char used to replace seperator
/*description: This register stores the second char used to replace separator
char in data . 0xdc 0xdb replace 0xc0 by default.*/
#define UHCI_SEPER_ESC_CHAR1 0x000000FF
#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
#define UHCI_SEPER_ESC_CHAR1_V 0xFF
#define UHCI_SEPER_ESC_CHAR1_S 16
/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
/*description: This register stores thee first char used to replace seperator char in data.*/
/*description: This register stores thee first char used to replace separator char in data.*/
#define UHCI_SEPER_ESC_CHAR0 0x000000FF
#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
#define UHCI_SEPER_ESC_CHAR0_V 0xFF
#define UHCI_SEPER_ESC_CHAR0_S 8
/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
/*description: This register stores the seperator char seperator char is used
to seperate the data frame.*/
/*description: This register stores the separator char separator char is used
to separate the data frame.*/
#define UHCI_SEPER_CHAR 0x000000FF
#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
#define UHCI_SEPER_CHAR_V 0xFF
@ -1189,7 +1181,7 @@
#define UHCI_ESC_SEQ0_CHAR0_S 8
/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
/*description: This register stores the first substitute char used to replace
the seperator char.*/
the separator char.*/
#define UHCI_ESC_SEQ0 0x000000FF
#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
#define UHCI_ESC_SEQ0_V 0xFF

18
components/soc/esp32/include/soc/uhci_struct.h → components/soc/esp32/register/soc/uhci_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_

27
tools/ci/check_copyright_ignore.txt
View File

@ -517,41 +517,14 @@ components/soc/esp32/include/soc/bb_reg.h
components/soc/esp32/include/soc/boot_mode.h
components/soc/esp32/include/soc/fe_reg.h
components/soc/esp32/include/soc/flash_encryption_reg.h
components/soc/esp32/include/soc/gpio_reg.h
components/soc/esp32/include/soc/gpio_sig_map.h
components/soc/esp32/include/soc/gpio_struct.h
components/soc/esp32/include/soc/hinf_reg.h
components/soc/esp32/include/soc/hinf_struct.h
components/soc/esp32/include/soc/host_reg.h
components/soc/esp32/include/soc/host_struct.h
components/soc/esp32/include/soc/hwcrypto_reg.h
components/soc/esp32/include/soc/i2c_reg.h
components/soc/esp32/include/soc/i2c_struct.h
components/soc/esp32/include/soc/ledc_reg.h
components/soc/esp32/include/soc/ledc_struct.h
components/soc/esp32/include/soc/nrx_reg.h
components/soc/esp32/include/soc/pid.h
components/soc/esp32/include/soc/reset_reasons.h
components/soc/esp32/include/soc/rtc_cntl_struct.h
components/soc/esp32/include/soc/rtc_i2c_reg.h
components/soc/esp32/include/soc/rtc_io_reg.h
components/soc/esp32/include/soc/rtc_io_struct.h
components/soc/esp32/include/soc/sdmmc_pins.h
components/soc/esp32/include/soc/sdmmc_reg.h
components/soc/esp32/include/soc/sens_reg.h
components/soc/esp32/include/soc/sens_struct.h
components/soc/esp32/include/soc/slc_reg.h
components/soc/esp32/include/soc/slc_struct.h
components/soc/esp32/include/soc/soc_pins.h
components/soc/esp32/include/soc/soc_ulp.h
components/soc/esp32/include/soc/syscon_reg.h
components/soc/esp32/include/soc/syscon_struct.h
components/soc/esp32/include/soc/touch_sensor_channel.h
components/soc/esp32/include/soc/uart_pins.h
components/soc/esp32/include/soc/uart_reg.h
components/soc/esp32/include/soc/uart_struct.h
components/soc/esp32/include/soc/uhci_reg.h
components/soc/esp32/include/soc/uhci_struct.h
components/soc/esp32/include/soc/wdev_reg.h
components/soc/esp32/ledc_periph.c
components/soc/esp32c3/include/soc/apb_saradc_reg.h

2
tools/ci/check_public_headers.py
View File

@ -97,7 +97,7 @@ class PublicHeaderChecker:
self.kconfig_macro = re.compile(r'\bCONFIG_[A-Z0-9_]+')
self.static_assert = re.compile(r'(_Static_assert|static_assert)')
self.defines_assert = re.compile(r'#define[ \t]+ESP_STATIC_ASSERT')
self.auto_soc_header = re.compile(r'components/soc/esp[a-z0-9_]+(?:/\w+)?/include/(soc|modem)/[a-zA-Z0-9_]+.h')
self.auto_soc_header = re.compile(r'components/soc/esp[a-z0-9_]+(?:/\w+)?/(include|register)/(soc|modem)/[a-zA-Z0-9_]+.h')
self.assembly_nocode = r'^\s*(\.file|\.text|\.ident|\.option|\.attribute|(\.section)?).*$'
self.check_threads: List[Thread] = []
self.stdc = '--std=c99'