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freertos: Fix FPU ISR core pinning bug
This commit fixes a bug where if an unpinned task is interrupted by a level 1
ISR that users the FPU, the FPU usage will cause the interrupted task to
become pinned to the current core.
Note: This bug was already fixed in SMP FreeRTOS in commit
d69361779e
. This commit simply backports the
fix to IDF FreeRTOS.
This commit is contained in:
parent
96058c25ab
commit
9f7f964363
@ -908,35 +908,32 @@ _xt_coproc_exc:
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/* Get co-processor state save area of new owner thread. */
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call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */
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#ifndef CONFIG_FREERTOS_FPU_IN_ISR
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beqz a15, .L_goto_invalid
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#if CONFIG_FREERTOS_FPU_IN_ISR
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beqz a15, .L_skip_core_pin /* CP used in ISR, skip task pinning */
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#else
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beqz a15, .L_goto_invalid /* not in a thread (invalid) */
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#endif
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/*When FPU in ISR is enabled we could deal with zeroed a15 */
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#if configNUM_CORES > 1
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/* CP operations are incompatible with unpinned tasks. Thus we pin the task
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to the current running core. */
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movi a2, pxCurrentTCB
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getcoreid a3 /* a3 = current core ID */
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addx4 a2, a3, a2
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l32i a2, a2, 0 /* a2 = start of pxCurrentTCB[cpuid] */
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addi a2, a2, TASKTCB_XCOREID_OFFSET /* a2 = &TCB.xCoreID */
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s32i a3, a2, 0 /* TCB.xCoreID = current core ID */
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#endif // configNUM_CORES > 1
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#if CONFIG_FREERTOS_FPU_IN_ISR
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.L_skip_core_pin:
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#endif
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/* Enable the co-processor's bit in CPENABLE. */
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movi a0, _xt_coproc_mask
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rsr a4, CPENABLE /* a4 = CPENABLE */
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addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
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l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
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/* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
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here, to keep the entire thing from crashing, it's better to pin the task to whatever
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core we're running on now. */
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movi a2, pxCurrentTCB
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getcoreid a3
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addx4 a2, a3, a2
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l32i a2, a2, 0 /* a2 = start of pxCurrentTCB[cpuid] */
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addi a2, a2, TASKTCB_XCOREID_OFFSET /* offset to xCoreID in tcb struct */
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s32i a3, a2, 0 /* store current cpuid */
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/* Grab correct xt_coproc_owner_sa for this core */
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movi a2, XCHAL_CP_MAX << 2
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mull a2, a2, a3 /* multiply by current processor id */
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movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
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add a3, a3, a2 /* a3 = owner area needed for this processor */
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extui a2, a0, 0, 16 /* coprocessor bitmask portion */
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or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
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wsr a4, CPENABLE
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@ -946,7 +943,11 @@ Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
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everywhere): _xt_coproc_release assumes it works like this in order not to need
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locking.
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*/
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/* Grab correct xt_coproc_owner_sa for this core */
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movi a2, XCHAL_CP_MAX << 2
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mull a2, a2, a3 /* multiply by current processor id */
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movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
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add a3, a3, a2 /* a3 = owner area needed for this processor */
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/* Get old coprocessor owner thread (save area ptr) and assign new one. */
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addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */
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