From 9ecd2fd7e3a7d1cd534941edfd628a81f3af6c95 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Tue, 16 Jan 2024 13:22:57 +0530 Subject: [PATCH] fix(soc): change debug addr range to CPU subsystem range For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same address range is part of CPU Subsystem range which contains debug mode specific code and interrupt config registers (CLINT, PLIC etc.). For now the PMP entry is provided with RWX permission for both machine and user mode but we can save this entry and allow the access to only machine mode for this range. For P4/C5 case, this PMP entry can have RW permission as the debug mode specific code is not present in this memory range. --- .../riscv/include/esp_gdbstub_memory_regions.h | 11 ++++++++--- .../port/esp32c6/cpu_region_protect.c | 14 +++++++------- .../port/esp32h2/cpu_region_protect.c | 14 +++++++------- components/soc/esp32c5/include/soc/soc.h | 8 ++++---- components/soc/esp32c6/include/soc/soc.h | 8 ++++---- components/soc/esp32h2/include/soc/soc.h | 8 ++++---- components/soc/esp32p4/include/soc/soc.h | 8 ++++---- 7 files changed, 38 insertions(+), 33 deletions(-) diff --git a/components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_memory_regions.h b/components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_memory_regions.h index 825a3cf384..67ff54e70a 100644 --- a/components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_memory_regions.h +++ b/components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_memory_regions.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,8 +26,13 @@ static inline bool __is_valid_memory_region(intptr_t addr) (addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH) || /* RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them */ #endif - (addr >= SOC_PERIPHERAL_LOW && addr < SOC_PERIPHERAL_HIGH) || - (addr >= SOC_DEBUG_LOW && addr < SOC_DEBUG_HIGH); +#if defined(SOC_DEBUG_LOW) && defined(SOC_DEBUG_HIGH) + (addr >= SOC_DEBUG_LOW && addr < SOC_DEBUG_HIGH) || +#endif +#if defined(SOC_CPU_SUBSYSTEM_LOW) && defined(SOC_CPU_SUBSYSTEM_HIGH) + (addr >= SOC_CPU_SUBSYSTEM_LOW && addr < SOC_CPU_SUBSYSTEM_HIGH) || +#endif + (addr >= SOC_PERIPHERAL_LOW && addr < SOC_PERIPHERAL_HIGH); } static inline bool is_valid_memory_region(intptr_t addr) diff --git a/components/esp_hw_support/port/esp32c6/cpu_region_protect.c b/components/esp_hw_support/port/esp32c6/cpu_region_protect.c index 68ee9f5f29..9dcadc4173 100644 --- a/components/esp_hw_support/port/esp32c6/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c6/cpu_region_protect.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,10 +32,10 @@ static void esp_cpu_configure_invalid_regions(void) __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; // 1. Gap at bottom of address space - PMA_ENTRY_SET_TOR(0, SOC_DEBUG_LOW, PMA_TOR | PMA_NONE); + PMA_ENTRY_SET_TOR(0, SOC_CPU_SUBSYSTEM_LOW, PMA_TOR | PMA_NONE); - // 2. Gap between debug region & IROM - PMA_ENTRY_SET_TOR(1, SOC_DEBUG_HIGH, PMA_NONE); + // 2. Gap between CPU subsystem region & IROM + PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); // 3. Gap between ROM & RAM @@ -111,10 +111,10 @@ void esp_cpu_configure_region_protection(void) // Configure all the valid address regions using PMP // - // 1. Debug region - const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_DEBUG_LOW, SOC_DEBUG_HIGH); + // 1. CPU Subsystem region - contains debug mode code and interrupt config registers + const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH); PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX); - _Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region"); + _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region"); // 2.1 I-ROM PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE); diff --git a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c index cfe2d66837..3eb7d03aad 100644 --- a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,10 +32,10 @@ static void esp_cpu_configure_invalid_regions(void) __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; // 1. Gap at bottom of address space - PMA_ENTRY_SET_TOR(0, SOC_DEBUG_LOW, PMA_TOR | PMA_NONE); + PMA_ENTRY_SET_TOR(0, SOC_CPU_SUBSYSTEM_LOW, PMA_TOR | PMA_NONE); - // 2. Gap between debug region & IROM - PMA_ENTRY_SET_TOR(1, SOC_DEBUG_HIGH, PMA_NONE); + // 2. Gap between CPU subsystem region & IROM + PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); // 3. Gap between ROM & RAM @@ -111,10 +111,10 @@ void esp_cpu_configure_region_protection(void) // Configure all the valid address regions using PMP // - // 1. Debug region - const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_DEBUG_LOW, SOC_DEBUG_HIGH); + // 1. CPU Subsystem region - contains debug mode code and interrupt config registers + const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH); PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX); - _Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region"); + _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region"); // 2.1 I-ROM PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE); diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 3794c3ae52..eaf6062299 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -200,9 +200,9 @@ #define SOC_PERIPHERAL_LOW 0x60000000 #define SOC_PERIPHERAL_HIGH 0x60100000 -// Debug region, not used by software -#define SOC_DEBUG_LOW 0x20000000 -#define SOC_DEBUG_HIGH 0x28000000 +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x4087e610 diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index bdcf25740e..7986a5c2f1 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -201,9 +201,9 @@ #define SOC_PERIPHERAL_LOW 0x60000000 #define SOC_PERIPHERAL_HIGH 0x60100000 -// Debug region, not used by software -#define SOC_DEBUG_LOW 0x20000000 -#define SOC_DEBUG_HIGH 0x28000000 +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x4087e610 diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index a49cfad682..1191c37e61 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -199,9 +199,9 @@ #define SOC_PERIPHERAL_LOW 0x60000000 #define SOC_PERIPHERAL_HIGH 0x60100000 -// Debug region, not used by software -#define SOC_DEBUG_LOW 0x20000000 -#define SOC_DEBUG_HIGH 0x28000000 +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x4084f380 diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 0c8d249165..3f729140fe 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -216,9 +216,9 @@ #define SOC_LP_PERIPH_LOW 0x50110000 #define SOC_LP_PERIPH_HIGH 0x50130000 -// Debug region, not used by software -#define SOC_DEBUG_LOW 0x20000000 -#define SOC_DEBUG_HIGH 0x28000000 +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x4ff3cfc0