mirror of
https://github.com/espressif/esp-idf.git
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feat(esp_gdma): adapt the gdma driver to ahb-dma and axi-dma
This commit is contained in:
morris
parent
56a376c696
commit
9eb145aa21
505
components/hal/esp32p4/include/ahb_dma_ll.h
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505
components/hal/esp32p4/include/ahb_dma_ll.h
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/gdma_types.h"
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#include "hal/gdma_ll.h"
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#include "soc/ahb_dma_struct.h"
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#include "soc/ahb_dma_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
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// any "dummy" peripheral ID can be used for M2M mode
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#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFAC2)
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#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
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///////////////////////////////////// Common /////////////////////////////////////////
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/**
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* @brief Force enable register clock
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*/
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static inline void ahb_dma_ll_force_enable_reg_clock(ahb_dma_dev_t *dev, bool enable)
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{
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dev->misc_conf.clk_en = enable;
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}
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/**
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* @brief Disable priority arbitration
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*
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* @param dev DMA register base address
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* @param dis True to disable, false to enable
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*/
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static inline void ahb_dma_ll_disable_prio_arb(ahb_dma_dev_t *dev, bool dis)
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{
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dev->misc_conf.arb_pri_dis = dis;
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}
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/**
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* @brief Reset DMA FSM
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*
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* @param dev DMA register base address
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*/
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static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
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{
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dev->misc_conf.ahbm_rst_inter = 1;
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dev->misc_conf.ahbm_rst_inter = 0;
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}
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///////////////////////////////////// RX /////////////////////////////////////////
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/**
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* @brief Get DMA RX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->in_intr[channel].st.val;
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}
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/**
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* @brief Enable DMA RX channel interrupt
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*/
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static inline void ahb_dma_ll_rx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->in_intr[channel].ena.val |= mask;
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} else {
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dev->in_intr[channel].ena.val &= ~mask;
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}
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}
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/**
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* @brief Clear DMA RX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->in_intr[channel].clr.val = mask;
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}
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/**
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* @brief Get DMA RX channel interrupt status register address
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*/
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static inline volatile void *ahb_dma_ll_rx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->in_intr[channel].st);
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}
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/**
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* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void ahb_dma_ll_rx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf1.in_check_owner_chn = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading data, disabled by default
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*/
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static inline void ahb_dma_ll_rx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.in_data_burst_en_chn = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
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*/
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static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
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}
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/**
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* @brief Reset DMA RX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_conf0.in_rst_chn = 1;
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dev->channel[channel].in.in_conf0.in_rst_chn = 0;
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}
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/**
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* @brief Check if DMA RX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool ahb_dma_ll_rx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA RX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool ahb_dma_ll_rx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes remained in the L1 RX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t ahb_dma_ll_rx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.infifo_cnt_chn;
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}
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/**
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* @brief Pop data from DMA RX FIFO
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*/
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static inline uint32_t ahb_dma_ll_rx_pop_data(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_pop.infifo_pop_chn = 1;
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return dev->channel[channel].in.in_pop.infifo_rdata_chn;
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}
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/**
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* @brief Set the descriptor link base address for RX channel
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->in_link_addr[channel].inlink_addr_chn = addr;
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}
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/**
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* @brief Start dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_start(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.inlink_start_chn = 1;
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}
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/**
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* @brief Stop dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_stop(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.inlink_stop_chn = 1;
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}
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/**
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* @brief Restart a new inlink right after the last descriptor
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_restart(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.inlink_restart_chn = 1;
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}
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/**
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* @brief Enable DMA RX to return the address of current descriptor when receives error
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*/
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static inline void ahb_dma_ll_rx_enable_auto_return(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_link.inlink_auto_ret_chn = enable;
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}
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/**
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* @brief Check if DMA RX FSM is in IDLE state
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*/
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static inline bool ahb_dma_ll_rx_is_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_link.inlink_park_chn;
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}
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/**
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* @brief Get RX success EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_success_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_suc_eof_des_addr.val;
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}
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/**
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* @brief Get RX error EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_error_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_err_eof_des_addr.val;
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}
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/**
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* @brief Get the pre-fetched RX descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_dscr.val;
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}
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/**
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* @brief Set priority for DMA RX channel
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*/
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static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio)
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{
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dev->channel[channel].in.in_pri.rx_pri_chn = prio;
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}
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/**
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* @brief Connect DMA RX channel to a given peripheral
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*/
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static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
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{
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dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
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dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
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}
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/**
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* @brief Disconnect DMA RX channel from peripheral
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*/
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static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
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dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
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}
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/**
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* @brief Whether to enable the ETM subsystem for RX channel
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*
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* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
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*/
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static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.in_etm_en_chn = enable;
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}
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///////////////////////////////////// TX /////////////////////////////////////////
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/**
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* @brief Get DMA TX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->out_intr[channel].st.val;
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}
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/**
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* @brief Enable DMA TX channel interrupt
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*/
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static inline void ahb_dma_ll_tx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->out_intr[channel].ena.val |= mask;
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} else {
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dev->out_intr[channel].ena.val &= ~mask;
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}
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}
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/**
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* @brief Clear DMA TX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->out_intr[channel].clr.val = mask;
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}
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/**
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* @brief Get DMA TX channel interrupt status register address
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*/
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static inline volatile void *ahb_dma_ll_tx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->out_intr[channel].st);
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}
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/**
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* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void ahb_dma_ll_tx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf1.out_check_owner_chn = enable;
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}
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/**
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* @brief Enable DMA TX channel burst sending data, disabled by default
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*/
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static inline void ahb_dma_ll_tx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_data_burst_en_chn = enable;
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}
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/**
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* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
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*/
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static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
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}
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/**
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* @brief Set TX channel EOF mode
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*/
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static inline void ahb_dma_ll_tx_set_eof_mode(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mode)
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{
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dev->channel[channel].out.out_conf0.out_eof_mode_chn = mode;
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}
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/**
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* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
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*/
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static inline void ahb_dma_ll_tx_enable_auto_write_back(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable;
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}
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/**
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* @brief Reset DMA TX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_conf0.out_rst_chn = 1;
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dev->channel[channel].out.out_conf0.out_rst_chn = 0;
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}
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/**
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* @brief Check if DMA TX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool ahb_dma_ll_tx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA TX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool ahb_dma_ll_tx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes in TX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t ahb_dma_ll_tx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.outfifo_cnt_chn;
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}
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/**
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* @brief Push data into DMA TX FIFO
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*/
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static inline void ahb_dma_ll_tx_push_data(ahb_dma_dev_t *dev, uint32_t channel, uint32_t data)
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{
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dev->channel[channel].out.out_push.outfifo_wdata_chn = data;
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dev->channel[channel].out.out_push.outfifo_push_chn = 1;
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}
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/**
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* @brief Set the descriptor link base address for TX channel
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->out_link_addr[channel].outlink_addr_chn = addr;
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}
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/**
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* @brief Start dealing with TX descriptors
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_start(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_link.outlink_start_chn = 1;
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}
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/**
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* @brief Stop dealing with TX descriptors
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_stop(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_link.outlink_stop_chn = 1;
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}
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/**
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* @brief Restart a new outlink right after the last descriptor
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_restart(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_link.outlink_restart_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX FSM is in IDLE state
|
||||
*/
|
||||
static inline bool ahb_dma_ll_tx_is_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->channel[channel].out.out_link.outlink_park_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TX EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t ahb_dma_ll_tx_get_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->channel[channel].out.out_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the pre-fetched TX descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t ahb_dma_ll_tx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->channel[channel].out.out_dscr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->channel[channel].out.out_pri.tx_pri_chn = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA TX channel to a given peripheral
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
|
||||
{
|
||||
(void)periph;
|
||||
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disconnect DMA TX channel from peripheral
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the ETM subsystem for TX channel
|
||||
*
|
||||
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
453
components/hal/esp32p4/include/axi_dma_ll.h
Normal file
453
components/hal/esp32p4/include/axi_dma_ll.h
Normal file
@ -0,0 +1,453 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/gdma_types.h"
|
||||
#include "hal/gdma_ll.h"
|
||||
#include "soc/axi_dma_struct.h"
|
||||
#include "soc/axi_dma_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AXI_DMA_LL_GET_HW(id) (((id) == 0) ? (&AXI_DMA) : NULL)
|
||||
|
||||
// any "dummy" peripheral ID can be used for M2M mode
|
||||
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
|
||||
#define AXI_DMA_LL_INVALID_PERIPH_ID (0x3F)
|
||||
|
||||
///////////////////////////////////// Common /////////////////////////////////////////
|
||||
/**
|
||||
* @brief Force enable register clock
|
||||
*/
|
||||
static inline void axi_dma_ll_force_enable_reg_clock(axi_dma_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->misc_conf.clk_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable priority arbitration
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
* @param dis True to disable, false to enable
|
||||
*/
|
||||
static inline void axi_dma_ll_disable_prio_arb(axi_dma_dev_t *dev, bool dis)
|
||||
{
|
||||
dev->misc_conf.arb_pri_dis = dis;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA FSM (Read and Write)
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
*/
|
||||
static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
|
||||
{
|
||||
dev->misc_conf.axim_rst_rd_inter = 1;
|
||||
dev->misc_conf.axim_rst_rd_inter = 0;
|
||||
dev->misc_conf.axim_rst_wr_inter = 1;
|
||||
dev->misc_conf.axim_rst_wr_inter = 0;
|
||||
}
|
||||
|
||||
///////////////////////////////////// RX /////////////////////////////////////////
|
||||
/**
|
||||
* @brief Get DMA RX channel interrupt status word
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].intr.st.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel interrupt
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_interrupt(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->in[channel].intr.ena.val |= mask;
|
||||
} else {
|
||||
dev->in[channel].intr.ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DMA RX channel interrupt
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_clear_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask)
|
||||
{
|
||||
dev->in[channel].intr.clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DMA RX channel interrupt status register address
|
||||
*/
|
||||
static inline volatile void *axi_dma_ll_rx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return (volatile void *)(&dev->in[channel].intr.st);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf1.in_check_owner_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel burst reading data, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
// TODO: IDF-6504
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_descriptor_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.indscr_burst_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA RX channel FSM and FIFO pointer
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.in_rst_chn = 1;
|
||||
dev->in[channel].conf.in_conf0.in_rst_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Pop data from DMA RX FIFO
|
||||
*/
|
||||
static inline uint32_t axi_dma_ll_rx_pop_data(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_pop.infifo_pop_chn = 1;
|
||||
return dev->in[channel].conf.in_pop.infifo_rdata_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the descriptor link base address for RX channel
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_set_desc_addr(axi_dma_dev_t *dev, uint32_t channel, uint32_t addr)
|
||||
{
|
||||
dev->in[channel].conf.in_link2.inlink_addr_chn = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start dealing with RX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_start(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_start_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop dealing with RX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_stop(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_stop_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restart a new inlink right after the last descriptor
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_restart(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_restart_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX to return the address of current descriptor when receives error
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_auto_return(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_auto_ret_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA RX FSM is in IDLE state
|
||||
*/
|
||||
static inline bool axi_dma_ll_rx_is_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_link1.inlink_park_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RX success EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_success_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_suc_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RX error EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_error_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_err_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the pre-fetched RX descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_prefetched_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_dscr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_set_priority(axi_dma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->in[channel].conf.in_pri.rx_pri_chn = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA RX channel to a given peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
|
||||
{
|
||||
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = periph_id;
|
||||
dev->in[channel].conf.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disconnect DMA RX channel from peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
|
||||
dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the ETM subsystem for RX channel
|
||||
*
|
||||
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.in_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
///////////////////////////////////// TX /////////////////////////////////////////
|
||||
/**
|
||||
* @brief Get DMA TX channel interrupt status word
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].intr.st.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel interrupt
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_interrupt(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->out[channel].intr.ena.val |= mask;
|
||||
} else {
|
||||
dev->out[channel].intr.ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DMA TX channel interrupt
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_clear_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask)
|
||||
{
|
||||
dev->out[channel].intr.clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DMA TX channel interrupt status register address
|
||||
*/
|
||||
static inline volatile void *axi_dma_ll_tx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return (volatile void *)(&dev->out[channel].intr.st);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf1.out_check_owner_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel burst sending data, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
// TODO: IDF-6504
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_descriptor_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.outdscr_burst_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set TX channel EOF mode
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_set_eof_mode(axi_dma_dev_t *dev, uint32_t channel, uint32_t mode)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_eof_mode_chn = mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_auto_write_back(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_auto_wrback_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA TX channel FSM and FIFO pointer
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_rst_chn = 1;
|
||||
dev->out[channel].conf.out_conf0.out_rst_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Push data into DMA TX FIFO
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_push_data(axi_dma_dev_t *dev, uint32_t channel, uint32_t data)
|
||||
{
|
||||
dev->out[channel].conf.out_push.outfifo_wdata_chn = data;
|
||||
dev->out[channel].conf.out_push.outfifo_push_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the descriptor link base address for TX channel
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_set_desc_addr(axi_dma_dev_t *dev, uint32_t channel, uint32_t addr)
|
||||
{
|
||||
dev->out[channel].conf.out_link2.outlink_addr_chn = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start dealing with TX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_start(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_link1.outlink_start_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop dealing with TX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_stop(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_link1.outlink_stop_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restart a new outlink right after the last descriptor
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_restart(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_link1.outlink_restart_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX FSM is in IDLE state
|
||||
*/
|
||||
static inline bool axi_dma_ll_tx_is_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].conf.out_link1.outlink_park_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TX EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_tx_get_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].conf.out_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the pre-fetched TX descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_tx_get_prefetched_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].conf.out_dscr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_set_priority(axi_dma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->out[channel].conf.out_pri.tx_pri_chn = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA TX channel to a given peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
|
||||
{
|
||||
(void)periph;
|
||||
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = periph_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disconnect DMA TX channel from peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the ETM subsystem for TX channel
|
||||
*
|
||||
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
43
components/hal/esp32p4/include/gdma_ll.h
Normal file
43
components/hal/esp32p4/include/gdma_ll.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief The contents defined in this file are common for both AXI-DMA and AHB-DMA
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
|
||||
|
||||
#define GDMA_LL_RX_EVENT_MASK (0x1F)
|
||||
#define GDMA_LL_TX_EVENT_MASK (0x0F)
|
||||
|
||||
#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
|
||||
#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
|
||||
#define GDMA_LL_EVENT_TX_EOF (1<<1)
|
||||
#define GDMA_LL_EVENT_TX_DONE (1<<0)
|
||||
|
||||
#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
|
||||
#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
|
||||
#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
|
||||
#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
|
||||
#define GDMA_LL_EVENT_RX_DONE (1<<0)
|
||||
|
||||
#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0
|
||||
#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups
|
||||
#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group
|
||||
|
||||
#define GDMA_LL_AXI_GROUP_START_ID 1 // AXI GDMA group ID starts from 1
|
||||
#define GDMA_LL_AXI_NUM_GROUPS 1 // Number of AXI GDMA groups
|
||||
#define GDMA_LL_AXI_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AXI group
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
167
components/hal/gdma_hal_ahb_v2.c
Normal file
167
components/hal/gdma_hal_ahb_v2.c
Normal file
@ -0,0 +1,167 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/gdma_hal_ahb.h"
|
||||
#include "hal/ahb_dma_ll.h"
|
||||
|
||||
static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
|
||||
.m2m_free_periph_mask = AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
|
||||
};
|
||||
|
||||
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_set_desc_addr(hal->ahb_dma_dev, chan_id, desc_base_addr);
|
||||
ahb_dma_ll_rx_start(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_set_desc_addr(hal->ahb_dma_dev, chan_id, desc_base_addr);
|
||||
ahb_dma_ll_tx_start(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_stop(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_stop(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_restart(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_restart(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_set_priority(hal->ahb_dma_dev, chan_id, priority);
|
||||
} else {
|
||||
ahb_dma_ll_tx_set_priority(hal->ahb_dma_dev, chan_id, priority);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
|
||||
ahb_dma_ll_rx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
|
||||
ahb_dma_ll_tx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_enable_data_burst(hal->ahb_dma_dev, chan_id, en_data_burst);
|
||||
ahb_dma_ll_rx_enable_descriptor_burst(hal->ahb_dma_dev, chan_id, en_desc_burst);
|
||||
} else {
|
||||
ahb_dma_ll_tx_enable_data_burst(hal->ahb_dma_dev, chan_id, en_data_burst);
|
||||
ahb_dma_ll_tx_enable_descriptor_burst(hal->ahb_dma_dev, chan_id, en_desc_burst);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
|
||||
} else {
|
||||
ahb_dma_ll_tx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
|
||||
ahb_dma_ll_tx_enable_auto_write_back(hal->ahb_dma_dev, chan_id, en_desc_write_back);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_enable_interrupt(hal->ahb_dma_dev, chan_id, intr_event_mask, en_or_dis);
|
||||
} else {
|
||||
ahb_dma_ll_tx_enable_interrupt(hal->ahb_dma_dev, chan_id, intr_event_mask, en_or_dis);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_clear_interrupt_status(hal->ahb_dma_dev, chan_id, intr_event_mask);
|
||||
} else {
|
||||
ahb_dma_ll_tx_clear_interrupt_status(hal->ahb_dma_dev, chan_id, intr_event_mask);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_ahb_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return (uint32_t)ahb_dma_ll_rx_get_interrupt_status_reg(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
return (uint32_t)ahb_dma_ll_tx_get_interrupt_status_reg(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_ahb_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return ahb_dma_ll_rx_get_success_eof_desc_addr(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
return ahb_dma_ll_tx_get_eof_desc_addr(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
|
||||
{
|
||||
hal->ahb_dma_dev = AHB_DMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID);
|
||||
hal->start_with_desc = gdma_ahb_hal_start_with_desc;
|
||||
hal->stop = gdma_ahb_hal_stop;
|
||||
hal->append = gdma_ahb_hal_append;
|
||||
hal->reset = gdma_ahb_hal_reset;
|
||||
hal->set_priority = gdma_ahb_hal_set_priority;
|
||||
hal->connect_peri = gdma_ahb_hal_connect_peri;
|
||||
hal->disconnect_peri = gdma_ahb_hal_disconnect_peri;
|
||||
hal->enable_burst = gdma_ahb_hal_enable_burst;
|
||||
hal->set_strategy = gdma_ahb_hal_set_strategy;
|
||||
hal->enable_intr = gdma_ahb_hal_enable_intr;
|
||||
hal->clear_intr = gdma_ahb_hal_clear_intr;
|
||||
hal->read_intr_status = gdma_ahb_hal_read_intr_status;
|
||||
hal->get_intr_status_reg = gdma_ahb_hal_get_intr_status_reg;
|
||||
hal->get_eof_desc_addr = gdma_ahb_hal_get_eof_desc_addr;
|
||||
hal->priv_data = &gdma_ahb_hal_priv_data;
|
||||
}
|
||||
167
components/hal/gdma_hal_axi.c
Normal file
167
components/hal/gdma_hal_axi.c
Normal file
@ -0,0 +1,167 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/gdma_hal_axi.h"
|
||||
#include "hal/axi_dma_ll.h"
|
||||
|
||||
static gdma_hal_priv_data_t gdma_axi_hal_priv_data = {
|
||||
.m2m_free_periph_mask = AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
|
||||
};
|
||||
|
||||
void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_set_desc_addr(hal->axi_dma_dev, chan_id, desc_base_addr);
|
||||
axi_dma_ll_rx_start(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_set_desc_addr(hal->axi_dma_dev, chan_id, desc_base_addr);
|
||||
axi_dma_ll_tx_start(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_stop(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_stop(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_restart(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_restart(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_reset_channel(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_reset_channel(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_set_priority(hal->axi_dma_dev, chan_id, priority);
|
||||
} else {
|
||||
axi_dma_ll_tx_set_priority(hal->axi_dma_dev, chan_id, priority);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_reset_channel(hal->axi_dma_dev, chan_id); // reset channel
|
||||
axi_dma_ll_rx_connect_to_periph(hal->axi_dma_dev, chan_id, periph, periph_sub_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_reset_channel(hal->axi_dma_dev, chan_id); // reset channel
|
||||
axi_dma_ll_tx_connect_to_periph(hal->axi_dma_dev, chan_id, periph, periph_sub_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_disconnect_from_periph(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_disconnect_from_periph(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_enable_data_burst(hal->axi_dma_dev, chan_id, en_data_burst);
|
||||
axi_dma_ll_rx_enable_descriptor_burst(hal->axi_dma_dev, chan_id, en_desc_burst);
|
||||
} else {
|
||||
axi_dma_ll_tx_enable_data_burst(hal->axi_dma_dev, chan_id, en_data_burst);
|
||||
axi_dma_ll_tx_enable_descriptor_burst(hal->axi_dma_dev, chan_id, en_desc_burst);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_enable_owner_check(hal->axi_dma_dev, chan_id, en_owner_check);
|
||||
} else {
|
||||
axi_dma_ll_tx_enable_owner_check(hal->axi_dma_dev, chan_id, en_owner_check);
|
||||
axi_dma_ll_tx_enable_auto_write_back(hal->axi_dma_dev, chan_id, en_desc_write_back);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_enable_interrupt(hal->axi_dma_dev, chan_id, intr_event_mask, en_or_dis);
|
||||
} else {
|
||||
axi_dma_ll_tx_enable_interrupt(hal->axi_dma_dev, chan_id, intr_event_mask, en_or_dis);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_clear_interrupt_status(hal->axi_dma_dev, chan_id, intr_event_mask);
|
||||
} else {
|
||||
axi_dma_ll_tx_clear_interrupt_status(hal->axi_dma_dev, chan_id, intr_event_mask);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return axi_dma_ll_rx_get_interrupt_status(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
return axi_dma_ll_tx_get_interrupt_status(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return (uint32_t)axi_dma_ll_rx_get_interrupt_status_reg(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
return (uint32_t)axi_dma_ll_tx_get_interrupt_status_reg(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return axi_dma_ll_rx_get_success_eof_desc_addr(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
return axi_dma_ll_tx_get_eof_desc_addr(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
|
||||
{
|
||||
hal->axi_dma_dev = AXI_DMA_LL_GET_HW(config->group_id - GDMA_LL_AXI_GROUP_START_ID);
|
||||
hal->start_with_desc = gdma_axi_hal_start_with_desc;
|
||||
hal->stop = gdma_axi_hal_stop;
|
||||
hal->append = gdma_axi_hal_append;
|
||||
hal->reset = gdma_axi_hal_reset;
|
||||
hal->set_priority = gdma_axi_hal_set_priority;
|
||||
hal->connect_peri = gdma_axi_hal_connect_peri;
|
||||
hal->disconnect_peri = gdma_axi_hal_disconnect_peri;
|
||||
hal->enable_burst = gdma_axi_hal_enable_burst;
|
||||
hal->set_strategy = gdma_axi_hal_set_strategy;
|
||||
hal->enable_intr = gdma_axi_hal_enable_intr;
|
||||
hal->clear_intr = gdma_axi_hal_clear_intr;
|
||||
hal->read_intr_status = gdma_axi_hal_read_intr_status;
|
||||
hal->get_intr_status_reg = gdma_axi_hal_get_intr_status_reg;
|
||||
hal->get_eof_desc_addr = gdma_axi_hal_get_eof_desc_addr;
|
||||
hal->priv_data = &gdma_axi_hal_priv_data;
|
||||
}
|
||||
49
components/hal/include/hal/gdma_hal_axi.h
Normal file
49
components/hal/include/hal/gdma_hal_axi.h
Normal file
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/gdma_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr);
|
||||
|
||||
void gdma_axi_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
void gdma_axi_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
void gdma_axi_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
|
||||
|
||||
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id);
|
||||
|
||||
void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
|
||||
|
||||
void gdma_axi_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align);
|
||||
|
||||
void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back);
|
||||
|
||||
void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis);
|
||||
|
||||
void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask);
|
||||
|
||||
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -27,6 +27,7 @@ typedef enum {
|
||||
GDMA_TRIG_PERIPH_CAM, /*!< GDMA trigger peripheral: CAM */
|
||||
GDMA_TRIG_PERIPH_RMT, /*!< GDMA trigger peripheral: RMT */
|
||||
GDMA_TRIG_PERIPH_PARLIO, /*!< GDMA trigger peripheral: PARLIO */
|
||||
GDMA_TRIG_PERIPH_I3C, /*!< GDMA trigger peripheral: I3C */
|
||||
} gdma_trigger_peripheral_t;
|
||||
|
||||
/**
|
||||
|
||||
@ -195,17 +195,21 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US
|
||||
int
|
||||
default 1100
|
||||
|
||||
config SOC_GDMA_GROUPS
|
||||
config SOC_AHB_GDMA_VERSION
|
||||
int
|
||||
default 1
|
||||
default 2
|
||||
|
||||
config SOC_GDMA_PAIRS_PER_GROUP
|
||||
config SOC_GDMA_NUM_GROUPS_MAX
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_GDMA_PAIRS_PER_GROUP_MAX
|
||||
int
|
||||
default 3
|
||||
|
||||
config SOC_GDMA_SUPPORT_ETM
|
||||
bool
|
||||
default n
|
||||
default y
|
||||
|
||||
config SOC_ETM_GROUPS
|
||||
int
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -5,3 +5,41 @@
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0 -1
|
||||
#define SOC_GDMA_TRIG_PERIPH_I3C0 0
|
||||
#define SOC_GDMA_TRIG_PERIPH_UHCI0 2
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0 3
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S1 4
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S2 5
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0 8
|
||||
#define SOC_GDMA_TRIG_PERIPH_RMT0 10
|
||||
#define SOC_GDMA_TRIG_PERIPH_LCD0 0
|
||||
#define SOC_GDMA_TRIG_PERIPH_CAM0 0
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2 1
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI3 2
|
||||
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 3
|
||||
#define SOC_GDMA_TRIG_PERIPH_AES0 4
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0 5
|
||||
|
||||
// On which system bus is the DMA instance of the peripheral connection mounted
|
||||
#define SOC_GDMA_BUS_ANY -1
|
||||
#define SOC_GDMA_BUS_AHB 0
|
||||
#define SOC_GDMA_BUS_AXI 1
|
||||
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
|
||||
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S1_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S2_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_RMT0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_I3C0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AXI
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI3_BUS SOC_GDMA_BUS_AXI
|
||||
#define SOC_GDMA_TRIG_PERIPH_LCD0_BUS SOC_GDMA_BUS_AXI
|
||||
#define SOC_GDMA_TRIG_PERIPH_CAM0_BUS SOC_GDMA_BUS_AXI
|
||||
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AXI
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AXI
|
||||
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AXI
|
||||
|
||||
@ -30,6 +30,8 @@
|
||||
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: IDF-7552
|
||||
#define SOC_UART_SUPPORTED 1
|
||||
// #define SOC_GDMA_SUPPORTED 1 //TODO: IDF-6504
|
||||
// #define SOC_AHB_GDMA_SUPPORTED 1
|
||||
// #define SOC_AXI_GDMA_SUPPORTED 1
|
||||
// #define SOC_GPTIMER_SUPPORTED 1 //TODO: IDF-6515
|
||||
// #define SOC_PCNT_SUPPORTED 1 //TODO: IDF-7475
|
||||
// #define SOC_MCPWM_SUPPORTED 1 //TODO: IDF-7493
|
||||
@ -154,9 +156,10 @@
|
||||
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
|
||||
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
|
||||
#define SOC_GDMA_SUPPORT_ETM (0) // Support ETM submodule
|
||||
#define SOC_AHB_GDMA_VERSION 2
|
||||
#define SOC_GDMA_NUM_GROUPS_MAX 2
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
#define SOC_GDMA_SUPPORT_ETM 1 // Both AHB-DMA and AXI-DMA supports ETM
|
||||
|
||||
/*-------------------------- ETM CAPS --------------------------------------*/
|
||||
#define SOC_ETM_GROUPS 1U // Number of ETM groups
|
||||
@ -421,7 +424,6 @@
|
||||
|
||||
/*-------------------------- MEMPROT CAPS ------------------------------------*/
|
||||
|
||||
|
||||
/*-------------------------- UART CAPS ---------------------------------------*/
|
||||
// ESP32-P4 has 2 UARTs
|
||||
#define SOC_UART_NUM (2)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user