From 9c4a12b11ec7d79142900b07b36cc31609ba957e Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Thu, 26 May 2022 11:38:21 +0800 Subject: [PATCH] Revert "ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V" This reverts commit f709faea7c7be7d4abaa7f9204c8e3ba26959193. --- components/ulp/ulp_riscv/ulp_riscv.c | 14 +++++++------- components/ulp/ulp_riscv/ulp_riscv_utils.c | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/components/ulp/ulp_riscv/ulp_riscv.c b/components/ulp/ulp_riscv/ulp_riscv.c index 588d13bef5..3992ea510b 100644 --- a/components/ulp/ulp_riscv/ulp_riscv.c +++ b/components/ulp/ulp_riscv/ulp_riscv.c @@ -55,10 +55,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) #endif //CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_IDF_TARGET_ESP32S2 - /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */ + /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); + esp_rom_delay_us(20); + CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - /* The coprocessor cpu trap signal doesnt have a stable reset value, + /* The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); @@ -75,14 +77,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source); #elif CONFIG_IDF_TARGET_ESP32S3 - /* The coprocessor cpu trap signal doesnt have a stable reset value, - force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ + /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); + SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); esp_rom_delay_us(20); CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); - - /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */ - SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); /* Disable ULP timer */ CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); diff --git a/components/ulp/ulp_riscv/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_riscv_utils.c index c14d08aeac..75e48982c0 100644 --- a/components/ulp/ulp_riscv/ulp_riscv_utils.c +++ b/components/ulp/ulp_riscv/ulp_riscv_utils.c @@ -13,7 +13,7 @@ void ulp_riscv_rescue_from_monitor(void) { /* Rescue RISCV from monitor state. */ - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE); + CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN); } void ulp_riscv_wakeup_main_processor(void)