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feat(hal): add hal utils for clock divider calculation
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@ -9,6 +9,7 @@ endif()
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set(srcs "mpu_hal.c"
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"efuse_hal.c"
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"hal_utils.c"
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"${target}/efuse_hal.c")
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118
components/hal/hal_utils.c
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118
components/hal/hal_utils.c
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/hal_utils.h"
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/**
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* @brief helper function, calculate the Greatest Common Divisor
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* @note gcd(a, b) = gcd(b, a % b)
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* @param a bigger value
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* @param b smaller value
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* @return result of gcd(a, b)
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*/
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__attribute__((always_inline))
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static inline uint32_t _gcd(uint32_t a, uint32_t b)
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{
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uint32_t c = a % b;
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while (c != 0) {
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a = b;
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b = c;
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c = a % b;
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}
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return b;
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}
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__attribute__((always_inline))
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static inline uint32_t _sub_abs(uint32_t a, uint32_t b)
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{
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return a > b ? a - b : b - a;
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}
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uint32_t hal_utils_calc_clk_div_fast(const hal_utils_clk_info_t *clk_info, hal_utils_clk_div_t *clk_div)
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{
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uint32_t div_denom = 1;
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uint32_t div_numer = 0;
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uint32_t div_integ = clk_info->src_freq_hz / clk_info->exp_freq_hz;
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uint32_t freq_error = clk_info->src_freq_hz % clk_info->exp_freq_hz;
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// If the expect frequency is too high or too low to satisfy the integral division range, failed and return 0
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if (div_integ < clk_info->min_integ || div_integ > clk_info->max_integ) {
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return 0;
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}
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// fractional divider
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if (freq_error) {
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// Calculate the Greatest Common Divisor, time complexity O(log n)
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uint32_t gcd = _gcd(clk_info->exp_freq_hz, freq_error);
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// divide by the Greatest Common Divisor to get the accurate fraction before normalization
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div_denom = clk_info->exp_freq_hz / gcd;
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div_numer = freq_error / gcd;
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// normalize div_denom and div_numer
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uint32_t d = div_denom / clk_info->max_fract + 1;
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// divide by the normalization coefficient to get the denominator and numerator within range of clk_info->max_fract
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div_denom /= d;
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div_numer /= d;
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}
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// Assign result
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clk_div->integ = div_integ;
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clk_div->denom = div_denom;
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clk_div->numer = div_numer;
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// Return the actual frequency
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if (div_numer) {
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uint32_t temp = div_integ * div_denom + div_numer;
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return (uint32_t)(((uint64_t)clk_info->src_freq_hz * div_denom + temp / 2) / temp);
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}
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return clk_info->src_freq_hz / div_integ;
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}
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uint32_t hal_utils_calc_clk_div_accurate(const hal_utils_clk_info_t *clk_info, hal_utils_clk_div_t *clk_div)
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{
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uint32_t div_denom = 1;
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uint32_t div_numer = 0;
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uint32_t div_integ = clk_info->src_freq_hz / clk_info->exp_freq_hz;
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uint32_t freq_error = clk_info->src_freq_hz % clk_info->exp_freq_hz;
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// If the expect frequency is too high to satisfy the minimum integral division, failed and return 0
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if (div_integ < clk_info->min_integ) {
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return 0;
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}
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if (freq_error) {
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// Carry bit if the decimal is greater than 1.0 - 1.0 / (PARLIO_LL_CLK_DIVIDER_MAX * 2)
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if (freq_error < clk_info->exp_freq_hz - clk_info->exp_freq_hz / (clk_info->max_fract * 2)) {
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// Search the closest fraction, time complexity O(n)
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for (uint32_t sub = 0, a = 2, b = 0, min = UINT32_MAX; min && a <= clk_info->max_fract; a++) {
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b = (a * freq_error + clk_info->exp_freq_hz / 2) / clk_info->exp_freq_hz;
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sub = _sub_abs(clk_info->exp_freq_hz * b, freq_error * a);
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if (sub < min) {
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div_denom = a;
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div_numer = b;
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min = sub;
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}
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}
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} else {
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div_integ++;
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}
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}
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// If the expect frequency is too low to satisfy the maximum integral division, failed and return 0
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if (div_integ > clk_info->max_integ) {
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return 0;
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}
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// Assign result
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clk_div->integ = div_integ;
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clk_div->denom = div_denom;
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clk_div->numer = div_numer;
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// Return the actual frequency
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if (div_numer) {
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uint32_t temp = div_integ * div_denom + div_numer;
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return (uint32_t)(((uint64_t)clk_info->src_freq_hz * div_denom + temp / 2) / temp);
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}
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return clk_info->src_freq_hz / div_integ;
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}
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65
components/hal/include/hal/hal_utils.h
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65
components/hal/include/hal/hal_utils.h
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@ -0,0 +1,65 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clock infomation
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*
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*/
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typedef struct {
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uint32_t src_freq_hz; /*!< Source clock frequency, unit: Hz */
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uint32_t exp_freq_hz; /*!< Expected output clock frequency, unit: Hz */
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uint32_t max_integ; /*!< The max value of the integral part */
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uint32_t min_integ; /*!< The min value of the integral part, integer range: [min_integ, max_integ) */
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uint32_t max_fract; /*!< The max value of the denominator and numerator, numerator range: [0, max_fract), denominator range: [1, max_fract) */
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} hal_utils_clk_info_t;
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/**
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* @brief Members of clock division
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*
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*/
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typedef struct {
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uint32_t integ; /*!< Integer part of division */
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uint32_t denom; /*!< Denominator part of division */
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uint32_t numer; /*!< Numerator part of division */
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} hal_utils_clk_div_t;
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/**
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* @brief Calculate the clock division
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* @note Speed first algorithm, Time complexity O(log n).
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* About 8~10 times faster than the accurate algorithm
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*
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* @param[in] clk_info The clock infomation
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* @param[out] clk_div The clock division
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* @return
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* - 0: Failed to get the result because the division is out of range
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* - others: The real output clock frequency
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*/
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uint32_t hal_utils_calc_clk_div_fast(const hal_utils_clk_info_t *clk_info, hal_utils_clk_div_t *clk_div);
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/**
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* @brief Calculate the clock division
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* @note Accuracy first algorithm, Time complexity O(n).
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* About 1~hundreds times more accurate than the fast algorithm
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*
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* @param[in] clk_info The clock infomation
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* @param[out] clk_div The clock division
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* @return
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* - 0: Failed to get the result because the division is out of range
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* - others: The real output clock frequency
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*/
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uint32_t hal_utils_calc_clk_div_accurate(const hal_utils_clk_info_t *clk_info, hal_utils_clk_div_t *clk_div);
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#ifdef __cplusplus
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}
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#endif
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