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spi: remove HSPI macro on esp32c3 and esp32s3

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This commit is contained in:
Armando 2021-03-05 16:20:33 +08:00
parent b603a0bea0
commit 9b9ea71ff9
32 changed files with 212 additions and 215 deletions
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12
components/driver/include/driver/sdspi_host.h
View File

@ -28,6 +28,12 @@ extern "C" {
/// Handle representing an SD SPI device
typedef int sdspi_dev_handle_t;
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
#define SDSPI_DEFAULT_HOST HSPI_HOST
#else
#define SDSPI_DEFAULT_HOST SPI2_HOST
#endif
/**
* @brief Default sdmmc_host_t structure initializer for SD over SPI driver
*
@ -37,7 +43,7 @@ typedef int sdspi_dev_handle_t;
*/
#define SDSPI_HOST_DEFAULT() {\
.flags = SDMMC_HOST_FLAG_SPI | SDMMC_HOST_FLAG_DEINIT_ARG, \
.slot = HSPI_HOST, \
.slot = SDSPI_DEFAULT_HOST, \
.max_freq_khz = SDMMC_FREQ_DEFAULT, \
.io_voltage = 3.3f, \
.init = &sdspi_host_init, \
@ -71,7 +77,7 @@ typedef struct {
* Macro defining default configuration of SD SPI device.
*/
#define SDSPI_DEVICE_CONFIG_DEFAULT() {\
.host_id = HSPI_HOST, \
.host_id = SDSPI_DEFAULT_HOST, \
.gpio_cs = GPIO_NUM_13, \
.gpio_cd = SDSPI_SLOT_NO_CD, \
.gpio_wp = SDSPI_SLOT_NO_WP, \
@ -228,7 +234,7 @@ typedef struct {
*
* @note The SDIO over sdspi needs an extra interrupt line. Call ``gpio_install_isr_service()`` before this function.
*
* @param slot SPI controller to use (HSPI_HOST or VSPI_HOST)
* @param slot SPI controller to use (SPI2_HOST or SPI3_HOST)
* @param slot_config pointer to slot configuration structure
* @deprecated Use `sdspi_host_init_device` instead.

2
components/driver/include/driver/spi_common.h
View File

@ -119,7 +119,7 @@ typedef struct {
/**
* @brief Initialize a SPI bus
*
* @warning For now, only supports HSPI and VSPI.
* @warning SPI0/1 is not supported
*
* @param host_id SPI peripheral that controls this bus
* @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized

2
components/driver/include/driver/spi_slave.h
View File

@ -88,7 +88,7 @@ struct spi_slave_transaction_t {
/**
* @brief Initialize a SPI bus as a slave interface
*
* @warning For now, only supports HSPI and VSPI.
* @warning SPI0/1 is not supported
*
* @param host SPI peripheral to use as a SPI slave interface
* @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized

1
components/driver/spi_slave.c
View File

@ -119,7 +119,6 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
uint32_t actual_rx_dma_chan = 0;
esp_err_t ret = ESP_OK;
esp_err_t err;
//We only support HSPI/VSPI, period.
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
#ifdef CONFIG_IDF_TARGET_ESP32
SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG );

126
components/driver/test/include/test/test_common_spi.h
View File

@ -16,32 +16,29 @@
// All the tests using the header should use this definition as much as possible,
// so that the working host can be changed easily in the future.
#if CONFIG_IDF_TARGET_ESP32
#define TEST_SPI_HOST HSPI_HOST
#define TEST_SLAVE_HOST VSPI_HOST
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI3_HOST
#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
#define SLAVE_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
#define MASTER_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_WP SPI2_IOMUX_PIN_NUM_WP
#define MASTER_IOMUX_PIN_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_IOMUX_PIN_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK VSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS VSPI_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_MISO HSPI_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK HSPI_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS HSPI_IOMUX_PIN_NUM_CS
#define SLAVE_IOMUX_PIN_MISO SPI3_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI SPI3_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK SPI3_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS SPI3_IOMUX_PIN_NUM_CS
#define SLAVE_IOMUX_PIN_WP SPI3_IOMUX_PIN_NUM_WP
#define SLAVE_IOMUX_PIN_HD SPI3_IOMUX_PIN_NUM_HD
#define UNCONNECTED_PIN 27
#define INPUT_ONLY_PIN 34
@ -50,34 +47,29 @@
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI3_HOST
#define TEST_SPI_HOST FSPI_HOST
#define TEST_SLAVE_HOST HSPI_HOST
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP -1
#define SLAVE_PIN_NUM_HD -1
#define MASTER_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_WP SPI2_IOMUX_PIN_NUM_WP
#define MASTER_IOMUX_PIN_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_IOMUX_PIN_MISO -1
#define SLAVE_IOMUX_PIN_MOSI -1
#define SLAVE_IOMUX_PIN_SCLK -1
#define SLAVE_IOMUX_PIN_CS -1
#define MASTER_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS
#define SLAVE_IOMUX_PIN_NUM_WP -1
#define SLAVE_IOMUX_PIN_NUM_HD -1
#define UNCONNECTED_PIN 41
#define INPUT_ONLY_PIN 46
@ -86,40 +78,30 @@
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32C3
#define TEST_SPI_HOST FSPI_HOST
#define TEST_SLAVE_HOST FSPI_HOST
#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO -1
#define SLAVE_PIN_NUM_MOSI -1
#define SLAVE_PIN_NUM_CLK -1
#define SLAVE_PIN_NUM_CS -1
#define SLAVE_PIN_NUM_WP -1
#define SLAVE_PIN_NUM_HD -1
//NOTE: On esp32c3, there is only 1 GPSPI controller, so master-slave test on single board should be disabled
#define SLAVE_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI2_HOST
#define MASTER_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define GPIO_DELAY 0
#define ESP_SPI_SLAVE_TV 0
#define WIRE_DELAY 12.5
#endif
#define GET_DMA_CHAN(HOST) (HOST)

2
components/driver/test/test_sdio.c
View File

@ -39,7 +39,7 @@
//TEST_CNT > 512
#define TEST_CNT 10000
#define TEST_SDSPI_HOST HSPI_HOST
#define TEST_SDSPI_HOST SPI2_HOST
#define TEST_SDSPI_DMACHAN 1
#define TEST_RESET_DATA_LEN 10

2
components/driver/test/test_spi_master.c
View File

@ -474,7 +474,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
}
TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)", "[spi]")
TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)", "[spi]")
{
//spi config
spi_bus_config_t bus_config;

6
components/driver/test/test_spi_slave.c
View File

@ -224,7 +224,7 @@ static void unaligned_test_slave(void)
unity_wait_for_signal("Master ready");
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA);
@ -248,7 +248,7 @@ static void unaligned_test_slave(void)
};
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_transmit(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY));
TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &slave_t, portMAX_DELAY));
//show result
ESP_LOGI(SLAVE_TAG, "trans_len: %d", slave_t.trans_len);
@ -265,7 +265,7 @@ static void unaligned_test_slave(void)
free(slave_send_buf);
free(slave_recv_buf);
free(master_send_buf);
TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK);
TEST_ASSERT(spi_slave_free(TEST_SPI_HOST) == ESP_OK);
}
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Unaligned_Test", "[spi_ms][test_env=Example_SPI_Multi_device][timeout=120]", unaligned_test_master, unaligned_test_slave);

4
components/driver/test/test_spi_slave_hd.c
View File

@ -115,8 +115,8 @@ static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callbac
{
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
bus_cfg.max_transfer_sz = TEST_DMA_MAX_SIZE*30;
bus_cfg.quadwp_io_num = SLAVE_PIN_NUM_WP;
bus_cfg.quadhd_io_num = SLAVE_PIN_NUM_HD;
bus_cfg.quadwp_io_num = -1;
bus_cfg.quadhd_io_num = -1;
#ifdef TEST_SLAVE_GPIO_MATRIX
bus_cfg.flags |= SPICOMMON_BUSFLAG_FORCE_GPIO;
#endif

2
components/fatfs/test/test_fatfs_sdmmc.c
View File

@ -35,7 +35,7 @@
#define SDSPI_MISO_PIN 2
#define SDSPI_CS_PIN 13
#define SDSPI_CLK_PIN 14
#define SDSPI_HOST_ID HSPI_HOST
#define SDSPI_HOST_ID SPI2_HOST
#if SOC_SDMMC_HOST_SUPPORTED

12
components/hal/esp32s3/include/hal/clk_gate_ll.h
View File

@ -67,12 +67,10 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return SYSTEM_PCNT_CLK_EN;
case PERIPH_SPI_MODULE:
return SYSTEM_SPI01_CLK_EN;
case PERIPH_FSPI_MODULE:
case PERIPH_SPI2_MODULE:
return SYSTEM_SPI2_CLK_EN;
case PERIPH_HSPI_MODULE:
case PERIPH_SPI3_MODULE:
return SYSTEM_SPI3_CLK_EN;
case PERIPH_VSPI_MODULE:
return SYSTEM_SPI4_CLK_EN;
case PERIPH_SDMMC_MODULE:
return SYSTEM_SDIO_HOST_CLK_EN;
case PERIPH_TWAI_MODULE:
@ -150,12 +148,10 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return SYSTEM_PCNT_RST;
case PERIPH_SPI_MODULE:
return SYSTEM_SPI01_RST;
case PERIPH_FSPI_MODULE:
case PERIPH_SPI2_MODULE:
return SYSTEM_SPI2_RST;
case PERIPH_HSPI_MODULE:
case PERIPH_SPI3_MODULE:
return SYSTEM_SPI3_RST;
case PERIPH_VSPI_MODULE:
return SYSTEM_SPI4_RST;
case PERIPH_SDMMC_MODULE:
return SYSTEM_SDIO_HOST_RST;
case PERIPH_TWAI_MODULE:

2
components/hal/include/hal/spi_hal.h
View File

@ -160,7 +160,7 @@ typedef struct {
* Init the peripheral and the context.
*
* @param hal Context of the HAL layer.
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for SPI2 and 2 for SPI3.
* @param hal_config Configuration of the hal defined by the upper layer.
*/
void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *hal_config);

4
components/hal/include/hal/spi_slave_hal.h
View File

@ -91,8 +91,8 @@ typedef struct {
/**
* Init the peripheral and the context.
*
* @param hal Context of the HAL layer.
* @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3).
* @param hal Context of the HAL layer.
* @param hal_config Configuration of the HAL
*/
void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config);

9
components/hal/include/hal/spi_types.h
View File

@ -44,21 +44,16 @@ FLAG_ATTR(spi_event_t)
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
//alias for different chips
//alias for different chips, deprecated for the chips after esp32s2
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_HOST SPI1_HOST
#define HSPI_HOST SPI2_HOST
#define VSPI_HOST SPI3_HOST
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#elif CONFIG_IDF_TARGET_ESP32S2
// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 and later
#define SPI_HOST SPI1_HOST
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI3_HOST
#elif CONFIG_IDF_TARGET_ESP32C3
/* No SPI3_host on C3 */
#define SPI_HOST SPI1_HOST
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI2_HOST
#endif
/** @endcond */

6
components/hal/spi_flash_hal.c
View File

@ -80,7 +80,7 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
return ESP_ERR_INVALID_ARG;
}
bool gpspi = (cfg->host_id > SPI_HOST);
bool gpspi = (cfg->host_id > SPI1_HOST);
const spi_flash_hal_clock_config_t *clock_cfg = gpspi? &spi_flash_gpspi_clk_cfg_reg[cfg->speed]: &spi_flash_clk_cfg_reg[cfg->speed];
*data_out = (spi_flash_hal_context_t) {
@ -102,7 +102,7 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p)
{
bool direct_write = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI_HOST)
bool direct_write = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST)
|| esp_ptr_in_dram(p) );
return direct_write;
}
@ -111,7 +111,7 @@ bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void
bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
{
//currently the host doesn't support to read through dma, no word-aligned requirements
bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI_HOST)
bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST)
|| esp_ptr_in_dram(p) );
return direct_read;
}

12
components/hal/spi_flash_hal_iram.c
View File

@ -120,7 +120,7 @@ uint32_t spi_flash_hal_check_status(spi_flash_host_inst_t *host)
#endif
// Not clear if this is necessary, or only necessary if
// chip->spi == SPI1. But probably doesn't hurt...
if ((void*) dev == spi_flash_ll_get_hw(SPI_HOST)) {
if ((void*) dev == spi_flash_ll_get_hw(SPI1_HOST)) {
#if CONFIG_IDF_TARGET_ESP32
status &= spi_flash_ll_host_idle(&SPI0);
#endif
@ -133,7 +133,7 @@ uint32_t spi_flash_hal_check_status(spi_flash_host_inst_t *host)
esp_err_t spi_flash_hal_setup_read_suspend(spi_flash_host_inst_t *host, const spi_flash_sus_cmd_conf *sus_conf)
{
#if SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
spi_mem_dev_t *dev = (spi_mem_dev_t *)spi_flash_ll_get_hw(SPI_HOST);
spi_mem_dev_t *dev = (spi_mem_dev_t *)spi_flash_ll_get_hw(SPI1_HOST);
spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host;
memcpy(&(ctx->sus_cfg), sus_conf, sizeof(spi_flash_sus_cmd_conf));
spimem_flash_ll_set_read_sus_status(dev, sus_conf->sus_mask);
@ -147,7 +147,7 @@ esp_err_t spi_flash_hal_setup_read_suspend(spi_flash_host_inst_t *host, const sp
#if SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host)
{
spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI_HOST);
spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI1_HOST);
spimem_flash_ll_auto_wait_idle_init(dev, true);
spimem_flash_ll_auto_suspend_init(dev, true);
#if SOC_SPI_MEM_SUPPORT_CHECK_SUS
@ -157,7 +157,7 @@ void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host)
void spi_flash_hal_setup_auto_resume_mode(spi_flash_host_inst_t *host)
{
spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI_HOST);
spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI1_HOST);
spimem_flash_ll_auto_resume_init(dev, true);
#if SOC_SPI_MEM_SUPPORT_CHECK_SUS
spimem_flash_ll_res_check_sus_setup(dev, true);
@ -166,7 +166,7 @@ void spi_flash_hal_setup_auto_resume_mode(spi_flash_host_inst_t *host)
void spi_flash_hal_disable_auto_suspend_mode(spi_flash_host_inst_t *host)
{
spi_mem_dev_t *dev = (spi_mem_dev_t *)spi_flash_ll_get_hw(SPI_HOST);
spi_mem_dev_t *dev = (spi_mem_dev_t *)spi_flash_ll_get_hw(SPI1_HOST);
spimem_flash_ll_auto_wait_idle_init(dev, false);
spimem_flash_ll_auto_suspend_init(dev, false);
#if SOC_SPI_MEM_SUPPORT_CHECK_SUS
@ -176,7 +176,7 @@ void spi_flash_hal_disable_auto_suspend_mode(spi_flash_host_inst_t *host)
void spi_flash_hal_disable_auto_resume_mode(spi_flash_host_inst_t *host)
{
spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI_HOST);
spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI1_HOST);
spimem_flash_ll_auto_resume_init(dev, false);
#if SOC_SPI_MEM_SUPPORT_CHECK_SUS
spimem_flash_ll_res_check_sus_setup(dev, false);

20
components/soc/esp32/include/soc/spi_pins.h
View File

@ -22,8 +22,6 @@
#define SPI_IOMUX_PIN_NUM_WP 10
#define SPI_IOMUX_PIN_NUM_HD 9
#define HSPI_FUNC_NUM 1
//For D2WD and PICO-D4 chip
#define SPI_D2WD_PIN_NUM_MISO 17
#define SPI_D2WD_PIN_NUM_MOSI 8
@ -32,6 +30,24 @@
#define SPI_D2WD_PIN_NUM_WP 7
#define SPI_D2WD_PIN_NUM_HD 11
#define SPI2_FUNC_NUM HSPI_FUNC_NUM
#define SPI2_IOMUX_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define SPI2_IOMUX_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define SPI2_IOMUX_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define SPI2_IOMUX_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define SPI2_IOMUX_PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define SPI2_IOMUX_PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#define SPI3_FUNC_NUM VSPI_FUNC_NUM
#define SPI3_IOMUX_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SPI3_IOMUX_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SPI3_IOMUX_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK
#define SPI3_IOMUX_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
#define SPI3_IOMUX_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
#define SPI3_IOMUX_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
//Following Macros are deprecated. Please use the Macros above
#define HSPI_FUNC_NUM 1
#define HSPI_IOMUX_PIN_NUM_MISO 12
#define HSPI_IOMUX_PIN_NUM_MOSI 13
#define HSPI_IOMUX_PIN_NUM_CLK 14

19
components/soc/esp32c3/include/soc/spi_pins.h
View File

@ -22,18 +22,13 @@
#define SPI_IOMUX_PIN_NUM_CLK 15
#define SPI_IOMUX_PIN_NUM_MISO 17
#define SPI_IOMUX_PIN_NUM_WP 13
//TODO: add the next slot
#define FSPI_FUNC_NUM 2
#define FSPI_IOMUX_PIN_NUM_MISO 2
#define FSPI_IOMUX_PIN_NUM_HD 4
#define FSPI_IOMUX_PIN_NUM_WP 5
#define FSPI_IOMUX_PIN_NUM_CLK 6
#define FSPI_IOMUX_PIN_NUM_MOSI 7
#define FSPI_IOMUX_PIN_NUM_CS 10
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2
#define SPI2_IOMUX_PIN_NUM_HD 4
#define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 10
#endif

14
components/soc/esp32c3/spi_periph.c
View File

@ -56,16 +56,16 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI2_INTR_SOURCE,
.irq_dma = -1,
.module = PERIPH_SPI2_MODULE,
.hw = &GPSPI2,
.func = FSPI_FUNC_NUM,
.func = SPI2_FUNC_NUM,
}
};

13
components/soc/esp32s2/include/soc/spi_pins.h
View File

@ -22,6 +22,17 @@
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
#define SPI2_FUNC_NUM FSPI_FUNC_NUM
#define SPI2_IOMUX_PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SPI2_IOMUX_PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define SPI2_IOMUX_PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define SPI2_IOMUX_PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define SPI2_IOMUX_PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define SPI2_IOMUX_PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
//SPI3 has no iomux pins
//Following Macros are deprecated. Please use the Macros above
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
@ -29,5 +40,3 @@
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//SPI3 has no iomux pins

13
components/soc/esp32s3/include/soc/periph_defs.h
View File

@ -39,10 +39,9 @@ typedef enum {
PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_FSPI_MODULE, //SPI2
PERIPH_HSPI_MODULE, //SPI3
PERIPH_VSPI_MODULE, //SPI4
PERIPH_SPI_MODULE,
PERIPH_SPI2_MODULE,
PERIPH_SPI3_MODULE,
PERIPH_SDMMC_MODULE,
PERIPH_TWAI_MODULE,
PERIPH_RNG_MODULE,
@ -85,8 +84,7 @@ typedef enum {
ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/
ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, level*/
ETS_LCD_CAM_INTR_SOURCE, /**< interrupt of LCD camera, level*/
ETS_LCD_CAM_INTR_SOURCE = 24, /**< interrupt of LCD camera, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
@ -106,8 +104,7 @@ typedef enum {
ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/
ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/
ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/
ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, level*/
ETS_WDT_INTR_SOURCE, /**< will be cancelled*/
ETS_WDT_INTR_SOURCE = 47, /**< will be cancelled*/
ETS_TIMER1_INTR_SOURCE = 48,
ETS_TIMER2_INTR_SOURCE,

16
components/soc/esp32s3/include/soc/spi_pins.h
View File

@ -22,12 +22,12 @@
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
#define SPI2_FUNC_NUM 4
#define SPI2_IOMUX_PIN_NUM_HD 9
#define SPI2_IOMUX_PIN_NUM_CS 10
#define SPI2_IOMUX_PIN_NUM_MOSI 11
#define SPI2_IOMUX_PIN_NUM_CLK 12
#define SPI2_IOMUX_PIN_NUM_MISO 13
#define SPI2_IOMUX_PIN_NUM_WP 14
//HSPI have no iomux pins
//SPI3 have no iomux pins

18
components/soc/esp32s3/spi_periph.c
View File

@ -56,17 +56,17 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI2_INTR_SOURCE,
.irq_dma = -1,
.module = PERIPH_FSPI_MODULE,
.module = PERIPH_SPI2_MODULE,
.hw = &GPSPI2,
.func = FSPI_FUNC_NUM,
.func = SPI2_FUNC_NUM,
}, {
.spiclk_out = SPI3_CLK_OUT_IDX,
.spiclk_in = SPI3_CLK_IN_IDX,
@ -90,7 +90,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spics0_iomux_pin = -1,
.irq = ETS_SPI3_INTR_SOURCE,
.irq_dma = -1,
.module = PERIPH_HSPI_MODULE,
.module = PERIPH_SPI3_MODULE,
.hw = &GPSPI3,
.func = -1,
}

14
components/spi_flash/esp_flash_spi_init.c
View File

@ -65,7 +65,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
//TODO: modify cs hold to meet requirements of all chips!!!
#if CONFIG_IDF_TARGET_ESP32
#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
.host_id = SPI_HOST,\
.host_id = SPI1_HOST,\
.speed = DEFAULT_FLASH_SPEED, \
.cs_num = 0, \
.iomux = false, \
@ -73,7 +73,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
}
#elif CONFIG_IDF_TARGET_ESP32S2
#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
.host_id = SPI_HOST,\
.host_id = SPI1_HOST,\
.speed = DEFAULT_FLASH_SPEED, \
.cs_num = 0, \
.iomux = true, \
@ -82,7 +82,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/efuse.h"
#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
.host_id = SPI_HOST,\
.host_id = SPI1_HOST,\
.speed = DEFAULT_FLASH_SPEED, \
.cs_num = 0, \
.iomux = true, \
@ -92,7 +92,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
#include "esp32c3/rom/efuse.h"
#if !CONFIG_SPI_FLASH_AUTO_SUSPEND
#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
.host_id = SPI_HOST,\
.host_id = SPI1_HOST,\
.speed = DEFAULT_FLASH_SPEED, \
.cs_num = 0, \
.iomux = true, \
@ -100,7 +100,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
}
#else
#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
.host_id = SPI_HOST,\
.host_id = SPI1_HOST,\
.speed = DEFAULT_FLASH_SPEED, \
.cs_num = 0, \
.iomux = true, \
@ -161,7 +161,7 @@ esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_d
esp_err_t ret = ESP_OK;
uint32_t caps = MALLOC_CAP_DEFAULT;
if (config->host_id == SPI_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
if (config->host_id == SPI1_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
if (!chip) {
@ -193,7 +193,7 @@ esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_d
// When `CONFIG_SPI_FLASH_SHARE_SPI1_BUS` is not enabled on SPI1 bus, the
// `esp_flash_init_os_functions` will not be able to assign a new device ID. In this case, we
// use the `cs_id` in the config structure.
if (dev_id == -1 && config->host_id == SPI_HOST) {
if (dev_id == -1 && config->host_id == SPI1_HOST) {
dev_id = config->cs_id;
}
assert(dev_id < SOC_SPI_PERIPH_CS_NUM(config->host_id) && dev_id >= 0);

4
components/spi_flash/memspi_host_driver.c
View File

@ -70,7 +70,7 @@ static const spi_flash_host_driver_t esp_flash_gpspi_host = {
esp_err_t memspi_host_init_pointers(memspi_host_inst_t *host, const memspi_host_config_t *cfg)
{
#if SOC_MEMSPI_IS_INDEPENDENT
if (cfg->host_id == SPI_HOST)
if (cfg->host_id == SPI1_HOST)
host->inst.driver = &esp_flash_default_host;
else {
host->inst.driver = &esp_flash_gpspi_host;
@ -130,7 +130,7 @@ esp_err_t memspi_host_read_status_hs(spi_flash_host_inst_t *host, uint8_t *out_s
esp_err_t memspi_host_flush_cache(spi_flash_host_inst_t *host, uint32_t addr, uint32_t size)
{
if ((void*)((memspi_host_inst_t*)host)->spi == (void*) spi_flash_ll_get_hw(SPI_HOST)) {
if ((void*)((memspi_host_inst_t*)host)->spi == (void*) spi_flash_ll_get_hw(SPI1_HOST)) {
spi_flash_check_and_flush_cache(addr, size);
}
return ESP_OK;

2
components/spi_flash/spi_flash_os_func_app.c
View File

@ -234,7 +234,7 @@ esp_err_t esp_flash_init_os_functions(esp_flash_t *chip, int host_id, int* out_d
// Skip initializing the bus lock when the bus is SPI1 and the bus is not shared with SPI Master
// driver, leaving dev_handle = NULL
bool skip_register_dev = (host_id == SPI_HOST);
bool skip_register_dev = (host_id == SPI1_HOST);
#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
skip_register_dev = false;
#endif

16
components/spi_flash/test/test_esp_flash.c
View File

@ -172,7 +172,7 @@ static const char TAG[] = "test_esp_flash";
{ \
.io_mode = TEST_SPI_READ_MODE,\
.speed = TEST_SPI_SPEED, \
.host_id = SPI_HOST, \
.host_id = SPI1_HOST, \
.cs_id = 1, \
/* the pin which is usually used by the PSRAM */ \
.cs_io_num = SPI1_CS_IO, \
@ -229,7 +229,7 @@ flashtest_config_t config_list[] = {
{
.io_mode = TEST_SPI_READ_MODE,
.speed = TEST_SPI_SPEED,
.host_id = FSPI_HOST,
.host_id = SPI2_HOST,
.cs_id = 0,
.cs_io_num = FSPI_PIN_NUM_CS,
.input_delay_ns = 0,
@ -245,7 +245,7 @@ flashtest_config_t config_list[] = {
{
.io_mode = TEST_SPI_READ_MODE,
.speed = TEST_SPI_SPEED,
.host_id = FSPI_HOST,
.host_id = SPI2_HOST,
.cs_id = 0,
.cs_io_num = FSPI_PIN_NUM_CS,
.input_delay_ns = 0,
@ -258,7 +258,7 @@ static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int
spi_host_device_t host_id;
int cs_id;
if (chip == NULL) {
host_id = SPI_HOST;
host_id = SPI1_HOST;
cs_id = 0;
} else {
spi_flash_hal_context_t* host_data = (spi_flash_hal_context_t*)chip->host;
@ -275,7 +275,7 @@ static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int
static void setup_bus(spi_host_device_t host_id)
{
if (host_id == SPI_HOST) {
if (host_id == SPI1_HOST) {
ESP_LOGI(TAG, "setup flash on SPI1 CS1...\n");
//no need to initialize the bus, however the CLK may need one more output if it's on the usual place of PSRAM
#ifdef EXTRA_SPI1_CLK_IO
@ -295,7 +295,7 @@ static void setup_bus(spi_host_device_t host_id)
#endif //!DISABLED_FOR_TARGETS(ESP32)
#if !DISABLED_FOR_TARGETS(ESP32)
} else if (host_id == FSPI_HOST) {
} else if (host_id == SPI2_HOST) {
ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1);
spi_bus_config_t fspi_bus_cfg = {
.mosi_io_num = FSPI_PIN_NUM_MOSI,
@ -312,7 +312,7 @@ static void setup_bus(spi_host_device_t host_id)
TEST_ESP_OK(ret);
#endif
//currently the SPI bus for main flash chip is initialized through GPIO matrix
} else if (host_id == HSPI_HOST) {
} else if (host_id == SPI2_HOST) {
ESP_LOGI(TAG, "setup flash on SPI%d (HSPI) CS0...\n", host_id + 1);
spi_bus_config_t hspi_bus_cfg = {
.mosi_io_num = HSPI_PIN_NUM_MOSI,
@ -1091,7 +1091,7 @@ static void test_flash_read_write_performance(const esp_partition_t *part)
int cs_id;
get_chip_host(chip, &host_id, &cs_id);
if (host_id != SPI_HOST) {
if (host_id != SPI1_HOST) {
// Chips on other SPI buses
CHECK_PERFORMANCE(EXT_);
} else if (cs_id == 0) {

2
docs/en/api-guides/unit-tests-legacy.rst
View File

@ -175,7 +175,7 @@ When unit test app is idle, press "Enter" will make it print test menu with all
(14) "SPI Master clockdiv calculation routines" [spi]
(15) "SPI Master test" [spi][ignore]
(16) "SPI Master test, interaction of multiple devs" [spi][ignore]
(17) "SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" [spi]
(17) "SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)" [spi]
(18) "SPI Master DMA test, TX and RX in different regions" [spi]
(19) "SPI Master DMA test: length, start, not aligned" [spi]
(20) "reset reason check for deepsleep" [esp32][test_env=UT_T2_1][multi_stage]

2
docs/en/api-guides/unit-tests.rst
View File

@ -204,7 +204,7 @@ When unit test app is idle, press "Enter" will make it print test menu with all
(14) "SPI Master clockdiv calculation routines" [spi]
(15) "SPI Master test" [spi][ignore]
(16) "SPI Master test, interaction of multiple devs" [spi][ignore]
(17) "SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" [spi]
(17) "SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)" [spi]
(18) "SPI Master DMA test, TX and RX in different regions" [spi]
(19) "SPI Master DMA test: length, start, not aligned" [spi]
(20) "reset reason check for deepsleep" [{IDF_TARGET_PATH_NAME}][test_env=UT_T2_1][multi_stage]

2
docs/zh_CN/api-guides/unit-tests-legacy.rst
View File

@ -204,7 +204,7 @@ DUT2 终端::
(14) "SPI Master clockdiv calculation routines" [spi]
(15) "SPI Master test" [spi][ignore]
(16) "SPI Master test, interaction of multiple devs" [spi][ignore]
(17) "SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" [spi]
(17) "SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)" [spi]
(18) "SPI Master DMA test, TX and RX in different regions" [spi]
(19) "SPI Master DMA test: length, start, not aligned" [spi]
(20) "reset reason check for deepsleep" [esp32][test_env=UT_T2_1][multi_stage]

54
docs/zh_CN/api-guides/unit-tests.rst
View File

@ -182,33 +182,35 @@ DUT2（slave）终端::
烧写完成后重启 {IDF_TARGET_NAME}， 它将启动单元测试程序。
当单元测试应用程序空闲时，输入回车键，它会打印出测试菜单，其中包含所有的测试项目::
当单元测试应用程序空闲时，输入回车键，它会打印出测试菜单，其中包含所有的测试项目。
Here's the test menu, pick your combo:
(1) "esp_ota_begin() verifies arguments" [ota]
(2) "esp_ota_get_next_update_partition logic" [ota]
(3) "Verify bootloader image in flash" [bootloader_support]
(4) "Verify unit test app image" [bootloader_support]
(5) "can use new and delete" [cxx]
(6) "can call virtual functions" [cxx]
(7) "can use static initializers for non-POD types" [cxx]
(8) "can use std::vector" [cxx]
(9) "static initialization guards work as expected" [cxx]
(10) "global initializers run in the correct order" [cxx]
(11) "before scheduler has started, static initializers work correctly" [cxx]
(12) "adc2 work with wifi" [adc]
(13) "gpio master/slave test example" [ignore][misc][test_env=UT_T2_1][multi_device]
(1) "gpio_master_test"
(2) "gpio_slave_test"
(14) "SPI Master clockdiv calculation routines" [spi]
(15) "SPI Master test" [spi][ignore]
(16) "SPI Master test, interaction of multiple devs" [spi][ignore]
(17) "SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" [spi]
(18) "SPI Master DMA test, TX and RX in different regions" [spi]
(19) "SPI Master DMA test: length, start, not aligned" [spi]
(20) "reset reason check for deepsleep" [{IDF_TARGET_PATH_NAME}][test_env=UT_T2_1][multi_stage]
(1) "trigger_deepsleep"
(2) "check_deepsleep_reset_reason"
.. code::
Here's the test menu, pick your combo:
(1) "esp_ota_begin() verifies arguments" [ota]
(2) "esp_ota_get_next_update_partition logic" [ota]
(3) "Verify bootloader image in flash" [bootloader_support]
(4) "Verify unit test app image" [bootloader_support]
(5) "can use new and delete" [cxx]
(6) "can call virtual functions" [cxx]
(7) "can use static initializers for non-POD types" [cxx]
(8) "can use std::vector" [cxx]
(9) "static initialization guards work as expected" [cxx]
(10) "global initializers run in the correct order" [cxx]
(11) "before scheduler has started, static initializers work correctly" [cxx]
(12) "adc2 work with wifi" [adc]
(13) "gpio master/slave test example" [ignore][misc][test_env=UT_T2_1][multi_device]
(1) "gpio_master_test"
(2) "gpio_slave_test"
(14) "SPI Master clockdiv calculation routines" [spi]
(15) "SPI Master test" [spi][ignore]
(16) "SPI Master test, interaction of multiple devs" [spi][ignore]
(17) "SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)" [spi]
(18) "SPI Master DMA test, TX and RX in different regions" [spi]
(19) "SPI Master DMA test: length, start, not aligned" [spi]
(20) "reset reason check for deepsleep" [{IDF_TARGET_PATH_NAME}][test_env=UT_T2_1][multi_stage]
(1) "trigger_deepsleep"
(2) "check_deepsleep_reset_reason"
常规测试用例会打印用例名字和描述，主从测试用例还会打印子菜单（已注册的测试函数的名字）。

2
docs/zh_CN/api-reference/storage/spi_flash.rst
View File

@ -8,7 +8,7 @@ SPI Flash API
SPI Flash 组件提供外部 flash 数据读取、写入、擦除和内存映射相关的 API 函数，同时也提供了更高层级的，面向分区的 API 函数（定义在 :doc:`分区表 </api-guides/partition-tables>` 中）。
与 ESP-IDF V4.0 之前的 API 不同，这一版 `esp_flash_*` API 功能并不局限于主 SPI Flash 芯片（即运行程序的 SPI Flash 芯片）。使用不同的芯片指针，您可以通过 SPI0/1 或 HSPI/VSPI 总线访问外部 flash。
与 ESP-IDF V4.0 之前的 API 不同，这一版 `esp_flash_*` API 功能并不局限于主 SPI Flash 芯片（即运行程序的 SPI Flash 芯片）。使用不同的芯片指针，您可以通过 SPI0/1 或 SPI2/SPI3 总线访问外部 flash。
.. note::