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Clean IRAM and DRAM address space conversion macros
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41bbc39669
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@ -70,13 +70,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
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#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000)
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const soc_memory_region_t soc_memory_regions[] = {
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{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
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{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
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{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
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#endif
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@ -70,13 +70,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
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#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000)
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const soc_memory_region_t soc_memory_regions[] = {
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{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
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{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
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{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
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#endif
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@ -59,7 +59,6 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
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#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x6F0000)
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const soc_memory_region_t soc_memory_regions[] = {
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#ifdef CONFIG_SPIRAM
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@ -75,7 +74,7 @@ const soc_memory_region_t soc_memory_regions[] = {
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{ 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy
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{ 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy
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{ 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), 2, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy,
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task
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#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB
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{ 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM
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#endif
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@ -238,6 +238,10 @@
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#define SOC_DIRAM_DRAM_LOW 0x3FC80000
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#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
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#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
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#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
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#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FC88000
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#define SOC_DMA_HIGH 0x3FD00000
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@ -250,10 +254,6 @@
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//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
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#define SOC_MEM_INTERNAL_LOW 0x3FC80000
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#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
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#define SOC_MEM_INTERNAL_LOW1 0x40370000
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#define SOC_MEM_INTERNAL_HIGH1 0x403E0000
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#define SOC_MEM_INTERNAL_LOW2 0x600FE000
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#define SOC_MEM_INTERNAL_HIGH2 0x60100000
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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@ -266,6 +266,10 @@
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#define SOC_DIRAM_DRAM_LOW 0x3FC80000
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#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
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#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
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#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
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#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FC88000
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#define SOC_DMA_HIGH 0x3FD00000
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@ -278,10 +282,6 @@
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//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
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#define SOC_MEM_INTERNAL_LOW 0x3FC80000
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#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
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#define SOC_MEM_INTERNAL_LOW1 0x40370000
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#define SOC_MEM_INTERNAL_HIGH1 0x403E0000
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#define SOC_MEM_INTERNAL_LOW2 0x600FE000
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#define SOC_MEM_INTERNAL_HIGH2 0x60100000
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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@ -277,6 +277,10 @@
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#define SOC_DIRAM_DRAM_LOW 0x3FFB0000
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#define SOC_DIRAM_DRAM_HIGH 0x40000000
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#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
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#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
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#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
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// Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FFB0000
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#define SOC_DMA_HIGH 0x40000000
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@ -284,6 +284,10 @@
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#define SOC_DIRAM_DRAM_LOW 0x3FC88000
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#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000
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#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
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#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
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#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
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// Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FC88000
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#define SOC_DMA_HIGH 0x3FD00000
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@ -94,9 +94,6 @@ static uint8_t fnc_call0_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x0
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volatile bool g_override_illegal_instruction = false;
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#define MAP_DRAM_TO_IRAM(addr) (addr - SOC_DIRAM_DRAM_LOW + SOC_DIRAM_IRAM_LOW)
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#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_DIRAM_IRAM_LOW + SOC_DIRAM_DRAM_LOW)
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#define SRAM_TEST_BUFFER_SIZE 0x400
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#define SRAM_TEST_OFFSET 0x200
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