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feat(soc): Added soc headers for esp32p4, part 2

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Armando 2023-06-26 15:39:57 +08:00
parent b3b9b327a1
commit 989c6f6e46
86 changed files with 119269 additions and 0 deletions
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578
components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_LP2HP_PMS_DATE_REG register
* NA
*/
#define TEE_LP2HP_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2294790;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_LP_MM_PMS_REG0_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_PSRAM_ALLOW (BIT(0))
#define TEE_REG_LP_MM_PSRAM_ALLOW_M (TEE_REG_LP_MM_PSRAM_ALLOW_V << TEE_REG_LP_MM_PSRAM_ALLOW_S)
#define TEE_REG_LP_MM_PSRAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_PSRAM_ALLOW_S 0
/** TEE_REG_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_FLASH_ALLOW (BIT(1))
#define TEE_REG_LP_MM_FLASH_ALLOW_M (TEE_REG_LP_MM_FLASH_ALLOW_V << TEE_REG_LP_MM_FLASH_ALLOW_S)
#define TEE_REG_LP_MM_FLASH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_FLASH_ALLOW_S 1
/** TEE_REG_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_L2MEM_ALLOW (BIT(2))
#define TEE_REG_LP_MM_L2MEM_ALLOW_M (TEE_REG_LP_MM_L2MEM_ALLOW_V << TEE_REG_LP_MM_L2MEM_ALLOW_S)
#define TEE_REG_LP_MM_L2MEM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_L2MEM_ALLOW_S 2
/** TEE_REG_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_L2ROM_ALLOW (BIT(3))
#define TEE_REG_LP_MM_L2ROM_ALLOW_M (TEE_REG_LP_MM_L2ROM_ALLOW_V << TEE_REG_LP_MM_L2ROM_ALLOW_S)
#define TEE_REG_LP_MM_L2ROM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_L2ROM_ALLOW_S 3
/** TEE_REG_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_TRACE0_ALLOW (BIT(6))
#define TEE_REG_LP_MM_TRACE0_ALLOW_M (TEE_REG_LP_MM_TRACE0_ALLOW_V << TEE_REG_LP_MM_TRACE0_ALLOW_S)
#define TEE_REG_LP_MM_TRACE0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_TRACE0_ALLOW_S 6
/** TEE_REG_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_TRACE1_ALLOW (BIT(7))
#define TEE_REG_LP_MM_TRACE1_ALLOW_M (TEE_REG_LP_MM_TRACE1_ALLOW_V << TEE_REG_LP_MM_TRACE1_ALLOW_S)
#define TEE_REG_LP_MM_TRACE1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_TRACE1_ALLOW_S 7
/** TEE_REG_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW (BIT(8))
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_M (TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S)
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S 8
/** TEE_REG_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW (BIT(9))
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_M (TEE_REG_LP_MM_L2MEM_MON_ALLOW_V << TEE_REG_LP_MM_L2MEM_MON_ALLOW_S)
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_S 9
/** TEE_REG_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_TCM_MON_ALLOW (BIT(10))
#define TEE_REG_LP_MM_TCM_MON_ALLOW_M (TEE_REG_LP_MM_TCM_MON_ALLOW_V << TEE_REG_LP_MM_TCM_MON_ALLOW_S)
#define TEE_REG_LP_MM_TCM_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_TCM_MON_ALLOW_S 10
/** TEE_REG_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_CACHE_ALLOW (BIT(11))
#define TEE_REG_LP_MM_CACHE_ALLOW_M (TEE_REG_LP_MM_CACHE_ALLOW_V << TEE_REG_LP_MM_CACHE_ALLOW_S)
#define TEE_REG_LP_MM_CACHE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_CACHE_ALLOW_S 11
/** TEE_LP_MM_PMS_REG1_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x30)
/** TEE_REG_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW (BIT(0))
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_S 0
/** TEE_REG_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW (BIT(1))
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S 1
/** TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2))
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S 2
/** TEE_REG_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GDMA_ALLOW (BIT(3))
#define TEE_REG_LP_MM_HP_GDMA_ALLOW_M (TEE_REG_LP_MM_HP_GDMA_ALLOW_V << TEE_REG_LP_MM_HP_GDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_GDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GDMA_ALLOW_S 3
/** TEE_REG_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW (BIT(4))
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_M (TEE_REG_LP_MM_HP_REGDMA_ALLOW_V << TEE_REG_LP_MM_HP_REGDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_S 4
/** TEE_REG_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW (BIT(5))
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_M (TEE_REG_LP_MM_HP_SDMMC_ALLOW_V << TEE_REG_LP_MM_HP_SDMMC_ALLOW_S)
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_S 5
/** TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW (BIT(6))
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S 6
/** TEE_REG_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_JPEG_ALLOW (BIT(7))
#define TEE_REG_LP_MM_HP_JPEG_ALLOW_M (TEE_REG_LP_MM_HP_JPEG_ALLOW_V << TEE_REG_LP_MM_HP_JPEG_ALLOW_S)
#define TEE_REG_LP_MM_HP_JPEG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_JPEG_ALLOW_S 7
/** TEE_REG_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PPA_ALLOW (BIT(8))
#define TEE_REG_LP_MM_HP_PPA_ALLOW_M (TEE_REG_LP_MM_HP_PPA_ALLOW_V << TEE_REG_LP_MM_HP_PPA_ALLOW_S)
#define TEE_REG_LP_MM_HP_PPA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PPA_ALLOW_S 8
/** TEE_REG_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW (BIT(9))
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_DMA2D_ALLOW_S)
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_S 9
/** TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW (BIT(10))
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S)
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S 10
/** TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW (BIT(11))
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S 11
/** TEE_REG_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_FLASH_ALLOW (BIT(12))
#define TEE_REG_LP_MM_HP_FLASH_ALLOW_M (TEE_REG_LP_MM_HP_FLASH_ALLOW_V << TEE_REG_LP_MM_HP_FLASH_ALLOW_S)
#define TEE_REG_LP_MM_HP_FLASH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_FLASH_ALLOW_S 12
/** TEE_REG_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW (BIT(13))
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_M (TEE_REG_LP_MM_HP_PSRAM_ALLOW_V << TEE_REG_LP_MM_HP_PSRAM_ALLOW_S)
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_S 13
/** TEE_REG_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW (BIT(14))
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_M (TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V << TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S)
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S 14
/** TEE_REG_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GMAC_ALLOW (BIT(15))
#define TEE_REG_LP_MM_HP_GMAC_ALLOW_M (TEE_REG_LP_MM_HP_GMAC_ALLOW_V << TEE_REG_LP_MM_HP_GMAC_ALLOW_S)
#define TEE_REG_LP_MM_HP_GMAC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GMAC_ALLOW_S 15
/** TEE_REG_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW (BIT(16))
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_M (TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V << TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S)
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S 16
/** TEE_REG_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PVT_ALLOW (BIT(17))
#define TEE_REG_LP_MM_HP_PVT_ALLOW_M (TEE_REG_LP_MM_HP_PVT_ALLOW_V << TEE_REG_LP_MM_HP_PVT_ALLOW_S)
#define TEE_REG_LP_MM_HP_PVT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PVT_ALLOW_S 17
/** TEE_REG_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW (BIT(18))
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S)
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S 18
/** TEE_REG_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW (BIT(19))
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S)
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S 19
/** TEE_REG_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_ISP_ALLOW (BIT(20))
#define TEE_REG_LP_MM_HP_ISP_ALLOW_M (TEE_REG_LP_MM_HP_ISP_ALLOW_V << TEE_REG_LP_MM_HP_ISP_ALLOW_S)
#define TEE_REG_LP_MM_HP_ISP_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_ISP_ALLOW_S 20
/** TEE_REG_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW (BIT(21))
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_M (TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V << TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S)
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S 21
/** TEE_REG_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_RMT_ALLOW (BIT(22))
#define TEE_REG_LP_MM_HP_RMT_ALLOW_M (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S)
#define TEE_REG_LP_MM_HP_RMT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_RMT_ALLOW_S 22
/** TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW (BIT(23))
#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S)
#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S 23
/** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW (BIT(24))
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_M (TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S)
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S 24
/** TEE_REG_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW (BIT(25))
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S)
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S 25
/** TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW (BIT(26))
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S)
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S 26
/** TEE_REG_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_DMA_PMS_ALLOW (BIT(27))
#define TEE_REG_LP_MM_DMA_PMS_ALLOW_M (TEE_REG_LP_MM_DMA_PMS_ALLOW_V << TEE_REG_LP_MM_DMA_PMS_ALLOW_S)
#define TEE_REG_LP_MM_DMA_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_DMA_PMS_ALLOW_S 27
/** TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW (BIT(28))
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S)
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S 28
/** TEE_LP_MM_PMS_REG2_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0xa4)
/** TEE_REG_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW (BIT(0))
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S)
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S 0
/** TEE_REG_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW (BIT(1))
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S)
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S 1
/** TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW (BIT(2))
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S)
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S 2
/** TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW (BIT(3))
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S)
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S 3
/** TEE_REG_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2C0_ALLOW (BIT(4))
#define TEE_REG_LP_MM_HP_I2C0_ALLOW_M (TEE_REG_LP_MM_HP_I2C0_ALLOW_V << TEE_REG_LP_MM_HP_I2C0_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2C0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2C0_ALLOW_S 4
/** TEE_REG_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2C1_ALLOW (BIT(5))
#define TEE_REG_LP_MM_HP_I2C1_ALLOW_M (TEE_REG_LP_MM_HP_I2C1_ALLOW_V << TEE_REG_LP_MM_HP_I2C1_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2C1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2C1_ALLOW_S 5
/** TEE_REG_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2S0_ALLOW (BIT(6))
#define TEE_REG_LP_MM_HP_I2S0_ALLOW_M (TEE_REG_LP_MM_HP_I2S0_ALLOW_V << TEE_REG_LP_MM_HP_I2S0_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2S0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2S0_ALLOW_S 6
/** TEE_REG_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2S1_ALLOW (BIT(7))
#define TEE_REG_LP_MM_HP_I2S1_ALLOW_M (TEE_REG_LP_MM_HP_I2S1_ALLOW_V << TEE_REG_LP_MM_HP_I2S1_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2S1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2S1_ALLOW_S 7
/** TEE_REG_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2S2_ALLOW (BIT(8))
#define TEE_REG_LP_MM_HP_I2S2_ALLOW_M (TEE_REG_LP_MM_HP_I2S2_ALLOW_V << TEE_REG_LP_MM_HP_I2S2_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2S2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2S2_ALLOW_S 8
/** TEE_REG_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PCNT_ALLOW (BIT(9))
#define TEE_REG_LP_MM_HP_PCNT_ALLOW_M (TEE_REG_LP_MM_HP_PCNT_ALLOW_V << TEE_REG_LP_MM_HP_PCNT_ALLOW_S)
#define TEE_REG_LP_MM_HP_PCNT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PCNT_ALLOW_S 9
/** TEE_REG_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART0_ALLOW (BIT(10))
#define TEE_REG_LP_MM_HP_UART0_ALLOW_M (TEE_REG_LP_MM_HP_UART0_ALLOW_V << TEE_REG_LP_MM_HP_UART0_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART0_ALLOW_S 10
/** TEE_REG_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART1_ALLOW (BIT(11))
#define TEE_REG_LP_MM_HP_UART1_ALLOW_M (TEE_REG_LP_MM_HP_UART1_ALLOW_V << TEE_REG_LP_MM_HP_UART1_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART1_ALLOW_S 11
/** TEE_REG_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART2_ALLOW (BIT(12))
#define TEE_REG_LP_MM_HP_UART2_ALLOW_M (TEE_REG_LP_MM_HP_UART2_ALLOW_V << TEE_REG_LP_MM_HP_UART2_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART2_ALLOW_S 12
/** TEE_REG_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART3_ALLOW (BIT(13))
#define TEE_REG_LP_MM_HP_UART3_ALLOW_M (TEE_REG_LP_MM_HP_UART3_ALLOW_V << TEE_REG_LP_MM_HP_UART3_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART3_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART3_ALLOW_S 13
/** TEE_REG_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART4_ALLOW (BIT(14))
#define TEE_REG_LP_MM_HP_UART4_ALLOW_M (TEE_REG_LP_MM_HP_UART4_ALLOW_V << TEE_REG_LP_MM_HP_UART4_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART4_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART4_ALLOW_S 14
/** TEE_REG_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW (BIT(15))
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_M (TEE_REG_LP_MM_HP_PARLIO_ALLOW_V << TEE_REG_LP_MM_HP_PARLIO_ALLOW_S)
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_S 15
/** TEE_REG_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW (BIT(16))
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S)
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S 16
/** TEE_REG_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW (BIT(17))
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S)
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S 17
/** TEE_REG_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW (BIT(18))
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_M (TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S 18
/** TEE_REG_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_LEDC_ALLOW (BIT(19))
#define TEE_REG_LP_MM_HP_LEDC_ALLOW_M (TEE_REG_LP_MM_HP_LEDC_ALLOW_V << TEE_REG_LP_MM_HP_LEDC_ALLOW_S)
#define TEE_REG_LP_MM_HP_LEDC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_LEDC_ALLOW_S 19
/** TEE_REG_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_ETM_ALLOW (BIT(21))
#define TEE_REG_LP_MM_HP_ETM_ALLOW_M (TEE_REG_LP_MM_HP_ETM_ALLOW_V << TEE_REG_LP_MM_HP_ETM_ALLOW_S)
#define TEE_REG_LP_MM_HP_ETM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_ETM_ALLOW_S 21
/** TEE_REG_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW (BIT(22))
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_M (TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V << TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S)
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S 22
/** TEE_REG_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW (BIT(23))
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_M (TEE_REG_LP_MM_HP_TWAI0_ALLOW_V << TEE_REG_LP_MM_HP_TWAI0_ALLOW_S)
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_S 23
/** TEE_REG_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW (BIT(24))
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_M (TEE_REG_LP_MM_HP_TWAI1_ALLOW_V << TEE_REG_LP_MM_HP_TWAI1_ALLOW_S)
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_S 24
/** TEE_REG_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW (BIT(25))
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_M (TEE_REG_LP_MM_HP_TWAI2_ALLOW_V << TEE_REG_LP_MM_HP_TWAI2_ALLOW_S)
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_S 25
/** TEE_REG_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW (BIT(26))
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_M (TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V << TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S)
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S 26
/** TEE_REG_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW (BIT(27))
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_M (TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S)
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S 27
/** TEE_REG_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW (BIT(28))
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_M (TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V << TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S)
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S 28
/** TEE_REG_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_ADC_ALLOW (BIT(30))
#define TEE_REG_LP_MM_HP_ADC_ALLOW_M (TEE_REG_LP_MM_HP_ADC_ALLOW_V << TEE_REG_LP_MM_HP_ADC_ALLOW_S)
#define TEE_REG_LP_MM_HP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_ADC_ALLOW_S 30
/** TEE_REG_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UHCI_ALLOW (BIT(31))
#define TEE_REG_LP_MM_HP_UHCI_ALLOW_M (TEE_REG_LP_MM_HP_UHCI_ALLOW_V << TEE_REG_LP_MM_HP_UHCI_ALLOW_S)
#define TEE_REG_LP_MM_HP_UHCI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UHCI_ALLOW_S 31
/** TEE_LP_MM_PMS_REG3_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x11c)
/** TEE_REG_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GPIO_ALLOW (BIT(0))
#define TEE_REG_LP_MM_HP_GPIO_ALLOW_M (TEE_REG_LP_MM_HP_GPIO_ALLOW_V << TEE_REG_LP_MM_HP_GPIO_ALLOW_S)
#define TEE_REG_LP_MM_HP_GPIO_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GPIO_ALLOW_S 0
/** TEE_REG_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW (BIT(1))
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_M (TEE_REG_LP_MM_HP_IOMUX_ALLOW_V << TEE_REG_LP_MM_HP_IOMUX_ALLOW_S)
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_S 1
/** TEE_REG_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW (BIT(2))
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_M (TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S)
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S 2
/** TEE_REG_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW (BIT(3))
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_M (TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V << TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S)
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S 3
/** TEE_REG_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW (BIT(4))
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_M (TEE_REG_LP_MM_HP_CLKRST_ALLOW_V << TEE_REG_LP_MM_HP_CLKRST_ALLOW_S)
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_S 4
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h Normal file
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@ -0,0 +1,409 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: TEE LP2HP PMS DATE REG */
/** Type of lp2hp_pms_date register
* NA
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294790;
* NA
*/
uint32_t tee_date:32;
};
uint32_t val;
} tee_lp2hp_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
/** Group: TEE LP MM PMS REG0 REG */
/** Type of lp_mm_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_lp_mm_psram_allow:1;
/** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_lp_mm_flash_allow:1;
/** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_lp_mm_l2mem_allow:1;
/** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_lp_mm_l2rom_allow:1;
uint32_t reserved_4:2;
/** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_lp_mm_trace0_allow:1;
/** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_lp_mm_trace1_allow:1;
/** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_lp_mm_cpu_bus_mon_allow:1;
/** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_lp_mm_l2mem_mon_allow:1;
/** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_lp_mm_tcm_mon_allow:1;
/** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_lp_mm_cache_allow:1;
uint32_t reserved_12:20;
};
uint32_t val;
} tee_lp_mm_pms_reg0_reg_t;
/** Group: TEE LP MM PMS REG1 REG */
/** Type of lp_mm_pms_reg1 register
* NA
*/
typedef union {
struct {
/** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_usbotg_allow:1;
/** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_usbotg11_allow:1;
/** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1;
/** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_gdma_allow:1;
/** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_regdma_allow:1;
/** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_sdmmc_allow:1;
/** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_ahb_pdma_allow:1;
/** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_jpeg_allow:1;
/** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_ppa_allow:1;
/** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_dma2d_allow:1;
/** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_key_manager_allow:1;
/** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_axi_pdma_allow:1;
/** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_flash_allow:1;
/** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_psram_allow:1;
/** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_crypto_allow:1;
/** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_gmac_allow:1;
/** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_usb_phy_allow:1;
/** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_pvt_allow:1;
/** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_csi_host_allow:1;
/** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_dsi_host_allow:1;
/** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_isp_allow:1;
/** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_h264_core_allow:1;
/** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_rmt_allow:1;
/** reg_lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_bitsrambler_allow:1;
/** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_axi_icm_allow:1;
/** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_peri_pms_allow:1;
/** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1;
/** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
* NA
*/
uint32_t reg_lp_mm_dma_pms_allow:1;
/** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_h264_dma2d_allow:1;
uint32_t reserved_29:3;
};
uint32_t val;
} tee_lp_mm_pms_reg1_reg_t;
/** Group: TEE LP MM PMS REG2 REG */
/** Type of lp_mm_pms_reg2 register
* NA
*/
typedef union {
struct {
/** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_mcpwm0_allow:1;
/** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_mcpwm1_allow:1;
/** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_timer_group0_allow:1;
/** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_timer_group1_allow:1;
/** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i2c0_allow:1;
/** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i2c1_allow:1;
/** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i2s0_allow:1;
/** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i2s1_allow:1;
/** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i2s2_allow:1;
/** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_pcnt_allow:1;
/** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_uart0_allow:1;
/** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_uart1_allow:1;
/** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_uart2_allow:1;
/** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_uart3_allow:1;
/** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_uart4_allow:1;
/** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_parlio_allow:1;
/** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_gpspi2_allow:1;
/** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_gpspi3_allow:1;
/** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_usbdevice_allow:1;
/** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_ledc_allow:1;
uint32_t reserved_20:1;
/** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_etm_allow:1;
/** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_intrmtx_allow:1;
/** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_twai0_allow:1;
/** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_twai1_allow:1;
/** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_twai2_allow:1;
/** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i3c_mst_allow:1;
/** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_i3c_slv_allow:1;
/** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_lcdcam_allow:1;
uint32_t reserved_29:1;
/** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_adc_allow:1;
/** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_uhci_allow:1;
};
uint32_t val;
} tee_lp_mm_pms_reg2_reg_t;
/** Group: TEE LP MM PMS REG3 REG */
/** Type of lp_mm_pms_reg3 register
* NA
*/
typedef union {
struct {
/** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_gpio_allow:1;
/** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_iomux_allow:1;
/** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_systimer_allow:1;
/** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_sys_reg_allow:1;
/** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp_clkrst_allow:1;
uint32_t reserved_5:27;
};
uint32_t val;
} tee_lp_mm_pms_reg3_reg_t;
typedef struct {
volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
uint32_t reserved_00c[9];
volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
uint32_t reserved_034[28];
volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
uint32_t reserved_0a8[29];
volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
} tee_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* need_des
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
* need_des
*/
uint32_t fast_clk_sel:2;
/** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
* need_des
*/
uint32_t lp_peri_div_num:6;
/** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t ana_sel_ref_pll8m:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_aonclkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* need_des
*/
typedef union {
struct {
/** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t clk_core_efuse_oen:1;
/** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t clk_lp_bus_oen:1;
/** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t clk_aon_slow_oen:1;
/** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
* need_des
*/
uint32_t clk_aon_fast_oen:1;
/** clk_slow_oen : R/W; bitpos: [4]; default: 0;
* need_des
*/
uint32_t clk_slow_oen:1;
/** clk_fast_oen : R/W; bitpos: [5]; default: 0;
* need_des
*/
uint32_t clk_fast_oen:1;
/** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t clk_fosc_oen:1;
/** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t clk_rc32k_oen:1;
/** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t clk_sxtal_oen:1;
/** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
* 1'b1: probe sosc clk on
* 1'b0: probe sosc clk off
*/
uint32_t clk_sosc_oen:1;
uint32_t reserved_10:22;
};
uint32_t val;
} lp_aonclkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lp_rtc_xtal_force_on:1;
/** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
* need_des
*/
uint32_t ck_en_lp_ram:1;
/** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t etm_event_tick_en:1;
/** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t pll8m_clk_force_on:1;
/** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t xtal_clk_force_on:1;
/** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t fosc_clk_force_on:1;
};
uint32_t val;
} lp_aonclkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
* need_des
*/
uint32_t rst_en_lp_huk:1;
/** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t rst_en_lp_anaperi:1;
/** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t rst_en_lp_wdt:1;
/** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t rst_en_lp_timer:1;
/** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t rst_en_lp_rtc:1;
/** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t rst_en_lp_mailbox:1;
/** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t rst_en_lp_aonefusereg:1;
/** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t rst_en_lp_ram:1;
};
uint32_t val;
} lp_aonclkrst_lp_rst_en_reg_t;
/** Type of reset_cause register
* need_des
*/
typedef union {
struct {
/** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
* 6'h1: POR reset
* 6'h9: PMU LP PERI power down reset
* 6'ha: PMU LP CPU reset
* 6'hf: brown out reset
* 6'h10: LP watchdog chip reset
* 6'h12: super watch dog reset
* 6'h13: glitch reset
* 6'h14: software reset
*/
uint32_t lpcore_reset_cause:6;
/** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t lpcore_reset_flag:1;
/** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
* 6'h1: POR reset
* 6'h3: digital system software reset
* 6'h5: PMU HP system power down reset
* 6'h7: HP system reset from HP watchdog
* 6'h9: HP system reset from LP watchdog
* 6'hb: HP core reset from HP watchdog
* 6'hc: HP core software reset
* 6'hd: HP core reset from LP watchdog
* 6'hf: brown out reset
* 6'h10: LP watchdog chip reset
* 6'h12: super watch dog reset
* 6'h13: glitch reset
* 6'h14: efuse crc error reset
* 6'h16: HP usb jtag chip reset
* 6'h17: HP usb uart chip reset
* 6'h18: HP jtag reset
* 6'h1a: HP core lockup
*/
uint32_t hpcore0_reset_cause:6;
/** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t hpcore0_reset_flag:1;
/** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
* 6'h1: POR reset
* 6'h3: digital system software reset
* 6'h5: PMU HP system power down reset
* 6'h7: HP system reset from HP watchdog
* 6'h9: HP system reset from LP watchdog
* 6'hb: HP core reset from HP watchdog
* 6'hc: HP core software reset
* 6'hd: HP core reset from LP watchdog
* 6'hf: brown out reset
* 6'h10: LP watchdog chip reset
* 6'h12: super watch dog reset
* 6'h13: glitch reset
* 6'h14: efuse crc error reset
* 6'h16: HP usb jtag chip reset
* 6'h17: HP usb uart chip reset
* 6'h18: HP jtag reset
* 6'h1a: HP core lockup
*/
uint32_t hpcore1_reset_cause:6;
/** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
* need_des
*/
uint32_t hpcore1_reset_flag:1;
uint32_t reserved_21:4;
/** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
* 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
* pmu_lp_cpu_reset reset_cause
*/
uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
/** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lpcore_reset_cause_clr:1;
/** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lpcore_reset_flag_clr:1;
/** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t hpcore0_reset_cause_clr:1;
/** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t hpcore0_reset_flag_clr:1;
/** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t hpcore1_reset_cause_clr:1;
/** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t hpcore1_reset_flag_clr:1;
};
uint32_t val;
} lp_aonclkrst_reset_cause_reg_t;
/** Type of hpcpu_reset_ctrl0 register
* need_des
*/
typedef union {
struct {
/** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
* write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
* reset feature
*/
uint32_t hpcore0_lockup_reset_en:1;
/** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
* need_des
*/
uint32_t lp_wdt_hpcore0_reset_length:3;
/** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
* write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
* hpcore0 feature
*/
uint32_t lp_wdt_hpcore0_reset_en:1;
/** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
* need_des
*/
uint32_t hpcore0_stall_wait:7;
/** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
* need_des
*/
uint32_t hpcore0_stall_en:1;
/** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
* need_des
*/
uint32_t hpcore0_sw_reset:1;
/** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
* need_des
*/
uint32_t hpcore0_ocd_halt_on_reset:1;
/** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
* 1'b1: boot from HP TCM ROM: 0x4FC00000
* 1'b0: boot from LP TCM RAM: 0x50108000
*/
uint32_t hpcore0_stat_vector_sel:1;
/** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
* write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
* reset feature
*/
uint32_t hpcore1_lockup_reset_en:1;
/** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
* need_des
*/
uint32_t lp_wdt_hpcore1_reset_length:3;
/** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
* write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
* hpcore1 feature
*/
uint32_t lp_wdt_hpcore1_reset_en:1;
/** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
* need_des
*/
uint32_t hpcore1_stall_wait:7;
/** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t hpcore1_stall_en:1;
/** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t hpcore1_sw_reset:1;
/** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t hpcore1_ocd_halt_on_reset:1;
/** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
* 1'b1: boot from HP TCM ROM: 0x4FC00000
* 1'b0: boot from LP TCM RAM: 0x50108000
*/
uint32_t hpcore1_stat_vector_sel:1;
};
uint32_t val;
} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t;
/** Type of hpcpu_reset_ctrl1 register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
* HP core0 software stall when set to 8'h86
*/
uint32_t hpcore0_sw_stall_code:8;
/** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
* HP core1 software stall when set to 8'h86
*/
uint32_t hpcore1_sw_stall_code:8;
};
uint32_t val;
} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t;
/** Type of fosc_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
* need_des
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_aonclkrst_fosc_cntl_reg_t;
/** Type of rc32k_cntl register
* need_des
*/
typedef union {
struct {
/** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
* need_des
*/
uint32_t rc32k_dfreq:32;
};
uint32_t val;
} lp_aonclkrst_rc32k_cntl_reg_t;
/** Type of sosc_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t sosc_dfreq:10;
};
uint32_t val;
} lp_aonclkrst_sosc_cntl_reg_t;
/** Type of clk_to_hp register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* reserved
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* reserved
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* reserved
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* reserved
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_aonclkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_aonclkrst_lpmem_force_reg_t;
/** Type of xtal32k register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_aonclkrst_xtal32k_reg_t;
/** Type of mux_hpsys_reset_bypass register
* need_des
*/
typedef union {
struct {
/** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t mux_hpsys_reset_bypass:32;
};
uint32_t val;
} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t;
/** Type of hpsys_0_reset_bypass register
* need_des
*/
typedef union {
struct {
/** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t hpsys_0_reset_bypass:32;
};
uint32_t val;
} lp_aonclkrst_hpsys_0_reset_bypass_reg_t;
/** Type of hpsys_apm_reset_bypass register
* need_des
*/
typedef union {
struct {
/** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t hpsys_apm_reset_bypass:32;
};
uint32_t val;
} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t;
/** Type of hp_clk_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
/** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
* HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
*/
uint32_t hp_root_clk_src_sel:2;
/** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
* HP SoC Root Clock Enable.
*/
uint32_t hp_root_clk_en:1;
/** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
* PARLIO TX Clock From Pad Enable.
*/
uint32_t hp_pad_parlio_tx_clk_en:1;
/** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
* PARLIO RX Clock From Pad Enable.
*/
uint32_t hp_pad_parlio_rx_clk_en:1;
/** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
* UART4 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart4_slp_clk_en:1;
/** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
* UART3 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart3_slp_clk_en:1;
/** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
* UART2 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart2_slp_clk_en:1;
/** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
* UART1 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart1_slp_clk_en:1;
/** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
* UART0 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart0_slp_clk_en:1;
/** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
* I2S2 MCLK Clock From Pad Enable.
*/
uint32_t hp_pad_i2s2_mclk_en:1;
/** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
* I2S1 MCLK Clock From Pad Enable.
*/
uint32_t hp_pad_i2s1_mclk_en:1;
/** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
* I2S0 MCLK Clock From Pad Enable.
*/
uint32_t hp_pad_i2s0_mclk_en:1;
/** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
* EMAC RX Clock From Pad Enable.
*/
uint32_t hp_pad_emac_tx_clk_en:1;
/** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
* EMAC TX Clock From Pad Enable.
*/
uint32_t hp_pad_emac_rx_clk_en:1;
/** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
* EMAC TXRX Clock From Pad Enable.
*/
uint32_t hp_pad_emac_txrx_clk_en:1;
/** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
* XTAL 32K Clock Enable.
*/
uint32_t hp_xtal_32k_clk_en:1;
/** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
* RC 32K Clock Enable.
*/
uint32_t hp_rc_32k_clk_en:1;
/** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
* SOSC 150K Clock Enable.
*/
uint32_t hp_sosc_150k_clk_en:1;
/** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
* PLL 8M Clock Enable.
*/
uint32_t hp_pll_8m_clk_en:1;
/** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
* AUDIO PLL Clock Enable.
*/
uint32_t hp_audio_pll_clk_en:1;
/** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
* SDIO PLL2 Clock Enable.
*/
uint32_t hp_sdio_pll2_clk_en:1;
/** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
* SDIO PLL1 Clock Enable.
*/
uint32_t hp_sdio_pll1_clk_en:1;
/** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
* SDIO PLL0 Clock Enable.
*/
uint32_t hp_sdio_pll0_clk_en:1;
/** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
* FOSC 20M Clock Enable.
*/
uint32_t hp_fosc_20m_clk_en:1;
/** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
* XTAL 40M Clock Enalbe.
*/
uint32_t hp_xtal_40m_clk_en:1;
/** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
* CPLL 400M Clock Enable.
*/
uint32_t hp_cpll_400m_clk_en:1;
/** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
* SPLL 480M Clock Enable.
*/
uint32_t hp_spll_480m_clk_en:1;
/** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
* MPLL 500M Clock Enable.
*/
uint32_t hp_mpll_500m_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} lp_aonclkrst_hp_clk_ctrl_reg_t;
/** Type of hp_usb_clkrst_ctrl0 register
* HP USB Clock Reset Control Register.
*/
typedef union {
struct {
/** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
* unused.
*/
uint32_t usb_otg20_sleep_mode:1;
/** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
* unused.
*/
uint32_t usb_otg20_bk_sys_clk_en:1;
/** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
* unused.
*/
uint32_t usb_otg11_sleep_mode:1;
/** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
* unused.
*/
uint32_t usb_otg11_bk_sys_clk_en:1;
/** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
* usb otg11 fs phy clock enable.
*/
uint32_t usb_otg11_48m_clk_en:1;
/** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
* usb device fs phy clock enable.
*/
uint32_t usb_device_48m_clk_en:1;
/** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
* usb 480m to 25m divide number.
*/
uint32_t usb_48m_div_num:8;
/** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
* usb 500m to 25m divide number.
*/
uint32_t usb_25m_div_num:8;
/** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
* usb 480m to 12m divide number.
*/
uint32_t usb_12m_div_num:8;
uint32_t reserved_30:2;
};
uint32_t val;
} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t;
/** Type of hp_usb_clkrst_ctrl1 register
* HP USB Clock Reset Control Register.
*/
typedef union {
struct {
/** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
* usb otg20 adp reset en
*/
uint32_t rst_en_usb_otg20_adp:1;
/** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
* usb otg20 phy reset en
*/
uint32_t rst_en_usb_otg20_phy:1;
/** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
* usb otg20 reset en
*/
uint32_t rst_en_usb_otg20:1;
/** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
* usb org11 reset en
*/
uint32_t rst_en_usb_otg11:1;
/** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
* usb device reset en
*/
uint32_t rst_en_usb_device:1;
uint32_t reserved_5:23;
/** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
* usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
*/
uint32_t usb_otg20_phyref_clk_src_sel:2;
/** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
* usb otg20 hs phy refclk enable.
*/
uint32_t usb_otg20_phyref_clk_en:1;
/** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
* usb otg20 ulpi clock enable.
*/
uint32_t usb_otg20_ulpi_clk_en:1;
};
uint32_t val;
} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t;
/** Type of hp_sdmmc_emac_rst_ctrl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
* hp sdmmc reset en
*/
uint32_t rst_en_sdmmc:1;
/** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
* hp sdmmc force norst
*/
uint32_t force_norst_sdmmc:1;
/** rst_en_emac : R/W; bitpos: [30]; default: 0;
* hp emac reset en
*/
uint32_t rst_en_emac:1;
/** force_norst_emac : R/W; bitpos: [31]; default: 0;
* hp emac force norst
*/
uint32_t force_norst_emac:1;
};
uint32_t val;
} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_aonclkrst_date_reg_t;
typedef struct {
volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_aonclkrst_reset_cause_reg_t reset_cause;
volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl;
volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force;
volatile lp_aonclkrst_xtal32k_reg_t xtal32k;
volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
uint32_t reserved_050[235];
volatile lp_aonclkrst_date_reg_t date;
} lp_aonclkrst_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: VAD registers */
/** Type of vad_conf register
* I2S VAD Configure register
*/
typedef union {
struct {
/** vad_en : R/W; bitpos: [0]; default: 0;
* VAD enable register
*/
uint32_t vad_en:1;
/** vad_reset : WT; bitpos: [1]; default: 0;
* VAD reset register
*/
uint32_t vad_reset:1;
/** vad_force_start : WT; bitpos: [2]; default: 0;
* VAD force start register.
*/
uint32_t vad_force_start:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_i2s_vad_conf_reg_t;
/** Type of vad_result register
* I2S VAD Result register
*/
typedef union {
struct {
/** vad_flag : RO; bitpos: [0]; default: 0;
* Reg vad flag observe signal
*/
uint32_t vad_flag:1;
/** energy_enough : RO; bitpos: [1]; default: 0;
* Reg energy enough observe signal
*/
uint32_t energy_enough:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_i2s_vad_result_reg_t;
/** Type of vad_param0 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_min_energy : R/W; bitpos: [15:0]; default: 5000;
* VAD parameter
*/
uint32_t param_min_energy:16;
/** param_init_frame_num : R/W; bitpos: [24:16]; default: 200;
* VAD parameter
*/
uint32_t param_init_frame_num:9;
uint32_t reserved_25:7;
};
uint32_t val;
} lp_i2s_vad_param0_reg_t;
/** Type of vad_param1 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_min_speech_count : R/W; bitpos: [3:0]; default: 3;
* VAD parameter
*/
uint32_t param_min_speech_count:4;
/** param_max_speech_count : R/W; bitpos: [10:4]; default: 100;
* VAD parameter
*/
uint32_t param_max_speech_count:7;
/** param_hangover_speech : R/W; bitpos: [15:11]; default: 3;
* VAD parameter
*/
uint32_t param_hangover_speech:5;
/** param_hangover_silent : R/W; bitpos: [23:16]; default: 30;
* VAD parameter
*/
uint32_t param_hangover_silent:8;
/** param_max_offset : R/W; bitpos: [30:24]; default: 40;
* VAD parameter
*/
uint32_t param_max_offset:7;
/** param_skip_band_energy : R/W; bitpos: [31]; default: 0;
* Set 1 to skip band energy check.
*/
uint32_t param_skip_band_energy:1;
};
uint32_t val;
} lp_i2s_vad_param1_reg_t;
/** Type of vad_param2 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_noise_amp_down : R/W; bitpos: [15:0]; default: 26214;
* VAD parameter
*/
uint32_t param_noise_amp_down:16;
/** param_noise_amp_up : R/W; bitpos: [31:16]; default: 32440;
* VAD parameter
*/
uint32_t param_noise_amp_up:16;
};
uint32_t val;
} lp_i2s_vad_param2_reg_t;
/** Type of vad_param3 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_noise_spe_up0 : R/W; bitpos: [15:0]; default: 32735;
* VAD parameter
*/
uint32_t param_noise_spe_up0:16;
/** param_noise_spe_up1 : R/W; bitpos: [31:16]; default: 32113;
* VAD parameter
*/
uint32_t param_noise_spe_up1:16;
};
uint32_t val;
} lp_i2s_vad_param3_reg_t;
/** Type of vad_param4 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_noise_spe_down : R/W; bitpos: [15:0]; default: 26214;
* VAD parameter
*/
uint32_t param_noise_spe_down:16;
/** param_noise_mean_down : R/W; bitpos: [31:16]; default: 31130;
* VAD parameter
*/
uint32_t param_noise_mean_down:16;
};
uint32_t val;
} lp_i2s_vad_param4_reg_t;
/** Type of vad_param5 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_noise_mean_up0 : R/W; bitpos: [15:0]; default: 32113;
* VAD parameter
*/
uint32_t param_noise_mean_up0:16;
/** param_noise_mean_up1 : R/W; bitpos: [31:16]; default: 31784;
* VAD parameter
*/
uint32_t param_noise_mean_up1:16;
};
uint32_t val;
} lp_i2s_vad_param5_reg_t;
/** Type of vad_param6 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_noise_std_fs_thsl : R/W; bitpos: [15:0]; default: 32000;
* Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to
* ((noise_std_max)>>11)^2*5
*/
uint32_t param_noise_std_fs_thsl:16;
/** param_noise_std_fs_thsh : R/W; bitpos: [31:16]; default: 46080;
* Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to
* ((noise_std_max)>>11)^2*5
*/
uint32_t param_noise_std_fs_thsh:16;
};
uint32_t val;
} lp_i2s_vad_param6_reg_t;
/** Type of vad_param7 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_thres_upd_base : R/W; bitpos: [15:0]; default: 32440;
* VAD parameter
*/
uint32_t param_thres_upd_base:16;
/** param_thres_upd_vary : R/W; bitpos: [31:16]; default: 328;
* VAD parameter
*/
uint32_t param_thres_upd_vary:16;
};
uint32_t val;
} lp_i2s_vad_param7_reg_t;
/** Type of vad_param8 register
* I2S VAD Parameter register
*/
typedef union {
struct {
/** param_thres_upd_bdl : R/W; bitpos: [7:0]; default: 64;
* Noise_std boundary low when updating threshold.
*/
uint32_t param_thres_upd_bdl:8;
/** param_thres_upd_bdh : R/W; bitpos: [15:8]; default: 80;
* Noise_std boundary high when updating threshold.
*/
uint32_t param_thres_upd_bdh:8;
/** param_feature_burst : R/W; bitpos: [31:16]; default: 8192;
* VAD parameter
*/
uint32_t param_feature_burst:16;
};
uint32_t val;
} lp_i2s_vad_param8_reg_t;
/** Type of vad_ob0 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** speech_count_ob : RO; bitpos: [7:0]; default: 0;
* Reg silent count observe
*/
uint32_t speech_count_ob:8;
/** silent_count_ob : RO; bitpos: [15:8]; default: 0;
* Reg speech count observe
*/
uint32_t silent_count_ob:8;
/** max_signal0_ob : RO; bitpos: [31:16]; default: 0;
* Reg max signal0 observe
*/
uint32_t max_signal0_ob:16;
};
uint32_t val;
} lp_i2s_vad_ob0_reg_t;
/** Type of vad_ob1 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** max_signal1_ob : RO; bitpos: [15:0]; default: 0;
* Reg max signal1 observe
*/
uint32_t max_signal1_ob:16;
/** max_signal2_ob : RO; bitpos: [31:16]; default: 0;
* Reg max signal2 observe
*/
uint32_t max_signal2_ob:16;
};
uint32_t val;
} lp_i2s_vad_ob1_reg_t;
/** Type of vad_ob2 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** noise_amp_ob : RO; bitpos: [31:0]; default: 0;
* Reg noise_amp observe signal
*/
uint32_t noise_amp_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob2_reg_t;
/** Type of vad_ob3 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** noise_mean_ob : RO; bitpos: [31:0]; default: 0;
* Reg noise_mean observe signal
*/
uint32_t noise_mean_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob3_reg_t;
/** Type of vad_ob4 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** noise_std_ob : RO; bitpos: [31:0]; default: 0;
* Reg noise_std observe signal
*/
uint32_t noise_std_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob4_reg_t;
/** Type of vad_ob5 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** offset_ob : RO; bitpos: [31:0]; default: 0;
* Reg offset observe signal
*/
uint32_t offset_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob5_reg_t;
/** Type of vad_ob6 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** threshold_ob : RO; bitpos: [31:0]; default: 0;
* Reg threshold observe signal
*/
uint32_t threshold_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob6_reg_t;
/** Type of vad_ob7 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** energy_low_ob : RO; bitpos: [31:0]; default: 0;
* Reg energy bit 31~0 observe signal
*/
uint32_t energy_low_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob7_reg_t;
/** Type of vad_ob8 register
* I2S VAD Observe register
*/
typedef union {
struct {
/** energy_high_ob : RO; bitpos: [31:0]; default: 0;
* Reg energy bit 63~32 observe signal
*/
uint32_t energy_high_ob:32;
};
uint32_t val;
} lp_i2s_vad_ob8_reg_t;
/** Group: RX Control and configuration registers */
/** Type of rx_mem_conf register
* I2S VAD Observe register
*/
typedef union {
struct {
/** rx_mem_fifo_cnt : RO; bitpos: [8:0]; default: 0;
* The number of data in the rx mem
*/
uint32_t rx_mem_fifo_cnt:9;
/** rx_mem_threshold : R/W; bitpos: [16:9]; default: 63;
* I2S rx mem will trigger an interrupt when the data in the mem is over(not including
* equal) reg_rx_mem_threshold
*/
uint32_t rx_mem_threshold:8;
uint32_t reserved_17:15;
};
uint32_t val;
} lp_i2s_rx_mem_conf_reg_t;
/** Type of rx_conf register
* I2S RX configure register
*/
typedef union {
struct {
/** rx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset receiver
*/
uint32_t rx_reset:1;
/** rx_fifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset Rx AFIFO
*/
uint32_t rx_fifo_reset:1;
/** rx_start : R/W; bitpos: [2]; default: 0;
* Set this bit to start receiving data
*/
uint32_t rx_start:1;
/** rx_slave_mod : R/W; bitpos: [3]; default: 0;
* Set this bit to enable slave receiver mode
*/
uint32_t rx_slave_mod:1;
/** rx_fifomem_reset : WT; bitpos: [4]; default: 0;
* Set this bit to reset Rx Syncfifomem
*/
uint32_t rx_fifomem_reset:1;
/** rx_mono : R/W; bitpos: [5]; default: 0;
* Set this bit to enable receiver in mono mode
*/
uint32_t rx_mono:1;
uint32_t reserved_6:1;
/** rx_big_endian : R/W; bitpos: [7]; default: 0;
* I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
*/
uint32_t rx_big_endian:1;
/** rx_update : R/W/SC; bitpos: [8]; default: 0;
* Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
* bit will be cleared by hardware after update register done.
*/
uint32_t rx_update:1;
/** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
* 1: The first channel data value is valid in I2S RX mono mode. 0: The second
* channel data value is valid in I2S RX mono mode.
*/
uint32_t rx_mono_fst_vld:1;
/** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
* I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
* (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
*/
uint32_t rx_pcm_conf:2;
/** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
* Set this bit to bypass Compress/Decompress module for received data.
*/
uint32_t rx_pcm_bypass:1;
/** rx_stop_mode : R/W; bitpos: [14:13]; default: 0;
* 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
* 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
*/
uint32_t rx_stop_mode:2;
/** rx_left_align : R/W; bitpos: [15]; default: 1;
* 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
*/
uint32_t rx_left_align:1;
/** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
* 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
*/
uint32_t rx_24_fill_en:1;
/** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
* 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
* 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
*/
uint32_t rx_ws_idle_pol:1;
/** rx_bit_order : R/W; bitpos: [18]; default: 0;
* I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
* is received first.
*/
uint32_t rx_bit_order:1;
/** rx_tdm_en : R/W; bitpos: [19]; default: 0;
* 1: Enable I2S TDM Rx mode . 0: Disable.
*/
uint32_t rx_tdm_en:1;
/** rx_pdm_en : R/W; bitpos: [20]; default: 0;
* 1: Enable I2S PDM Rx mode . 0: Disable.
*/
uint32_t rx_pdm_en:1;
uint32_t reserved_21:11;
};
uint32_t val;
} lp_i2s_rx_conf_reg_t;
/** Type of rx_conf1 register
* I2S RX configure register 1
*/
typedef union {
struct {
/** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
*/
uint32_t rx_tdm_ws_width:7;
/** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
* Bit clock configuration bits in receiver mode.
*/
uint32_t rx_bck_div_num:6;
/** rx_bits_mod : R/W; bitpos: [17:13]; default: 15;
* Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
* the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
* 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
* channel data is in 32-bit-mode.
*/
uint32_t rx_bits_mod:5;
/** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
* I2S Rx half sample bits -1.
*/
uint32_t rx_half_sample_bits:6;
/** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
* The Rx bit number for each channel minus 1in TDM mode.
*/
uint32_t rx_tdm_chan_bits:5;
/** rx_msb_shift : R/W; bitpos: [29]; default: 1;
* Set this bit to enable receiver in Phillips standard mode
*/
uint32_t rx_msb_shift:1;
uint32_t reserved_30:2;
};
uint32_t val;
} lp_i2s_rx_conf1_reg_t;
/** Type of rx_tdm_ctrl register
* I2S TX TDM mode control register
*/
typedef union {
struct {
/** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
* 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
* input 0 in this channel.
*/
uint32_t rx_tdm_pdm_chan0_en:1;
/** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
* 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
* input 0 in this channel.
*/
uint32_t rx_tdm_pdm_chan1_en:1;
uint32_t reserved_2:14;
/** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
* The total channel number of I2S TX TDM mode.
*/
uint32_t rx_tdm_tot_chan_num:4;
uint32_t reserved_20:12;
};
uint32_t val;
} lp_i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
* I2S RX data number control register.
*/
typedef union {
struct {
/** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
* The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
* 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
*/
uint32_t rx_eof_num:12;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2s_rxeof_num_reg_t;
/** Type of rx_pdm_conf register
* I2S RX configure register
*/
typedef union {
struct {
uint32_t reserved_0:19;
/** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
* 1: Enable PDM2PCM RX mode. 0: DIsable.
*/
uint32_t rx_pdm2pcm_en:1;
/** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
* sampling rate is 128. 0: down sampling rate is 64.
*/
uint32_t rx_pdm_sinc_dsr_16_en:1;
/** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
* Configure PDM RX amplify number.
*/
uint32_t rx_pdm2pcm_amplify_num:4;
/** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
* I2S PDM RX bypass hp filter or not.
*/
uint32_t rx_pdm_hp_bypass:1;
/** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
*/
uint32_t rx_iir_hp_mult12_5:3;
/** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
*/
uint32_t rx_iir_hp_mult12_0:3;
};
uint32_t val;
} lp_i2s_rx_pdm_conf_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* I2S interrupt raw register, valid in level.
*/
typedef union {
struct {
/** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the i2s_rx_done_int interrupt
*/
uint32_t rx_done_int_raw:1;
/** rx_hung_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the i2s_rx_hung_int interrupt
*/
uint32_t rx_hung_int_raw:1;
/** rx_fifomem_udf_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt
*/
uint32_t rx_fifomem_udf_int_raw:1;
/** vad_done_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the vad_done_int interrupt
*/
uint32_t vad_done_int_raw:1;
/** vad_reset_done_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt status bit for the vad_reset_done_int interrupt
*/
uint32_t vad_reset_done_int_raw:1;
/** rx_mem_threshold_int_raw : RO/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt status bit for the rx_mem_threshold_int interrupt
*/
uint32_t rx_mem_threshold_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_i2s_int_raw_reg_t;
/** Type of int_st register
* I2S interrupt status register.
*/
typedef union {
struct {
/** rx_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the i2s_rx_done_int interrupt
*/
uint32_t rx_done_int_st:1;
/** rx_hung_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the i2s_rx_hung_int interrupt
*/
uint32_t rx_hung_int_st:1;
/** rx_fifomem_udf_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt
*/
uint32_t rx_fifomem_udf_int_st:1;
/** vad_done_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the vad_done_int interrupt
*/
uint32_t vad_done_int_st:1;
/** vad_reset_done_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status bit for the vad_reset_done_int interrupt
*/
uint32_t vad_reset_done_int_st:1;
/** rx_mem_threshold_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status bit for the rx_mem_threshold_int interrupt
*/
uint32_t rx_mem_threshold_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_i2s_int_st_reg_t;
/** Type of int_ena register
* I2S interrupt enable register.
*/
typedef union {
struct {
/** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the i2s_rx_done_int interrupt
*/
uint32_t rx_done_int_ena:1;
/** rx_hung_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the i2s_rx_hung_int interrupt
*/
uint32_t rx_hung_int_ena:1;
/** rx_fifomem_udf_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt
*/
uint32_t rx_fifomem_udf_int_ena:1;
/** vad_done_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the vad_done_int interrupt
*/
uint32_t vad_done_int_ena:1;
/** vad_reset_done_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the vad_reset_done_int interrupt
*/
uint32_t vad_reset_done_int_ena:1;
/** rx_mem_threshold_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the rx_mem_threshold_int interrupt
*/
uint32_t rx_mem_threshold_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_i2s_int_ena_reg_t;
/** Type of int_clr register
* I2S interrupt clear register.
*/
typedef union {
struct {
/** rx_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the i2s_rx_done_int interrupt
*/
uint32_t rx_done_int_clr:1;
/** rx_hung_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the i2s_rx_hung_int interrupt
*/
uint32_t rx_hung_int_clr:1;
/** rx_fifomem_udf_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the i2s_rx_fifomem_udf_int interrupt
*/
uint32_t rx_fifomem_udf_int_clr:1;
/** vad_done_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the vad_done_int interrupt
*/
uint32_t vad_done_int_clr:1;
/** vad_reset_done_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the vad_reset_done_int interrupt
*/
uint32_t vad_reset_done_int_clr:1;
/** rx_mem_threshold_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the rx_mem_threshold_int interrupt
*/
uint32_t rx_mem_threshold_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_i2s_int_clr_reg_t;
/** Group: RX clock and timing registers */
/** Type of rx_timing register
* I2S RX timing control register
*/
typedef union {
struct {
/** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
* The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
*/
uint32_t rx_sd_in_dm:2;
uint32_t reserved_2:14;
/** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
* The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
*/
uint32_t rx_ws_out_dm:2;
uint32_t reserved_18:2;
/** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
* The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
*/
uint32_t rx_bck_out_dm:2;
uint32_t reserved_22:2;
/** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
* The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
*/
uint32_t rx_ws_in_dm:2;
uint32_t reserved_26:2;
/** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
* The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
*/
uint32_t rx_bck_in_dm:2;
uint32_t reserved_30:2;
};
uint32_t val;
} lp_i2s_rx_timing_reg_t;
/** Group: Control and configuration registers */
/** Type of lc_hung_conf register
* I2S HUNG configure register.
*/
typedef union {
struct {
/** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
* the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
* when fifo hung counter is equal to this value
*/
uint32_t lc_fifo_timeout:8;
/** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
* The bits are used to scale tick counter threshold. The tick counter is reset when
* counter value >= 88000/2^i2s_lc_fifo_timeout_shift
*/
uint32_t lc_fifo_timeout_shift:3;
/** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
* The enable bit for FIFO timeout
*/
uint32_t lc_fifo_timeout_ena:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
* I2S signal data register
*/
typedef union {
struct {
/** single_data : R/W; bitpos: [31:0]; default: 0;
* The configured constant channel data to be sent out.
*/
uint32_t single_data:32;
};
uint32_t val;
} lp_i2s_conf_sigle_data_reg_t;
/** Group: ECO registers */
/** Type of eco_low register
* I2S ECO register
*/
typedef union {
struct {
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
* logic low eco registers
*/
uint32_t rdn_eco_low:32;
};
uint32_t val;
} lp_i2s_eco_low_reg_t;
/** Type of eco_high register
* I2S ECO register
*/
typedef union {
struct {
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* logic high eco registers
*/
uint32_t rdn_eco_high:32;
};
uint32_t val;
} lp_i2s_eco_high_reg_t;
/** Type of eco_conf register
* I2S ECO register
*/
typedef union {
struct {
/** rdn_ena : R/W; bitpos: [0]; default: 0;
* enable rdn counter bit
*/
uint32_t rdn_ena:1;
/** rdn_result : RO; bitpos: [1]; default: 0;
* rdn result
*/
uint32_t rdn_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_i2s_eco_conf_reg_t;
/** Group: Clock registers */
/** Type of clk_gate register
* Clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* set this bit to enable clock gate
*/
uint32_t clk_en:1;
/** vad_cg_force_on : R/W; bitpos: [1]; default: 1;
* VAD clock gate force on register
*/
uint32_t vad_cg_force_on:1;
/** rx_mem_cg_force_on : R/W; bitpos: [2]; default: 0;
* I2S rx mem clock gate force on register
*/
uint32_t rx_mem_cg_force_on:1;
/** rx_reg_cg_force_on : R/W; bitpos: [3]; default: 1;
* I2S rx reg clock gate force on register
*/
uint32_t rx_reg_cg_force_on:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_i2s_clk_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* I2S version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_i2s_date_reg_t;
typedef struct {
volatile lp_i2s_vad_conf_reg_t vad_conf;
volatile lp_i2s_vad_result_reg_t vad_result;
volatile lp_i2s_rx_mem_conf_reg_t rx_mem_conf;
volatile lp_i2s_int_raw_reg_t int_raw;
volatile lp_i2s_int_st_reg_t int_st;
volatile lp_i2s_int_ena_reg_t int_ena;
volatile lp_i2s_int_clr_reg_t int_clr;
uint32_t reserved_01c;
volatile lp_i2s_rx_conf_reg_t rx_conf;
uint32_t reserved_024;
volatile lp_i2s_rx_conf1_reg_t rx_conf1;
uint32_t reserved_02c[9];
volatile lp_i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
uint32_t reserved_054;
volatile lp_i2s_rx_timing_reg_t rx_timing;
uint32_t reserved_05c;
volatile lp_i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile lp_i2s_rxeof_num_reg_t rxeof_num;
volatile lp_i2s_conf_sigle_data_reg_t conf_sigle_data;
uint32_t reserved_06c;
volatile lp_i2s_rx_pdm_conf_reg_t rx_pdm_conf;
volatile lp_i2s_eco_low_reg_t eco_low;
volatile lp_i2s_eco_high_reg_t eco_high;
volatile lp_i2s_eco_conf_reg_t eco_conf;
volatile lp_i2s_vad_param0_reg_t vad_param0;
volatile lp_i2s_vad_param1_reg_t vad_param1;
volatile lp_i2s_vad_param2_reg_t vad_param2;
volatile lp_i2s_vad_param3_reg_t vad_param3;
volatile lp_i2s_vad_param4_reg_t vad_param4;
volatile lp_i2s_vad_param5_reg_t vad_param5;
volatile lp_i2s_vad_param6_reg_t vad_param6;
volatile lp_i2s_vad_param7_reg_t vad_param7;
volatile lp_i2s_vad_param8_reg_t vad_param8;
uint32_t reserved_0a4[3];
volatile lp_i2s_vad_ob0_reg_t vad_ob0;
volatile lp_i2s_vad_ob1_reg_t vad_ob1;
volatile lp_i2s_vad_ob2_reg_t vad_ob2;
volatile lp_i2s_vad_ob3_reg_t vad_ob3;
volatile lp_i2s_vad_ob4_reg_t vad_ob4;
volatile lp_i2s_vad_ob5_reg_t vad_ob5;
volatile lp_i2s_vad_ob6_reg_t vad_ob6;
volatile lp_i2s_vad_ob7_reg_t vad_ob7;
volatile lp_i2s_vad_ob8_reg_t vad_ob8;
uint32_t reserved_0d4[9];
volatile lp_i2s_clk_gate_reg_t clk_gate;
volatile lp_i2s_date_reg_t date;
} lp_i2s_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2s_dev_t) == 0x100, "Invalid size of lp_i2s_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPINTR_SW_INT_RAW_REG register
* need_des
*/
#define LPINTR_SW_INT_RAW_REG (DR_REG_LPINTR_BASE + 0x0)
/** LPINTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0;
* need_des
*/
#define LPINTR_LP_SW_INT_RAW (BIT(31))
#define LPINTR_LP_SW_INT_RAW_M (LPINTR_LP_SW_INT_RAW_V << LPINTR_LP_SW_INT_RAW_S)
#define LPINTR_LP_SW_INT_RAW_V 0x00000001U
#define LPINTR_LP_SW_INT_RAW_S 31
/** LPINTR_SW_INT_ST_REG register
* need_des
*/
#define LPINTR_SW_INT_ST_REG (DR_REG_LPINTR_BASE + 0x4)
/** LPINTR_LP_SW_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LPINTR_LP_SW_INT_ST (BIT(31))
#define LPINTR_LP_SW_INT_ST_M (LPINTR_LP_SW_INT_ST_V << LPINTR_LP_SW_INT_ST_S)
#define LPINTR_LP_SW_INT_ST_V 0x00000001U
#define LPINTR_LP_SW_INT_ST_S 31
/** LPINTR_SW_INT_ENA_REG register
* need_des
*/
#define LPINTR_SW_INT_ENA_REG (DR_REG_LPINTR_BASE + 0x8)
/** LPINTR_LP_SW_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPINTR_LP_SW_INT_ENA (BIT(31))
#define LPINTR_LP_SW_INT_ENA_M (LPINTR_LP_SW_INT_ENA_V << LPINTR_LP_SW_INT_ENA_S)
#define LPINTR_LP_SW_INT_ENA_V 0x00000001U
#define LPINTR_LP_SW_INT_ENA_S 31
/** LPINTR_SW_INT_CLR_REG register
* need_des
*/
#define LPINTR_SW_INT_CLR_REG (DR_REG_LPINTR_BASE + 0xc)
/** LPINTR_LP_SW_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LPINTR_LP_SW_INT_CLR (BIT(31))
#define LPINTR_LP_SW_INT_CLR_M (LPINTR_LP_SW_INT_CLR_V << LPINTR_LP_SW_INT_CLR_S)
#define LPINTR_LP_SW_INT_CLR_V 0x00000001U
#define LPINTR_LP_SW_INT_CLR_S 31
/** LPINTR_STATUS_REG register
* need_des
*/
#define LPINTR_STATUS_REG (DR_REG_LPINTR_BASE + 0x10)
/** LPINTR_LP_HUK_INTR_ST : RO; bitpos: [10]; default: 0;
* need_des
*/
#define LPINTR_LP_HUK_INTR_ST (BIT(10))
#define LPINTR_LP_HUK_INTR_ST_M (LPINTR_LP_HUK_INTR_ST_V << LPINTR_LP_HUK_INTR_ST_S)
#define LPINTR_LP_HUK_INTR_ST_V 0x00000001U
#define LPINTR_LP_HUK_INTR_ST_S 10
/** LPINTR_SYSREG_INTR_ST : RO; bitpos: [11]; default: 0;
* need_des
*/
#define LPINTR_SYSREG_INTR_ST (BIT(11))
#define LPINTR_SYSREG_INTR_ST_M (LPINTR_SYSREG_INTR_ST_V << LPINTR_SYSREG_INTR_ST_S)
#define LPINTR_SYSREG_INTR_ST_V 0x00000001U
#define LPINTR_SYSREG_INTR_ST_S 11
/** LPINTR_LP_SW_INTR_ST : RO; bitpos: [12]; default: 0;
* need_des
*/
#define LPINTR_LP_SW_INTR_ST (BIT(12))
#define LPINTR_LP_SW_INTR_ST_M (LPINTR_LP_SW_INTR_ST_V << LPINTR_LP_SW_INTR_ST_S)
#define LPINTR_LP_SW_INTR_ST_V 0x00000001U
#define LPINTR_LP_SW_INTR_ST_S 12
/** LPINTR_LP_EFUSE_INTR_ST : RO; bitpos: [13]; default: 0;
* need_des
*/
#define LPINTR_LP_EFUSE_INTR_ST (BIT(13))
#define LPINTR_LP_EFUSE_INTR_ST_M (LPINTR_LP_EFUSE_INTR_ST_V << LPINTR_LP_EFUSE_INTR_ST_S)
#define LPINTR_LP_EFUSE_INTR_ST_V 0x00000001U
#define LPINTR_LP_EFUSE_INTR_ST_S 13
/** LPINTR_LP_UART_INTR_ST : RO; bitpos: [14]; default: 0;
* need_des
*/
#define LPINTR_LP_UART_INTR_ST (BIT(14))
#define LPINTR_LP_UART_INTR_ST_M (LPINTR_LP_UART_INTR_ST_V << LPINTR_LP_UART_INTR_ST_S)
#define LPINTR_LP_UART_INTR_ST_V 0x00000001U
#define LPINTR_LP_UART_INTR_ST_S 14
/** LPINTR_LP_TSENS_INTR_ST : RO; bitpos: [15]; default: 0;
* need_des
*/
#define LPINTR_LP_TSENS_INTR_ST (BIT(15))
#define LPINTR_LP_TSENS_INTR_ST_M (LPINTR_LP_TSENS_INTR_ST_V << LPINTR_LP_TSENS_INTR_ST_S)
#define LPINTR_LP_TSENS_INTR_ST_V 0x00000001U
#define LPINTR_LP_TSENS_INTR_ST_S 15
/** LPINTR_LP_TOUCH_INTR_ST : RO; bitpos: [16]; default: 0;
* need_des
*/
#define LPINTR_LP_TOUCH_INTR_ST (BIT(16))
#define LPINTR_LP_TOUCH_INTR_ST_M (LPINTR_LP_TOUCH_INTR_ST_V << LPINTR_LP_TOUCH_INTR_ST_S)
#define LPINTR_LP_TOUCH_INTR_ST_V 0x00000001U
#define LPINTR_LP_TOUCH_INTR_ST_S 16
/** LPINTR_LP_SPI_INTR_ST : RO; bitpos: [17]; default: 0;
* need_des
*/
#define LPINTR_LP_SPI_INTR_ST (BIT(17))
#define LPINTR_LP_SPI_INTR_ST_M (LPINTR_LP_SPI_INTR_ST_V << LPINTR_LP_SPI_INTR_ST_S)
#define LPINTR_LP_SPI_INTR_ST_V 0x00000001U
#define LPINTR_LP_SPI_INTR_ST_S 17
/** LPINTR_LP_I2S_INTR_ST : RO; bitpos: [18]; default: 0;
* need_des
*/
#define LPINTR_LP_I2S_INTR_ST (BIT(18))
#define LPINTR_LP_I2S_INTR_ST_M (LPINTR_LP_I2S_INTR_ST_V << LPINTR_LP_I2S_INTR_ST_S)
#define LPINTR_LP_I2S_INTR_ST_V 0x00000001U
#define LPINTR_LP_I2S_INTR_ST_S 18
/** LPINTR_LP_I2C_INTR_ST : RO; bitpos: [19]; default: 0;
* need_des
*/
#define LPINTR_LP_I2C_INTR_ST (BIT(19))
#define LPINTR_LP_I2C_INTR_ST_M (LPINTR_LP_I2C_INTR_ST_V << LPINTR_LP_I2C_INTR_ST_S)
#define LPINTR_LP_I2C_INTR_ST_V 0x00000001U
#define LPINTR_LP_I2C_INTR_ST_S 19
/** LPINTR_LP_GPIO_INTR_ST : RO; bitpos: [20]; default: 0;
* need_des
*/
#define LPINTR_LP_GPIO_INTR_ST (BIT(20))
#define LPINTR_LP_GPIO_INTR_ST_M (LPINTR_LP_GPIO_INTR_ST_V << LPINTR_LP_GPIO_INTR_ST_S)
#define LPINTR_LP_GPIO_INTR_ST_V 0x00000001U
#define LPINTR_LP_GPIO_INTR_ST_S 20
/** LPINTR_LP_ADC_INTR_ST : RO; bitpos: [21]; default: 0;
* need_des
*/
#define LPINTR_LP_ADC_INTR_ST (BIT(21))
#define LPINTR_LP_ADC_INTR_ST_M (LPINTR_LP_ADC_INTR_ST_V << LPINTR_LP_ADC_INTR_ST_S)
#define LPINTR_LP_ADC_INTR_ST_V 0x00000001U
#define LPINTR_LP_ADC_INTR_ST_S 21
/** LPINTR_ANAPERI_INTR_ST : RO; bitpos: [22]; default: 0;
* need_des
*/
#define LPINTR_ANAPERI_INTR_ST (BIT(22))
#define LPINTR_ANAPERI_INTR_ST_M (LPINTR_ANAPERI_INTR_ST_V << LPINTR_ANAPERI_INTR_ST_S)
#define LPINTR_ANAPERI_INTR_ST_V 0x00000001U
#define LPINTR_ANAPERI_INTR_ST_S 22
/** LPINTR_PMU_REG_1_INTR_ST : RO; bitpos: [23]; default: 0;
* need_des
*/
#define LPINTR_PMU_REG_1_INTR_ST (BIT(23))
#define LPINTR_PMU_REG_1_INTR_ST_M (LPINTR_PMU_REG_1_INTR_ST_V << LPINTR_PMU_REG_1_INTR_ST_S)
#define LPINTR_PMU_REG_1_INTR_ST_V 0x00000001U
#define LPINTR_PMU_REG_1_INTR_ST_S 23
/** LPINTR_PMU_REG_0_INTR_ST : RO; bitpos: [24]; default: 0;
* need_des
*/
#define LPINTR_PMU_REG_0_INTR_ST (BIT(24))
#define LPINTR_PMU_REG_0_INTR_ST_M (LPINTR_PMU_REG_0_INTR_ST_V << LPINTR_PMU_REG_0_INTR_ST_S)
#define LPINTR_PMU_REG_0_INTR_ST_V 0x00000001U
#define LPINTR_PMU_REG_0_INTR_ST_S 24
/** LPINTR_MB_LP_INTR_ST : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LPINTR_MB_LP_INTR_ST (BIT(25))
#define LPINTR_MB_LP_INTR_ST_M (LPINTR_MB_LP_INTR_ST_V << LPINTR_MB_LP_INTR_ST_S)
#define LPINTR_MB_LP_INTR_ST_V 0x00000001U
#define LPINTR_MB_LP_INTR_ST_S 25
/** LPINTR_MB_HP_INTR_ST : RO; bitpos: [26]; default: 0;
* need_des
*/
#define LPINTR_MB_HP_INTR_ST (BIT(26))
#define LPINTR_MB_HP_INTR_ST_M (LPINTR_MB_HP_INTR_ST_V << LPINTR_MB_HP_INTR_ST_S)
#define LPINTR_MB_HP_INTR_ST_V 0x00000001U
#define LPINTR_MB_HP_INTR_ST_S 26
/** LPINTR_LP_TIMER_REG_1_INTR_ST : RO; bitpos: [27]; default: 0;
* need_des
*/
#define LPINTR_LP_TIMER_REG_1_INTR_ST (BIT(27))
#define LPINTR_LP_TIMER_REG_1_INTR_ST_M (LPINTR_LP_TIMER_REG_1_INTR_ST_V << LPINTR_LP_TIMER_REG_1_INTR_ST_S)
#define LPINTR_LP_TIMER_REG_1_INTR_ST_V 0x00000001U
#define LPINTR_LP_TIMER_REG_1_INTR_ST_S 27
/** LPINTR_LP_TIMER_REG_0_INTR_ST : RO; bitpos: [28]; default: 0;
* need_des
*/
#define LPINTR_LP_TIMER_REG_0_INTR_ST (BIT(28))
#define LPINTR_LP_TIMER_REG_0_INTR_ST_M (LPINTR_LP_TIMER_REG_0_INTR_ST_V << LPINTR_LP_TIMER_REG_0_INTR_ST_S)
#define LPINTR_LP_TIMER_REG_0_INTR_ST_V 0x00000001U
#define LPINTR_LP_TIMER_REG_0_INTR_ST_S 28
/** LPINTR_LP_WDT_INTR_ST : RO; bitpos: [29]; default: 0;
* need_des
*/
#define LPINTR_LP_WDT_INTR_ST (BIT(29))
#define LPINTR_LP_WDT_INTR_ST_M (LPINTR_LP_WDT_INTR_ST_V << LPINTR_LP_WDT_INTR_ST_S)
#define LPINTR_LP_WDT_INTR_ST_V 0x00000001U
#define LPINTR_LP_WDT_INTR_ST_S 29
/** LPINTR_LP_RTC_INTR_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LPINTR_LP_RTC_INTR_ST (BIT(30))
#define LPINTR_LP_RTC_INTR_ST_M (LPINTR_LP_RTC_INTR_ST_V << LPINTR_LP_RTC_INTR_ST_S)
#define LPINTR_LP_RTC_INTR_ST_V 0x00000001U
#define LPINTR_LP_RTC_INTR_ST_S 30
/** LPINTR_HP_INTR_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LPINTR_HP_INTR_ST (BIT(31))
#define LPINTR_HP_INTR_ST_M (LPINTR_HP_INTR_ST_V << LPINTR_HP_INTR_ST_S)
#define LPINTR_HP_INTR_ST_V 0x00000001U
#define LPINTR_HP_INTR_ST_S 31
/** LPINTR_DATE_REG register
* need_des
*/
#define LPINTR_DATE_REG (DR_REG_LPINTR_BASE + 0x3fc)
/** LPINTR_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPINTR_CLK_EN (BIT(31))
#define LPINTR_CLK_EN_M (LPINTR_CLK_EN_V << LPINTR_CLK_EN_S)
#define LPINTR_CLK_EN_V 0x00000001U
#define LPINTR_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of sw_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lp_sw_int_raw : R/W/WTC; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_sw_int_raw:1;
};
uint32_t val;
} lpintr_sw_int_raw_reg_t;
/** Type of sw_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lp_sw_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_sw_int_st:1;
};
uint32_t val;
} lpintr_sw_int_st_reg_t;
/** Type of sw_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lp_sw_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_sw_int_ena:1;
};
uint32_t val;
} lpintr_sw_int_ena_reg_t;
/** Type of sw_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lp_sw_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_sw_int_clr:1;
};
uint32_t val;
} lpintr_sw_int_clr_reg_t;
/** Group: Status Registers */
/** Type of status register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** lp_huk_intr_st : RO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t lp_huk_intr_st:1;
/** sysreg_intr_st : RO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t sysreg_intr_st:1;
/** lp_sw_intr_st : RO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t lp_sw_intr_st:1;
/** lp_efuse_intr_st : RO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t lp_efuse_intr_st:1;
/** lp_uart_intr_st : RO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t lp_uart_intr_st:1;
/** lp_tsens_intr_st : RO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t lp_tsens_intr_st:1;
/** lp_touch_intr_st : RO; bitpos: [16]; default: 0;
* need_des
*/
uint32_t lp_touch_intr_st:1;
/** lp_spi_intr_st : RO; bitpos: [17]; default: 0;
* need_des
*/
uint32_t lp_spi_intr_st:1;
/** lp_i2s_intr_st : RO; bitpos: [18]; default: 0;
* need_des
*/
uint32_t lp_i2s_intr_st:1;
/** lp_i2c_intr_st : RO; bitpos: [19]; default: 0;
* need_des
*/
uint32_t lp_i2c_intr_st:1;
/** lp_gpio_intr_st : RO; bitpos: [20]; default: 0;
* need_des
*/
uint32_t lp_gpio_intr_st:1;
/** lp_adc_intr_st : RO; bitpos: [21]; default: 0;
* need_des
*/
uint32_t lp_adc_intr_st:1;
/** anaperi_intr_st : RO; bitpos: [22]; default: 0;
* need_des
*/
uint32_t anaperi_intr_st:1;
/** pmu_reg_1_intr_st : RO; bitpos: [23]; default: 0;
* need_des
*/
uint32_t pmu_reg_1_intr_st:1;
/** pmu_reg_0_intr_st : RO; bitpos: [24]; default: 0;
* need_des
*/
uint32_t pmu_reg_0_intr_st:1;
/** mb_lp_intr_st : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t mb_lp_intr_st:1;
/** mb_hp_intr_st : RO; bitpos: [26]; default: 0;
* need_des
*/
uint32_t mb_hp_intr_st:1;
/** lp_timer_reg_1_intr_st : RO; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lp_timer_reg_1_intr_st:1;
/** lp_timer_reg_0_intr_st : RO; bitpos: [28]; default: 0;
* need_des
*/
uint32_t lp_timer_reg_0_intr_st:1;
/** lp_wdt_intr_st : RO; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_wdt_intr_st:1;
/** lp_rtc_intr_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_rtc_intr_st:1;
/** hp_intr_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t hp_intr_st:1;
};
uint32_t val;
} lpintr_status_reg_t;
/** Group: configure_register */
/** Type of date register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpintr_date_reg_t;
typedef struct {
volatile lpintr_sw_int_raw_reg_t sw_int_raw;
volatile lpintr_sw_int_st_reg_t sw_int_st;
volatile lpintr_sw_int_ena_reg_t sw_int_ena;
volatile lpintr_sw_int_clr_reg_t sw_int_clr;
volatile lpintr_status_reg_t status;
uint32_t reserved_014[250];
volatile lpintr_date_reg_t date;
} lpintr_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lpintr_dev_t) == 0x400, "Invalid size of lpintr_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en register
* Reserved
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* Reserved
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_iomux_clk_en_reg_t;
/** Group: ver_date */
/** Type of ver_date register
* Reserved
*/
typedef union {
struct {
/** reg_ver_date : R/W; bitpos: [27:0]; default: 2294547;
* Reserved
*/
uint32_t reg_ver_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_iomux_ver_date_reg_t;
/** Group: pad0 */
/** Type of pad0 register
* Reserved
*/
typedef union {
struct {
/** reg_pad0_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad0_drv:2;
/** reg_pad0_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad0_rde:1;
/** reg_pad0_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad0_rue:1;
/** reg_pad0_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad0_mux_sel:1;
/** reg_pad0_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad0_fun_sel:2;
/** reg_pad0_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad0_slp_sel:1;
/** reg_pad0_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad0_slp_ie:1;
/** reg_pad0_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad0_slp_oe:1;
/** reg_pad0_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad0_fun_ie:1;
/** reg_pad0_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad0_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad0_reg_t;
/** Group: pad1 */
/** Type of pad1 register
* Reserved
*/
typedef union {
struct {
/** reg_pad1_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad1_drv:2;
/** reg_pad1_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad1_rde:1;
/** reg_pad1_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad1_rue:1;
/** reg_pad1_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad1_mux_sel:1;
/** reg_pad1_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad1_fun_sel:2;
/** reg_pad1_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad1_slp_sel:1;
/** reg_pad1_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad1_slp_ie:1;
/** reg_pad1_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad1_slp_oe:1;
/** reg_pad1_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad1_fun_ie:1;
/** reg_pad1_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad1_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad1_reg_t;
/** Group: pad2 */
/** Type of pad2 register
* Reserved
*/
typedef union {
struct {
/** reg_pad2_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad2_drv:2;
/** reg_pad2_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad2_rde:1;
/** reg_pad2_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad2_rue:1;
/** reg_pad2_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad2_mux_sel:1;
/** reg_pad2_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad2_fun_sel:2;
/** reg_pad2_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad2_slp_sel:1;
/** reg_pad2_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad2_slp_ie:1;
/** reg_pad2_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad2_slp_oe:1;
/** reg_pad2_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad2_fun_ie:1;
/** reg_pad2_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad2_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad2_reg_t;
/** Group: pad3 */
/** Type of pad3 register
* Reserved
*/
typedef union {
struct {
/** reg_pad3_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad3_drv:2;
/** reg_pad3_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad3_rde:1;
/** reg_pad3_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad3_rue:1;
/** reg_pad3_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad3_mux_sel:1;
/** reg_pad3_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad3_fun_sel:2;
/** reg_pad3_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad3_slp_sel:1;
/** reg_pad3_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad3_slp_ie:1;
/** reg_pad3_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad3_slp_oe:1;
/** reg_pad3_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad3_fun_ie:1;
/** reg_pad3_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad3_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad3_reg_t;
/** Group: pad4 */
/** Type of pad4 register
* Reserved
*/
typedef union {
struct {
/** reg_pad4_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad4_drv:2;
/** reg_pad4_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad4_rde:1;
/** reg_pad4_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad4_rue:1;
/** reg_pad4_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad4_mux_sel:1;
/** reg_pad4_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad4_fun_sel:2;
/** reg_pad4_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad4_slp_sel:1;
/** reg_pad4_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad4_slp_ie:1;
/** reg_pad4_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad4_slp_oe:1;
/** reg_pad4_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad4_fun_ie:1;
/** reg_pad4_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad4_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad4_reg_t;
/** Group: pad5 */
/** Type of pad5 register
* Reserved
*/
typedef union {
struct {
/** reg_pad5_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad5_drv:2;
/** reg_pad5_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad5_rde:1;
/** reg_pad5_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad5_rue:1;
/** reg_pad5_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad5_mux_sel:1;
/** reg_pad5_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad5_fun_sel:2;
/** reg_pad5_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad5_slp_sel:1;
/** reg_pad5_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad5_slp_ie:1;
/** reg_pad5_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad5_slp_oe:1;
/** reg_pad5_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad5_fun_ie:1;
/** reg_pad5_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad5_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad5_reg_t;
/** Group: pad6 */
/** Type of pad6 register
* Reserved
*/
typedef union {
struct {
/** reg_pad6_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad6_drv:2;
/** reg_pad6_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad6_rde:1;
/** reg_pad6_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad6_rue:1;
/** reg_pad6_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad6_mux_sel:1;
/** reg_pad6_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad6_fun_sel:2;
/** reg_pad6_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad6_slp_sel:1;
/** reg_pad6_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad6_slp_ie:1;
/** reg_pad6_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad6_slp_oe:1;
/** reg_pad6_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad6_fun_ie:1;
/** reg_pad6_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad6_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad6_reg_t;
/** Group: pad7 */
/** Type of pad7 register
* Reserved
*/
typedef union {
struct {
/** reg_pad7_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad7_drv:2;
/** reg_pad7_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad7_rde:1;
/** reg_pad7_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad7_rue:1;
/** reg_pad7_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad7_mux_sel:1;
/** reg_pad7_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad7_fun_sel:2;
/** reg_pad7_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad7_slp_sel:1;
/** reg_pad7_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad7_slp_ie:1;
/** reg_pad7_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad7_slp_oe:1;
/** reg_pad7_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad7_fun_ie:1;
/** reg_pad7_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad7_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad7_reg_t;
/** Group: pad8 */
/** Type of pad8 register
* Reserved
*/
typedef union {
struct {
/** reg_pad8_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad8_drv:2;
/** reg_pad8_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad8_rde:1;
/** reg_pad8_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad8_rue:1;
/** reg_pad8_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad8_mux_sel:1;
/** reg_pad8_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad8_fun_sel:2;
/** reg_pad8_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad8_slp_sel:1;
/** reg_pad8_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad8_slp_ie:1;
/** reg_pad8_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad8_slp_oe:1;
/** reg_pad8_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad8_fun_ie:1;
/** reg_pad8_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad8_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad8_reg_t;
/** Group: pad9 */
/** Type of pad9 register
* Reserved
*/
typedef union {
struct {
/** reg_pad9_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad9_drv:2;
/** reg_pad9_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad9_rde:1;
/** reg_pad9_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad9_rue:1;
/** reg_pad9_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad9_mux_sel:1;
/** reg_pad9_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad9_fun_sel:2;
/** reg_pad9_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad9_slp_sel:1;
/** reg_pad9_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad9_slp_ie:1;
/** reg_pad9_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad9_slp_oe:1;
/** reg_pad9_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad9_fun_ie:1;
/** reg_pad9_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad9_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad9_reg_t;
/** Group: pad10 */
/** Type of pad10 register
* Reserved
*/
typedef union {
struct {
/** reg_pad10_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad10_drv:2;
/** reg_pad10_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad10_rde:1;
/** reg_pad10_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad10_rue:1;
/** reg_pad10_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad10_mux_sel:1;
/** reg_pad10_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad10_fun_sel:2;
/** reg_pad10_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad10_slp_sel:1;
/** reg_pad10_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad10_slp_ie:1;
/** reg_pad10_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad10_slp_oe:1;
/** reg_pad10_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad10_fun_ie:1;
/** reg_pad10_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad10_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad10_reg_t;
/** Group: pad11 */
/** Type of pad11 register
* Reserved
*/
typedef union {
struct {
/** reg_pad11_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad11_drv:2;
/** reg_pad11_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad11_rde:1;
/** reg_pad11_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad11_rue:1;
/** reg_pad11_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad11_mux_sel:1;
/** reg_pad11_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad11_fun_sel:2;
/** reg_pad11_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad11_slp_sel:1;
/** reg_pad11_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad11_slp_ie:1;
/** reg_pad11_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad11_slp_oe:1;
/** reg_pad11_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad11_fun_ie:1;
/** reg_pad11_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad11_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad11_reg_t;
/** Group: pad12 */
/** Type of pad120 register
* Reserved
*/
typedef union {
struct {
/** reg_pad12_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad12_drv:2;
/** reg_pad12_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad12_rde:1;
/** reg_pad12_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad12_rue:1;
/** reg_pad12_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad12_mux_sel:1;
/** reg_pad12_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad12_fun_sel:2;
/** reg_pad12_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad12_slp_sel:1;
/** reg_pad12_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad12_slp_ie:1;
/** reg_pad12_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad12_slp_oe:1;
/** reg_pad12_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad12_fun_ie:1;
/** reg_pad12_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad12_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad120_reg_t;
/** Group: pad13 */
/** Type of pad13 register
* Reserved
*/
typedef union {
struct {
/** reg_pad13_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad13_drv:2;
/** reg_pad13_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad13_rde:1;
/** reg_pad13_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad13_rue:1;
/** reg_pad13_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad13_mux_sel:1;
/** reg_pad13_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad13_fun_sel:2;
/** reg_pad13_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad13_slp_sel:1;
/** reg_pad13_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad13_slp_ie:1;
/** reg_pad13_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad13_slp_oe:1;
/** reg_pad13_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad13_fun_ie:1;
/** reg_pad13_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad13_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad13_reg_t;
/** Group: pad14 */
/** Type of pad14 register
* Reserved
*/
typedef union {
struct {
/** reg_pad14_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad14_drv:2;
/** reg_pad14_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad14_rde:1;
/** reg_pad14_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad14_rue:1;
/** reg_pad14_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad14_mux_sel:1;
/** reg_pad14_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad14_fun_sel:2;
/** reg_pad14_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad14_slp_sel:1;
/** reg_pad14_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad14_slp_ie:1;
/** reg_pad14_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad14_slp_oe:1;
/** reg_pad14_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad14_fun_ie:1;
/** reg_pad14_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad14_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad14_reg_t;
/** Group: pad15 */
/** Type of pad15 register
* Reserved
*/
typedef union {
struct {
/** reg_pad15_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad15_drv:2;
/** reg_pad15_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad15_rde:1;
/** reg_pad15_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad15_rue:1;
/** reg_pad15_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad15_mux_sel:1;
/** reg_pad15_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad15_fun_sel:2;
/** reg_pad15_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad15_slp_sel:1;
/** reg_pad15_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad15_slp_ie:1;
/** reg_pad15_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad15_slp_oe:1;
/** reg_pad15_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad15_fun_ie:1;
/** reg_pad15_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad15_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad15_reg_t;
/** Group: ext_wakeup0_sel */
/** Type of ext_wakeup0_sel register
* Reserved
*/
typedef union {
struct {
/** reg_xtl_ext_ctr_sel : R/W; bitpos: [4:0]; default: 0;
* select LP GPIO 0 ~ 15 to control XTAL
*/
uint32_t reg_xtl_ext_ctr_sel:5;
/** reg_ext_wakeup0_sel : R/W; bitpos: [9:5]; default: 0;
* Reserved
*/
uint32_t reg_ext_wakeup0_sel:5;
uint32_t reserved_10:22;
};
uint32_t val;
} lp_iomux_ext_wakeup0_sel_reg_t;
/** Group: lp_pad_hold */
/** Type of lp_pad_hold register
* Reserved
*/
typedef union {
struct {
/** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
* Reserved
*/
uint32_t reg_lp_gpio_hold:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_iomux_lp_pad_hold_reg_t;
/** Group: lp_pad_hys */
/** Type of lp_pad_hys register
* Reserved
*/
typedef union {
struct {
/** reg_lp_gpio_hys : R/W; bitpos: [15:0]; default: 0;
* Reserved
*/
uint32_t reg_lp_gpio_hys:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_iomux_lp_pad_hys_reg_t;
typedef struct {
volatile lp_iomux_clk_en_reg_t clk_en;
volatile lp_iomux_ver_date_reg_t ver_date;
volatile lp_iomux_pad0_reg_t pad0;
volatile lp_iomux_pad1_reg_t pad1;
volatile lp_iomux_pad2_reg_t pad2;
volatile lp_iomux_pad3_reg_t pad3;
volatile lp_iomux_pad4_reg_t pad4;
volatile lp_iomux_pad5_reg_t pad5;
volatile lp_iomux_pad6_reg_t pad6;
volatile lp_iomux_pad7_reg_t pad7;
volatile lp_iomux_pad8_reg_t pad8;
volatile lp_iomux_pad9_reg_t pad9;
volatile lp_iomux_pad10_reg_t pad10;
volatile lp_iomux_pad11_reg_t pad11;
volatile lp_iomux_pad120_reg_t pad120;
volatile lp_iomux_pad13_reg_t pad13;
volatile lp_iomux_pad14_reg_t pad14;
volatile lp_iomux_pad15_reg_t pad15;
volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
} lp_iomux_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_iomux_dev_t) == 0x54, "Invalid size of lp_iomux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of massege_0 register
* need_des
*/
typedef union {
struct {
/** massege_0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_0:32;
};
uint32_t val;
} mb_massege_0_reg_t;
/** Type of massege_1 register
* need_des
*/
typedef union {
struct {
/** massege_1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_1:32;
};
uint32_t val;
} mb_massege_1_reg_t;
/** Type of massege_2 register
* need_des
*/
typedef union {
struct {
/** massege_2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_2:32;
};
uint32_t val;
} mb_massege_2_reg_t;
/** Type of massege_3 register
* need_des
*/
typedef union {
struct {
/** massege_3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_3:32;
};
uint32_t val;
} mb_massege_3_reg_t;
/** Type of massege_4 register
* need_des
*/
typedef union {
struct {
/** massege_4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_4:32;
};
uint32_t val;
} mb_massege_4_reg_t;
/** Type of massege_5 register
* need_des
*/
typedef union {
struct {
/** massege_5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_5:32;
};
uint32_t val;
} mb_massege_5_reg_t;
/** Type of massege_6 register
* need_des
*/
typedef union {
struct {
/** massege_6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_6:32;
};
uint32_t val;
} mb_massege_6_reg_t;
/** Type of massege_7 register
* need_des
*/
typedef union {
struct {
/** massege_7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_7:32;
};
uint32_t val;
} mb_massege_7_reg_t;
/** Type of massege_8 register
* need_des
*/
typedef union {
struct {
/** massege_8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_8:32;
};
uint32_t val;
} mb_massege_8_reg_t;
/** Type of massege_9 register
* need_des
*/
typedef union {
struct {
/** massege_9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_9:32;
};
uint32_t val;
} mb_massege_9_reg_t;
/** Type of massege_10 register
* need_des
*/
typedef union {
struct {
/** massege_10 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_10:32;
};
uint32_t val;
} mb_massege_10_reg_t;
/** Type of massege_11 register
* need_des
*/
typedef union {
struct {
/** massege_11 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_11:32;
};
uint32_t val;
} mb_massege_11_reg_t;
/** Type of massege_12 register
* need_des
*/
typedef union {
struct {
/** massege_12 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_12:32;
};
uint32_t val;
} mb_massege_12_reg_t;
/** Type of massege_13 register
* need_des
*/
typedef union {
struct {
/** massege_13 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_13:32;
};
uint32_t val;
} mb_massege_13_reg_t;
/** Type of massege_14 register
* need_des
*/
typedef union {
struct {
/** massege_14 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_14:32;
};
uint32_t val;
} mb_massege_14_reg_t;
/** Type of massege_15 register
* need_des
*/
typedef union {
struct {
/** massege_15 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t massege_15:32;
};
uint32_t val;
} mb_massege_15_reg_t;
/** Type of reg_clk_en register
* need_des
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mb_reg_clk_en_reg_t;
/** Group: Interrupt Registers */
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
/** lp_0_int_raw : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lp_0_int_raw:1;
/** lp_1_int_raw : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lp_1_int_raw:1;
/** lp_2_int_raw : RO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t lp_2_int_raw:1;
/** lp_3_int_raw : RO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t lp_3_int_raw:1;
/** lp_4_int_raw : RO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t lp_4_int_raw:1;
/** lp_5_int_raw : RO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t lp_5_int_raw:1;
/** lp_6_int_raw : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t lp_6_int_raw:1;
/** lp_7_int_raw : RO; bitpos: [7]; default: 0;
* need_des
*/
uint32_t lp_7_int_raw:1;
/** lp_8_int_raw : RO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t lp_8_int_raw:1;
/** lp_9_int_raw : RO; bitpos: [9]; default: 0;
* need_des
*/
uint32_t lp_9_int_raw:1;
/** lp_10_int_raw : RO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t lp_10_int_raw:1;
/** lp_11_int_raw : RO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t lp_11_int_raw:1;
/** lp_12_int_raw : RO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t lp_12_int_raw:1;
/** lp_13_int_raw : RO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t lp_13_int_raw:1;
/** lp_14_int_raw : RO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t lp_14_int_raw:1;
/** lp_15_int_raw : RO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t lp_15_int_raw:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
/** lp_0_int_st : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lp_0_int_st:1;
/** lp_1_int_st : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lp_1_int_st:1;
/** lp_2_int_st : RO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t lp_2_int_st:1;
/** lp_3_int_st : RO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t lp_3_int_st:1;
/** lp_4_int_st : RO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t lp_4_int_st:1;
/** lp_5_int_st : RO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t lp_5_int_st:1;
/** lp_6_int_st : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t lp_6_int_st:1;
/** lp_7_int_st : RO; bitpos: [7]; default: 0;
* need_des
*/
uint32_t lp_7_int_st:1;
/** lp_8_int_st : RO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t lp_8_int_st:1;
/** lp_9_int_st : RO; bitpos: [9]; default: 0;
* need_des
*/
uint32_t lp_9_int_st:1;
/** lp_10_int_st : RO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t lp_10_int_st:1;
/** lp_11_int_st : RO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t lp_11_int_st:1;
/** lp_12_int_st : RO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t lp_12_int_st:1;
/** lp_13_int_st : RO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t lp_13_int_st:1;
/** lp_14_int_st : RO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t lp_14_int_st:1;
/** lp_15_int_st : RO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t lp_15_int_st:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
/** lp_0_int_ena : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t lp_0_int_ena:1;
/** lp_1_int_ena : R/W; bitpos: [1]; default: 1;
* need_des
*/
uint32_t lp_1_int_ena:1;
/** lp_2_int_ena : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t lp_2_int_ena:1;
/** lp_3_int_ena : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t lp_3_int_ena:1;
/** lp_4_int_ena : R/W; bitpos: [4]; default: 1;
* need_des
*/
uint32_t lp_4_int_ena:1;
/** lp_5_int_ena : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t lp_5_int_ena:1;
/** lp_6_int_ena : R/W; bitpos: [6]; default: 1;
* need_des
*/
uint32_t lp_6_int_ena:1;
/** lp_7_int_ena : R/W; bitpos: [7]; default: 1;
* need_des
*/
uint32_t lp_7_int_ena:1;
/** lp_8_int_ena : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t lp_8_int_ena:1;
/** lp_9_int_ena : R/W; bitpos: [9]; default: 0;
* need_des
*/
uint32_t lp_9_int_ena:1;
/** lp_10_int_ena : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t lp_10_int_ena:1;
/** lp_11_int_ena : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t lp_11_int_ena:1;
/** lp_12_int_ena : R/W; bitpos: [12]; default: 0;
* need_des
*/
uint32_t lp_12_int_ena:1;
/** lp_13_int_ena : R/W; bitpos: [13]; default: 0;
* need_des
*/
uint32_t lp_13_int_ena:1;
/** lp_14_int_ena : R/W; bitpos: [14]; default: 0;
* need_des
*/
uint32_t lp_14_int_ena:1;
/** lp_15_int_ena : R/W; bitpos: [15]; default: 0;
* need_des
*/
uint32_t lp_15_int_ena:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
/** lp_0_int_clr : WO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lp_0_int_clr:1;
/** lp_1_int_clr : WO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lp_1_int_clr:1;
/** lp_2_int_clr : WO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t lp_2_int_clr:1;
/** lp_3_int_clr : WO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t lp_3_int_clr:1;
/** lp_4_int_clr : WO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t lp_4_int_clr:1;
/** lp_5_int_clr : WO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t lp_5_int_clr:1;
/** lp_6_int_clr : WO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t lp_6_int_clr:1;
/** lp_7_int_clr : WO; bitpos: [7]; default: 0;
* need_des
*/
uint32_t lp_7_int_clr:1;
/** lp_8_int_clr : WO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t lp_8_int_clr:1;
/** lp_9_int_clr : WO; bitpos: [9]; default: 0;
* need_des
*/
uint32_t lp_9_int_clr:1;
/** lp_10_int_clr : WO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t lp_10_int_clr:1;
/** lp_11_int_clr : WO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t lp_11_int_clr:1;
/** lp_12_int_clr : WO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t lp_12_int_clr:1;
/** lp_13_int_clr : WO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t lp_13_int_clr:1;
/** lp_14_int_clr : WO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t lp_14_int_clr:1;
/** lp_15_int_clr : WO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t lp_15_int_clr:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_lp_int_clr_reg_t;
/** Type of hp_int_raw register
* need_des
*/
typedef union {
struct {
/** hp_0_int_raw : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t hp_0_int_raw:1;
/** hp_1_int_raw : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t hp_1_int_raw:1;
/** hp_2_int_raw : RO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t hp_2_int_raw:1;
/** hp_3_int_raw : RO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t hp_3_int_raw:1;
/** hp_4_int_raw : RO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t hp_4_int_raw:1;
/** hp_5_int_raw : RO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t hp_5_int_raw:1;
/** hp_6_int_raw : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t hp_6_int_raw:1;
/** hp_7_int_raw : RO; bitpos: [7]; default: 0;
* need_des
*/
uint32_t hp_7_int_raw:1;
/** hp_8_int_raw : RO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t hp_8_int_raw:1;
/** hp_9_int_raw : RO; bitpos: [9]; default: 0;
* need_des
*/
uint32_t hp_9_int_raw:1;
/** hp_10_int_raw : RO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t hp_10_int_raw:1;
/** hp_11_int_raw : RO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t hp_11_int_raw:1;
/** hp_12_int_raw : RO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t hp_12_int_raw:1;
/** hp_13_int_raw : RO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t hp_13_int_raw:1;
/** hp_14_int_raw : RO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t hp_14_int_raw:1;
/** hp_15_int_raw : RO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t hp_15_int_raw:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_hp_int_raw_reg_t;
/** Type of hp_int_st register
* need_des
*/
typedef union {
struct {
/** hp_0_int_st : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t hp_0_int_st:1;
/** hp_1_int_st : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t hp_1_int_st:1;
/** hp_2_int_st : RO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t hp_2_int_st:1;
/** hp_3_int_st : RO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t hp_3_int_st:1;
/** hp_4_int_st : RO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t hp_4_int_st:1;
/** hp_5_int_st : RO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t hp_5_int_st:1;
/** hp_6_int_st : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t hp_6_int_st:1;
/** hp_7_int_st : RO; bitpos: [7]; default: 0;
* need_des
*/
uint32_t hp_7_int_st:1;
/** hp_8_int_st : RO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t hp_8_int_st:1;
/** hp_9_int_st : RO; bitpos: [9]; default: 0;
* need_des
*/
uint32_t hp_9_int_st:1;
/** hp_10_int_st : RO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t hp_10_int_st:1;
/** hp_11_int_st : RO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t hp_11_int_st:1;
/** hp_12_int_st : RO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t hp_12_int_st:1;
/** hp_13_int_st : RO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t hp_13_int_st:1;
/** hp_14_int_st : RO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t hp_14_int_st:1;
/** hp_15_int_st : RO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t hp_15_int_st:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_hp_int_st_reg_t;
/** Type of hp_int_ena register
* need_des
*/
typedef union {
struct {
/** hp_0_int_ena : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t hp_0_int_ena:1;
/** hp_1_int_ena : R/W; bitpos: [1]; default: 1;
* need_des
*/
uint32_t hp_1_int_ena:1;
/** hp_2_int_ena : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t hp_2_int_ena:1;
/** hp_3_int_ena : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t hp_3_int_ena:1;
/** hp_4_int_ena : R/W; bitpos: [4]; default: 1;
* need_des
*/
uint32_t hp_4_int_ena:1;
/** hp_5_int_ena : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t hp_5_int_ena:1;
/** hp_6_int_ena : R/W; bitpos: [6]; default: 1;
* need_des
*/
uint32_t hp_6_int_ena:1;
/** hp_7_int_ena : R/W; bitpos: [7]; default: 1;
* need_des
*/
uint32_t hp_7_int_ena:1;
/** hp_8_int_ena : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t hp_8_int_ena:1;
/** hp_9_int_ena : R/W; bitpos: [9]; default: 0;
* need_des
*/
uint32_t hp_9_int_ena:1;
/** hp_10_int_ena : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t hp_10_int_ena:1;
/** hp_11_int_ena : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t hp_11_int_ena:1;
/** hp_12_int_ena : R/W; bitpos: [12]; default: 0;
* need_des
*/
uint32_t hp_12_int_ena:1;
/** hp_13_int_ena : R/W; bitpos: [13]; default: 0;
* need_des
*/
uint32_t hp_13_int_ena:1;
/** hp_14_int_ena : R/W; bitpos: [14]; default: 0;
* need_des
*/
uint32_t hp_14_int_ena:1;
/** hp_15_int_ena : R/W; bitpos: [15]; default: 0;
* need_des
*/
uint32_t hp_15_int_ena:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_hp_int_ena_reg_t;
/** Type of hp_int_clr register
* need_des
*/
typedef union {
struct {
/** hp_0_int_clr : WO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t hp_0_int_clr:1;
/** hp_1_int_clr : WO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t hp_1_int_clr:1;
/** hp_2_int_clr : WO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t hp_2_int_clr:1;
/** hp_3_int_clr : WO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t hp_3_int_clr:1;
/** hp_4_int_clr : WO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t hp_4_int_clr:1;
/** hp_5_int_clr : WO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t hp_5_int_clr:1;
/** hp_6_int_clr : WO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t hp_6_int_clr:1;
/** hp_7_int_clr : WO; bitpos: [7]; default: 0;
* need_des
*/
uint32_t hp_7_int_clr:1;
/** hp_8_int_clr : WO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t hp_8_int_clr:1;
/** hp_9_int_clr : WO; bitpos: [9]; default: 0;
* need_des
*/
uint32_t hp_9_int_clr:1;
/** hp_10_int_clr : WO; bitpos: [10]; default: 0;
* need_des
*/
uint32_t hp_10_int_clr:1;
/** hp_11_int_clr : WO; bitpos: [11]; default: 0;
* need_des
*/
uint32_t hp_11_int_clr:1;
/** hp_12_int_clr : WO; bitpos: [12]; default: 0;
* need_des
*/
uint32_t hp_12_int_clr:1;
/** hp_13_int_clr : WO; bitpos: [13]; default: 0;
* need_des
*/
uint32_t hp_13_int_clr:1;
/** hp_14_int_clr : WO; bitpos: [14]; default: 0;
* need_des
*/
uint32_t hp_14_int_clr:1;
/** hp_15_int_clr : WO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t hp_15_int_clr:1;
uint32_t reserved_16:16;
};
uint32_t val;
} mb_hp_int_clr_reg_t;
typedef struct {
volatile mb_massege_0_reg_t massege_0;
volatile mb_massege_1_reg_t massege_1;
volatile mb_massege_2_reg_t massege_2;
volatile mb_massege_3_reg_t massege_3;
volatile mb_massege_4_reg_t massege_4;
volatile mb_massege_5_reg_t massege_5;
volatile mb_massege_6_reg_t massege_6;
volatile mb_massege_7_reg_t massege_7;
volatile mb_massege_8_reg_t massege_8;
volatile mb_massege_9_reg_t massege_9;
volatile mb_massege_10_reg_t massege_10;
volatile mb_massege_11_reg_t massege_11;
volatile mb_massege_12_reg_t massege_12;
volatile mb_massege_13_reg_t massege_13;
volatile mb_massege_14_reg_t massege_14;
volatile mb_massege_15_reg_t massege_15;
volatile mb_lp_int_raw_reg_t lp_int_raw;
volatile mb_lp_int_st_reg_t lp_int_st;
volatile mb_lp_int_ena_reg_t lp_int_ena;
volatile mb_lp_int_clr_reg_t lp_int_clr;
volatile mb_hp_int_raw_reg_t hp_int_raw;
volatile mb_hp_int_st_reg_t hp_int_st;
volatile mb_hp_int_ena_reg_t hp_int_ena;
volatile mb_hp_int_clr_reg_t hp_int_clr;
volatile mb_reg_clk_en_reg_t reg_clk_en;
} mb_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(mb_dev_t) == 0x64, "Invalid size of mb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

301
components/soc/esp32p4/include/soc/lp_peri_pms_reg.h Normal file
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@ -0,0 +1,301 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_PMS_DATE_REG register
* NA
*/
#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2294537;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_LP_MM_PMS_REG0_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_LP_MM_LP_PMU_ALLOW_M (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S)
#define TEE_REG_LP_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_LP_MM_LP_WDT_ALLOW_M (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S)
#define TEE_REG_LP_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_LP_MM_LP_RTC_ALLOW_M (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S)
#define TEE_REG_LP_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_LP_MM_LP_UART_ALLOW_M (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S)
#define TEE_REG_LP_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_UART_ALLOW_S 9
/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_LP_MM_LP_I2C_ALLOW_M (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_LP_MM_LP_SPI_ALLOW_M (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S)
#define TEE_REG_LP_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_LP_MM_LP_I2S_ALLOW_M (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_LP_MM_LP_ADC_ALLOW_M (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S)
#define TEE_REG_LP_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_LP_MM_LP_INTR_ALLOW_M (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S)
#define TEE_REG_LP_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_LP_MM_LP_PMS_ALLOW_M (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S)
#define TEE_REG_LP_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_LP_MM_LP_HUK_ALLOW_M (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S)
#define TEE_REG_LP_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_PERI_REGION0_LOW_REG register
* NA
*/
#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION0_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_LOW_M (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S)
#define TEE_REG_PERI_REGION0_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_LOW_S 2
/** TEE_PERI_REGION0_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION0_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_HIGH_M (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S)
#define TEE_REG_PERI_REGION0_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_HIGH_S 2
/** TEE_PERI_REGION1_LOW_REG register
* NA
*/
#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION1_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_LOW_M (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S)
#define TEE_REG_PERI_REGION1_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_LOW_S 2
/** TEE_PERI_REGION1_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION1_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_HIGH_M (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S)
#define TEE_REG_PERI_REGION1_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_HIGH_S 2
/** TEE_PERI_REGION_PMS_REG register
* NA
*/
#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c)
/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
* NA
*/
#define TEE_REG_LP_CORE_REGION_PMS 0x00000003U
#define TEE_REG_LP_CORE_REGION_PMS_M (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S)
#define TEE_REG_LP_CORE_REGION_PMS_V 0x00000003U
#define TEE_REG_LP_CORE_REGION_PMS_S 0
/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE0_UM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE0_UM_REGION_PMS_M (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S)
#define TEE_REG_HP_CORE0_UM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE0_UM_REGION_PMS_S 2
/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE0_MM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE0_MM_REGION_PMS_M (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S)
#define TEE_REG_HP_CORE0_MM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE0_MM_REGION_PMS_S 4
/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE1_UM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE1_UM_REGION_PMS_M (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S)
#define TEE_REG_HP_CORE1_UM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE1_UM_REGION_PMS_S 6
/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE1_MM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE1_MM_REGION_PMS_M (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S)
#define TEE_REG_HP_CORE1_MM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE1_MM_REGION_PMS_S 8
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_peri_pms_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: TEE PMS DATE REG */
/** Type of pms_date register
* NA
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294537;
* NA
*/
uint32_t tee_date:32;
};
uint32_t val;
} tee_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
/** Group: TEE LP MM PMS REG0 REG */
/** Type of lp_mm_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_sysreg_allow:1;
/** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_aonclkrst_allow:1;
/** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_timer_allow:1;
/** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_anaperi_allow:1;
/** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_pmu_allow:1;
/** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_wdt_allow:1;
/** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_mailbox_allow:1;
/** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_rtc_allow:1;
/** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_periclkrst_allow:1;
/** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_uart_allow:1;
/** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_i2c_allow:1;
/** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_spi_allow:1;
/** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_i2cmst_allow:1;
/** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_i2s_allow:1;
/** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_adc_allow:1;
/** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_touch_allow:1;
/** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_iomux_allow:1;
/** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_intr_allow:1;
/** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_efuse_allow:1;
/** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_pms_allow:1;
/** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_lp_mm_hp2lp_pms_allow:1;
/** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_tsens_allow:1;
/** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_huk_allow:1;
/** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_lp_mm_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_lp_mm_pms_reg0_reg_t;
/** Group: TEE PERI REGION0 LOW REG */
/** Type of peri_region0_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region0_low:30;
};
uint32_t val;
} tee_peri_region0_low_reg_t;
/** Group: TEE PERI REGION0 HIGH REG */
/** Type of peri_region0_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region0_high:30;
};
uint32_t val;
} tee_peri_region0_high_reg_t;
/** Group: TEE PERI REGION1 LOW REG */
/** Type of peri_region1_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region1_low:30;
};
uint32_t val;
} tee_peri_region1_low_reg_t;
/** Group: TEE PERI REGION1 HIGH REG */
/** Type of peri_region1_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region1_high:30;
};
uint32_t val;
} tee_peri_region1_high_reg_t;
/** Group: TEE PERI REGION PMS REG */
/** Type of peri_region_pms register
* NA
*/
typedef union {
struct {
/** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
* NA
*/
uint32_t reg_lp_core_region_pms:2;
/** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
* NA
*/
uint32_t reg_hp_core0_um_region_pms:2;
/** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
* NA
*/
uint32_t reg_hp_core0_mm_region_pms:2;
/** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
* NA
*/
uint32_t reg_hp_core1_um_region_pms:2;
/** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
* NA
*/
uint32_t reg_hp_core1_mm_region_pms:2;
uint32_t reserved_10:22;
};
uint32_t val;
} tee_peri_region_pms_reg_t;
typedef struct {
volatile tee_pms_date_reg_t pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
volatile tee_peri_region0_low_reg_t peri_region0_low;
volatile tee_peri_region0_high_reg_t peri_region0_high;
volatile tee_peri_region1_low_reg_t peri_region1_low;
volatile tee_peri_region1_high_reg_t peri_region1_high;
volatile tee_peri_region_pms_reg_t peri_region_pms;
} tee_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x20, "Invalid size of tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* need_des
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_CK_EN_RNG : R/W; bitpos: [16]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_RNG (BIT(16))
#define LPPERI_CK_EN_RNG_M (LPPERI_CK_EN_RNG_V << LPPERI_CK_EN_RNG_S)
#define LPPERI_CK_EN_RNG_V 0x00000001U
#define LPPERI_CK_EN_RNG_S 16
/** LPPERI_CK_EN_LP_TSENS : R/W; bitpos: [17]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_TSENS (BIT(17))
#define LPPERI_CK_EN_LP_TSENS_M (LPPERI_CK_EN_LP_TSENS_V << LPPERI_CK_EN_LP_TSENS_S)
#define LPPERI_CK_EN_LP_TSENS_V 0x00000001U
#define LPPERI_CK_EN_LP_TSENS_S 17
/** LPPERI_CK_EN_LP_PMS : R/W; bitpos: [18]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_PMS (BIT(18))
#define LPPERI_CK_EN_LP_PMS_M (LPPERI_CK_EN_LP_PMS_V << LPPERI_CK_EN_LP_PMS_S)
#define LPPERI_CK_EN_LP_PMS_V 0x00000001U
#define LPPERI_CK_EN_LP_PMS_S 18
/** LPPERI_CK_EN_LP_EFUSE : R/W; bitpos: [19]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_EFUSE (BIT(19))
#define LPPERI_CK_EN_LP_EFUSE_M (LPPERI_CK_EN_LP_EFUSE_V << LPPERI_CK_EN_LP_EFUSE_S)
#define LPPERI_CK_EN_LP_EFUSE_V 0x00000001U
#define LPPERI_CK_EN_LP_EFUSE_S 19
/** LPPERI_CK_EN_LP_IOMUX : R/W; bitpos: [20]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_IOMUX (BIT(20))
#define LPPERI_CK_EN_LP_IOMUX_M (LPPERI_CK_EN_LP_IOMUX_V << LPPERI_CK_EN_LP_IOMUX_S)
#define LPPERI_CK_EN_LP_IOMUX_V 0x00000001U
#define LPPERI_CK_EN_LP_IOMUX_S 20
/** LPPERI_CK_EN_LP_TOUCH : R/W; bitpos: [21]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_TOUCH (BIT(21))
#define LPPERI_CK_EN_LP_TOUCH_M (LPPERI_CK_EN_LP_TOUCH_V << LPPERI_CK_EN_LP_TOUCH_S)
#define LPPERI_CK_EN_LP_TOUCH_V 0x00000001U
#define LPPERI_CK_EN_LP_TOUCH_S 21
/** LPPERI_CK_EN_LP_SPI : R/W; bitpos: [22]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_SPI (BIT(22))
#define LPPERI_CK_EN_LP_SPI_M (LPPERI_CK_EN_LP_SPI_V << LPPERI_CK_EN_LP_SPI_S)
#define LPPERI_CK_EN_LP_SPI_V 0x00000001U
#define LPPERI_CK_EN_LP_SPI_S 22
/** LPPERI_CK_EN_LP_ADC : R/W; bitpos: [23]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_ADC (BIT(23))
#define LPPERI_CK_EN_LP_ADC_M (LPPERI_CK_EN_LP_ADC_V << LPPERI_CK_EN_LP_ADC_S)
#define LPPERI_CK_EN_LP_ADC_V 0x00000001U
#define LPPERI_CK_EN_LP_ADC_S 23
/** LPPERI_CK_EN_LP_I2S_TX : R/W; bitpos: [24]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_I2S_TX (BIT(24))
#define LPPERI_CK_EN_LP_I2S_TX_M (LPPERI_CK_EN_LP_I2S_TX_V << LPPERI_CK_EN_LP_I2S_TX_S)
#define LPPERI_CK_EN_LP_I2S_TX_V 0x00000001U
#define LPPERI_CK_EN_LP_I2S_TX_S 24
/** LPPERI_CK_EN_LP_I2S_RX : R/W; bitpos: [25]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_I2S_RX (BIT(25))
#define LPPERI_CK_EN_LP_I2S_RX_M (LPPERI_CK_EN_LP_I2S_RX_V << LPPERI_CK_EN_LP_I2S_RX_S)
#define LPPERI_CK_EN_LP_I2S_RX_V 0x00000001U
#define LPPERI_CK_EN_LP_I2S_RX_S 25
/** LPPERI_CK_EN_LP_I2S : R/W; bitpos: [26]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_I2S (BIT(26))
#define LPPERI_CK_EN_LP_I2S_M (LPPERI_CK_EN_LP_I2S_V << LPPERI_CK_EN_LP_I2S_S)
#define LPPERI_CK_EN_LP_I2S_V 0x00000001U
#define LPPERI_CK_EN_LP_I2S_S 26
/** LPPERI_CK_EN_LP_I2CMST : R/W; bitpos: [27]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_I2CMST (BIT(27))
#define LPPERI_CK_EN_LP_I2CMST_M (LPPERI_CK_EN_LP_I2CMST_V << LPPERI_CK_EN_LP_I2CMST_S)
#define LPPERI_CK_EN_LP_I2CMST_V 0x00000001U
#define LPPERI_CK_EN_LP_I2CMST_S 27
/** LPPERI_CK_EN_LP_I2C : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_I2C (BIT(28))
#define LPPERI_CK_EN_LP_I2C_M (LPPERI_CK_EN_LP_I2C_V << LPPERI_CK_EN_LP_I2C_S)
#define LPPERI_CK_EN_LP_I2C_V 0x00000001U
#define LPPERI_CK_EN_LP_I2C_S 28
/** LPPERI_CK_EN_LP_UART : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_UART (BIT(29))
#define LPPERI_CK_EN_LP_UART_M (LPPERI_CK_EN_LP_UART_V << LPPERI_CK_EN_LP_UART_S)
#define LPPERI_CK_EN_LP_UART_V 0x00000001U
#define LPPERI_CK_EN_LP_UART_S 29
/** LPPERI_CK_EN_LP_INTR : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LPPERI_CK_EN_LP_INTR (BIT(30))
#define LPPERI_CK_EN_LP_INTR_M (LPPERI_CK_EN_LP_INTR_V << LPPERI_CK_EN_LP_INTR_S)
#define LPPERI_CK_EN_LP_INTR_V 0x00000001U
#define LPPERI_CK_EN_LP_INTR_S 30
/** LPPERI_CK_EN_LP_CORE : R/W; bitpos: [31]; default: 0;
* write 1 to force on lp_core clk
*/
#define LPPERI_CK_EN_LP_CORE (BIT(31))
#define LPPERI_CK_EN_LP_CORE_M (LPPERI_CK_EN_LP_CORE_V << LPPERI_CK_EN_LP_CORE_S)
#define LPPERI_CK_EN_LP_CORE_V 0x00000001U
#define LPPERI_CK_EN_LP_CORE_S 31
/** LPPERI_CORE_CLK_SEL_REG register
* need_des
*/
#define LPPERI_CORE_CLK_SEL_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_LP_I2S_TX_CLK_SEL : R/W; bitpos: [25:24]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_TX_CLK_SEL 0x00000003U
#define LPPERI_LP_I2S_TX_CLK_SEL_M (LPPERI_LP_I2S_TX_CLK_SEL_V << LPPERI_LP_I2S_TX_CLK_SEL_S)
#define LPPERI_LP_I2S_TX_CLK_SEL_V 0x00000003U
#define LPPERI_LP_I2S_TX_CLK_SEL_S 24
/** LPPERI_LP_I2S_RX_CLK_SEL : R/W; bitpos: [27:26]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_RX_CLK_SEL 0x00000003U
#define LPPERI_LP_I2S_RX_CLK_SEL_M (LPPERI_LP_I2S_RX_CLK_SEL_V << LPPERI_LP_I2S_RX_CLK_SEL_S)
#define LPPERI_LP_I2S_RX_CLK_SEL_V 0x00000003U
#define LPPERI_LP_I2S_RX_CLK_SEL_S 26
/** LPPERI_LP_I2C_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
* need_des
*/
#define LPPERI_LP_I2C_CLK_SEL 0x00000003U
#define LPPERI_LP_I2C_CLK_SEL_M (LPPERI_LP_I2C_CLK_SEL_V << LPPERI_LP_I2C_CLK_SEL_S)
#define LPPERI_LP_I2C_CLK_SEL_V 0x00000003U
#define LPPERI_LP_I2C_CLK_SEL_S 28
/** LPPERI_LP_UART_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_CLK_SEL 0x00000003U
#define LPPERI_LP_UART_CLK_SEL_M (LPPERI_LP_UART_CLK_SEL_V << LPPERI_LP_UART_CLK_SEL_S)
#define LPPERI_LP_UART_CLK_SEL_V 0x00000003U
#define LPPERI_LP_UART_CLK_SEL_S 30
/** LPPERI_RESET_EN_REG register
* need_des
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x8)
/** LPPERI_RST_EN_LP_TSENS : R/W; bitpos: [18]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_TSENS (BIT(18))
#define LPPERI_RST_EN_LP_TSENS_M (LPPERI_RST_EN_LP_TSENS_V << LPPERI_RST_EN_LP_TSENS_S)
#define LPPERI_RST_EN_LP_TSENS_V 0x00000001U
#define LPPERI_RST_EN_LP_TSENS_S 18
/** LPPERI_RST_EN_LP_PMS : R/W; bitpos: [19]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_PMS (BIT(19))
#define LPPERI_RST_EN_LP_PMS_M (LPPERI_RST_EN_LP_PMS_V << LPPERI_RST_EN_LP_PMS_S)
#define LPPERI_RST_EN_LP_PMS_V 0x00000001U
#define LPPERI_RST_EN_LP_PMS_S 19
/** LPPERI_RST_EN_LP_EFUSE : R/W; bitpos: [20]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_EFUSE (BIT(20))
#define LPPERI_RST_EN_LP_EFUSE_M (LPPERI_RST_EN_LP_EFUSE_V << LPPERI_RST_EN_LP_EFUSE_S)
#define LPPERI_RST_EN_LP_EFUSE_V 0x00000001U
#define LPPERI_RST_EN_LP_EFUSE_S 20
/** LPPERI_RST_EN_LP_IOMUX : R/W; bitpos: [21]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_IOMUX (BIT(21))
#define LPPERI_RST_EN_LP_IOMUX_M (LPPERI_RST_EN_LP_IOMUX_V << LPPERI_RST_EN_LP_IOMUX_S)
#define LPPERI_RST_EN_LP_IOMUX_V 0x00000001U
#define LPPERI_RST_EN_LP_IOMUX_S 21
/** LPPERI_RST_EN_LP_TOUCH : R/W; bitpos: [22]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_TOUCH (BIT(22))
#define LPPERI_RST_EN_LP_TOUCH_M (LPPERI_RST_EN_LP_TOUCH_V << LPPERI_RST_EN_LP_TOUCH_S)
#define LPPERI_RST_EN_LP_TOUCH_V 0x00000001U
#define LPPERI_RST_EN_LP_TOUCH_S 22
/** LPPERI_RST_EN_LP_SPI : R/W; bitpos: [23]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_SPI (BIT(23))
#define LPPERI_RST_EN_LP_SPI_M (LPPERI_RST_EN_LP_SPI_V << LPPERI_RST_EN_LP_SPI_S)
#define LPPERI_RST_EN_LP_SPI_V 0x00000001U
#define LPPERI_RST_EN_LP_SPI_S 23
/** LPPERI_RST_EN_LP_ADC : R/W; bitpos: [24]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_ADC (BIT(24))
#define LPPERI_RST_EN_LP_ADC_M (LPPERI_RST_EN_LP_ADC_V << LPPERI_RST_EN_LP_ADC_S)
#define LPPERI_RST_EN_LP_ADC_V 0x00000001U
#define LPPERI_RST_EN_LP_ADC_S 24
/** LPPERI_RST_EN_LP_I2S : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_I2S (BIT(25))
#define LPPERI_RST_EN_LP_I2S_M (LPPERI_RST_EN_LP_I2S_V << LPPERI_RST_EN_LP_I2S_S)
#define LPPERI_RST_EN_LP_I2S_V 0x00000001U
#define LPPERI_RST_EN_LP_I2S_S 25
/** LPPERI_RST_EN_LP_I2CMST : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_I2CMST (BIT(26))
#define LPPERI_RST_EN_LP_I2CMST_M (LPPERI_RST_EN_LP_I2CMST_V << LPPERI_RST_EN_LP_I2CMST_S)
#define LPPERI_RST_EN_LP_I2CMST_V 0x00000001U
#define LPPERI_RST_EN_LP_I2CMST_S 26
/** LPPERI_RST_EN_LP_I2C : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_I2C (BIT(27))
#define LPPERI_RST_EN_LP_I2C_M (LPPERI_RST_EN_LP_I2C_V << LPPERI_RST_EN_LP_I2C_S)
#define LPPERI_RST_EN_LP_I2C_V 0x00000001U
#define LPPERI_RST_EN_LP_I2C_S 27
/** LPPERI_RST_EN_LP_UART : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_UART (BIT(28))
#define LPPERI_RST_EN_LP_UART_M (LPPERI_RST_EN_LP_UART_V << LPPERI_RST_EN_LP_UART_S)
#define LPPERI_RST_EN_LP_UART_V 0x00000001U
#define LPPERI_RST_EN_LP_UART_S 28
/** LPPERI_RST_EN_LP_INTR : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_INTR (BIT(29))
#define LPPERI_RST_EN_LP_INTR_M (LPPERI_RST_EN_LP_INTR_V << LPPERI_RST_EN_LP_INTR_S)
#define LPPERI_RST_EN_LP_INTR_V 0x00000001U
#define LPPERI_RST_EN_LP_INTR_S 29
/** LPPERI_RST_EN_LP_ROM : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_ROM (BIT(30))
#define LPPERI_RST_EN_LP_ROM_M (LPPERI_RST_EN_LP_ROM_V << LPPERI_RST_EN_LP_ROM_S)
#define LPPERI_RST_EN_LP_ROM_V 0x00000001U
#define LPPERI_RST_EN_LP_ROM_S 30
/** LPPERI_RST_EN_LP_CORE : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_RST_EN_LP_CORE (BIT(31))
#define LPPERI_RST_EN_LP_CORE_M (LPPERI_RST_EN_LP_CORE_V << LPPERI_RST_EN_LP_CORE_S)
#define LPPERI_RST_EN_LP_CORE_V 0x00000001U
#define LPPERI_RST_EN_LP_CORE_S 31
/** LPPERI_CPU_REG register
* need_des
*/
#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
/** LPPERI_LPCORE_DBGM_UNAVAILABLE : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LPCORE_DBGM_UNAVAILABLE (BIT(31))
#define LPPERI_LPCORE_DBGM_UNAVAILABLE_M (LPPERI_LPCORE_DBGM_UNAVAILABLE_V << LPPERI_LPCORE_DBGM_UNAVAILABLE_S)
#define LPPERI_LPCORE_DBGM_UNAVAILABLE_V 0x00000001U
#define LPPERI_LPCORE_DBGM_UNAVAILABLE_S 31
/** LPPERI_MEM_CTRL_REG register
* need_des
*/
#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x28)
/** LPPERI_LP_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_WAKEUP_FLAG_CLR (BIT(0))
#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_M (LPPERI_LP_UART_WAKEUP_FLAG_CLR_V << LPPERI_LP_UART_WAKEUP_FLAG_CLR_S)
#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_V 0x00000001U
#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_S 0
/** LPPERI_LP_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_WAKEUP_FLAG (BIT(1))
#define LPPERI_LP_UART_WAKEUP_FLAG_M (LPPERI_LP_UART_WAKEUP_FLAG_V << LPPERI_LP_UART_WAKEUP_FLAG_S)
#define LPPERI_LP_UART_WAKEUP_FLAG_V 0x00000001U
#define LPPERI_LP_UART_WAKEUP_FLAG_S 1
/** LPPERI_LP_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_WAKEUP_EN (BIT(29))
#define LPPERI_LP_UART_WAKEUP_EN_M (LPPERI_LP_UART_WAKEUP_EN_V << LPPERI_LP_UART_WAKEUP_EN_S)
#define LPPERI_LP_UART_WAKEUP_EN_V 0x00000001U
#define LPPERI_LP_UART_WAKEUP_EN_S 29
/** LPPERI_LP_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_MEM_FORCE_PD (BIT(30))
#define LPPERI_LP_UART_MEM_FORCE_PD_M (LPPERI_LP_UART_MEM_FORCE_PD_V << LPPERI_LP_UART_MEM_FORCE_PD_S)
#define LPPERI_LP_UART_MEM_FORCE_PD_V 0x00000001U
#define LPPERI_LP_UART_MEM_FORCE_PD_S 30
/** LPPERI_LP_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LP_UART_MEM_FORCE_PU (BIT(31))
#define LPPERI_LP_UART_MEM_FORCE_PU_M (LPPERI_LP_UART_MEM_FORCE_PU_V << LPPERI_LP_UART_MEM_FORCE_PU_S)
#define LPPERI_LP_UART_MEM_FORCE_PU_V 0x00000001U
#define LPPERI_LP_UART_MEM_FORCE_PU_S 31
/** LPPERI_ADC_CTRL_REG register
* need_des
*/
#define LPPERI_ADC_CTRL_REG (DR_REG_LPPERI_BASE + 0x2c)
/** LPPERI_SAR2_CLK_FORCE_ON : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define LPPERI_SAR2_CLK_FORCE_ON (BIT(6))
#define LPPERI_SAR2_CLK_FORCE_ON_M (LPPERI_SAR2_CLK_FORCE_ON_V << LPPERI_SAR2_CLK_FORCE_ON_S)
#define LPPERI_SAR2_CLK_FORCE_ON_V 0x00000001U
#define LPPERI_SAR2_CLK_FORCE_ON_S 6
/** LPPERI_SAR1_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
* need_des
*/
#define LPPERI_SAR1_CLK_FORCE_ON (BIT(7))
#define LPPERI_SAR1_CLK_FORCE_ON_M (LPPERI_SAR1_CLK_FORCE_ON_V << LPPERI_SAR1_CLK_FORCE_ON_S)
#define LPPERI_SAR1_CLK_FORCE_ON_V 0x00000001U
#define LPPERI_SAR1_CLK_FORCE_ON_S 7
/** LPPERI_LPADC_FUNC_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
* need_des
*/
#define LPPERI_LPADC_FUNC_DIV_NUM 0x000000FFU
#define LPPERI_LPADC_FUNC_DIV_NUM_M (LPPERI_LPADC_FUNC_DIV_NUM_V << LPPERI_LPADC_FUNC_DIV_NUM_S)
#define LPPERI_LPADC_FUNC_DIV_NUM_V 0x000000FFU
#define LPPERI_LPADC_FUNC_DIV_NUM_S 8
/** LPPERI_LPADC_SAR2_DIV_NUM : R/W; bitpos: [23:16]; default: 4;
* need_des
*/
#define LPPERI_LPADC_SAR2_DIV_NUM 0x000000FFU
#define LPPERI_LPADC_SAR2_DIV_NUM_M (LPPERI_LPADC_SAR2_DIV_NUM_V << LPPERI_LPADC_SAR2_DIV_NUM_S)
#define LPPERI_LPADC_SAR2_DIV_NUM_V 0x000000FFU
#define LPPERI_LPADC_SAR2_DIV_NUM_S 16
/** LPPERI_LPADC_SAR1_DIV_NUM : R/W; bitpos: [31:24]; default: 4;
* need_des
*/
#define LPPERI_LPADC_SAR1_DIV_NUM 0x000000FFU
#define LPPERI_LPADC_SAR1_DIV_NUM_M (LPPERI_LPADC_SAR1_DIV_NUM_V << LPPERI_LPADC_SAR1_DIV_NUM_S)
#define LPPERI_LPADC_SAR1_DIV_NUM_V 0x000000FFU
#define LPPERI_LPADC_SAR1_DIV_NUM_S 24
/** LPPERI_LP_I2S_RXCLK_DIV_NUM_REG register
* need_des
*/
#define LPPERI_LP_I2S_RXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x30)
/** LPPERI_LP_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
* need_des
*/
#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM 0x000000FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_M (LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S)
#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S 24
/** LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG register
* need_des
*/
#define LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x34)
/** LPPERI_LP_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1 (BIT(4))
#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_M (LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S)
#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V 0x00000001U
#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S 4
/** LPPERI_LP_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_RX_CLKM_DIV_Z 0x000001FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_M (LPPERI_LP_I2S_RX_CLKM_DIV_Z_V << LPPERI_LP_I2S_RX_CLKM_DIV_Z_S)
#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_V 0x000001FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_S 5
/** LPPERI_LP_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1;
* need_des
*/
#define LPPERI_LP_I2S_RX_CLKM_DIV_Y 0x000001FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_M (LPPERI_LP_I2S_RX_CLKM_DIV_Y_V << LPPERI_LP_I2S_RX_CLKM_DIV_Y_S)
#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_V 0x000001FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_S 14
/** LPPERI_LP_I2S_RX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_RX_CLKM_DIV_X 0x000001FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_X_M (LPPERI_LP_I2S_RX_CLKM_DIV_X_V << LPPERI_LP_I2S_RX_CLKM_DIV_X_S)
#define LPPERI_LP_I2S_RX_CLKM_DIV_X_V 0x000001FFU
#define LPPERI_LP_I2S_RX_CLKM_DIV_X_S 23
/** LPPERI_LP_I2S_TXCLK_DIV_NUM_REG register
* need_des
*/
#define LPPERI_LP_I2S_TXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x38)
/** LPPERI_LP_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
* need_des
*/
#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM 0x000000FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_M (LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S)
#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S 24
/** LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG register
* need_des
*/
#define LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x3c)
/** LPPERI_LP_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1 (BIT(4))
#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_M (LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S)
#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V 0x00000001U
#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S 4
/** LPPERI_LP_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_TX_CLKM_DIV_Z 0x000001FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_M (LPPERI_LP_I2S_TX_CLKM_DIV_Z_V << LPPERI_LP_I2S_TX_CLKM_DIV_Z_S)
#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_V 0x000001FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_S 5
/** LPPERI_LP_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1;
* need_des
*/
#define LPPERI_LP_I2S_TX_CLKM_DIV_Y 0x000001FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_M (LPPERI_LP_I2S_TX_CLKM_DIV_Y_V << LPPERI_LP_I2S_TX_CLKM_DIV_Y_S)
#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_V 0x000001FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_S 14
/** LPPERI_LP_I2S_TX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0;
* need_des
*/
#define LPPERI_LP_I2S_TX_CLKM_DIV_X 0x000001FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_X_M (LPPERI_LP_I2S_TX_CLKM_DIV_X_V << LPPERI_LP_I2S_TX_CLKM_DIV_X_S)
#define LPPERI_LP_I2S_TX_CLKM_DIV_X_V 0x000001FFU
#define LPPERI_LP_I2S_TX_CLKM_DIV_X_S 23
/** LPPERI_DATE_REG register
* need_des
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

374
components/soc/esp32p4/include/soc/lp_peri_struct.h Normal file
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@ -0,0 +1,374 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** ck_en_rng : R/W; bitpos: [16]; default: 1;
* need_des
*/
uint32_t ck_en_rng:1;
/** ck_en_lp_tsens : R/W; bitpos: [17]; default: 1;
* need_des
*/
uint32_t ck_en_lp_tsens:1;
/** ck_en_lp_pms : R/W; bitpos: [18]; default: 1;
* need_des
*/
uint32_t ck_en_lp_pms:1;
/** ck_en_lp_efuse : R/W; bitpos: [19]; default: 1;
* need_des
*/
uint32_t ck_en_lp_efuse:1;
/** ck_en_lp_iomux : R/W; bitpos: [20]; default: 1;
* need_des
*/
uint32_t ck_en_lp_iomux:1;
/** ck_en_lp_touch : R/W; bitpos: [21]; default: 1;
* need_des
*/
uint32_t ck_en_lp_touch:1;
/** ck_en_lp_spi : R/W; bitpos: [22]; default: 1;
* need_des
*/
uint32_t ck_en_lp_spi:1;
/** ck_en_lp_adc : R/W; bitpos: [23]; default: 1;
* need_des
*/
uint32_t ck_en_lp_adc:1;
/** ck_en_lp_i2s_tx : R/W; bitpos: [24]; default: 1;
* need_des
*/
uint32_t ck_en_lp_i2s_tx:1;
/** ck_en_lp_i2s_rx : R/W; bitpos: [25]; default: 1;
* need_des
*/
uint32_t ck_en_lp_i2s_rx:1;
/** ck_en_lp_i2s : R/W; bitpos: [26]; default: 1;
* need_des
*/
uint32_t ck_en_lp_i2s:1;
/** ck_en_lp_i2cmst : R/W; bitpos: [27]; default: 1;
* need_des
*/
uint32_t ck_en_lp_i2cmst:1;
/** ck_en_lp_i2c : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t ck_en_lp_i2c:1;
/** ck_en_lp_uart : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t ck_en_lp_uart:1;
/** ck_en_lp_intr : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t ck_en_lp_intr:1;
/** ck_en_lp_core : R/W; bitpos: [31]; default: 0;
* write 1 to force on lp_core clk
*/
uint32_t ck_en_lp_core:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of core_clk_sel register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** lp_i2s_tx_clk_sel : R/W; bitpos: [25:24]; default: 0;
* need_des
*/
uint32_t lp_i2s_tx_clk_sel:2;
/** lp_i2s_rx_clk_sel : R/W; bitpos: [27:26]; default: 0;
* need_des
*/
uint32_t lp_i2s_rx_clk_sel:2;
/** lp_i2c_clk_sel : R/W; bitpos: [29:28]; default: 0;
* need_des
*/
uint32_t lp_i2c_clk_sel:2;
/** lp_uart_clk_sel : R/W; bitpos: [31:30]; default: 0;
* need_des
*/
uint32_t lp_uart_clk_sel:2;
};
uint32_t val;
} lpperi_core_clk_sel_reg_t;
/** Type of reset_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** rst_en_lp_tsens : R/W; bitpos: [18]; default: 0;
* need_des
*/
uint32_t rst_en_lp_tsens:1;
/** rst_en_lp_pms : R/W; bitpos: [19]; default: 0;
* need_des
*/
uint32_t rst_en_lp_pms:1;
/** rst_en_lp_efuse : R/W; bitpos: [20]; default: 0;
* need_des
*/
uint32_t rst_en_lp_efuse:1;
/** rst_en_lp_iomux : R/W; bitpos: [21]; default: 0;
* need_des
*/
uint32_t rst_en_lp_iomux:1;
/** rst_en_lp_touch : R/W; bitpos: [22]; default: 0;
* need_des
*/
uint32_t rst_en_lp_touch:1;
/** rst_en_lp_spi : R/W; bitpos: [23]; default: 0;
* need_des
*/
uint32_t rst_en_lp_spi:1;
/** rst_en_lp_adc : R/W; bitpos: [24]; default: 0;
* need_des
*/
uint32_t rst_en_lp_adc:1;
/** rst_en_lp_i2s : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t rst_en_lp_i2s:1;
/** rst_en_lp_i2cmst : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t rst_en_lp_i2cmst:1;
/** rst_en_lp_i2c : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t rst_en_lp_i2c:1;
/** rst_en_lp_uart : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t rst_en_lp_uart:1;
/** rst_en_lp_intr : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t rst_en_lp_intr:1;
/** rst_en_lp_rom : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t rst_en_lp_rom:1;
/** rst_en_lp_core : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t rst_en_lp_core:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of cpu register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpcore_dbgm_unavailable : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lpcore_dbgm_unavailable:1;
};
uint32_t val;
} lpperi_cpu_reg_t;
/** Type of mem_ctrl register
* need_des
*/
typedef union {
struct {
/** lp_uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lp_uart_wakeup_flag_clr:1;
/** lp_uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lp_uart_wakeup_flag:1;
uint32_t reserved_2:27;
/** lp_uart_wakeup_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_uart_wakeup_en:1;
/** lp_uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_uart_mem_force_pd:1;
/** lp_uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lp_uart_mem_force_pu:1;
};
uint32_t val;
} lpperi_mem_ctrl_reg_t;
/** Type of adc_ctrl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** sar2_clk_force_on : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t sar2_clk_force_on:1;
/** sar1_clk_force_on : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t sar1_clk_force_on:1;
/** lpadc_func_div_num : R/W; bitpos: [15:8]; default: 4;
* need_des
*/
uint32_t lpadc_func_div_num:8;
/** lpadc_sar2_div_num : R/W; bitpos: [23:16]; default: 4;
* need_des
*/
uint32_t lpadc_sar2_div_num:8;
/** lpadc_sar1_div_num : R/W; bitpos: [31:24]; default: 4;
* need_des
*/
uint32_t lpadc_sar1_div_num:8;
};
uint32_t val;
} lpperi_adc_ctrl_reg_t;
/** Type of lp_i2s_rxclk_div_num register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** lp_i2s_rx_clkm_div_num : R/W; bitpos: [31:24]; default: 2;
* need_des
*/
uint32_t lp_i2s_rx_clkm_div_num:8;
};
uint32_t val;
} lpperi_lp_i2s_rxclk_div_num_reg_t;
/** Type of lp_i2s_rxclk_div_xyz register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:4;
/** lp_i2s_rx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0;
* need_des
*/
uint32_t lp_i2s_rx_clkm_div_yn1:1;
/** lp_i2s_rx_clkm_div_z : R/W; bitpos: [13:5]; default: 0;
* need_des
*/
uint32_t lp_i2s_rx_clkm_div_z:9;
/** lp_i2s_rx_clkm_div_y : R/W; bitpos: [22:14]; default: 1;
* need_des
*/
uint32_t lp_i2s_rx_clkm_div_y:9;
/** lp_i2s_rx_clkm_div_x : R/W; bitpos: [31:23]; default: 0;
* need_des
*/
uint32_t lp_i2s_rx_clkm_div_x:9;
};
uint32_t val;
} lpperi_lp_i2s_rxclk_div_xyz_reg_t;
/** Type of lp_i2s_txclk_div_num register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** lp_i2s_tx_clkm_div_num : R/W; bitpos: [31:24]; default: 2;
* need_des
*/
uint32_t lp_i2s_tx_clkm_div_num:8;
};
uint32_t val;
} lpperi_lp_i2s_txclk_div_num_reg_t;
/** Type of lp_i2s_txclk_div_xyz register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:4;
/** lp_i2s_tx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0;
* need_des
*/
uint32_t lp_i2s_tx_clkm_div_yn1:1;
/** lp_i2s_tx_clkm_div_z : R/W; bitpos: [13:5]; default: 0;
* need_des
*/
uint32_t lp_i2s_tx_clkm_div_z:9;
/** lp_i2s_tx_clkm_div_y : R/W; bitpos: [22:14]; default: 1;
* need_des
*/
uint32_t lp_i2s_tx_clkm_div_y:9;
/** lp_i2s_tx_clkm_div_x : R/W; bitpos: [31:23]; default: 0;
* need_des
*/
uint32_t lp_i2s_tx_clkm_div_x:9;
};
uint32_t val;
} lpperi_lp_i2s_txclk_div_xyz_reg_t;
/** Group: Version register */
/** Type of date register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_core_clk_sel_reg_t core_clk_sel;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_cpu_reg_t cpu;
uint32_t reserved_010[6];
volatile lpperi_mem_ctrl_reg_t mem_ctrl;
volatile lpperi_adc_ctrl_reg_t adc_ctrl;
volatile lpperi_lp_i2s_rxclk_div_num_reg_t lp_i2s_rxclk_div_num;
volatile lpperi_lp_i2s_rxclk_div_xyz_reg_t lp_i2s_rxclk_div_xyz;
volatile lpperi_lp_i2s_txclk_div_num_reg_t lp_i2s_txclk_div_num;
volatile lpperi_lp_i2s_txclk_div_xyz_reg_t lp_i2s_txclk_div_xyz;
uint32_t reserved_040[239];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** CSI_BRIG_CLK_EN_REG register
* csi bridge register mapping unit clock gating.
*/
#define CSI_BRIG_CLK_EN_REG (DR_REG_CSI_BRIG_BASE + 0x0)
/** CSI_BRIG_CLK_EN : R/W; bitpos: [0]; default: 0;
* 0: enable clock gating. 1: disable clock gating, clock always on.
*/
#define CSI_BRIG_CLK_EN (BIT(0))
#define CSI_BRIG_CLK_EN_M (CSI_BRIG_CLK_EN_V << CSI_BRIG_CLK_EN_S)
#define CSI_BRIG_CLK_EN_V 0x00000001U
#define CSI_BRIG_CLK_EN_S 0
/** CSI_BRIG_CSI_EN_REG register
* csi bridge enable.
*/
#define CSI_BRIG_CSI_EN_REG (DR_REG_CSI_BRIG_BASE + 0x4)
/** CSI_BRIG_CSI_BRIG_EN : R/W; bitpos: [0]; default: 0;
* 0: disable csi bridge. 1: enable csi bridge.
*/
#define CSI_BRIG_CSI_BRIG_EN (BIT(0))
#define CSI_BRIG_CSI_BRIG_EN_M (CSI_BRIG_CSI_BRIG_EN_V << CSI_BRIG_CSI_BRIG_EN_S)
#define CSI_BRIG_CSI_BRIG_EN_V 0x00000001U
#define CSI_BRIG_CSI_BRIG_EN_S 0
/** CSI_BRIG_DMA_REQ_CFG_REG register
* dma request configuration.
*/
#define CSI_BRIG_DMA_REQ_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x8)
/** CSI_BRIG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128;
* DMA burst length.
*/
#define CSI_BRIG_DMA_BURST_LEN 0x00000FFFU
#define CSI_BRIG_DMA_BURST_LEN_M (CSI_BRIG_DMA_BURST_LEN_V << CSI_BRIG_DMA_BURST_LEN_S)
#define CSI_BRIG_DMA_BURST_LEN_V 0x00000FFFU
#define CSI_BRIG_DMA_BURST_LEN_S 0
/** CSI_BRIG_DMA_CFG_UPD_BY_BLK : R/W; bitpos: [12]; default: 0;
* 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
* updated by frame.
*/
#define CSI_BRIG_DMA_CFG_UPD_BY_BLK (BIT(12))
#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_M (CSI_BRIG_DMA_CFG_UPD_BY_BLK_V << CSI_BRIG_DMA_CFG_UPD_BY_BLK_S)
#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_V 0x00000001U
#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_S 12
/** CSI_BRIG_DMA_FORCE_RD_STATUS : R/W; bitpos: [16]; default: 0;
* 1: mask dma request when reading frame info. 0: disable mask.
*/
#define CSI_BRIG_DMA_FORCE_RD_STATUS (BIT(16))
#define CSI_BRIG_DMA_FORCE_RD_STATUS_M (CSI_BRIG_DMA_FORCE_RD_STATUS_V << CSI_BRIG_DMA_FORCE_RD_STATUS_S)
#define CSI_BRIG_DMA_FORCE_RD_STATUS_V 0x00000001U
#define CSI_BRIG_DMA_FORCE_RD_STATUS_S 16
/** CSI_BRIG_BUF_FLOW_CTL_REG register
* csi bridge buffer control.
*/
#define CSI_BRIG_BUF_FLOW_CTL_REG (DR_REG_CSI_BRIG_BASE + 0xc)
/** CSI_BRIG_CSI_BUF_AFULL_THRD : R/W; bitpos: [13:0]; default: 2040;
* buffer almost full threshold.
*/
#define CSI_BRIG_CSI_BUF_AFULL_THRD 0x00003FFFU
#define CSI_BRIG_CSI_BUF_AFULL_THRD_M (CSI_BRIG_CSI_BUF_AFULL_THRD_V << CSI_BRIG_CSI_BUF_AFULL_THRD_S)
#define CSI_BRIG_CSI_BUF_AFULL_THRD_V 0x00003FFFU
#define CSI_BRIG_CSI_BUF_AFULL_THRD_S 0
/** CSI_BRIG_CSI_BUF_DEPTH : RO; bitpos: [29:16]; default: 0;
* buffer data count.
*/
#define CSI_BRIG_CSI_BUF_DEPTH 0x00003FFFU
#define CSI_BRIG_CSI_BUF_DEPTH_M (CSI_BRIG_CSI_BUF_DEPTH_V << CSI_BRIG_CSI_BUF_DEPTH_S)
#define CSI_BRIG_CSI_BUF_DEPTH_V 0x00003FFFU
#define CSI_BRIG_CSI_BUF_DEPTH_S 16
/** CSI_BRIG_DATA_TYPE_CFG_REG register
* pixel data type configuration.
*/
#define CSI_BRIG_DATA_TYPE_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x10)
/** CSI_BRIG_DATA_TYPE_MIN : R/W; bitpos: [5:0]; default: 24;
* the min value of data type used for pixel filter.
*/
#define CSI_BRIG_DATA_TYPE_MIN 0x0000003FU
#define CSI_BRIG_DATA_TYPE_MIN_M (CSI_BRIG_DATA_TYPE_MIN_V << CSI_BRIG_DATA_TYPE_MIN_S)
#define CSI_BRIG_DATA_TYPE_MIN_V 0x0000003FU
#define CSI_BRIG_DATA_TYPE_MIN_S 0
/** CSI_BRIG_DATA_TYPE_MAX : R/W; bitpos: [13:8]; default: 47;
* the max value of data type used for pixel filter.
*/
#define CSI_BRIG_DATA_TYPE_MAX 0x0000003FU
#define CSI_BRIG_DATA_TYPE_MAX_M (CSI_BRIG_DATA_TYPE_MAX_V << CSI_BRIG_DATA_TYPE_MAX_S)
#define CSI_BRIG_DATA_TYPE_MAX_V 0x0000003FU
#define CSI_BRIG_DATA_TYPE_MAX_S 8
/** CSI_BRIG_FRAME_CFG_REG register
* frame configuration.
*/
#define CSI_BRIG_FRAME_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x14)
/** CSI_BRIG_VADR_NUM : R/W; bitpos: [11:0]; default: 480;
* vadr of frame data.
*/
#define CSI_BRIG_VADR_NUM 0x00000FFFU
#define CSI_BRIG_VADR_NUM_M (CSI_BRIG_VADR_NUM_V << CSI_BRIG_VADR_NUM_S)
#define CSI_BRIG_VADR_NUM_V 0x00000FFFU
#define CSI_BRIG_VADR_NUM_S 0
/** CSI_BRIG_HADR_NUM : R/W; bitpos: [23:12]; default: 480;
* hadr of frame data.
*/
#define CSI_BRIG_HADR_NUM 0x00000FFFU
#define CSI_BRIG_HADR_NUM_M (CSI_BRIG_HADR_NUM_V << CSI_BRIG_HADR_NUM_S)
#define CSI_BRIG_HADR_NUM_V 0x00000FFFU
#define CSI_BRIG_HADR_NUM_S 12
/** CSI_BRIG_HAS_HSYNC_E : R/W; bitpos: [24]; default: 1;
* 0: frame data doesn't contain hsync. 1: frame data contains hsync.
*/
#define CSI_BRIG_HAS_HSYNC_E (BIT(24))
#define CSI_BRIG_HAS_HSYNC_E_M (CSI_BRIG_HAS_HSYNC_E_V << CSI_BRIG_HAS_HSYNC_E_S)
#define CSI_BRIG_HAS_HSYNC_E_V 0x00000001U
#define CSI_BRIG_HAS_HSYNC_E_S 24
/** CSI_BRIG_VADR_NUM_CHECK : R/W; bitpos: [25]; default: 0;
* 0: disable vadr check. 1: enable vadr check.
*/
#define CSI_BRIG_VADR_NUM_CHECK (BIT(25))
#define CSI_BRIG_VADR_NUM_CHECK_M (CSI_BRIG_VADR_NUM_CHECK_V << CSI_BRIG_VADR_NUM_CHECK_S)
#define CSI_BRIG_VADR_NUM_CHECK_V 0x00000001U
#define CSI_BRIG_VADR_NUM_CHECK_S 25
/** CSI_BRIG_ENDIAN_MODE_REG register
* data endianness order configuration.
*/
#define CSI_BRIG_ENDIAN_MODE_REG (DR_REG_CSI_BRIG_BASE + 0x18)
/** CSI_BRIG_BYTE_ENDIAN_ORDER : R/W; bitpos: [0]; default: 0;
* endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
* when isp is bapassed.
*/
#define CSI_BRIG_BYTE_ENDIAN_ORDER (BIT(0))
#define CSI_BRIG_BYTE_ENDIAN_ORDER_M (CSI_BRIG_BYTE_ENDIAN_ORDER_V << CSI_BRIG_BYTE_ENDIAN_ORDER_S)
#define CSI_BRIG_BYTE_ENDIAN_ORDER_V 0x00000001U
#define CSI_BRIG_BYTE_ENDIAN_ORDER_S 0
/** CSI_BRIG_BIT_ENDIAN_ORDER : R/W; bitpos: [1]; default: 0;
* N/A
*/
#define CSI_BRIG_BIT_ENDIAN_ORDER (BIT(1))
#define CSI_BRIG_BIT_ENDIAN_ORDER_M (CSI_BRIG_BIT_ENDIAN_ORDER_V << CSI_BRIG_BIT_ENDIAN_ORDER_S)
#define CSI_BRIG_BIT_ENDIAN_ORDER_V 0x00000001U
#define CSI_BRIG_BIT_ENDIAN_ORDER_S 1
/** CSI_BRIG_INT_RAW_REG register
* csi bridge interrupt raw.
*/
#define CSI_BRIG_INT_RAW_REG (DR_REG_CSI_BRIG_BASE + 0x1c)
/** CSI_BRIG_VADR_NUM_GT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt raw.
*/
#define CSI_BRIG_VADR_NUM_GT_INT_RAW (BIT(0))
#define CSI_BRIG_VADR_NUM_GT_INT_RAW_M (CSI_BRIG_VADR_NUM_GT_INT_RAW_V << CSI_BRIG_VADR_NUM_GT_INT_RAW_S)
#define CSI_BRIG_VADR_NUM_GT_INT_RAW_V 0x00000001U
#define CSI_BRIG_VADR_NUM_GT_INT_RAW_S 0
/** CSI_BRIG_VADR_NUM_LT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt raw.
*/
#define CSI_BRIG_VADR_NUM_LT_INT_RAW (BIT(1))
#define CSI_BRIG_VADR_NUM_LT_INT_RAW_M (CSI_BRIG_VADR_NUM_LT_INT_RAW_V << CSI_BRIG_VADR_NUM_LT_INT_RAW_S)
#define CSI_BRIG_VADR_NUM_LT_INT_RAW_V 0x00000001U
#define CSI_BRIG_VADR_NUM_LT_INT_RAW_S 1
/** CSI_BRIG_DISCARD_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt raw.
*/
#define CSI_BRIG_DISCARD_INT_RAW (BIT(2))
#define CSI_BRIG_DISCARD_INT_RAW_M (CSI_BRIG_DISCARD_INT_RAW_V << CSI_BRIG_DISCARD_INT_RAW_S)
#define CSI_BRIG_DISCARD_INT_RAW_V 0x00000001U
#define CSI_BRIG_DISCARD_INT_RAW_S 2
/** CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* buffer overrun interrupt raw.
*/
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW (BIT(3))
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S)
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V 0x00000001U
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S 3
/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* buffer overflow interrupt raw.
*/
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW (BIT(4))
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S)
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V 0x00000001U
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S 4
/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* dma configuration update complete interrupt raw.
*/
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW (BIT(5))
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S)
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V 0x00000001U
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S 5
/** CSI_BRIG_INT_CLR_REG register
* csi bridge interrupt clr.
*/
#define CSI_BRIG_INT_CLR_REG (DR_REG_CSI_BRIG_BASE + 0x20)
/** CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR : WT; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt clr.
*/
#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR (BIT(0))
#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_M (CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S)
#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V 0x00000001U
#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S 0
/** CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR : WT; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt clr.
*/
#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR (BIT(1))
#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_M (CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S)
#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V 0x00000001U
#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S 1
/** CSI_BRIG_DISCARD_INT_CLR : WT; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt clr.
*/
#define CSI_BRIG_DISCARD_INT_CLR (BIT(2))
#define CSI_BRIG_DISCARD_INT_CLR_M (CSI_BRIG_DISCARD_INT_CLR_V << CSI_BRIG_DISCARD_INT_CLR_S)
#define CSI_BRIG_DISCARD_INT_CLR_V 0x00000001U
#define CSI_BRIG_DISCARD_INT_CLR_S 2
/** CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0;
* buffer overrun interrupt clr.
*/
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR (BIT(3))
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S)
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V 0x00000001U
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S 3
/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
* buffer overflow interrupt clr.
*/
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR (BIT(4))
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S)
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V 0x00000001U
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S 4
/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR : WT; bitpos: [5]; default: 0;
* dma configuration update complete interrupt clr.
*/
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR (BIT(5))
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S)
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V 0x00000001U
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S 5
/** CSI_BRIG_INT_ST_REG register
* csi bridge interrupt st.
*/
#define CSI_BRIG_INT_ST_REG (DR_REG_CSI_BRIG_BASE + 0x24)
/** CSI_BRIG_VADR_NUM_GT_INT_ST : RO; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt st.
*/
#define CSI_BRIG_VADR_NUM_GT_INT_ST (BIT(0))
#define CSI_BRIG_VADR_NUM_GT_INT_ST_M (CSI_BRIG_VADR_NUM_GT_INT_ST_V << CSI_BRIG_VADR_NUM_GT_INT_ST_S)
#define CSI_BRIG_VADR_NUM_GT_INT_ST_V 0x00000001U
#define CSI_BRIG_VADR_NUM_GT_INT_ST_S 0
/** CSI_BRIG_VADR_NUM_LT_INT_ST : RO; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt st.
*/
#define CSI_BRIG_VADR_NUM_LT_INT_ST (BIT(1))
#define CSI_BRIG_VADR_NUM_LT_INT_ST_M (CSI_BRIG_VADR_NUM_LT_INT_ST_V << CSI_BRIG_VADR_NUM_LT_INT_ST_S)
#define CSI_BRIG_VADR_NUM_LT_INT_ST_V 0x00000001U
#define CSI_BRIG_VADR_NUM_LT_INT_ST_S 1
/** CSI_BRIG_DISCARD_INT_ST : RO; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt st.
*/
#define CSI_BRIG_DISCARD_INT_ST (BIT(2))
#define CSI_BRIG_DISCARD_INT_ST_M (CSI_BRIG_DISCARD_INT_ST_V << CSI_BRIG_DISCARD_INT_ST_S)
#define CSI_BRIG_DISCARD_INT_ST_V 0x00000001U
#define CSI_BRIG_DISCARD_INT_ST_S 2
/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
* buffer overrun interrupt st.
*/
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST (BIT(3))
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S)
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V 0x00000001U
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S 3
/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
* buffer overflow interrupt st.
*/
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST (BIT(4))
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S)
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V 0x00000001U
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S 4
/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST : RO; bitpos: [5]; default: 0;
* dma configuration update complete interrupt st.
*/
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST (BIT(5))
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S)
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V 0x00000001U
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S 5
/** CSI_BRIG_INT_ENA_REG register
* csi bridge interrupt enable.
*/
#define CSI_BRIG_INT_ENA_REG (DR_REG_CSI_BRIG_BASE + 0x28)
/** CSI_BRIG_VADR_NUM_GT_INT_ENA : R/W; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt enable.
*/
#define CSI_BRIG_VADR_NUM_GT_INT_ENA (BIT(0))
#define CSI_BRIG_VADR_NUM_GT_INT_ENA_M (CSI_BRIG_VADR_NUM_GT_INT_ENA_V << CSI_BRIG_VADR_NUM_GT_INT_ENA_S)
#define CSI_BRIG_VADR_NUM_GT_INT_ENA_V 0x00000001U
#define CSI_BRIG_VADR_NUM_GT_INT_ENA_S 0
/** CSI_BRIG_VADR_NUM_LT_INT_ENA : R/W; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt enable.
*/
#define CSI_BRIG_VADR_NUM_LT_INT_ENA (BIT(1))
#define CSI_BRIG_VADR_NUM_LT_INT_ENA_M (CSI_BRIG_VADR_NUM_LT_INT_ENA_V << CSI_BRIG_VADR_NUM_LT_INT_ENA_S)
#define CSI_BRIG_VADR_NUM_LT_INT_ENA_V 0x00000001U
#define CSI_BRIG_VADR_NUM_LT_INT_ENA_S 1
/** CSI_BRIG_DISCARD_INT_ENA : R/W; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt enable.
*/
#define CSI_BRIG_DISCARD_INT_ENA (BIT(2))
#define CSI_BRIG_DISCARD_INT_ENA_M (CSI_BRIG_DISCARD_INT_ENA_V << CSI_BRIG_DISCARD_INT_ENA_S)
#define CSI_BRIG_DISCARD_INT_ENA_V 0x00000001U
#define CSI_BRIG_DISCARD_INT_ENA_S 2
/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
* buffer overrun interrupt enable.
*/
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA (BIT(3))
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S)
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V 0x00000001U
#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S 3
/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
* buffer overflow interrupt enable.
*/
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA (BIT(4))
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S)
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V 0x00000001U
#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S 4
/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA : R/W; bitpos: [5]; default: 0;
* dma configuration update complete interrupt enable.
*/
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA (BIT(5))
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S)
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V 0x00000001U
#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S 5
/** CSI_BRIG_DMA_REQ_INTERVAL_REG register
* DMA interval configuration.
*/
#define CSI_BRIG_DMA_REQ_INTERVAL_REG (DR_REG_CSI_BRIG_BASE + 0x2c)
/** CSI_BRIG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1;
* 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
*/
#define CSI_BRIG_DMA_REQ_INTERVAL 0x0000FFFFU
#define CSI_BRIG_DMA_REQ_INTERVAL_M (CSI_BRIG_DMA_REQ_INTERVAL_V << CSI_BRIG_DMA_REQ_INTERVAL_S)
#define CSI_BRIG_DMA_REQ_INTERVAL_V 0x0000FFFFU
#define CSI_BRIG_DMA_REQ_INTERVAL_S 0
/** CSI_BRIG_DMABLK_SIZE_REG register
* DMA block size configuration.
*/
#define CSI_BRIG_DMABLK_SIZE_REG (DR_REG_CSI_BRIG_BASE + 0x30)
/** CSI_BRIG_DMABLK_SIZE : R/W; bitpos: [12:0]; default: 8191;
* the number of reg_dma_burst_len in a block
*/
#define CSI_BRIG_DMABLK_SIZE 0x00001FFFU
#define CSI_BRIG_DMABLK_SIZE_M (CSI_BRIG_DMABLK_SIZE_V << CSI_BRIG_DMABLK_SIZE_S)
#define CSI_BRIG_DMABLK_SIZE_V 0x00001FFFU
#define CSI_BRIG_DMABLK_SIZE_S 0
/** CSI_BRIG_HOST_CTRL_REG register
* csi host control by csi bridge.
*/
#define CSI_BRIG_HOST_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x40)
/** CSI_BRIG_CSI_ENABLECLK : R/W; bitpos: [0]; default: 1;
* enable clock lane module of csi phy.
*/
#define CSI_BRIG_CSI_ENABLECLK (BIT(0))
#define CSI_BRIG_CSI_ENABLECLK_M (CSI_BRIG_CSI_ENABLECLK_V << CSI_BRIG_CSI_ENABLECLK_S)
#define CSI_BRIG_CSI_ENABLECLK_V 0x00000001U
#define CSI_BRIG_CSI_ENABLECLK_S 0
/** CSI_BRIG_CSI_CFG_CLK_EN : R/W; bitpos: [1]; default: 1;
* enable cfg_clk of csi host module.
*/
#define CSI_BRIG_CSI_CFG_CLK_EN (BIT(1))
#define CSI_BRIG_CSI_CFG_CLK_EN_M (CSI_BRIG_CSI_CFG_CLK_EN_V << CSI_BRIG_CSI_CFG_CLK_EN_S)
#define CSI_BRIG_CSI_CFG_CLK_EN_V 0x00000001U
#define CSI_BRIG_CSI_CFG_CLK_EN_S 1
/** CSI_BRIG_LOOPBK_TEST_EN : R/W; bitpos: [2]; default: 0;
* for phy test by loopback dsi phy to csi phy.
*/
#define CSI_BRIG_LOOPBK_TEST_EN (BIT(2))
#define CSI_BRIG_LOOPBK_TEST_EN_M (CSI_BRIG_LOOPBK_TEST_EN_V << CSI_BRIG_LOOPBK_TEST_EN_S)
#define CSI_BRIG_LOOPBK_TEST_EN_V 0x00000001U
#define CSI_BRIG_LOOPBK_TEST_EN_S 2
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: csi bridge regbank clock gating control register. */
/** Type of clk_en register
* csi bridge register mapping unit clock gating.
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* 0: enable clock gating. 1: disable clock gating, clock always on.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} csi_brig_clk_en_reg_t;
/** Group: csi bridge control registers. */
/** Type of csi_en register
* csi bridge enable.
*/
typedef union {
struct {
/** csi_brig_en : R/W; bitpos: [0]; default: 0;
* 0: disable csi bridge. 1: enable csi bridge.
*/
uint32_t csi_brig_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} csi_brig_csi_en_reg_t;
/** Type of buf_flow_ctl register
* csi bridge buffer control.
*/
typedef union {
struct {
/** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040;
* buffer almost full threshold.
*/
uint32_t csi_buf_afull_thrd:14;
uint32_t reserved_14:2;
/** csi_buf_depth : RO; bitpos: [29:16]; default: 0;
* buffer data count.
*/
uint32_t csi_buf_depth:14;
uint32_t reserved_30:2;
};
uint32_t val;
} csi_brig_buf_flow_ctl_reg_t;
/** Group: csi bridge dma control registers. */
/** Type of dma_req_cfg register
* dma request configuration.
*/
typedef union {
struct {
/** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
* DMA burst length.
*/
uint32_t dma_burst_len:12;
/** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
* 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
* updated by frame.
*/
uint32_t dma_cfg_upd_by_blk:1;
uint32_t reserved_13:3;
/** dma_force_rd_status : R/W; bitpos: [16]; default: 0;
* 1: mask dma request when reading frame info. 0: disable mask.
*/
uint32_t dma_force_rd_status:1;
uint32_t reserved_17:15;
};
uint32_t val;
} csi_brig_dma_req_cfg_reg_t;
/** Type of dma_req_interval register
* DMA interval configuration.
*/
typedef union {
struct {
/** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
* 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
*/
uint32_t dma_req_interval:16;
uint32_t reserved_16:16;
};
uint32_t val;
} csi_brig_dma_req_interval_reg_t;
/** Type of dmablk_size register
* DMA block size configuration.
*/
typedef union {
struct {
/** dmablk_size : R/W; bitpos: [12:0]; default: 8191;
* the number of reg_dma_burst_len in a block
*/
uint32_t dmablk_size:13;
uint32_t reserved_13:19;
};
uint32_t val;
} csi_brig_dmablk_size_reg_t;
/** Group: csi bridge frame format configuration registers. */
/** Type of data_type_cfg register
* pixel data type configuration.
*/
typedef union {
struct {
/** data_type_min : R/W; bitpos: [5:0]; default: 24;
* the min value of data type used for pixel filter.
*/
uint32_t data_type_min:6;
uint32_t reserved_6:2;
/** data_type_max : R/W; bitpos: [13:8]; default: 47;
* the max value of data type used for pixel filter.
*/
uint32_t data_type_max:6;
uint32_t reserved_14:18;
};
uint32_t val;
} csi_brig_data_type_cfg_reg_t;
/** Type of frame_cfg register
* frame configuration.
*/
typedef union {
struct {
/** vadr_num : R/W; bitpos: [11:0]; default: 480;
* vadr of frame data.
*/
uint32_t vadr_num:12;
/** hadr_num : R/W; bitpos: [23:12]; default: 480;
* hadr of frame data.
*/
uint32_t hadr_num:12;
/** has_hsync_e : R/W; bitpos: [24]; default: 1;
* 0: frame data doesn't contain hsync. 1: frame data contains hsync.
*/
uint32_t has_hsync_e:1;
/** vadr_num_check : R/W; bitpos: [25]; default: 0;
* 0: disable vadr check. 1: enable vadr check.
*/
uint32_t vadr_num_check:1;
uint32_t reserved_26:6;
};
uint32_t val;
} csi_brig_frame_cfg_reg_t;
/** Type of endian_mode register
* data endianness order configuration.
*/
typedef union {
struct {
/** byte_endian_order : R/W; bitpos: [0]; default: 0;
* endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
* when isp is bapassed.
*/
uint32_t byte_endian_order:1;
/** bit_endian_order : R/W; bitpos: [1]; default: 0;
* N/A
*/
uint32_t bit_endian_order:1;
uint32_t reserved_2:30;
};
uint32_t val;
} csi_brig_endian_mode_reg_t;
/** Group: csi bridge interrupt registers. */
/** Type of int_raw register
* csi bridge interrupt raw.
*/
typedef union {
struct {
/** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt raw.
*/
uint32_t vadr_num_gt_int_raw:1;
/** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt raw.
*/
uint32_t vadr_num_lt_int_raw:1;
/** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt raw.
*/
uint32_t discard_int_raw:1;
/** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* buffer overrun interrupt raw.
*/
uint32_t csi_buf_overrun_int_raw:1;
/** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* buffer overflow interrupt raw.
*/
uint32_t csi_async_fifo_ovf_int_raw:1;
/** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* dma configuration update complete interrupt raw.
*/
uint32_t dma_cfg_has_updated_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} csi_brig_int_raw_reg_t;
/** Type of int_clr register
* csi bridge interrupt clr.
*/
typedef union {
struct {
/** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt clr.
*/
uint32_t vadr_num_gt_real_int_clr:1;
/** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt clr.
*/
uint32_t vadr_num_lt_real_int_clr:1;
/** discard_int_clr : WT; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt clr.
*/
uint32_t discard_int_clr:1;
/** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0;
* buffer overrun interrupt clr.
*/
uint32_t csi_buf_overrun_int_clr:1;
/** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
* buffer overflow interrupt clr.
*/
uint32_t csi_async_fifo_ovf_int_clr:1;
/** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0;
* dma configuration update complete interrupt clr.
*/
uint32_t dma_cfg_has_updated_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} csi_brig_int_clr_reg_t;
/** Type of int_st register
* csi bridge interrupt st.
*/
typedef union {
struct {
/** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt st.
*/
uint32_t vadr_num_gt_int_st:1;
/** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt st.
*/
uint32_t vadr_num_lt_int_st:1;
/** discard_int_st : RO; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt st.
*/
uint32_t discard_int_st:1;
/** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0;
* buffer overrun interrupt st.
*/
uint32_t csi_buf_overrun_int_st:1;
/** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0;
* buffer overflow interrupt st.
*/
uint32_t csi_async_fifo_ovf_int_st:1;
/** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0;
* dma configuration update complete interrupt st.
*/
uint32_t dma_cfg_has_updated_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} csi_brig_int_st_reg_t;
/** Type of int_ena register
* csi bridge interrupt enable.
*/
typedef union {
struct {
/** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0;
* reg_vadr_num is greater than real interrupt enable.
*/
uint32_t vadr_num_gt_int_ena:1;
/** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0;
* reg_vadr_num is less than real interrupt enable.
*/
uint32_t vadr_num_lt_int_ena:1;
/** discard_int_ena : R/W; bitpos: [2]; default: 0;
* an incomplete frame of data was sent interrupt enable.
*/
uint32_t discard_int_ena:1;
/** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0;
* buffer overrun interrupt enable.
*/
uint32_t csi_buf_overrun_int_ena:1;
/** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
* buffer overflow interrupt enable.
*/
uint32_t csi_async_fifo_ovf_int_ena:1;
/** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0;
* dma configuration update complete interrupt enable.
*/
uint32_t dma_cfg_has_updated_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} csi_brig_int_ena_reg_t;
/** Group: csi-host control registers from csi bridge regbank. */
/** Type of host_ctrl register
* csi host control by csi bridge.
*/
typedef union {
struct {
/** csi_enableclk : R/W; bitpos: [0]; default: 1;
* enable clock lane module of csi phy.
*/
uint32_t csi_enableclk:1;
/** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
* enable cfg_clk of csi host module.
*/
uint32_t csi_cfg_clk_en:1;
/** loopbk_test_en : R/W; bitpos: [2]; default: 0;
* for phy test by loopback dsi phy to csi phy.
*/
uint32_t loopbk_test_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} csi_brig_host_ctrl_reg_t;
typedef struct {
volatile csi_brig_clk_en_reg_t clk_en;
volatile csi_brig_csi_en_reg_t csi_en;
volatile csi_brig_dma_req_cfg_reg_t dma_req_cfg;
volatile csi_brig_buf_flow_ctl_reg_t buf_flow_ctl;
volatile csi_brig_data_type_cfg_reg_t data_type_cfg;
volatile csi_brig_frame_cfg_reg_t frame_cfg;
volatile csi_brig_endian_mode_reg_t endian_mode;
volatile csi_brig_int_raw_reg_t int_raw;
volatile csi_brig_int_clr_reg_t int_clr;
volatile csi_brig_int_st_reg_t int_st;
volatile csi_brig_int_ena_reg_t int_ena;
volatile csi_brig_dma_req_interval_reg_t dma_req_interval;
volatile csi_brig_dmablk_size_reg_t dmablk_size;
uint32_t reserved_034[3];
volatile csi_brig_host_ctrl_reg_t host_ctrl;
} csi_brig_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(csi_brig_dev_t) == 0x44, "Invalid size of csi_brig_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DSI_BRG_CLK_EN_REG register
* dsi bridge clk control register
*/
#define DSI_BRG_CLK_EN_REG (DR_REG_DSI_BRG_BASE + 0x0)
/** DSI_BRG_CLK_EN : R/W; bitpos: [0]; default: 0;
* this bit configures force_on of dsi_bridge register clock gate
*/
#define DSI_BRG_CLK_EN (BIT(0))
#define DSI_BRG_CLK_EN_M (DSI_BRG_CLK_EN_V << DSI_BRG_CLK_EN_S)
#define DSI_BRG_CLK_EN_V 0x00000001U
#define DSI_BRG_CLK_EN_S 0
/** DSI_BRG_EN_REG register
* dsi bridge en register
*/
#define DSI_BRG_EN_REG (DR_REG_DSI_BRG_BASE + 0x4)
/** DSI_BRG_DSI_EN : R/W; bitpos: [0]; default: 0;
* this bit configures module enable of dsi_bridge. 0: disable, 1: enable
*/
#define DSI_BRG_DSI_EN (BIT(0))
#define DSI_BRG_DSI_EN_M (DSI_BRG_DSI_EN_V << DSI_BRG_DSI_EN_S)
#define DSI_BRG_DSI_EN_V 0x00000001U
#define DSI_BRG_DSI_EN_S 0
/** DSI_BRG_DMA_REQ_CFG_REG register
* dsi bridge dma burst len register
*/
#define DSI_BRG_DMA_REQ_CFG_REG (DR_REG_DSI_BRG_BASE + 0x8)
/** DSI_BRG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128;
* this field configures the num of 64-bit in one dma burst transfer, valid only when
* dsi_bridge as flow controller
*/
#define DSI_BRG_DMA_BURST_LEN 0x00000FFFU
#define DSI_BRG_DMA_BURST_LEN_M (DSI_BRG_DMA_BURST_LEN_V << DSI_BRG_DMA_BURST_LEN_S)
#define DSI_BRG_DMA_BURST_LEN_V 0x00000FFFU
#define DSI_BRG_DMA_BURST_LEN_S 0
/** DSI_BRG_RAW_NUM_CFG_REG register
* dsi bridge raw number control register
*/
#define DSI_BRG_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0xc)
/** DSI_BRG_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400;
* this field configures number of total pix bits/64
*/
#define DSI_BRG_RAW_NUM_TOTAL 0x003FFFFFU
#define DSI_BRG_RAW_NUM_TOTAL_M (DSI_BRG_RAW_NUM_TOTAL_V << DSI_BRG_RAW_NUM_TOTAL_S)
#define DSI_BRG_RAW_NUM_TOTAL_V 0x003FFFFFU
#define DSI_BRG_RAW_NUM_TOTAL_S 0
/** DSI_BRG_UNALIGN_64BIT_EN : R/W; bitpos: [22]; default: 0;
* this field configures whether the total pix bits is a multiple of 64bits. 0: align
* to 64-bit, 1: unalign to 64-bit
*/
#define DSI_BRG_UNALIGN_64BIT_EN (BIT(22))
#define DSI_BRG_UNALIGN_64BIT_EN_M (DSI_BRG_UNALIGN_64BIT_EN_V << DSI_BRG_UNALIGN_64BIT_EN_S)
#define DSI_BRG_UNALIGN_64BIT_EN_V 0x00000001U
#define DSI_BRG_UNALIGN_64BIT_EN_S 22
/** DSI_BRG_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
* this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
* 1: enable. valid only when dsi_bridge as flow controller
*/
#define DSI_BRG_RAW_NUM_TOTAL_SET (BIT(31))
#define DSI_BRG_RAW_NUM_TOTAL_SET_M (DSI_BRG_RAW_NUM_TOTAL_SET_V << DSI_BRG_RAW_NUM_TOTAL_SET_S)
#define DSI_BRG_RAW_NUM_TOTAL_SET_V 0x00000001U
#define DSI_BRG_RAW_NUM_TOTAL_SET_S 31
/** DSI_BRG_RAW_BUF_CREDIT_CTL_REG register
* dsi bridge credit register
*/
#define DSI_BRG_RAW_BUF_CREDIT_CTL_REG (DR_REG_DSI_BRG_BASE + 0x10)
/** DSI_BRG_CREDIT_THRD : R/W; bitpos: [14:0]; default: 1024;
* this field configures the threshold whether dsi_bridge fifo can receive one more
* 64-bit, valid only when dsi_bridge as flow controller
*/
#define DSI_BRG_CREDIT_THRD 0x00007FFFU
#define DSI_BRG_CREDIT_THRD_M (DSI_BRG_CREDIT_THRD_V << DSI_BRG_CREDIT_THRD_S)
#define DSI_BRG_CREDIT_THRD_V 0x00007FFFU
#define DSI_BRG_CREDIT_THRD_S 0
/** DSI_BRG_CREDIT_BURST_THRD : R/W; bitpos: [30:16]; default: 800;
* this field configures the threshold whether dsi_bridge fifo can receive one more
* dma burst, valid only when dsi_bridge as flow controller
*/
#define DSI_BRG_CREDIT_BURST_THRD 0x00007FFFU
#define DSI_BRG_CREDIT_BURST_THRD_M (DSI_BRG_CREDIT_BURST_THRD_V << DSI_BRG_CREDIT_BURST_THRD_S)
#define DSI_BRG_CREDIT_BURST_THRD_V 0x00007FFFU
#define DSI_BRG_CREDIT_BURST_THRD_S 16
/** DSI_BRG_CREDIT_RESET : R/W; bitpos: [31]; default: 0;
* this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
* dsi_bridge as flow controller
*/
#define DSI_BRG_CREDIT_RESET (BIT(31))
#define DSI_BRG_CREDIT_RESET_M (DSI_BRG_CREDIT_RESET_V << DSI_BRG_CREDIT_RESET_S)
#define DSI_BRG_CREDIT_RESET_V 0x00000001U
#define DSI_BRG_CREDIT_RESET_S 31
/** DSI_BRG_FIFO_FLOW_STATUS_REG register
* dsi bridge raw buffer depth register
*/
#define DSI_BRG_FIFO_FLOW_STATUS_REG (DR_REG_DSI_BRG_BASE + 0x14)
/** DSI_BRG_RAW_BUF_DEPTH : RO; bitpos: [13:0]; default: 0;
* this field configures the depth of dsi_bridge fifo depth
*/
#define DSI_BRG_RAW_BUF_DEPTH 0x00003FFFU
#define DSI_BRG_RAW_BUF_DEPTH_M (DSI_BRG_RAW_BUF_DEPTH_V << DSI_BRG_RAW_BUF_DEPTH_S)
#define DSI_BRG_RAW_BUF_DEPTH_V 0x00003FFFU
#define DSI_BRG_RAW_BUF_DEPTH_S 0
/** DSI_BRG_PIXEL_TYPE_REG register
* dsi bridge dpi type control register
*/
#define DSI_BRG_PIXEL_TYPE_REG (DR_REG_DSI_BRG_BASE + 0x18)
/** DSI_BRG_RAW_TYPE : R/W; bitpos: [3:0]; default: 0;
* this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565
*/
#define DSI_BRG_RAW_TYPE 0x0000000FU
#define DSI_BRG_RAW_TYPE_M (DSI_BRG_RAW_TYPE_V << DSI_BRG_RAW_TYPE_S)
#define DSI_BRG_RAW_TYPE_V 0x0000000FU
#define DSI_BRG_RAW_TYPE_S 0
/** DSI_BRG_DPI_CONFIG : R/W; bitpos: [5:4]; default: 0;
* this field configures the pixel arrange type of dpi interface
*/
#define DSI_BRG_DPI_CONFIG 0x00000003U
#define DSI_BRG_DPI_CONFIG_M (DSI_BRG_DPI_CONFIG_V << DSI_BRG_DPI_CONFIG_S)
#define DSI_BRG_DPI_CONFIG_V 0x00000003U
#define DSI_BRG_DPI_CONFIG_S 4
/** DSI_BRG_DATA_IN_TYPE : R/W; bitpos: [6]; default: 0;
* input data type, 0: rgb, 1: yuv
*/
#define DSI_BRG_DATA_IN_TYPE (BIT(6))
#define DSI_BRG_DATA_IN_TYPE_M (DSI_BRG_DATA_IN_TYPE_V << DSI_BRG_DATA_IN_TYPE_S)
#define DSI_BRG_DATA_IN_TYPE_V 0x00000001U
#define DSI_BRG_DATA_IN_TYPE_S 6
/** DSI_BRG_DMA_BLOCK_INTERVAL_REG register
* dsi bridge dma block interval control register
*/
#define DSI_BRG_DMA_BLOCK_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x1c)
/** DSI_BRG_DMA_BLOCK_SLOT : R/W; bitpos: [9:0]; default: 9;
* this field configures the max block_slot_cnt
*/
#define DSI_BRG_DMA_BLOCK_SLOT 0x000003FFU
#define DSI_BRG_DMA_BLOCK_SLOT_M (DSI_BRG_DMA_BLOCK_SLOT_V << DSI_BRG_DMA_BLOCK_SLOT_S)
#define DSI_BRG_DMA_BLOCK_SLOT_V 0x000003FFU
#define DSI_BRG_DMA_BLOCK_SLOT_S 0
/** DSI_BRG_DMA_BLOCK_INTERVAL : R/W; bitpos: [27:10]; default: 9;
* this field configures the max block_interval_cnt, block_interval_cnt increased by 1
* when block_slot_cnt if full
*/
#define DSI_BRG_DMA_BLOCK_INTERVAL 0x0003FFFFU
#define DSI_BRG_DMA_BLOCK_INTERVAL_M (DSI_BRG_DMA_BLOCK_INTERVAL_V << DSI_BRG_DMA_BLOCK_INTERVAL_S)
#define DSI_BRG_DMA_BLOCK_INTERVAL_V 0x0003FFFFU
#define DSI_BRG_DMA_BLOCK_INTERVAL_S 10
/** DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD : R/W; bitpos: [28]; default: 1;
* this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
*/
#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD (BIT(28))
#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_M (DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V << DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S)
#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V 0x00000001U
#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S 28
/** DSI_BRG_DMA_BLOCK_INTERVAL_EN : R/W; bitpos: [29]; default: 1;
* this bit configures enable of interval between dma block transfer, 0: disable, 1:
* enable
*/
#define DSI_BRG_DMA_BLOCK_INTERVAL_EN (BIT(29))
#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_M (DSI_BRG_DMA_BLOCK_INTERVAL_EN_V << DSI_BRG_DMA_BLOCK_INTERVAL_EN_S)
#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_V 0x00000001U
#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_S 29
/** DSI_BRG_DMA_REQ_INTERVAL_REG register
* dsi bridge dma req interval control register
*/
#define DSI_BRG_DMA_REQ_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x20)
/** DSI_BRG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1;
* this field configures the interval between dma req events
*/
#define DSI_BRG_DMA_REQ_INTERVAL 0x0000FFFFU
#define DSI_BRG_DMA_REQ_INTERVAL_M (DSI_BRG_DMA_REQ_INTERVAL_V << DSI_BRG_DMA_REQ_INTERVAL_S)
#define DSI_BRG_DMA_REQ_INTERVAL_V 0x0000FFFFU
#define DSI_BRG_DMA_REQ_INTERVAL_S 0
/** DSI_BRG_DPI_LCD_CTL_REG register
* dsi bridge dpi signal control register
*/
#define DSI_BRG_DPI_LCD_CTL_REG (DR_REG_DSI_BRG_BASE + 0x24)
/** DSI_BRG_DPISHUTDN : R/W; bitpos: [0]; default: 0;
* this bit configures dpishutdn signal in dpi interface
*/
#define DSI_BRG_DPISHUTDN (BIT(0))
#define DSI_BRG_DPISHUTDN_M (DSI_BRG_DPISHUTDN_V << DSI_BRG_DPISHUTDN_S)
#define DSI_BRG_DPISHUTDN_V 0x00000001U
#define DSI_BRG_DPISHUTDN_S 0
/** DSI_BRG_DPICOLORM : R/W; bitpos: [1]; default: 0;
* this bit configures dpicolorm signal in dpi interface
*/
#define DSI_BRG_DPICOLORM (BIT(1))
#define DSI_BRG_DPICOLORM_M (DSI_BRG_DPICOLORM_V << DSI_BRG_DPICOLORM_S)
#define DSI_BRG_DPICOLORM_V 0x00000001U
#define DSI_BRG_DPICOLORM_S 1
/** DSI_BRG_DPIUPDATECFG : R/W; bitpos: [2]; default: 0;
* this bit configures dpiupdatecfg signal in dpi interface
*/
#define DSI_BRG_DPIUPDATECFG (BIT(2))
#define DSI_BRG_DPIUPDATECFG_M (DSI_BRG_DPIUPDATECFG_V << DSI_BRG_DPIUPDATECFG_S)
#define DSI_BRG_DPIUPDATECFG_V 0x00000001U
#define DSI_BRG_DPIUPDATECFG_S 2
/** DSI_BRG_DPI_RSV_DPI_DATA_REG register
* dsi bridge dpi reserved data register
*/
#define DSI_BRG_DPI_RSV_DPI_DATA_REG (DR_REG_DSI_BRG_BASE + 0x28)
/** DSI_BRG_DPI_RSV_DATA : R/W; bitpos: [29:0]; default: 16383;
* this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
*/
#define DSI_BRG_DPI_RSV_DATA 0x3FFFFFFFU
#define DSI_BRG_DPI_RSV_DATA_M (DSI_BRG_DPI_RSV_DATA_V << DSI_BRG_DPI_RSV_DATA_S)
#define DSI_BRG_DPI_RSV_DATA_V 0x3FFFFFFFU
#define DSI_BRG_DPI_RSV_DATA_S 0
/** DSI_BRG_DPI_V_CFG0_REG register
* dsi bridge dpi v config register 0
*/
#define DSI_BRG_DPI_V_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x30)
/** DSI_BRG_VTOTAL : R/W; bitpos: [11:0]; default: 525;
* this field configures the total length of one frame (by line) for dpi output, must
* meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
*/
#define DSI_BRG_VTOTAL 0x00000FFFU
#define DSI_BRG_VTOTAL_M (DSI_BRG_VTOTAL_V << DSI_BRG_VTOTAL_S)
#define DSI_BRG_VTOTAL_V 0x00000FFFU
#define DSI_BRG_VTOTAL_S 0
/** DSI_BRG_VDISP : R/W; bitpos: [27:16]; default: 480;
* this field configures the length of valid line (by line) for dpi output
*/
#define DSI_BRG_VDISP 0x00000FFFU
#define DSI_BRG_VDISP_M (DSI_BRG_VDISP_V << DSI_BRG_VDISP_S)
#define DSI_BRG_VDISP_V 0x00000FFFU
#define DSI_BRG_VDISP_S 16
/** DSI_BRG_DPI_V_CFG1_REG register
* dsi bridge dpi v config register 1
*/
#define DSI_BRG_DPI_V_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x34)
/** DSI_BRG_VBANK : R/W; bitpos: [11:0]; default: 33;
* this field configures the length between vsync and valid line (by line) for dpi
* output
*/
#define DSI_BRG_VBANK 0x00000FFFU
#define DSI_BRG_VBANK_M (DSI_BRG_VBANK_V << DSI_BRG_VBANK_S)
#define DSI_BRG_VBANK_V 0x00000FFFU
#define DSI_BRG_VBANK_S 0
/** DSI_BRG_VSYNC : R/W; bitpos: [27:16]; default: 2;
* this field configures the length of vsync (by line) for dpi output
*/
#define DSI_BRG_VSYNC 0x00000FFFU
#define DSI_BRG_VSYNC_M (DSI_BRG_VSYNC_V << DSI_BRG_VSYNC_S)
#define DSI_BRG_VSYNC_V 0x00000FFFU
#define DSI_BRG_VSYNC_S 16
/** DSI_BRG_DPI_H_CFG0_REG register
* dsi bridge dpi h config register 0
*/
#define DSI_BRG_DPI_H_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x38)
/** DSI_BRG_HTOTAL : R/W; bitpos: [11:0]; default: 800;
* this field configures the total length of one line (by pixel num) for dpi output,
* must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
*/
#define DSI_BRG_HTOTAL 0x00000FFFU
#define DSI_BRG_HTOTAL_M (DSI_BRG_HTOTAL_V << DSI_BRG_HTOTAL_S)
#define DSI_BRG_HTOTAL_V 0x00000FFFU
#define DSI_BRG_HTOTAL_S 0
/** DSI_BRG_HDISP : R/W; bitpos: [27:16]; default: 640;
* this field configures the length of valid pixel data (by pixel num) for dpi output
*/
#define DSI_BRG_HDISP 0x00000FFFU
#define DSI_BRG_HDISP_M (DSI_BRG_HDISP_V << DSI_BRG_HDISP_S)
#define DSI_BRG_HDISP_V 0x00000FFFU
#define DSI_BRG_HDISP_S 16
/** DSI_BRG_DPI_H_CFG1_REG register
* dsi bridge dpi h config register 1
*/
#define DSI_BRG_DPI_H_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x3c)
/** DSI_BRG_HBANK : R/W; bitpos: [11:0]; default: 48;
* this field configures the length between hsync and pixel data valid (by pixel num)
* for dpi output
*/
#define DSI_BRG_HBANK 0x00000FFFU
#define DSI_BRG_HBANK_M (DSI_BRG_HBANK_V << DSI_BRG_HBANK_S)
#define DSI_BRG_HBANK_V 0x00000FFFU
#define DSI_BRG_HBANK_S 0
/** DSI_BRG_HSYNC : R/W; bitpos: [27:16]; default: 96;
* this field configures the length of hsync (by pixel num) for dpi output
*/
#define DSI_BRG_HSYNC 0x00000FFFU
#define DSI_BRG_HSYNC_M (DSI_BRG_HSYNC_V << DSI_BRG_HSYNC_S)
#define DSI_BRG_HSYNC_V 0x00000FFFU
#define DSI_BRG_HSYNC_S 16
/** DSI_BRG_DPI_MISC_CONFIG_REG register
* dsi_bridge dpi misc config register
*/
#define DSI_BRG_DPI_MISC_CONFIG_REG (DR_REG_DSI_BRG_BASE + 0x40)
/** DSI_BRG_DPI_EN : R/W; bitpos: [0]; default: 0;
* this bit configures enable of dpi output, 0: disable, 1: enable
*/
#define DSI_BRG_DPI_EN (BIT(0))
#define DSI_BRG_DPI_EN_M (DSI_BRG_DPI_EN_V << DSI_BRG_DPI_EN_S)
#define DSI_BRG_DPI_EN_V 0x00000001U
#define DSI_BRG_DPI_EN_S 0
/** DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT : R/W; bitpos: [15:4]; default: 413;
* this field configures the underrun interrupt musk, when underrun occurs and line
* cnt is less then this field
*/
#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT 0x00000FFFU
#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_M (DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V << DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S)
#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V 0x00000FFFU
#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S 4
/** DSI_BRG_DPI_CONFIG_UPDATE_REG register
* dsi_bridge dpi config update register
*/
#define DSI_BRG_DPI_CONFIG_UPDATE_REG (DR_REG_DSI_BRG_BASE + 0x44)
/** DSI_BRG_DPI_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
* write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
*/
#define DSI_BRG_DPI_CONFIG_UPDATE (BIT(0))
#define DSI_BRG_DPI_CONFIG_UPDATE_M (DSI_BRG_DPI_CONFIG_UPDATE_V << DSI_BRG_DPI_CONFIG_UPDATE_S)
#define DSI_BRG_DPI_CONFIG_UPDATE_V 0x00000001U
#define DSI_BRG_DPI_CONFIG_UPDATE_S 0
/** DSI_BRG_INT_ENA_REG register
* dsi_bridge interrupt enable register
*/
#define DSI_BRG_INT_ENA_REG (DR_REG_DSI_BRG_BASE + 0x50)
/** DSI_BRG_UNDERRUN_INT_ENA : R/W; bitpos: [0]; default: 0;
* write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
* by dpi_underrun interrupt signal
*/
#define DSI_BRG_UNDERRUN_INT_ENA (BIT(0))
#define DSI_BRG_UNDERRUN_INT_ENA_M (DSI_BRG_UNDERRUN_INT_ENA_V << DSI_BRG_UNDERRUN_INT_ENA_S)
#define DSI_BRG_UNDERRUN_INT_ENA_V 0x00000001U
#define DSI_BRG_UNDERRUN_INT_ENA_S 0
/** DSI_BRG_INT_CLR_REG register
* dsi_bridge interrupt clear register
*/
#define DSI_BRG_INT_CLR_REG (DR_REG_DSI_BRG_BASE + 0x54)
/** DSI_BRG_UNDERRUN_INT_CLR : WT; bitpos: [0]; default: 0;
* write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
*/
#define DSI_BRG_UNDERRUN_INT_CLR (BIT(0))
#define DSI_BRG_UNDERRUN_INT_CLR_M (DSI_BRG_UNDERRUN_INT_CLR_V << DSI_BRG_UNDERRUN_INT_CLR_S)
#define DSI_BRG_UNDERRUN_INT_CLR_V 0x00000001U
#define DSI_BRG_UNDERRUN_INT_CLR_S 0
/** DSI_BRG_INT_RAW_REG register
* dsi_bridge raw interrupt register
*/
#define DSI_BRG_INT_RAW_REG (DR_REG_DSI_BRG_BASE + 0x58)
/** DSI_BRG_UNDERRUN_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* the raw interrupt status of dpi_underrun
*/
#define DSI_BRG_UNDERRUN_INT_RAW (BIT(0))
#define DSI_BRG_UNDERRUN_INT_RAW_M (DSI_BRG_UNDERRUN_INT_RAW_V << DSI_BRG_UNDERRUN_INT_RAW_S)
#define DSI_BRG_UNDERRUN_INT_RAW_V 0x00000001U
#define DSI_BRG_UNDERRUN_INT_RAW_S 0
/** DSI_BRG_INT_ST_REG register
* dsi_bridge masked interrupt register
*/
#define DSI_BRG_INT_ST_REG (DR_REG_DSI_BRG_BASE + 0x5c)
/** DSI_BRG_UNDERRUN_INT_ST : RO; bitpos: [0]; default: 0;
* the masked interrupt status of dpi_underrun
*/
#define DSI_BRG_UNDERRUN_INT_ST (BIT(0))
#define DSI_BRG_UNDERRUN_INT_ST_M (DSI_BRG_UNDERRUN_INT_ST_V << DSI_BRG_UNDERRUN_INT_ST_S)
#define DSI_BRG_UNDERRUN_INT_ST_V 0x00000001U
#define DSI_BRG_UNDERRUN_INT_ST_S 0
/** DSI_BRG_HOST_BIST_CTL_REG register
* dsi_bridge host bist control register
*/
#define DSI_BRG_HOST_BIST_CTL_REG (DR_REG_DSI_BRG_BASE + 0x60)
/** DSI_BRG_BISTOK : RO; bitpos: [0]; default: 0;
* bistok
*/
#define DSI_BRG_BISTOK (BIT(0))
#define DSI_BRG_BISTOK_M (DSI_BRG_BISTOK_V << DSI_BRG_BISTOK_S)
#define DSI_BRG_BISTOK_V 0x00000001U
#define DSI_BRG_BISTOK_S 0
/** DSI_BRG_BISTON : R/W; bitpos: [1]; default: 0;
* biston
*/
#define DSI_BRG_BISTON (BIT(1))
#define DSI_BRG_BISTON_M (DSI_BRG_BISTON_V << DSI_BRG_BISTON_S)
#define DSI_BRG_BISTON_V 0x00000001U
#define DSI_BRG_BISTON_S 1
/** DSI_BRG_HOST_TRIGGER_REV_REG register
* dsi_bridge host trigger reverse control register
*/
#define DSI_BRG_HOST_TRIGGER_REV_REG (DR_REG_DSI_BRG_BASE + 0x64)
/** DSI_BRG_TX_TRIGGER_REV_EN : R/W; bitpos: [0]; default: 0;
* tx_trigger reverse. 0: disable, 1: enable
*/
#define DSI_BRG_TX_TRIGGER_REV_EN (BIT(0))
#define DSI_BRG_TX_TRIGGER_REV_EN_M (DSI_BRG_TX_TRIGGER_REV_EN_V << DSI_BRG_TX_TRIGGER_REV_EN_S)
#define DSI_BRG_TX_TRIGGER_REV_EN_V 0x00000001U
#define DSI_BRG_TX_TRIGGER_REV_EN_S 0
/** DSI_BRG_RX_TRIGGER_REV_EN : R/W; bitpos: [1]; default: 0;
* rx_trigger reverse. 0: disable, 1: enable
*/
#define DSI_BRG_RX_TRIGGER_REV_EN (BIT(1))
#define DSI_BRG_RX_TRIGGER_REV_EN_M (DSI_BRG_RX_TRIGGER_REV_EN_V << DSI_BRG_RX_TRIGGER_REV_EN_S)
#define DSI_BRG_RX_TRIGGER_REV_EN_V 0x00000001U
#define DSI_BRG_RX_TRIGGER_REV_EN_S 1
/** DSI_BRG_BLK_RAW_NUM_CFG_REG register
* dsi_bridge block raw number control register
*/
#define DSI_BRG_BLK_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0x68)
/** DSI_BRG_BLK_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400;
* this field configures number of total block pix bits/64
*/
#define DSI_BRG_BLK_RAW_NUM_TOTAL 0x003FFFFFU
#define DSI_BRG_BLK_RAW_NUM_TOTAL_M (DSI_BRG_BLK_RAW_NUM_TOTAL_V << DSI_BRG_BLK_RAW_NUM_TOTAL_S)
#define DSI_BRG_BLK_RAW_NUM_TOTAL_V 0x003FFFFFU
#define DSI_BRG_BLK_RAW_NUM_TOTAL_S 0
/** DSI_BRG_BLK_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
* write 1 to reload reg_blk_raw_num_total to internal cnt
*/
#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET (BIT(31))
#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_M (DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V << DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S)
#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V 0x00000001U
#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S 31
/** DSI_BRG_DMA_FRAME_INTERVAL_REG register
* dsi_bridge dam frame interval control register
*/
#define DSI_BRG_DMA_FRAME_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x6c)
/** DSI_BRG_DMA_FRAME_SLOT : R/W; bitpos: [9:0]; default: 9;
* this field configures the max frame_slot_cnt
*/
#define DSI_BRG_DMA_FRAME_SLOT 0x000003FFU
#define DSI_BRG_DMA_FRAME_SLOT_M (DSI_BRG_DMA_FRAME_SLOT_V << DSI_BRG_DMA_FRAME_SLOT_S)
#define DSI_BRG_DMA_FRAME_SLOT_V 0x000003FFU
#define DSI_BRG_DMA_FRAME_SLOT_S 0
/** DSI_BRG_DMA_FRAME_INTERVAL : R/W; bitpos: [27:10]; default: 9;
* this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
* when frame_slot_cnt if full
*/
#define DSI_BRG_DMA_FRAME_INTERVAL 0x0003FFFFU
#define DSI_BRG_DMA_FRAME_INTERVAL_M (DSI_BRG_DMA_FRAME_INTERVAL_V << DSI_BRG_DMA_FRAME_INTERVAL_S)
#define DSI_BRG_DMA_FRAME_INTERVAL_V 0x0003FFFFU
#define DSI_BRG_DMA_FRAME_INTERVAL_S 10
/** DSI_BRG_DMA_MULTIBLK_EN : R/W; bitpos: [28]; default: 0;
* this bit configures enable multi-blk transfer, 0: disable, 1: enable
*/
#define DSI_BRG_DMA_MULTIBLK_EN (BIT(28))
#define DSI_BRG_DMA_MULTIBLK_EN_M (DSI_BRG_DMA_MULTIBLK_EN_V << DSI_BRG_DMA_MULTIBLK_EN_S)
#define DSI_BRG_DMA_MULTIBLK_EN_V 0x00000001U
#define DSI_BRG_DMA_MULTIBLK_EN_S 28
/** DSI_BRG_DMA_FRAME_INTERVAL_EN : R/W; bitpos: [29]; default: 1;
* this bit configures enable interval between frame transfer, 0: disable, 1: enable
*/
#define DSI_BRG_DMA_FRAME_INTERVAL_EN (BIT(29))
#define DSI_BRG_DMA_FRAME_INTERVAL_EN_M (DSI_BRG_DMA_FRAME_INTERVAL_EN_V << DSI_BRG_DMA_FRAME_INTERVAL_EN_S)
#define DSI_BRG_DMA_FRAME_INTERVAL_EN_V 0x00000001U
#define DSI_BRG_DMA_FRAME_INTERVAL_EN_S 29
/** DSI_BRG_MEM_AUX_CTRL_REG register
* dsi_bridge mem aux control register
*/
#define DSI_BRG_MEM_AUX_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x70)
/** DSI_BRG_DSI_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
* this field configures dsi_bridge fifo memory aux ctrl
*/
#define DSI_BRG_DSI_MEM_AUX_CTRL 0x00003FFFU
#define DSI_BRG_DSI_MEM_AUX_CTRL_M (DSI_BRG_DSI_MEM_AUX_CTRL_V << DSI_BRG_DSI_MEM_AUX_CTRL_S)
#define DSI_BRG_DSI_MEM_AUX_CTRL_V 0x00003FFFU
#define DSI_BRG_DSI_MEM_AUX_CTRL_S 0
/** DSI_BRG_RDN_ECO_CS_REG register
* dsi_bridge rdn eco cs register
*/
#define DSI_BRG_RDN_ECO_CS_REG (DR_REG_DSI_BRG_BASE + 0x74)
/** DSI_BRG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
* rdn_eco_en
*/
#define DSI_BRG_RDN_ECO_EN (BIT(0))
#define DSI_BRG_RDN_ECO_EN_M (DSI_BRG_RDN_ECO_EN_V << DSI_BRG_RDN_ECO_EN_S)
#define DSI_BRG_RDN_ECO_EN_V 0x00000001U
#define DSI_BRG_RDN_ECO_EN_S 0
/** DSI_BRG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
* rdn_eco_result
*/
#define DSI_BRG_RDN_ECO_RESULT (BIT(1))
#define DSI_BRG_RDN_ECO_RESULT_M (DSI_BRG_RDN_ECO_RESULT_V << DSI_BRG_RDN_ECO_RESULT_S)
#define DSI_BRG_RDN_ECO_RESULT_V 0x00000001U
#define DSI_BRG_RDN_ECO_RESULT_S 1
/** DSI_BRG_RDN_ECO_LOW_REG register
* dsi_bridge rdn eco all low register
*/
#define DSI_BRG_RDN_ECO_LOW_REG (DR_REG_DSI_BRG_BASE + 0x78)
/** DSI_BRG_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* rdn_eco_low
*/
#define DSI_BRG_RDN_ECO_LOW 0xFFFFFFFFU
#define DSI_BRG_RDN_ECO_LOW_M (DSI_BRG_RDN_ECO_LOW_V << DSI_BRG_RDN_ECO_LOW_S)
#define DSI_BRG_RDN_ECO_LOW_V 0xFFFFFFFFU
#define DSI_BRG_RDN_ECO_LOW_S 0
/** DSI_BRG_RDN_ECO_HIGH_REG register
* dsi_bridge rdn eco all high register
*/
#define DSI_BRG_RDN_ECO_HIGH_REG (DR_REG_DSI_BRG_BASE + 0x7c)
/** DSI_BRG_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* rdn_eco_high
*/
#define DSI_BRG_RDN_ECO_HIGH 0xFFFFFFFFU
#define DSI_BRG_RDN_ECO_HIGH_M (DSI_BRG_RDN_ECO_HIGH_V << DSI_BRG_RDN_ECO_HIGH_S)
#define DSI_BRG_RDN_ECO_HIGH_V 0xFFFFFFFFU
#define DSI_BRG_RDN_ECO_HIGH_S 0
/** DSI_BRG_HOST_CTRL_REG register
* dsi_bridge host control register
*/
#define DSI_BRG_HOST_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x80)
/** DSI_BRG_DSI_CFG_REF_CLK_EN : R/W; bitpos: [0]; default: 1;
* this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
* enable
*/
#define DSI_BRG_DSI_CFG_REF_CLK_EN (BIT(0))
#define DSI_BRG_DSI_CFG_REF_CLK_EN_M (DSI_BRG_DSI_CFG_REF_CLK_EN_V << DSI_BRG_DSI_CFG_REF_CLK_EN_S)
#define DSI_BRG_DSI_CFG_REF_CLK_EN_V 0x00000001U
#define DSI_BRG_DSI_CFG_REF_CLK_EN_S 0
/** DSI_BRG_MEM_CLK_CTRL_REG register
* dsi_bridge mem force on control register
*/
#define DSI_BRG_MEM_CLK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x84)
/** DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
* this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
* force on
*/
#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON (BIT(0))
#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_M (DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S)
#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V 0x00000001U
#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S 0
/** DSI_BRG_DSI_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
* this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
*/
#define DSI_BRG_DSI_MEM_CLK_FORCE_ON (BIT(1))
#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_M (DSI_BRG_DSI_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_MEM_CLK_FORCE_ON_S)
#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_V 0x00000001U
#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_S 1
/** DSI_BRG_DMA_FLOW_CTRL_REG register
* dsi_bridge dma flow controller register
*/
#define DSI_BRG_DMA_FLOW_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x88)
/** DSI_BRG_DSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [0]; default: 1;
* this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
* as flow controller
*/
#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER (BIT(0))
#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_M (DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V << DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S)
#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V 0x00000001U
#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S 0
/** DSI_BRG_DMA_FLOW_MULTIBLK_NUM : R/W; bitpos: [7:4]; default: 1;
* this field configures the num of blocks when multi-blk is enable and dmac as flow
* controller
*/
#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM 0x0000000FU
#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_M (DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V << DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S)
#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V 0x0000000FU
#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S 4
/** DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG register
* dsi_bridge buffer empty threshold register
*/
#define DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG (DR_REG_DSI_BRG_BASE + 0x8c)
/** DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD : R/W; bitpos: [10:0]; default: 512;
* this field configures the fifo almost empty threshold, is valid only when dmac as
* flow controller
*/
#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD 0x000007FFU
#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_M (DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V << DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S)
#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V 0x000007FFU
#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S 0
/** DSI_BRG_YUV_CFG_REG register
* dsi_bridge yuv format config register
*/
#define DSI_BRG_YUV_CFG_REG (DR_REG_DSI_BRG_BASE + 0x90)
/** DSI_BRG_PROTOCAL : R/W; bitpos: [0]; default: 0;
* this bit configures yuv protoocl, 0: bt.601, 1: bt.709
*/
#define DSI_BRG_PROTOCAL (BIT(0))
#define DSI_BRG_PROTOCAL_M (DSI_BRG_PROTOCAL_V << DSI_BRG_PROTOCAL_S)
#define DSI_BRG_PROTOCAL_V 0x00000001U
#define DSI_BRG_PROTOCAL_S 0
/** DSI_BRG_YUV_PIX_ENDIAN : R/W; bitpos: [1]; default: 0;
* this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
*/
#define DSI_BRG_YUV_PIX_ENDIAN (BIT(1))
#define DSI_BRG_YUV_PIX_ENDIAN_M (DSI_BRG_YUV_PIX_ENDIAN_V << DSI_BRG_YUV_PIX_ENDIAN_S)
#define DSI_BRG_YUV_PIX_ENDIAN_V 0x00000001U
#define DSI_BRG_YUV_PIX_ENDIAN_S 1
/** DSI_BRG_YUV422_FORMAT : R/W; bitpos: [3:2]; default: 0;
* this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
*/
#define DSI_BRG_YUV422_FORMAT 0x00000003U
#define DSI_BRG_YUV422_FORMAT_M (DSI_BRG_YUV422_FORMAT_V << DSI_BRG_YUV422_FORMAT_S)
#define DSI_BRG_YUV422_FORMAT_V 0x00000003U
#define DSI_BRG_YUV422_FORMAT_S 2
/** DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG register
* dsi phy lp_loopback test ctrl
*/
#define DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x94)
/** DSI_BRG_PHY_LP_TXDATAESC_1 : R/W; bitpos: [7:0]; default: 0;
* txdataesc_1 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXDATAESC_1 0x000000FFU
#define DSI_BRG_PHY_LP_TXDATAESC_1_M (DSI_BRG_PHY_LP_TXDATAESC_1_V << DSI_BRG_PHY_LP_TXDATAESC_1_S)
#define DSI_BRG_PHY_LP_TXDATAESC_1_V 0x000000FFU
#define DSI_BRG_PHY_LP_TXDATAESC_1_S 0
/** DSI_BRG_PHY_LP_TXREQUESTESC_1 : R/W; bitpos: [8]; default: 0;
* txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXREQUESTESC_1 (BIT(8))
#define DSI_BRG_PHY_LP_TXREQUESTESC_1_M (DSI_BRG_PHY_LP_TXREQUESTESC_1_V << DSI_BRG_PHY_LP_TXREQUESTESC_1_S)
#define DSI_BRG_PHY_LP_TXREQUESTESC_1_V 0x00000001U
#define DSI_BRG_PHY_LP_TXREQUESTESC_1_S 8
/** DSI_BRG_PHY_LP_TXVALIDESC_1 : R/W; bitpos: [9]; default: 0;
* txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXVALIDESC_1 (BIT(9))
#define DSI_BRG_PHY_LP_TXVALIDESC_1_M (DSI_BRG_PHY_LP_TXVALIDESC_1_V << DSI_BRG_PHY_LP_TXVALIDESC_1_S)
#define DSI_BRG_PHY_LP_TXVALIDESC_1_V 0x00000001U
#define DSI_BRG_PHY_LP_TXVALIDESC_1_S 9
/** DSI_BRG_PHY_LP_TXLPDTESC_1 : R/W; bitpos: [10]; default: 0;
* txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXLPDTESC_1 (BIT(10))
#define DSI_BRG_PHY_LP_TXLPDTESC_1_M (DSI_BRG_PHY_LP_TXLPDTESC_1_V << DSI_BRG_PHY_LP_TXLPDTESC_1_S)
#define DSI_BRG_PHY_LP_TXLPDTESC_1_V 0x00000001U
#define DSI_BRG_PHY_LP_TXLPDTESC_1_S 10
/** DSI_BRG_PHY_LP_BASEDIR_1 : R/W; bitpos: [11]; default: 0;
* basedir_1 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_BASEDIR_1 (BIT(11))
#define DSI_BRG_PHY_LP_BASEDIR_1_M (DSI_BRG_PHY_LP_BASEDIR_1_V << DSI_BRG_PHY_LP_BASEDIR_1_S)
#define DSI_BRG_PHY_LP_BASEDIR_1_V 0x00000001U
#define DSI_BRG_PHY_LP_BASEDIR_1_S 11
/** DSI_BRG_PHY_LP_TXDATAESC_0 : R/W; bitpos: [23:16]; default: 0;
* txdataesc_0 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXDATAESC_0 0x000000FFU
#define DSI_BRG_PHY_LP_TXDATAESC_0_M (DSI_BRG_PHY_LP_TXDATAESC_0_V << DSI_BRG_PHY_LP_TXDATAESC_0_S)
#define DSI_BRG_PHY_LP_TXDATAESC_0_V 0x000000FFU
#define DSI_BRG_PHY_LP_TXDATAESC_0_S 16
/** DSI_BRG_PHY_LP_TXREQUESTESC_0 : R/W; bitpos: [24]; default: 0;
* txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXREQUESTESC_0 (BIT(24))
#define DSI_BRG_PHY_LP_TXREQUESTESC_0_M (DSI_BRG_PHY_LP_TXREQUESTESC_0_V << DSI_BRG_PHY_LP_TXREQUESTESC_0_S)
#define DSI_BRG_PHY_LP_TXREQUESTESC_0_V 0x00000001U
#define DSI_BRG_PHY_LP_TXREQUESTESC_0_S 24
/** DSI_BRG_PHY_LP_TXVALIDESC_0 : R/W; bitpos: [25]; default: 0;
* txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXVALIDESC_0 (BIT(25))
#define DSI_BRG_PHY_LP_TXVALIDESC_0_M (DSI_BRG_PHY_LP_TXVALIDESC_0_V << DSI_BRG_PHY_LP_TXVALIDESC_0_S)
#define DSI_BRG_PHY_LP_TXVALIDESC_0_V 0x00000001U
#define DSI_BRG_PHY_LP_TXVALIDESC_0_S 25
/** DSI_BRG_PHY_LP_TXLPDTESC_0 : R/W; bitpos: [26]; default: 0;
* txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_TXLPDTESC_0 (BIT(26))
#define DSI_BRG_PHY_LP_TXLPDTESC_0_M (DSI_BRG_PHY_LP_TXLPDTESC_0_V << DSI_BRG_PHY_LP_TXLPDTESC_0_S)
#define DSI_BRG_PHY_LP_TXLPDTESC_0_V 0x00000001U
#define DSI_BRG_PHY_LP_TXLPDTESC_0_S 26
/** DSI_BRG_PHY_LP_BASEDIR_0 : R/W; bitpos: [27]; default: 0;
* basedir_0 ctrl when enable dsi phy lp_loopback_test
*/
#define DSI_BRG_PHY_LP_BASEDIR_0 (BIT(27))
#define DSI_BRG_PHY_LP_BASEDIR_0_M (DSI_BRG_PHY_LP_BASEDIR_0_V << DSI_BRG_PHY_LP_BASEDIR_0_S)
#define DSI_BRG_PHY_LP_BASEDIR_0_V 0x00000001U
#define DSI_BRG_PHY_LP_BASEDIR_0_S 27
/** DSI_BRG_PHY_LP_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0;
* dsi phy lp_loopback test start check
*/
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK (BIT(28))
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_M (DSI_BRG_PHY_LP_LOOPBACK_CHECK_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_S)
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_V 0x00000001U
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_S 28
/** DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0;
* dsi phy lp_loopback test check done
*/
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE (BIT(29))
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_M (DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S)
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V 0x00000001U
#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S 29
/** DSI_BRG_PHY_LP_LOOPBACK_EN : R/W; bitpos: [30]; default: 0;
* dsi phy lp_loopback ctrl en
*/
#define DSI_BRG_PHY_LP_LOOPBACK_EN (BIT(30))
#define DSI_BRG_PHY_LP_LOOPBACK_EN_M (DSI_BRG_PHY_LP_LOOPBACK_EN_V << DSI_BRG_PHY_LP_LOOPBACK_EN_S)
#define DSI_BRG_PHY_LP_LOOPBACK_EN_V 0x00000001U
#define DSI_BRG_PHY_LP_LOOPBACK_EN_S 30
/** DSI_BRG_PHY_LP_LOOPBACK_OK : RO; bitpos: [31]; default: 0;
* result of dsi phy lp_loopback test
*/
#define DSI_BRG_PHY_LP_LOOPBACK_OK (BIT(31))
#define DSI_BRG_PHY_LP_LOOPBACK_OK_M (DSI_BRG_PHY_LP_LOOPBACK_OK_V << DSI_BRG_PHY_LP_LOOPBACK_OK_S)
#define DSI_BRG_PHY_LP_LOOPBACK_OK_V 0x00000001U
#define DSI_BRG_PHY_LP_LOOPBACK_OK_S 31
/** DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG register
* dsi phy hp_loopback test ctrl
*/
#define DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x98)
/** DSI_BRG_PHY_HS_TXDATAHS_1 : R/W; bitpos: [7:0]; default: 0;
* txdatahs_1 ctrl when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_TXDATAHS_1 0x000000FFU
#define DSI_BRG_PHY_HS_TXDATAHS_1_M (DSI_BRG_PHY_HS_TXDATAHS_1_V << DSI_BRG_PHY_HS_TXDATAHS_1_S)
#define DSI_BRG_PHY_HS_TXDATAHS_1_V 0x000000FFU
#define DSI_BRG_PHY_HS_TXDATAHS_1_S 0
/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_1 : R/W; bitpos: [8]; default: 0;
* txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1 (BIT(8))
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_M (DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S)
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V 0x00000001U
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S 8
/** DSI_BRG_PHY_HS_BASEDIR_1 : R/W; bitpos: [9]; default: 1;
* basedir_1 ctrl when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_BASEDIR_1 (BIT(9))
#define DSI_BRG_PHY_HS_BASEDIR_1_M (DSI_BRG_PHY_HS_BASEDIR_1_V << DSI_BRG_PHY_HS_BASEDIR_1_S)
#define DSI_BRG_PHY_HS_BASEDIR_1_V 0x00000001U
#define DSI_BRG_PHY_HS_BASEDIR_1_S 9
/** DSI_BRG_PHY_HS_TXDATAHS_0 : R/W; bitpos: [23:16]; default: 0;
* txdatahs_0 ctrl when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_TXDATAHS_0 0x000000FFU
#define DSI_BRG_PHY_HS_TXDATAHS_0_M (DSI_BRG_PHY_HS_TXDATAHS_0_V << DSI_BRG_PHY_HS_TXDATAHS_0_S)
#define DSI_BRG_PHY_HS_TXDATAHS_0_V 0x000000FFU
#define DSI_BRG_PHY_HS_TXDATAHS_0_S 16
/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_0 : R/W; bitpos: [24]; default: 0;
* txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0 (BIT(24))
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_M (DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S)
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V 0x00000001U
#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S 24
/** DSI_BRG_PHY_HS_BASEDIR_0 : R/W; bitpos: [25]; default: 0;
* basedir_0 ctrl when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_BASEDIR_0 (BIT(25))
#define DSI_BRG_PHY_HS_BASEDIR_0_M (DSI_BRG_PHY_HS_BASEDIR_0_V << DSI_BRG_PHY_HS_BASEDIR_0_S)
#define DSI_BRG_PHY_HS_BASEDIR_0_V 0x00000001U
#define DSI_BRG_PHY_HS_BASEDIR_0_S 25
/** DSI_BRG_PHY_HS_TXREQUESTHSCLK : R/W; bitpos: [27]; default: 0;
* txrequesthsclk when enable dsi phy hs_loopback_test
*/
#define DSI_BRG_PHY_HS_TXREQUESTHSCLK (BIT(27))
#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_M (DSI_BRG_PHY_HS_TXREQUESTHSCLK_V << DSI_BRG_PHY_HS_TXREQUESTHSCLK_S)
#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_V 0x00000001U
#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_S 27
/** DSI_BRG_PHY_HS_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0;
* dsi phy hs_loopback test start check
*/
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK (BIT(28))
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_M (DSI_BRG_PHY_HS_LOOPBACK_CHECK_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_S)
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_V 0x00000001U
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_S 28
/** DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0;
* dsi phy hs_loopback test check done
*/
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE (BIT(29))
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_M (DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S)
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V 0x00000001U
#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S 29
/** DSI_BRG_PHY_HS_LOOPBACK_EN : R/W; bitpos: [30]; default: 0;
* dsi phy hs_loopback ctrl en
*/
#define DSI_BRG_PHY_HS_LOOPBACK_EN (BIT(30))
#define DSI_BRG_PHY_HS_LOOPBACK_EN_M (DSI_BRG_PHY_HS_LOOPBACK_EN_V << DSI_BRG_PHY_HS_LOOPBACK_EN_S)
#define DSI_BRG_PHY_HS_LOOPBACK_EN_V 0x00000001U
#define DSI_BRG_PHY_HS_LOOPBACK_EN_S 30
/** DSI_BRG_PHY_HS_LOOPBACK_OK : RO; bitpos: [31]; default: 0;
* result of dsi phy hs_loopback test
*/
#define DSI_BRG_PHY_HS_LOOPBACK_OK (BIT(31))
#define DSI_BRG_PHY_HS_LOOPBACK_OK_M (DSI_BRG_PHY_HS_LOOPBACK_OK_V << DSI_BRG_PHY_HS_LOOPBACK_OK_S)
#define DSI_BRG_PHY_HS_LOOPBACK_OK_V 0x00000001U
#define DSI_BRG_PHY_HS_LOOPBACK_OK_S 31
/** DSI_BRG_PHY_LOOPBACK_CNT_REG register
* loopback test cnt
*/
#define DSI_BRG_PHY_LOOPBACK_CNT_REG (DR_REG_DSI_BRG_BASE + 0x9c)
/** DSI_BRG_PHY_HS_CHECK_CNT_TH : R/W; bitpos: [7:0]; default: 64;
* hs_loopback test check cnt
*/
#define DSI_BRG_PHY_HS_CHECK_CNT_TH 0x000000FFU
#define DSI_BRG_PHY_HS_CHECK_CNT_TH_M (DSI_BRG_PHY_HS_CHECK_CNT_TH_V << DSI_BRG_PHY_HS_CHECK_CNT_TH_S)
#define DSI_BRG_PHY_HS_CHECK_CNT_TH_V 0x000000FFU
#define DSI_BRG_PHY_HS_CHECK_CNT_TH_S 0
/** DSI_BRG_PHY_LP_CHECK_CNT_TH : R/W; bitpos: [23:16]; default: 64;
* lp_loopback test check cnt
*/
#define DSI_BRG_PHY_LP_CHECK_CNT_TH 0x000000FFU
#define DSI_BRG_PHY_LP_CHECK_CNT_TH_M (DSI_BRG_PHY_LP_CHECK_CNT_TH_V << DSI_BRG_PHY_LP_CHECK_CNT_TH_S)
#define DSI_BRG_PHY_LP_CHECK_CNT_TH_V 0x000000FFU
#define DSI_BRG_PHY_LP_CHECK_CNT_TH_S 16
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of clk_en register
* dsi bridge clk control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* this bit configures force_on of dsi_bridge register clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_clk_en_reg_t;
/** Type of en register
* dsi bridge en register
*/
typedef union {
struct {
/** dsi_en : R/W; bitpos: [0]; default: 0;
* this bit configures module enable of dsi_bridge. 0: disable, 1: enable
*/
uint32_t dsi_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_en_reg_t;
/** Type of dma_req_cfg register
* dsi bridge dma burst len register
*/
typedef union {
struct {
/** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
* this field configures the num of 64-bit in one dma burst transfer, valid only when
* dsi_bridge as flow controller
*/
uint32_t dma_burst_len:12;
uint32_t reserved_12:20;
};
uint32_t val;
} dsi_brg_dma_req_cfg_reg_t;
/** Type of raw_num_cfg register
* dsi bridge raw number control register
*/
typedef union {
struct {
/** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
* this field configures number of total pix bits/64
*/
uint32_t raw_num_total:22;
/** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
* this field configures whether the total pix bits is a multiple of 64bits. 0: align
* to 64-bit, 1: unalign to 64-bit
*/
uint32_t unalign_64bit_en:1;
uint32_t reserved_23:8;
/** raw_num_total_set : WT; bitpos: [31]; default: 0;
* this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
* 1: enable. valid only when dsi_bridge as flow controller
*/
uint32_t raw_num_total_set:1;
};
uint32_t val;
} dsi_brg_raw_num_cfg_reg_t;
/** Type of raw_buf_credit_ctl register
* dsi bridge credit register
*/
typedef union {
struct {
/** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
* this field configures the threshold whether dsi_bridge fifo can receive one more
* 64-bit, valid only when dsi_bridge as flow controller
*/
uint32_t credit_thrd:15;
uint32_t reserved_15:1;
/** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
* this field configures the threshold whether dsi_bridge fifo can receive one more
* dma burst, valid only when dsi_bridge as flow controller
*/
uint32_t credit_burst_thrd:15;
/** credit_reset : R/W; bitpos: [31]; default: 0;
* this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
* dsi_bridge as flow controller
*/
uint32_t credit_reset:1;
};
uint32_t val;
} dsi_brg_raw_buf_credit_ctl_reg_t;
/** Type of pixel_type register
* dsi bridge dpi type control register
*/
typedef union {
struct {
/** raw_type : R/W; bitpos: [3:0]; default: 0;
* this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565
*/
uint32_t raw_type:4;
/** dpi_config : R/W; bitpos: [5:4]; default: 0;
* this field configures the pixel arrange type of dpi interface
*/
uint32_t dpi_config:2;
/** data_in_type : R/W; bitpos: [6]; default: 0;
* input data type, 0: rgb, 1: yuv
*/
uint32_t data_in_type:1;
uint32_t reserved_7:25;
};
uint32_t val;
} dsi_brg_pixel_type_reg_t;
/** Type of dma_block_interval register
* dsi bridge dma block interval control register
*/
typedef union {
struct {
/** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
* this field configures the max block_slot_cnt
*/
uint32_t dma_block_slot:10;
/** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
* this field configures the max block_interval_cnt, block_interval_cnt increased by 1
* when block_slot_cnt if full
*/
uint32_t dma_block_interval:18;
/** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
* this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
*/
uint32_t raw_num_total_auto_reload:1;
/** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
* this bit configures enable of interval between dma block transfer, 0: disable, 1:
* enable
*/
uint32_t dma_block_interval_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} dsi_brg_dma_block_interval_reg_t;
/** Type of dma_req_interval register
* dsi bridge dma req interval control register
*/
typedef union {
struct {
/** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
* this field configures the interval between dma req events
*/
uint32_t dma_req_interval:16;
uint32_t reserved_16:16;
};
uint32_t val;
} dsi_brg_dma_req_interval_reg_t;
/** Type of dpi_lcd_ctl register
* dsi bridge dpi signal control register
*/
typedef union {
struct {
/** dpishutdn : R/W; bitpos: [0]; default: 0;
* this bit configures dpishutdn signal in dpi interface
*/
uint32_t dpishutdn:1;
/** dpicolorm : R/W; bitpos: [1]; default: 0;
* this bit configures dpicolorm signal in dpi interface
*/
uint32_t dpicolorm:1;
/** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
* this bit configures dpiupdatecfg signal in dpi interface
*/
uint32_t dpiupdatecfg:1;
uint32_t reserved_3:29;
};
uint32_t val;
} dsi_brg_dpi_lcd_ctl_reg_t;
/** Type of dpi_rsv_dpi_data register
* dsi bridge dpi reserved data register
*/
typedef union {
struct {
/** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
* this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
*/
uint32_t dpi_rsv_data:30;
uint32_t reserved_30:2;
};
uint32_t val;
} dsi_brg_dpi_rsv_dpi_data_reg_t;
/** Type of dpi_v_cfg0 register
* dsi bridge dpi v config register 0
*/
typedef union {
struct {
/** vtotal : R/W; bitpos: [11:0]; default: 525;
* this field configures the total length of one frame (by line) for dpi output, must
* meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
*/
uint32_t vtotal:12;
uint32_t reserved_12:4;
/** vdisp : R/W; bitpos: [27:16]; default: 480;
* this field configures the length of valid line (by line) for dpi output
*/
uint32_t vdisp:12;
uint32_t reserved_28:4;
};
uint32_t val;
} dsi_brg_dpi_v_cfg0_reg_t;
/** Type of dpi_v_cfg1 register
* dsi bridge dpi v config register 1
*/
typedef union {
struct {
/** vbank : R/W; bitpos: [11:0]; default: 33;
* this field configures the length between vsync and valid line (by line) for dpi
* output
*/
uint32_t vbank:12;
uint32_t reserved_12:4;
/** vsync : R/W; bitpos: [27:16]; default: 2;
* this field configures the length of vsync (by line) for dpi output
*/
uint32_t vsync:12;
uint32_t reserved_28:4;
};
uint32_t val;
} dsi_brg_dpi_v_cfg1_reg_t;
/** Type of dpi_h_cfg0 register
* dsi bridge dpi h config register 0
*/
typedef union {
struct {
/** htotal : R/W; bitpos: [11:0]; default: 800;
* this field configures the total length of one line (by pixel num) for dpi output,
* must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
*/
uint32_t htotal:12;
uint32_t reserved_12:4;
/** hdisp : R/W; bitpos: [27:16]; default: 640;
* this field configures the length of valid pixel data (by pixel num) for dpi output
*/
uint32_t hdisp:12;
uint32_t reserved_28:4;
};
uint32_t val;
} dsi_brg_dpi_h_cfg0_reg_t;
/** Type of dpi_h_cfg1 register
* dsi bridge dpi h config register 1
*/
typedef union {
struct {
/** hbank : R/W; bitpos: [11:0]; default: 48;
* this field configures the length between hsync and pixel data valid (by pixel num)
* for dpi output
*/
uint32_t hbank:12;
uint32_t reserved_12:4;
/** hsync : R/W; bitpos: [27:16]; default: 96;
* this field configures the length of hsync (by pixel num) for dpi output
*/
uint32_t hsync:12;
uint32_t reserved_28:4;
};
uint32_t val;
} dsi_brg_dpi_h_cfg1_reg_t;
/** Type of dpi_misc_config register
* dsi_bridge dpi misc config register
*/
typedef union {
struct {
/** dpi_en : R/W; bitpos: [0]; default: 0;
* this bit configures enable of dpi output, 0: disable, 1: enable
*/
uint32_t dpi_en:1;
uint32_t reserved_1:3;
/** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
* this field configures the underrun interrupt musk, when underrun occurs and line
* cnt is less then this field
*/
uint32_t fifo_underrun_discard_vcnt:12;
uint32_t reserved_16:16;
};
uint32_t val;
} dsi_brg_dpi_misc_config_reg_t;
/** Type of dpi_config_update register
* dsi_bridge dpi config update register
*/
typedef union {
struct {
/** dpi_config_update : WT; bitpos: [0]; default: 0;
* write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
*/
uint32_t dpi_config_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_dpi_config_update_reg_t;
/** Type of host_trigger_rev register
* dsi_bridge host trigger reverse control register
*/
typedef union {
struct {
/** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
* tx_trigger reverse. 0: disable, 1: enable
*/
uint32_t tx_trigger_rev_en:1;
/** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
* rx_trigger reverse. 0: disable, 1: enable
*/
uint32_t rx_trigger_rev_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} dsi_brg_host_trigger_rev_reg_t;
/** Type of blk_raw_num_cfg register
* dsi_bridge block raw number control register
*/
typedef union {
struct {
/** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
* this field configures number of total block pix bits/64
*/
uint32_t blk_raw_num_total:22;
uint32_t reserved_22:9;
/** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
* write 1 to reload reg_blk_raw_num_total to internal cnt
*/
uint32_t blk_raw_num_total_set:1;
};
uint32_t val;
} dsi_brg_blk_raw_num_cfg_reg_t;
/** Type of dma_frame_interval register
* dsi_bridge dam frame interval control register
*/
typedef union {
struct {
/** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
* this field configures the max frame_slot_cnt
*/
uint32_t dma_frame_slot:10;
/** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
* this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
* when frame_slot_cnt if full
*/
uint32_t dma_frame_interval:18;
/** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
* this bit configures enable multi-blk transfer, 0: disable, 1: enable
*/
uint32_t dma_multiblk_en:1;
/** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
* this bit configures enable interval between frame transfer, 0: disable, 1: enable
*/
uint32_t dma_frame_interval_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} dsi_brg_dma_frame_interval_reg_t;
/** Type of mem_aux_ctrl register
* dsi_bridge mem aux control register
*/
typedef union {
struct {
/** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
* this field configures dsi_bridge fifo memory aux ctrl
*/
uint32_t dsi_mem_aux_ctrl:14;
uint32_t reserved_14:18;
};
uint32_t val;
} dsi_brg_mem_aux_ctrl_reg_t;
/** Type of rdn_eco_low register
* dsi_bridge rdn eco all low register
*/
typedef union {
struct {
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
* rdn_eco_low
*/
uint32_t rdn_eco_low:32;
};
uint32_t val;
} dsi_brg_rdn_eco_low_reg_t;
/** Type of rdn_eco_high register
* dsi_bridge rdn eco all high register
*/
typedef union {
struct {
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* rdn_eco_high
*/
uint32_t rdn_eco_high:32;
};
uint32_t val;
} dsi_brg_rdn_eco_high_reg_t;
/** Type of host_ctrl register
* dsi_bridge host control register
*/
typedef union {
struct {
/** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
* this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
* enable
*/
uint32_t dsi_cfg_ref_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_host_ctrl_reg_t;
/** Type of mem_clk_ctrl register
* dsi_bridge mem force on control register
*/
typedef union {
struct {
/** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
* this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
* force on
*/
uint32_t dsi_bridge_mem_clk_force_on:1;
/** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
* this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
*/
uint32_t dsi_mem_clk_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} dsi_brg_mem_clk_ctrl_reg_t;
/** Type of dma_flow_ctrl register
* dsi_bridge dma flow controller register
*/
typedef union {
struct {
/** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
* this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
* as flow controller
*/
uint32_t dsi_dma_flow_controller:1;
uint32_t reserved_1:3;
/** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
* this field configures the num of blocks when multi-blk is enable and dmac as flow
* controller
*/
uint32_t dma_flow_multiblk_num:4;
uint32_t reserved_8:24;
};
uint32_t val;
} dsi_brg_dma_flow_ctrl_reg_t;
/** Type of raw_buf_almost_empty_thrd register
* dsi_bridge buffer empty threshold register
*/
typedef union {
struct {
/** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
* this field configures the fifo almost empty threshold, is valid only when dmac as
* flow controller
*/
uint32_t dsi_raw_buf_almost_empty_thrd:11;
uint32_t reserved_11:21;
};
uint32_t val;
} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
/** Type of yuv_cfg register
* dsi_bridge yuv format config register
*/
typedef union {
struct {
/** protocal : R/W; bitpos: [0]; default: 0;
* this bit configures yuv protoocl, 0: bt.601, 1: bt.709
*/
uint32_t protocal:1;
/** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
* this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
*/
uint32_t yuv_pix_endian:1;
/** yuv422_format : R/W; bitpos: [3:2]; default: 0;
* this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
*/
uint32_t yuv422_format:2;
uint32_t reserved_4:28;
};
uint32_t val;
} dsi_brg_yuv_cfg_reg_t;
/** Type of phy_lp_loopback_ctrl register
* dsi phy lp_loopback test ctrl
*/
typedef union {
struct {
/** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
* txdataesc_1 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txdataesc_1:8;
/** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
* txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txrequestesc_1:1;
/** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
* txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txvalidesc_1:1;
/** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
* txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txlpdtesc_1:1;
/** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
* basedir_1 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_basedir_1:1;
uint32_t reserved_12:4;
/** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
* txdataesc_0 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txdataesc_0:8;
/** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
* txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txrequestesc_0:1;
/** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
* txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txvalidesc_0:1;
/** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
* txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_txlpdtesc_0:1;
/** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
* basedir_0 ctrl when enable dsi phy lp_loopback_test
*/
uint32_t phy_lp_basedir_0:1;
/** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
* dsi phy lp_loopback test start check
*/
uint32_t phy_lp_loopback_check:1;
/** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
* dsi phy lp_loopback test check done
*/
uint32_t phy_lp_loopback_check_done:1;
/** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
* dsi phy lp_loopback ctrl en
*/
uint32_t phy_lp_loopback_en:1;
/** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
* result of dsi phy lp_loopback test
*/
uint32_t phy_lp_loopback_ok:1;
};
uint32_t val;
} dsi_brg_phy_lp_loopback_ctrl_reg_t;
/** Type of phy_hs_loopback_ctrl register
* dsi phy hp_loopback test ctrl
*/
typedef union {
struct {
/** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
* txdatahs_1 ctrl when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_txdatahs_1:8;
/** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
* txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_txrequestdatahs_1:1;
/** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
* basedir_1 ctrl when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_basedir_1:1;
uint32_t reserved_10:6;
/** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
* txdatahs_0 ctrl when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_txdatahs_0:8;
/** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
* txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_txrequestdatahs_0:1;
/** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
* basedir_0 ctrl when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_basedir_0:1;
uint32_t reserved_26:1;
/** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
* txrequesthsclk when enable dsi phy hs_loopback_test
*/
uint32_t phy_hs_txrequesthsclk:1;
/** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
* dsi phy hs_loopback test start check
*/
uint32_t phy_hs_loopback_check:1;
/** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
* dsi phy hs_loopback test check done
*/
uint32_t phy_hs_loopback_check_done:1;
/** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
* dsi phy hs_loopback ctrl en
*/
uint32_t phy_hs_loopback_en:1;
/** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
* result of dsi phy hs_loopback test
*/
uint32_t phy_hs_loopback_ok:1;
};
uint32_t val;
} dsi_brg_phy_hs_loopback_ctrl_reg_t;
/** Type of phy_loopback_cnt register
* loopback test cnt
*/
typedef union {
struct {
/** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
* hs_loopback test check cnt
*/
uint32_t phy_hs_check_cnt_th:8;
uint32_t reserved_8:8;
/** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
* lp_loopback test check cnt
*/
uint32_t phy_lp_check_cnt_th:8;
uint32_t reserved_24:8;
};
uint32_t val;
} dsi_brg_phy_loopback_cnt_reg_t;
/** Group: Status Registers */
/** Type of fifo_flow_status register
* dsi bridge raw buffer depth register
*/
typedef union {
struct {
/** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
* this field configures the depth of dsi_bridge fifo depth
*/
uint32_t raw_buf_depth:14;
uint32_t reserved_14:18;
};
uint32_t val;
} dsi_brg_fifo_flow_status_reg_t;
/** Type of host_bist_ctl register
* dsi_bridge host bist control register
*/
typedef union {
struct {
/** bistok : RO; bitpos: [0]; default: 0;
* bistok
*/
uint32_t bistok:1;
/** biston : R/W; bitpos: [1]; default: 0;
* biston
*/
uint32_t biston:1;
uint32_t reserved_2:30;
};
uint32_t val;
} dsi_brg_host_bist_ctl_reg_t;
/** Type of rdn_eco_cs register
* dsi_bridge rdn eco cs register
*/
typedef union {
struct {
/** rdn_eco_en : R/W; bitpos: [0]; default: 0;
* rdn_eco_en
*/
uint32_t rdn_eco_en:1;
/** rdn_eco_result : RO; bitpos: [1]; default: 0;
* rdn_eco_result
*/
uint32_t rdn_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} dsi_brg_rdn_eco_cs_reg_t;
/** Group: Interrupt Registers */
/** Type of int_ena register
* dsi_bridge interrupt enable register
*/
typedef union {
struct {
/** underrun_int_ena : R/W; bitpos: [0]; default: 0;
* write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
* by dpi_underrun interrupt signal
*/
uint32_t underrun_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_int_ena_reg_t;
/** Type of int_clr register
* dsi_bridge interrupt clear register
*/
typedef union {
struct {
/** underrun_int_clr : WT; bitpos: [0]; default: 0;
* write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
*/
uint32_t underrun_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_int_clr_reg_t;
/** Type of int_raw register
* dsi_bridge raw interrupt register
*/
typedef union {
struct {
/** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* the raw interrupt status of dpi_underrun
*/
uint32_t underrun_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_int_raw_reg_t;
/** Type of int_st register
* dsi_bridge masked interrupt register
*/
typedef union {
struct {
/** underrun_int_st : RO; bitpos: [0]; default: 0;
* the masked interrupt status of dpi_underrun
*/
uint32_t underrun_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} dsi_brg_int_st_reg_t;
typedef struct {
volatile dsi_brg_clk_en_reg_t clk_en;
volatile dsi_brg_en_reg_t en;
volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
volatile dsi_brg_pixel_type_reg_t pixel_type;
volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
uint32_t reserved_02c;
volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
uint32_t reserved_048[2];
volatile dsi_brg_int_ena_reg_t int_ena;
volatile dsi_brg_int_clr_reg_t int_clr;
volatile dsi_brg_int_raw_reg_t int_raw;
volatile dsi_brg_int_st_reg_t int_st;
volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
volatile dsi_brg_host_ctrl_reg_t host_ctrl;
volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
} dsi_brg_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PARL_IO_RX_MODE_CFG_REG register
* Parallel RX Sampling mode configuration register.
*/
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_S 21
/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
* Set this bit to enable data sampling by software.
*/
#define PARL_IO_RX_SW_EN (BIT(25))
#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
#define PARL_IO_RX_SW_EN_V 0x00000001U
#define PARL_IO_RX_SW_EN_S 25
/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
* Set this bit to invert the external enable signal.
*/
#define PARL_IO_RX_EXT_EN_INV (BIT(26))
#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U
#define PARL_IO_RX_EXT_EN_INV_S 26
/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 4'd0: positive pulse start(data bit included) && positive pulse end(data bit
* included)
* 4'd1: positive pulse start(data bit included) && positive pulse end (data bit
* excluded)
* 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
* included)
* 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
* excluded)
* 4'd4: positive pulse start(data bit included) && length end
* 4'd5: positive pulse start(data bit excluded) && length end
*/
#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27
/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 2'b00: external level enable mode
* 2'b01: external pulse enable mode
* 2'b10: internal software enable mode
*/
#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_S 30
/** PARL_IO_RX_DATA_CFG_REG register
* Parallel RX data configuration register.
*/
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
#define PARL_IO_RX_BITLEN 0x0007FFFFU
#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
#define PARL_IO_RX_BITLEN_V 0x0007FFFFU
#define PARL_IO_RX_BITLEN_S 9
/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
*/
#define PARL_IO_RX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_RX_DATA_ORDER_INV_S 28
/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 3'd0: bus width is 1.
* 3'd1: bus width is 2.
* 3'd2: bus width is 4.
* 3'd3: bus width is 8.
*/
#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_S 29
/** PARL_IO_RX_GENRL_CFG_REG register
* Parallel RX general configuration register.
*/
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
* Set this bit to enable the clock gating of output rx clock.
*/
#define PARL_IO_RX_GATING_EN (BIT(12))
#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
#define PARL_IO_RX_GATING_EN_V 0x00000001U
#define PARL_IO_RX_GATING_EN_S 12
/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_S 13
/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
* Set this bit to enable timeout function to generate error eof.
*/
#define PARL_IO_RX_TIMEOUT_EN (BIT(29))
#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
#define PARL_IO_RX_TIMEOUT_EN_S 29
/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
#define PARL_IO_RX_EOF_GEN_SEL (BIT(30))
#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_RX_EOF_GEN_SEL_S 30
/** PARL_IO_RX_START_CFG_REG register
* Parallel RX Start configuration register.
*/
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
* Set this bit to start rx data sampling.
*/
#define PARL_IO_RX_START (BIT(31))
#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
#define PARL_IO_RX_START_V 0x00000001U
#define PARL_IO_RX_START_S 31
/** PARL_IO_TX_DATA_CFG_REG register
* Parallel TX data configuration register.
*/
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
#define PARL_IO_TX_BITLEN 0x0007FFFFU
#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
#define PARL_IO_TX_BITLEN_V 0x0007FFFFU
#define PARL_IO_TX_BITLEN_S 9
/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
*/
#define PARL_IO_TX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_TX_DATA_ORDER_INV_S 28
/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 3'd0: bus width is 1.
* 3'd1: bus width is 2.
* 3'd2: bus width is 4.
* 3'd3: bus width is 8.
*/
#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_S 29
/** PARL_IO_TX_START_CFG_REG register
* Parallel TX Start configuration register.
*/
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
* Set this bit to start tx data transmit.
*/
#define PARL_IO_TX_START (BIT(31))
#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
#define PARL_IO_TX_START_V 0x00000001U
#define PARL_IO_TX_START_S 31
/** PARL_IO_TX_GENRL_CFG_REG register
* Parallel TX general configuration register.
*/
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
#define PARL_IO_TX_EOF_GEN_SEL (BIT(13))
#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_TX_EOF_GEN_SEL_S 13
/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_S 14
/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
* Set this bit to enable the clock gating of output tx clock.
*/
#define PARL_IO_TX_GATING_EN (BIT(30))
#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
#define PARL_IO_TX_GATING_EN_V 0x00000001U
#define PARL_IO_TX_GATING_EN_S 30
/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
* Set this bit to enable the output of tx data valid signal.
*/
#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31))
#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U
#define PARL_IO_TX_VALID_OUTPUT_EN_S 31
/** PARL_IO_FIFO_CFG_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
* Set this bit to reset async fifo in tx module.
*/
#define PARL_IO_TX_FIFO_SRST (BIT(30))
#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
#define PARL_IO_TX_FIFO_SRST_S 30
/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
* Set this bit to reset async fifo in rx module.
*/
#define PARL_IO_RX_FIFO_SRST (BIT(31))
#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
#define PARL_IO_RX_FIFO_SRST_S 31
/** PARL_IO_REG_UPDATE_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
* Set this bit to update rx register configuration.
*/
#define PARL_IO_RX_REG_UPDATE (BIT(31))
#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
#define PARL_IO_RX_REG_UPDATE_S 31
/** PARL_IO_ST_REG register
* Parallel IO module status register0.
*/
#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
#define PARL_IO_TX_READY (BIT(31))
#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
#define PARL_IO_TX_READY_V 0x00000001U
#define PARL_IO_TX_READY_S 31
/** PARL_IO_INT_ENA_REG register
* Parallel IO interrupt enable singal configuration register.
*/
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
* Set this bit to enable RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1
/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
* Set this bit to enable TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ENA_S 2
/** PARL_IO_INT_RAW_REG register
* Parallel IO interrupt raw singal status register.
*/
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1
/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
#define PARL_IO_TX_EOF_INT_RAW_S 2
/** PARL_IO_INT_ST_REG register
* Parallel IO interrupt singal status register.
*/
#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1
/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ST (BIT(2))
#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ST_S 2
/** PARL_IO_INT_CLR_REG register
* Parallel IO interrupt clear singal configuration register.
*/
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1
/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
#define PARL_IO_TX_EOF_INT_CLR_S 2
/** PARL_IO_RX_ST0_REG register
* Parallel IO RX status register0
*/
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
#define PARL_IO_RX_CNT 0x0000001FU
#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
#define PARL_IO_RX_CNT_V 0x0000001FU
#define PARL_IO_RX_CNT_S 8
/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13
/** PARL_IO_RX_ST1_REG register
* Parallel IO RX status register1
*/
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_TX_ST0_REG register
* Parallel IO TX status register0
*/
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
#define PARL_IO_TX_CNT 0x0000007FU
#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
#define PARL_IO_TX_CNT_V 0x0000007FU
#define PARL_IO_TX_CNT_S 6
/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_RX_CLK_CFG_REG register
* Parallel IO RX clk configuration register
*/
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Set this bit to invert the input Rx core clock.
*/
#define PARL_IO_RX_CLK_I_INV (BIT(30))
#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
#define PARL_IO_RX_CLK_I_INV_V 0x00000001U
#define PARL_IO_RX_CLK_I_INV_S 30
/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Set this bit to invert the output Rx core clock.
*/
#define PARL_IO_RX_CLK_O_INV (BIT(31))
#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
#define PARL_IO_RX_CLK_O_INV_V 0x00000001U
#define PARL_IO_RX_CLK_O_INV_S 31
/** PARL_IO_TX_CLK_CFG_REG register
* Parallel IO TX clk configuration register
*/
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Set this bit to invert the input Tx core clock.
*/
#define PARL_IO_TX_CLK_I_INV (BIT(30))
#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
#define PARL_IO_TX_CLK_I_INV_V 0x00000001U
#define PARL_IO_TX_CLK_I_INV_S 30
/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Set this bit to invert the output Tx core clock.
*/
#define PARL_IO_TX_CLK_O_INV (BIT(31))
#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
#define PARL_IO_TX_CLK_O_INV_V 0x00000001U
#define PARL_IO_TX_CLK_O_INV_S 31
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
#define PARL_IO_CLK_EN (BIT(31))
#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
#define PARL_IO_CLK_EN_V 0x00000001U
#define PARL_IO_CLK_EN_S 31
/** PARL_IO_VERSION_REG register
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
* Version of this register file
*/
#define PARL_IO_DATE 0x0FFFFFFFU
#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
#define PARL_IO_DATE_V 0x0FFFFFFFU
#define PARL_IO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/parl_io_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: PARL_IO RX Mode Configuration */
/** Type of rx_mode_cfg register
* Parallel RX Sampling mode configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
uint32_t rx_ext_en_sel:4;
/** rx_sw_en : R/W; bitpos: [25]; default: 0;
* Set this bit to enable data sampling by software.
*/
uint32_t rx_sw_en:1;
/** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
* Set this bit to invert the external enable signal.
*/
uint32_t rx_ext_en_inv:1;
/** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 4'd0: positive pulse start(data bit included) && positive pulse end(data bit
* included)
* 4'd1: positive pulse start(data bit included) && positive pulse end (data bit
* excluded)
* 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
* included)
* 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
* excluded)
* 4'd4: positive pulse start(data bit included) && length end
* 4'd5: positive pulse start(data bit excluded) && length end
*/
uint32_t rx_pulse_submode_sel:3;
/** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 2'b00: external level enable mode
* 2'b01: external pulse enable mode
* 2'b10: internal software enable mode
*/
uint32_t rx_smp_mode_sel:2;
};
uint32_t val;
} parl_io_rx_mode_cfg_reg_t;
/** Group: PARL_IO RX Data Configuration */
/** Type of rx_data_cfg register
* Parallel RX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
uint32_t rx_bitlen:19;
/** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
*/
uint32_t rx_data_order_inv:1;
/** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 3'd0: bus width is 1.
* 3'd1: bus width is 2.
* 3'd2: bus width is 4.
* 3'd3: bus width is 8.
*/
uint32_t rx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_rx_data_cfg_reg_t;
/** Group: PARL_IO RX General Configuration */
/** Type of rx_genrl_cfg register
* Parallel RX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rx_gating_en : R/W; bitpos: [12]; default: 0;
* Set this bit to enable the clock gating of output rx clock.
*/
uint32_t rx_gating_en:1;
/** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
uint32_t rx_timeout_thres:16;
/** rx_timeout_en : R/W; bitpos: [29]; default: 1;
* Set this bit to enable timeout function to generate error eof.
*/
uint32_t rx_timeout_en:1;
/** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
uint32_t rx_eof_gen_sel:1;
uint32_t reserved_31:1;
};
uint32_t val;
} parl_io_rx_genrl_cfg_reg_t;
/** Group: PARL_IO RX Start Configuration */
/** Type of rx_start_cfg register
* Parallel RX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rx_start : R/W; bitpos: [31]; default: 0;
* Set this bit to start rx data sampling.
*/
uint32_t rx_start:1;
};
uint32_t val;
} parl_io_rx_start_cfg_reg_t;
/** Group: PARL_IO TX Data Configuration */
/** Type of tx_data_cfg register
* Parallel TX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
uint32_t tx_bitlen:19;
/** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
*/
uint32_t tx_data_order_inv:1;
/** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 3'd0: bus width is 1.
* 3'd1: bus width is 2.
* 3'd2: bus width is 4.
* 3'd3: bus width is 8.
*/
uint32_t tx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_tx_data_cfg_reg_t;
/** Group: PARL_IO TX Start Configuration */
/** Type of tx_start_cfg register
* Parallel TX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_start : R/W; bitpos: [31]; default: 0;
* Set this bit to start tx data transmit.
*/
uint32_t tx_start:1;
};
uint32_t val;
} parl_io_tx_start_cfg_reg_t;
/** Group: PARL_IO TX General Configuration */
/** Type of tx_genrl_cfg register
* Parallel TX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
uint32_t tx_eof_gen_sel:1;
/** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
uint32_t tx_idle_value:16;
/** tx_gating_en : R/W; bitpos: [30]; default: 0;
* Set this bit to enable the clock gating of output tx clock.
*/
uint32_t tx_gating_en:1;
/** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
* Set this bit to enable the output of tx data valid signal.
*/
uint32_t tx_valid_output_en:1;
};
uint32_t val;
} parl_io_tx_genrl_cfg_reg_t;
/** Group: PARL_IO FIFO Configuration */
/** Type of fifo_cfg register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
* Set this bit to reset async fifo in tx module.
*/
uint32_t tx_fifo_srst:1;
/** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
* Set this bit to reset async fifo in rx module.
*/
uint32_t rx_fifo_srst:1;
};
uint32_t val;
} parl_io_fifo_cfg_reg_t;
/** Group: PARL_IO Register Update Configuration */
/** Type of reg_update register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rx_reg_update : WT; bitpos: [31]; default: 0;
* Set this bit to update rx register configuration.
*/
uint32_t rx_reg_update:1;
};
uint32_t val;
} parl_io_reg_update_reg_t;
/** Group: PARL_IO Status */
/** Type of st register
* Parallel IO module status register0.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_ready : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
uint32_t tx_ready:1;
};
uint32_t val;
} parl_io_st_reg_t;
/** Group: PARL_IO Interrupt Configuration and Status */
/** Type of int_ena register
* Parallel IO interrupt enable singal configuration register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_ena:1;
/** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
* Set this bit to enable RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_ena:1;
/** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable TX_EOF_INT.
*/
uint32_t tx_eof_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_ena_reg_t;
/** Type of int_raw register
* Parallel IO interrupt raw singal status register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_raw:1;
/** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_raw:1;
/** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
uint32_t tx_eof_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_raw_reg_t;
/** Type of int_st register
* Parallel IO interrupt singal status register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_st:1;
/** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_st:1;
/** tx_eof_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
uint32_t tx_eof_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_st_reg_t;
/** Type of int_clr register
* Parallel IO interrupt clear singal configuration register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_clr:1;
/** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_clr:1;
/** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear TX_EOF_INT.
*/
uint32_t tx_eof_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_clr_reg_t;
/** Group: PARL_IO Rx Status0 */
/** Type of rx_st0 register
* Parallel IO RX status register0
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** rx_cnt : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
uint32_t rx_cnt:5;
/** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
uint32_t rx_fifo_wr_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st0_reg_t;
/** Group: PARL_IO Rx Status1 */
/** Type of rx_st1 register
* Parallel IO RX status register1
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
uint32_t rx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st1_reg_t;
/** Group: PARL_IO Tx Status0 */
/** Type of tx_st0 register
* Parallel IO TX status register0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** tx_cnt : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
uint32_t tx_cnt:7;
/** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
uint32_t tx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_tx_st0_reg_t;
/** Group: PARL_IO Rx Clock Configuration */
/** Type of rx_clk_cfg register
* Parallel IO RX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Set this bit to invert the input Rx core clock.
*/
uint32_t rx_clk_i_inv:1;
/** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Set this bit to invert the output Rx core clock.
*/
uint32_t rx_clk_o_inv:1;
};
uint32_t val;
} parl_io_rx_clk_cfg_reg_t;
/** Group: PARL_IO Tx Clock Configuration */
/** Type of tx_clk_cfg register
* Parallel IO TX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Set this bit to invert the input Tx core clock.
*/
uint32_t tx_clk_i_inv:1;
/** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Set this bit to invert the output Tx core clock.
*/
uint32_t tx_clk_o_inv:1;
};
uint32_t val;
} parl_io_tx_clk_cfg_reg_t;
/** Group: PARL_IO Clock Configuration */
/** Type of clk register
* Parallel IO clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
uint32_t clk_en:1;
};
uint32_t val;
} parl_io_clk_reg_t;
/** Group: PARL_IO Version Register */
/** Type of version register
* Version register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725920;
* Version of this register file
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} parl_io_version_reg_t;
typedef struct {
volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
volatile parl_io_fifo_cfg_reg_t fifo_cfg;
volatile parl_io_reg_update_reg_t reg_update;
volatile parl_io_st_reg_t st;
volatile parl_io_int_ena_reg_t int_ena;
volatile parl_io_int_raw_reg_t int_raw;
volatile parl_io_int_st_reg_t int_st;
volatile parl_io_int_clr_reg_t int_clr;
volatile parl_io_rx_st0_reg_t rx_st0;
volatile parl_io_rx_st1_reg_t rx_st1;
volatile parl_io_tx_st0_reg_t tx_st0;
volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
uint32_t reserved_04c[53];
volatile parl_io_clk_reg_t clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t version;
} parl_io_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/pau_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
* Peri backup control register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
#define PAU_FLOW_ERR_V 0x00000007U
#define PAU_FLOW_ERR_S 0
/** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal
*/
#define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U
#define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
* Link select
*/
#define PAU_LINK_SEL 0x00000003U
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x00000003U
#define PAU_LINK_SEL_S 5
/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
* mac sw backup start signal
*/
#define PAU_START_MAC (BIT(7))
#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
#define PAU_START_MAC_V 0x00000001U
#define PAU_START_MAC_S 7
/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM_MAC (BIT(8))
#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
#define PAU_TO_MEM_MAC_V 0x00000001U
#define PAU_TO_MEM_MAC_S 8
/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
* mac hw/sw select
*/
#define PAU_SEL_MAC (BIT(9))
#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
#define PAU_SEL_MAC_V 0x00000001U
#define PAU_SEL_MAC_S 9
/** PAU_REGDMA_CLK_CONF_REG register
* Clock control register
*/
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable
*/
#define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
#define PAU_CLK_EN_V 0x00000001U
#define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg
*/
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
#define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
#define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
#define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
#define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
#define PAU_ETM_START_3_V 0x00000001U
#define PAU_ETM_START_3_S 3
/** PAU_REGDMA_LINK_0_ADDR_REG register
* link_0_addr
*/
#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg
*/
#define PAU_LINK_ADDR_0 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_S 0
/** PAU_REGDMA_LINK_1_ADDR_REG register
* Link_1_addr
*/
#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg
*/
#define PAU_LINK_ADDR_1 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_S 0
/** PAU_REGDMA_LINK_2_ADDR_REG register
* Link_2_addr
*/
#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg
*/
#define PAU_LINK_ADDR_2 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_S 0
/** PAU_REGDMA_LINK_3_ADDR_REG register
* Link_3_addr
*/
#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg
*/
#define PAU_LINK_ADDR_3 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_S 0
/** PAU_REGDMA_LINK_MAC_ADDR_REG register
* Link_mac_addr
*/
#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg
*/
#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_S 0
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr
*/
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_BACKUP_ADDR_REG register
* Backup addr
*/
#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
* backup addr reg
*/
#define PAU_BACKUP_ADDR 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register
* mem addr
*/
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
#define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
#define PAU_MEM_ADDR_V 0xFFFFFFFFU
#define PAU_MEM_ADDR_S 0
/** PAU_REGDMA_BKP_CONF_REG register
* backup config
*/
#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
* Link read_interval
*/
#define PAU_READ_INTERVAL 0x0000007FU
#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
#define PAU_READ_INTERVAL_V 0x0000007FU
#define PAU_READ_INTERVAL_S 0
/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold
*/
#define PAU_LINK_TOUT_THRES 0x000003FFU
#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
#define PAU_LINK_TOUT_THRES_V 0x000003FFU
#define PAU_LINK_TOUT_THRES_S 7
/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
* burst limit
*/
#define PAU_BURST_LIMIT 0x0000001FU
#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
#define PAU_BURST_LIMIT_V 0x0000001FU
#define PAU_BURST_LIMIT_S 17
/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold
*/
#define PAU_BACKUP_TOUT_THRES 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_S 22
/** PAU_INT_ENA_REG register
* Read only register for error and done
*/
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
#define PAU_ERROR_INT_ENA_V 0x00000001U
#define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register
* Read only register for error and done
*/
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
#define PAU_ERROR_INT_RAW_V 0x00000001U
#define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register
* Read only register for error and done
*/
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
#define PAU_ERROR_INT_CLR_V 0x00000001U
#define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register
* Read only register for error and done
*/
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
#define PAU_ERROR_INT_ST_V 0x00000001U
#define PAU_ERROR_INT_ST_S 1
/** PAU_DATE_REG register
* Date register.
*/
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 35663984;
* REGDMA date information/ REGDMA version information.
*/
#define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
#define PAU_DATE_V 0x0FFFFFFFU
#define PAU_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
* Peri backup control register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
* backup start signal
*/
uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [6:5]; default: 0;
* Link select
*/
uint32_t link_sel:2;
/** start_mac : WT; bitpos: [7]; default: 0;
* mac sw backup start signal
*/
uint32_t start_mac:1;
/** to_mem_mac : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem_mac:1;
/** sel_mac : R/W; bitpos: [9]; default: 0;
* mac hw/sw select
*/
uint32_t sel_mac:1;
uint32_t reserved_10:22;
};
uint32_t val;
} pau_regdma_conf_reg_t;
/** Type of regdma_clk_conf register
* Clock control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register
* ETM start ctrl reg
*/
typedef union {
struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
uint32_t etm_start_3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_link_0_addr register
* link_0_addr
*/
typedef union {
struct {
/** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg
*/
uint32_t link_addr_0:32;
};
uint32_t val;
} pau_regdma_link_0_addr_reg_t;
/** Type of regdma_link_1_addr register
* Link_1_addr
*/
typedef union {
struct {
/** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg
*/
uint32_t link_addr_1:32;
};
uint32_t val;
} pau_regdma_link_1_addr_reg_t;
/** Type of regdma_link_2_addr register
* Link_2_addr
*/
typedef union {
struct {
/** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg
*/
uint32_t link_addr_2:32;
};
uint32_t val;
} pau_regdma_link_2_addr_reg_t;
/** Type of regdma_link_3_addr register
* Link_3_addr
*/
typedef union {
struct {
/** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg
*/
uint32_t link_addr_3:32;
};
uint32_t val;
} pau_regdma_link_3_addr_reg_t;
/** Type of regdma_link_mac_addr register
* Link_mac_addr
*/
typedef union {
struct {
/** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg
*/
uint32_t link_addr_mac:32;
};
uint32_t val;
} pau_regdma_link_mac_addr_reg_t;
/** Type of regdma_current_link_addr register
* current link addr
*/
typedef union {
struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
uint32_t current_link_addr:32;
};
uint32_t val;
} pau_regdma_current_link_addr_reg_t;
/** Type of regdma_backup_addr register
* Backup addr
*/
typedef union {
struct {
/** backup_addr : RO; bitpos: [31:0]; default: 0;
* backup addr reg
*/
uint32_t backup_addr:32;
};
uint32_t val;
} pau_regdma_backup_addr_reg_t;
/** Type of regdma_mem_addr register
* mem addr
*/
typedef union {
struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
uint32_t mem_addr:32;
};
uint32_t val;
} pau_regdma_mem_addr_reg_t;
/** Type of regdma_bkp_conf register
* backup config
*/
typedef union {
struct {
/** read_interval : R/W; bitpos: [6:0]; default: 32;
* Link read_interval
*/
uint32_t read_interval:7;
/** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold
*/
uint32_t link_tout_thres:10;
/** burst_limit : R/W; bitpos: [21:17]; default: 8;
* burst limit
*/
uint32_t burst_limit:5;
/** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold
*/
uint32_t backup_tout_thres:10;
};
uint32_t val;
} pau_regdma_bkp_conf_reg_t;
/** Type of int_ena register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_ena_reg_t;
/** Type of int_raw register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_raw_reg_t;
/** Type of int_clr register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_clr_reg_t;
/** Type of int_st register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_st_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35663984;
* REGDMA date information/ REGDMA version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_date_reg_t;
typedef struct {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr;
volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr;
volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr;
volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr;
volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr;
volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
volatile pau_regdma_backup_addr_reg_t regdma_backup_addr;
volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf;
volatile pau_int_ena_reg_t int_ena;
volatile pau_int_raw_reg_t int_raw;
volatile pau_int_clr_reg_t int_clr;
volatile pau_int_st_reg_t int_st;
uint32_t reserved_040[239];
volatile pau_date_reg_t date;
} pau_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* This sets the maximum threshold, in APB_CLK cycles, for the filter.
*
* Any pulses with width less than this will be ignored when the filter is enabled.
*/
uint32_t filter_thres_un:10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un:1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un:1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
* the high limit interrupt.
*/
uint32_t thr_h_lim_en_un:1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
* the low limit interrupt.
*/
uint32_t thr_l_lim_en_un:1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un:1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un:1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* negative edge.
*
* 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
*/
uint32_t ch0_neg_mode_un:2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* positive edge.
*
* 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
*/
uint32_t ch0_pos_mode_un:2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode_un:2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode_un:2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* negative edge.
*
* 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
*/
uint32_t ch1_neg_mode_un:2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* positive edge.
*
* 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
*/
uint32_t ch1_pos_mode_un:2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode_un:2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode_un:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thres0 value for unit n.
*/
uint32_t cnt_thres0_un:16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thres1 value for unit n.
*/
uint32_t cnt_thres1_un:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thr_h_lim value for unit n. When pcnt
* reaches this value, the counter will be cleared to 0.
*/
uint32_t cnt_h_lim_un:16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thr_l_lim value for unit n. When pcnt
* reaches this value, the counter will be cleared to 0.
*/
uint32_t cnt_l_lim_un:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
/** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
* Configures this bit to enable unit 0's step comparator.
*/
uint32_t dalta_change_en_u0:1;
/** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
* Configures this bit to enable unit 1's step comparator.
*/
uint32_t dalta_change_en_u1:1;
/** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
* Configures this bit to enable unit 2's step comparator.
*/
uint32_t dalta_change_en_u2:1;
/** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
* Configures this bit to enable unit 3's step comparator.
*/
uint32_t dalta_change_en_u3:1;
uint32_t reserved_12:4;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Type of u3_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 3.
*/
uint32_t cnt_step_u3:16;
/** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 3.
*/
uint32_t cnt_step_lim_u3:16;
};
uint32_t val;
} pcnt_u3_change_conf_reg_t;
/** Type of u2_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 2.
*/
uint32_t cnt_step_u2:16;
/** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 2.
*/
uint32_t cnt_step_lim_u2:16;
};
uint32_t val;
} pcnt_u2_change_conf_reg_t;
/** Type of u1_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 1.
*/
uint32_t cnt_step_u1:16;
/** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 1.
*/
uint32_t cnt_step_lim_u1:16;
};
uint32_t val;
} pcnt_u1_change_conf_reg_t;
/** Type of u0_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 0.
*/
uint32_t cnt_step_u0:16;
/** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 0.
*/
uint32_t cnt_step_lim_u0:16;
};
uint32_t val;
} pcnt_u0_change_conf_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* This register stores the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
* from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
* is negative. 3: pulse counter is positive.
*/
uint32_t cnt_thr_zero_mode_un:2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* The latched value of thres1 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres1_lat_un:1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* The latched value of thres0 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres0_lat_un:1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* The latched value of low limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
* valid. 0: others
*/
uint32_t cnt_thr_l_lim_lat_un:1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* The latched value of high limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
* valid. 0: others
*/
uint32_t cnt_thr_h_lim_lat_un:1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* The latched value of zero threshold event of PCNT_Un when threshold event interrupt
* is valid. 1: the current pulse counter equals to 0 and zero threshold event is
* valid. 0: others
*/
uint32_t cnt_thr_zero_lat_un:1;
uint32_t reserved_7:25;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 571021568;
* This is the PCNT version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
volatile pcnt_u3_change_conf_reg_t u3_change_conf;
volatile pcnt_u2_change_conf_reg_t u2_change_conf;
volatile pcnt_u1_change_conf_reg_t u1_change_conf;
volatile pcnt_u0_change_conf_reg_t u0_change_conf;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of blend0_clut_data register
* CLUT sram data read/write register in background plane of blender
*/
typedef union {
struct {
/** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0;
* Write and read data to/from CLUT RAM in background plane of blender engine through
* this field in fifo mode.
*/
uint32_t rdwr_word_blend0_clut:32;
};
uint32_t val;
} ppa_blend0_clut_data_reg_t;
/** Type of blend1_clut_data register
* CLUT sram data read/write register in foreground plane of blender
*/
typedef union {
struct {
/** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0;
* Write and read data to/from CLUT RAM in foreground plane of blender engine through
* this field in fifo mode.
*/
uint32_t rdwr_word_blend1_clut:32;
};
uint32_t val;
} ppa_blend1_clut_data_reg_t;
/** Type of clut_conf register
* CLUT configure register
*/
typedef union {
struct {
/** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
* 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
* PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
* memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
* should be 01 to access sr clut and should be 10 to access blend0 clut and should be
* 11 to access blend 1 clut in memory mode.
*/
uint32_t apb_fifo_mask:1;
/** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0;
* Write 1 then write 0 to this bit to reset BLEND0 CLUT.
*/
uint32_t blend0_clut_mem_rst:1;
/** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0;
* Write 1 then write 0 to this bit to reset BLEND1 CLUT.
*/
uint32_t blend1_clut_mem_rst:1;
/** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0;
* Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode.
*/
uint32_t blend0_clut_mem_rdaddr_rst:1;
/** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0;
* Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode.
*/
uint32_t blend1_clut_mem_rdaddr_rst:1;
/** blend0_clut_mem_force_pd : R/W; bitpos: [5]; default: 0;
* 1: force power down BLEND CLUT memory.
*/
uint32_t blend0_clut_mem_force_pd:1;
/** blend0_clut_mem_force_pu : R/W; bitpos: [6]; default: 0;
* 1: force power up BLEND CLUT memory.
*/
uint32_t blend0_clut_mem_force_pu:1;
/** blend0_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0;
* 1: Force clock on for BLEND CLUT memory.
*/
uint32_t blend0_clut_mem_clk_ena:1;
uint32_t reserved_8:24;
};
uint32_t val;
} ppa_clut_conf_reg_t;
/** Type of sr_color_mode register
* Scaling and rotating engine color mode register
*/
typedef union {
struct {
/** sr_rx_cm : R/W; bitpos: [3:0]; default: 0;
* The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
* RGB888. 2: RGB565. 8: YUV420. others: Reserved.
*/
uint32_t sr_rx_cm:4;
/** sr_tx_cm : R/W; bitpos: [7:4]; default: 0;
* The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
* 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved.
*/
uint32_t sr_tx_cm:4;
/** yuv_rx_range : R/W; bitpos: [8]; default: 0;
* YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range
*/
uint32_t yuv_rx_range:1;
/** yuv_tx_range : R/W; bitpos: [9]; default: 0;
* YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range
*/
uint32_t yuv_tx_range:1;
/** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0;
* YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
*/
uint32_t yuv2rgb_protocal:1;
/** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0;
* RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
*/
uint32_t rgb2yuv_protocal:1;
uint32_t reserved_12:20;
};
uint32_t val;
} ppa_sr_color_mode_reg_t;
/** Type of blend_color_mode register
* blending engine color mode register
*/
typedef union {
struct {
/** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0;
* The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
* RGB565. 3: Reserved. 4: L8. 5: L4.
*/
uint32_t blend0_rx_cm:4;
/** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0;
* The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2:
* RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4.
*/
uint32_t blend1_rx_cm:4;
/** blend_tx_cm : R/W; bitpos: [11:8]; default: 0;
* The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
* RGB565. 3: Reserved..
*/
uint32_t blend_tx_cm:4;
uint32_t reserved_12:20;
};
uint32_t val;
} ppa_blend_color_mode_reg_t;
/** Type of sr_byte_order register
* Scaling and rotating engine byte order register
*/
typedef union {
struct {
/** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0
* and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
*/
uint32_t sr_rx_byte_swap_en:1;
/** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0;
* Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb
* would be swap to bgr.
*/
uint32_t sr_rx_rgb_swap_en:1;
/** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0;
* Set this bit to 1 to bypass the macro block order function. This function is used
* to improve efficient accessing external memory.
*/
uint32_t sr_macro_bk_ro_bypass:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_sr_byte_order_reg_t;
/** Type of blend_byte_order register
* Blending engine byte order register
*/
typedef union {
struct {
/** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0
* and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
*/
uint32_t blend0_rx_byte_swap_en:1;
/** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0;
* Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0
* and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
*/
uint32_t blend1_rx_byte_swap_en:1;
/** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0;
* Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb
* would be swap to bgr.
*/
uint32_t blend0_rx_rgb_swap_en:1;
/** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0;
* Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb
* would be swap to bgr.
*/
uint32_t blend1_rx_rgb_swap_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ppa_blend_byte_order_reg_t;
/** Type of blend_trans_mode register
* Blending engine mode configure register
*/
typedef union {
struct {
/** blend_en : R/W; bitpos: [0]; default: 0;
* Set this bit to enable alpha blending.
*/
uint32_t blend_en:1;
/** blend_bypass : R/W; bitpos: [1]; default: 0;
* Set this bit to bypass blender. Then background date would be output.
*/
uint32_t blend_bypass:1;
/** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0;
* This bit is used to enable fix pixel filling. When this mode is enable only Tx
* channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL.
*/
uint32_t blend_fix_pixel_fill_en:1;
/** blend_trans_mode_update : WT; bitpos: [3]; default: 0;
* Set this bit to update the transfer mode. Only the bit is set the transfer mode is
* valid.
*/
uint32_t blend_trans_mode_update:1;
/** blend_rst : R/W; bitpos: [4]; default: 0;
* write 1 then write 0 to reset blending engine.
*/
uint32_t blend_rst:1;
uint32_t reserved_5:27;
};
uint32_t val;
} ppa_blend_trans_mode_reg_t;
/** Type of sr_fix_alpha register
* Scaling and rotating engine alpha override register
*/
typedef union {
struct {
/** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
* The value would replace the alpha value in received pixel for Scaling and Rotating
* engine when PPA_SR_RX_ALPHA_CONF_EN is enabled.
*/
uint32_t sr_rx_fix_alpha:8;
/** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
*/
uint32_t sr_rx_alpha_mod:2;
/** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0;
* Set this bit to invert the original alpha value. When RX color mode is
* RGB565/RGB88. The original alpha value is 255.
*/
uint32_t sr_rx_alpha_inv:1;
uint32_t reserved_11:21;
};
uint32_t val;
} ppa_sr_fix_alpha_reg_t;
/** Type of blend_tx_size register
* Fix pixel filling mode image size register
*/
typedef union {
struct {
/** blend_hb : R/W; bitpos: [13:0]; default: 0;
* The horizontal width of image block that would be filled in fix pixel filling mode.
* The unit is pixel
*/
uint32_t blend_hb:14;
/** blend_vb : R/W; bitpos: [27:14]; default: 0;
* The vertical width of image block that would be filled in fix pixel filling mode.
* The unit is pixel
*/
uint32_t blend_vb:14;
uint32_t reserved_28:4;
};
uint32_t val;
} ppa_blend_tx_size_reg_t;
/** Type of blend_fix_alpha register
* Blending engine alpha override register
*/
typedef union {
struct {
/** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
* The value would replace the alpha value in received pixel for background plane of
* blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled.
*/
uint32_t blend0_rx_fix_alpha:8;
/** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128;
* The value would replace the alpha value in received pixel for foreground plane of
* blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled.
*/
uint32_t blend1_rx_fix_alpha:8;
/** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
*/
uint32_t blend0_rx_alpha_mod:2;
/** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
*/
uint32_t blend1_rx_alpha_mod:2;
/** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0;
* Set this bit to invert the original alpha value. When RX color mode is
* RGB565/RGB88. The original alpha value is 255.
*/
uint32_t blend0_rx_alpha_inv:1;
/** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0;
* Set this bit to invert the original alpha value. When RX color mode is
* RGB565/RGB88. The original alpha value is 255.
*/
uint32_t blend1_rx_alpha_inv:1;
uint32_t reserved_22:10;
};
uint32_t val;
} ppa_blend_fix_alpha_reg_t;
/** Type of blend_rgb register
* RGB color register
*/
typedef union {
struct {
/** blend1_rx_b : R/W; bitpos: [7:0]; default: 128;
* blue color for A4/A8 mode.
*/
uint32_t blend1_rx_b:8;
/** blend1_rx_g : R/W; bitpos: [15:8]; default: 128;
* green color for A4/A8 mode.
*/
uint32_t blend1_rx_g:8;
/** blend1_rx_r : R/W; bitpos: [23:16]; default: 128;
* red color for A4/A8 mode.
*/
uint32_t blend1_rx_r:8;
uint32_t reserved_24:8;
};
uint32_t val;
} ppa_blend_rgb_reg_t;
/** Type of blend_fix_pixel register
* Blending engine fix pixel register
*/
typedef union {
struct {
/** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0;
* The configure fix pixel in fix pixel filling mode for blender engine.
*/
uint32_t blend_tx_fix_pixel:32;
};
uint32_t val;
} ppa_blend_fix_pixel_reg_t;
/** Type of ck_fg_low register
* foreground color key lower threshold
*/
typedef union {
struct {
/** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255;
* color key lower threshold of foreground b channel
*/
uint32_t colorkey_fg_b_low:8;
/** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255;
* color key lower threshold of foreground g channel
*/
uint32_t colorkey_fg_g_low:8;
/** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255;
* color key lower threshold of foreground r channel
*/
uint32_t colorkey_fg_r_low:8;
uint32_t reserved_24:8;
};
uint32_t val;
} ppa_ck_fg_low_reg_t;
/** Type of ck_fg_high register
* foreground color key higher threshold
*/
typedef union {
struct {
/** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0;
* color key higher threshold of foreground b channel
*/
uint32_t colorkey_fg_b_high:8;
/** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0;
* color key higher threshold of foreground g channel
*/
uint32_t colorkey_fg_g_high:8;
/** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0;
* color key higher threshold of foreground r channel
*/
uint32_t colorkey_fg_r_high:8;
uint32_t reserved_24:8;
};
uint32_t val;
} ppa_ck_fg_high_reg_t;
/** Type of ck_bg_low register
* background color key lower threshold
*/
typedef union {
struct {
/** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255;
* color key lower threshold of background b channel
*/
uint32_t colorkey_bg_b_low:8;
/** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255;
* color key lower threshold of background g channel
*/
uint32_t colorkey_bg_g_low:8;
/** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255;
* color key lower threshold of background r channel
*/
uint32_t colorkey_bg_r_low:8;
uint32_t reserved_24:8;
};
uint32_t val;
} ppa_ck_bg_low_reg_t;
/** Type of ck_bg_high register
* background color key higher threshold
*/
typedef union {
struct {
/** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0;
* color key higher threshold of background b channel
*/
uint32_t colorkey_bg_b_high:8;
/** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0;
* color key higher threshold of background g channel
*/
uint32_t colorkey_bg_g_high:8;
/** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0;
* color key higher threshold of background r channel
*/
uint32_t colorkey_bg_r_high:8;
uint32_t reserved_24:8;
};
uint32_t val;
} ppa_ck_bg_high_reg_t;
/** Type of ck_default register
* default value when foreground and background both in color key range
*/
typedef union {
struct {
/** colorkey_default_b : R/W; bitpos: [7:0]; default: 0;
* default B channle value of color key
*/
uint32_t colorkey_default_b:8;
/** colorkey_default_g : R/W; bitpos: [15:8]; default: 0;
* default G channle value of color key
*/
uint32_t colorkey_default_g:8;
/** colorkey_default_r : R/W; bitpos: [23:16]; default: 0;
* default R channle value of color key
*/
uint32_t colorkey_default_r:8;
/** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0;
* when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the
* result is fg
*/
uint32_t colorkey_fg_bg_reverse:1;
uint32_t reserved_25:7;
};
uint32_t val;
} ppa_ck_default_reg_t;
/** Type of sr_scal_rotate register
* Scaling and rotating coefficient register
*/
typedef union {
struct {
/** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1;
* The integrated part of scaling coefficient in X direction.
*/
uint32_t sr_scal_x_int:8;
/** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0;
* The fragment part of scaling coefficient in X direction.
*/
uint32_t sr_scal_x_frag:4;
/** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1;
* The integrated part of scaling coefficient in Y direction.
*/
uint32_t sr_scal_y_int:8;
/** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0;
* The fragment part of scaling coefficient in Y direction.
*/
uint32_t sr_scal_y_frag:4;
/** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0;
* The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree.
*/
uint32_t sr_rotate_angle:2;
/** scal_rotate_rst : R/W; bitpos: [26]; default: 0;
* Write 1 then write 0 to this bit to reset scaling and rotating engine.
*/
uint32_t scal_rotate_rst:1;
/** scal_rotate_start : WT; bitpos: [27]; default: 0;
* Write 1 to enable scaling and rotating engine after parameter is configured.
*/
uint32_t scal_rotate_start:1;
/** sr_mirror_x : R/W; bitpos: [28]; default: 0;
* Image mirror in X direction. 0: disable, 1: enable
*/
uint32_t sr_mirror_x:1;
/** sr_mirror_y : R/W; bitpos: [29]; default: 0;
* Image mirror in Y direction. 0: disable, 1: enable
*/
uint32_t sr_mirror_y:1;
uint32_t reserved_30:2;
};
uint32_t val;
} ppa_sr_scal_rotate_reg_t;
/** Type of sr_mem_pd register
* SR memory power done register
*/
typedef union {
struct {
/** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to force clock enable of scaling and rotating engine's data memory.
*/
uint32_t sr_mem_clk_ena:1;
/** sr_mem_force_pd : R/W; bitpos: [1]; default: 0;
* Set this bit to force power down scaling and rotating engine's data memory.
*/
uint32_t sr_mem_force_pd:1;
/** sr_mem_force_pu : R/W; bitpos: [2]; default: 0;
* Set this bit to force power up scaling and rotating engine's data memory.
*/
uint32_t sr_mem_force_pu:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_sr_mem_pd_reg_t;
/** Type of reg_conf register
* Register clock enable register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* PPA register clock gate enable signal.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ppa_reg_conf_reg_t;
/** Type of eco_low register
* Reserved.
*/
typedef union {
struct {
/** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
* Reserved.
*/
uint32_t rnd_eco_low:32;
};
uint32_t val;
} ppa_eco_low_reg_t;
/** Type of eco_high register
* Reserved.
*/
typedef union {
struct {
/** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* Reserved.
*/
uint32_t rnd_eco_high:32;
};
uint32_t val;
} ppa_eco_high_reg_t;
/** Type of sram_ctrl register
* PPA SRAM Control Register
*/
typedef union {
struct {
/** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
* Control signals
*/
uint32_t mem_aux_ctrl:14;
uint32_t reserved_14:18;
};
uint32_t val;
} ppa_sram_ctrl_reg_t;
/** Group: Interrupt Registers */
/** Type of int_raw register
* Raw status interrupt
*/
typedef union {
struct {
/** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when scaling and rotating engine
* calculate one frame image.
*/
uint32_t sr_eof_int_raw:1;
/** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when blending engine calculate one frame
* image.
*/
uint32_t blend_eof_int_raw:1;
/** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when the configured scaling and rotating
* coefficient is wrong. User can check the reasons through register
* PPA_SR_PARAM_ERR_ST_REG.
*/
uint32_t sr_param_cfg_err_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt
*/
typedef union {
struct {
/** sr_eof_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PPA_SR_EOF_INT interrupt.
*/
uint32_t sr_eof_int_st:1;
/** blend_eof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt.
*/
uint32_t blend_eof_int_st:1;
/** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
*/
uint32_t sr_param_cfg_err_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** sr_eof_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PPA_SR_EOF_INT interrupt.
*/
uint32_t sr_eof_int_ena:1;
/** blend_eof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt.
*/
uint32_t blend_eof_int_ena:1;
/** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
*/
uint32_t sr_param_cfg_err_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** sr_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PPA_SR_EOF_INT interrupt.
*/
uint32_t sr_eof_int_clr:1;
/** blend_eof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PPA_BLEND_EOF_INT interrupt.
*/
uint32_t blend_eof_int_clr:1;
/** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
*/
uint32_t sr_param_cfg_err_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_int_clr_reg_t;
/** Group: Status Registers */
/** Type of clut_cnt register
* BLEND CLUT write counter register
*/
typedef union {
struct {
/** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0;
* The write data counter of BLEND0 CLUT in fifo mode.
*/
uint32_t blend0_clut_cnt:9;
/** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0;
* The write data counter of BLEND1 CLUT in fifo mode.
*/
uint32_t blend1_clut_cnt:9;
uint32_t reserved_18:14;
};
uint32_t val;
} ppa_clut_cnt_reg_t;
/** Type of blend_st register
* Blending engine status register
*/
typedef union {
struct {
/** blend_size_diff_st : RO; bitpos: [0]; default: 0;
* 1: indicate the size of two image is different.
*/
uint32_t blend_size_diff_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ppa_blend_st_reg_t;
/** Type of sr_param_err_st register
* Scaling and rotating coefficient error register
*/
typedef union {
struct {
/** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0;
* The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive
* descriptor is larger than VA in 2DDMA receive descriptor.
*/
uint32_t tx_dscr_vb_err_st:1;
/** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0;
* The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive
* descriptor is larger than HA in 2DDMA receive descriptor.
*/
uint32_t tx_dscr_hb_err_st:1;
/** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0;
* The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0.
*/
uint32_t y_rx_scal_equal_0_err_st:1;
/** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0;
* The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in
* 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor
*/
uint32_t rx_dscr_vb_err_st:1;
/** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0;
* The error is that the scaled image width is 0. For example. when source width is
* 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as
* the result would be floored.
*/
uint32_t ydst_len_too_samll_err_st:1;
/** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0;
* The error is that the scaled width is larger than (2^13 - 1).
*/
uint32_t ydst_len_too_large_err_st:1;
/** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0;
* The error is that the scaled image height is 0.
*/
uint32_t x_rx_scal_equal_0_err_st:1;
/** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0;
* The error is that the HB in 2DDMA transmit descriptor plus the offset of X
* coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit
* descriptor.
*/
uint32_t rx_dscr_hb_err_st:1;
/** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0;
* The error is that the scaled image height is 0. For example. when source height is
* 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as
* the result would be floored.
*/
uint32_t xdst_len_too_samll_err_st:1;
/** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0;
* The error is that the scaled image height is larger than (2^13 - 1).
*/
uint32_t xdst_len_too_large_err_st:1;
/** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0;
* The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
* yuv420 rx
*/
uint32_t x_yuv420_rx_scale_err_st:1;
/** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0;
* The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
* yuv420 rx
*/
uint32_t y_yuv420_rx_scale_err_st:1;
/** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0;
* The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
* yuv420 tx
*/
uint32_t x_yuv420_tx_scale_err_st:1;
/** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0;
* The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
* yuv420 tx
*/
uint32_t y_yuv420_tx_scale_err_st:1;
uint32_t reserved_14:18;
};
uint32_t val;
} ppa_sr_param_err_st_reg_t;
/** Type of sr_status register
* SR FSM register
*/
typedef union {
struct {
/** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0;
* Reserved.
*/
uint32_t sr_rx_dscr_sample_state:2;
/** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0;
* Reserved.
*/
uint32_t sr_rx_scan_state:2;
/** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0;
* Reserved.
*/
uint32_t sr_tx_dscr_sample_state:2;
/** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0;
* Reserved.
*/
uint32_t sr_tx_scan_state:3;
uint32_t reserved_9:23;
};
uint32_t val;
} ppa_sr_status_reg_t;
/** Type of eco_cell_ctrl register
* Reserved.
*/
typedef union {
struct {
/** rdn_result : RO; bitpos: [0]; default: 0;
* Reserved.
*/
uint32_t rdn_result:1;
/** rdn_ena : R/W; bitpos: [1]; default: 0;
* Reserved.
*/
uint32_t rdn_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ppa_eco_cell_ctrl_reg_t;
/** Group: Version Register */
/** Type of date register
* PPA Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36716609;
* register version.
*/
uint32_t date:32;
};
uint32_t val;
} ppa_date_reg_t;
typedef struct {
volatile ppa_blend0_clut_data_reg_t blend0_clut_data;
volatile ppa_blend1_clut_data_reg_t blend1_clut_data;
uint32_t reserved_008;
volatile ppa_clut_conf_reg_t clut_conf;
volatile ppa_int_raw_reg_t int_raw;
volatile ppa_int_st_reg_t int_st;
volatile ppa_int_ena_reg_t int_ena;
volatile ppa_int_clr_reg_t int_clr;
volatile ppa_sr_color_mode_reg_t sr_color_mode;
volatile ppa_blend_color_mode_reg_t blend_color_mode;
volatile ppa_sr_byte_order_reg_t sr_byte_order;
volatile ppa_blend_byte_order_reg_t blend_byte_order;
uint32_t reserved_030;
volatile ppa_blend_trans_mode_reg_t blend_trans_mode;
volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha;
volatile ppa_blend_tx_size_reg_t blend_tx_size;
volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha;
uint32_t reserved_044;
volatile ppa_blend_rgb_reg_t blend_rgb;
volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel;
volatile ppa_ck_fg_low_reg_t ck_fg_low;
volatile ppa_ck_fg_high_reg_t ck_fg_high;
volatile ppa_ck_bg_low_reg_t ck_bg_low;
volatile ppa_ck_bg_high_reg_t ck_bg_high;
volatile ppa_ck_default_reg_t ck_default;
volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate;
volatile ppa_sr_mem_pd_reg_t sr_mem_pd;
volatile ppa_reg_conf_reg_t reg_conf;
volatile ppa_clut_cnt_reg_t clut_cnt;
volatile ppa_blend_st_reg_t blend_st;
volatile ppa_sr_param_err_st_reg_t sr_param_err_st;
volatile ppa_sr_status_reg_t sr_status;
volatile ppa_eco_low_reg_t eco_low;
volatile ppa_eco_high_reg_t eco_high;
volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl;
volatile ppa_sram_ctrl_reg_t sram_ctrl;
uint32_t reserved_090[28];
volatile ppa_date_reg_t date;
} ppa_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
* Represents M
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
* Represents Z
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM register
* Represents Y
*/
#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
#define RSA_Y_MEM_SIZE_BYTES 16
/** RSA_X_MEM register
* Represents X
*/
#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
#define RSA_X_MEM_SIZE_BYTES 16
/** RSA_M_PRIME_REG register
* Represents M’
*/
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
* Represents M’
*/
#define RSA_M_PRIME 0xFFFFFFFFU
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
#define RSA_M_PRIME_V 0xFFFFFFFFU
#define RSA_M_PRIME_S 0
/** RSA_MODE_REG register
* Configures RSA length
*/
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
#define RSA_MODE 0x0000007FU
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
#define RSA_MODE_V 0x0000007FU
#define RSA_MODE_S 0
/** RSA_QUERY_CLEAN_REG register
* RSA clean register
*/
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.
*
* 0: Not complete
*
* 1: Completed
*
*/
#define RSA_QUERY_CLEAN (BIT(0))
#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
#define RSA_QUERY_CLEAN_V 0x00000001U
#define RSA_QUERY_CLEAN_S 0
/** RSA_SET_START_MODEXP_REG register
* Starts modular exponentiation
*/
#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular exponentiation.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MODEXP (BIT(0))
#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
#define RSA_SET_START_MODEXP_V 0x00000001U
#define RSA_SET_START_MODEXP_S 0
/** RSA_SET_START_MODMULT_REG register
* Starts modular multiplication
*/
#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MODMULT (BIT(0))
#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
#define RSA_SET_START_MODMULT_V 0x00000001U
#define RSA_SET_START_MODMULT_S 0
/** RSA_SET_START_MULT_REG register
* Starts multiplication
*/
#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MULT (BIT(0))
#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
#define RSA_SET_START_MULT_V 0x00000001U
#define RSA_SET_START_MULT_S 0
/** RSA_QUERY_IDLE_REG register
* Represents the RSA status
*/
#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
* Represents the RSA status.
*
* 0: Busy
*
* 1: Idle
*
*/
#define RSA_QUERY_IDLE (BIT(0))
#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
#define RSA_QUERY_IDLE_V 0x00000001U
#define RSA_QUERY_IDLE_S 0
/** RSA_INT_CLR_REG register
* Clears RSA interrupt
*/
#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
#define RSA_CLEAR_INTERRUPT (BIT(0))
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
#define RSA_CLEAR_INTERRUPT_V 0x00000001U
#define RSA_CLEAR_INTERRUPT_S 0
/** RSA_CONSTANT_TIME_REG register
* Configures the constant_time option
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option.
*
* 0: Acceleration
*
* 1: No acceleration (default)
*
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
#define RSA_CONSTANT_TIME_V 0x00000001U
#define RSA_CONSTANT_TIME_S 0
/** RSA_SEARCH_ENABLE_REG register
* Configures the search option
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Configure the search option.
*
* 0: No acceleration (default)
*
* 1: Acceleration
*
* This option should be used together with RSA_SEARCH_POS.
*/
#define RSA_SEARCH_ENABLE (BIT(0))
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
#define RSA_SEARCH_ENABLE_V 0x00000001U
#define RSA_SEARCH_ENABLE_S 0
/** RSA_SEARCH_POS_REG register
* Configures the search position
*/
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
#define RSA_SEARCH_POS 0x00000FFFU
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
#define RSA_SEARCH_POS_V 0x00000FFFU
#define RSA_SEARCH_POS_S 0
/** RSA_INT_ENA_REG register
* Enables the RSA interrupt
*/
#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
#define RSA_INT_ENA (BIT(0))
#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S)
#define RSA_INT_ENA_V 0x00000001U
#define RSA_INT_ENA_S 0
/** RSA_DATE_REG register
* Version control register
*/
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
#define RSA_DATE 0x3FFFFFFFU
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
#define RSA_DATE_V 0x3FFFFFFFU
#define RSA_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory */
/** Group: Control / Configuration Registers */
/** Type of m_prime register
* Represents M’
*/
typedef union {
struct {
/** m_prime : R/W; bitpos: [31:0]; default: 0;
* Represents M’
*/
uint32_t m_prime:32;
};
uint32_t val;
} rsa_m_prime_reg_t;
/** Type of mode register
* Configures RSA length
*/
typedef union {
struct {
/** mode : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
uint32_t mode:7;
uint32_t reserved_7:25;
};
uint32_t val;
} rsa_mode_reg_t;
/** Type of set_start_modexp register
* Starts modular exponentiation
*/
typedef union {
struct {
/** set_start_modexp : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular exponentiation.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_modexp:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modexp_reg_t;
/** Type of set_start_modmult register
* Starts modular multiplication
*/
typedef union {
struct {
/** set_start_modmult : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_modmult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modmult_reg_t;
/** Type of set_start_mult register
* Starts multiplication
*/
typedef union {
struct {
/** set_start_mult : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_mult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_mult_reg_t;
/** Type of query_idle register
* Represents the RSA status
*/
typedef union {
struct {
/** query_idle : RO; bitpos: [0]; default: 0;
* Represents the RSA status.
*
* 0: Busy
*
* 1: Idle
*
*/
uint32_t query_idle:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_idle_reg_t;
/** Type of constant_time register
* Configures the constant_time option
*/
typedef union {
struct {
/** constant_time : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option.
*
* 0: Acceleration
*
* 1: No acceleration (default)
*
*/
uint32_t constant_time:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_constant_time_reg_t;
/** Type of search_enable register
* Configures the search option
*/
typedef union {
struct {
/** search_enable : R/W; bitpos: [0]; default: 0;
* Configure the search option.
*
* 0: No acceleration (default)
*
* 1: Acceleration
*
* This option should be used together with RSA_SEARCH_POS.
*/
uint32_t search_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_search_enable_reg_t;
/** Type of search_pos register
* Configures the search position
*/
typedef union {
struct {
/** search_pos : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
uint32_t search_pos:12;
uint32_t reserved_12:20;
};
uint32_t val;
} rsa_search_pos_reg_t;
/** Group: Status Register */
/** Type of query_clean register
* RSA clean register
*/
typedef union {
struct {
/** query_clean : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.
*
* 0: Not complete
*
* 1: Completed
*
*/
uint32_t query_clean:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_clean_reg_t;
/** Group: Interrupt Registers */
/** Type of int_clr register
* Clears RSA interrupt
*/
typedef union {
struct {
/** clear_interrupt : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_clr_reg_t;
/** Type of int_ena register
* Enables the RSA interrupt
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_ena_reg_t;
/** Group: Version Control Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} rsa_date_reg_t;
typedef struct {
volatile uint32_t m[4];
uint32_t reserved_010[124];
volatile uint32_t z[4];
uint32_t reserved_210[124];
volatile uint32_t y[4];
uint32_t reserved_410[124];
volatile uint32_t x[4];
uint32_t reserved_610[124];
volatile rsa_m_prime_reg_t m_prime;
volatile rsa_mode_reg_t mode;
volatile rsa_query_clean_reg_t query_clean;
volatile rsa_set_start_modexp_reg_t set_start_modexp;
volatile rsa_set_start_modmult_reg_t set_start_modmult;
volatile rsa_set_start_mult_reg_t set_start_mult;
volatile rsa_query_idle_reg_t query_idle;
volatile rsa_int_clr_reg_t int_clr;
volatile rsa_constant_time_reg_t constant_time;
volatile rsa_search_enable_reg_t search_enable;
volatile rsa_search_pos_reg_t search_pos;
volatile rsa_int_ena_reg_t int_ena;
volatile rsa_date_reg_t date;
} rsa_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RTC_TIMER_TAR0_LOW_REG register
* need_des
*/
#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0)
/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** RTC_TIMER_TAR0_HIGH_REG register
* need_des
*/
#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4)
/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S)
#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** RTC_TIMER_TAR1_LOW_REG register
* need_des
*/
#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8)
/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** RTC_TIMER_TAR1_HIGH_REG register
* need_des
*/
#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc)
/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S)
#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** RTC_TIMER_UPDATE_REG register
* need_des
*/
#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10)
/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28))
#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S)
#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28
/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S)
#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S)
#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31
/** RTC_TIMER_MAIN_BUF0_LOW_REG register
* need_des
*/
#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14)
/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** RTC_TIMER_MAIN_BUF0_HIGH_REG register
* need_des
*/
#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18)
/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** RTC_TIMER_MAIN_BUF1_LOW_REG register
* need_des
*/
#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c)
/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** RTC_TIMER_MAIN_BUF1_HIGH_REG register
* need_des
*/
#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20)
/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** RTC_TIMER_MAIN_OVERFLOW_REG register
* need_des
*/
#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24)
/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** RTC_TIMER_INT_RAW_REG register
* need_des
*/
#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28)
/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_OVERFLOW_RAW (BIT(30))
#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S)
#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U
#define RTC_TIMER_OVERFLOW_RAW_S 30
/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S)
#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** RTC_TIMER_INT_ST_REG register
* need_des
*/
#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c)
/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_OVERFLOW_ST (BIT(30))
#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S)
#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U
#define RTC_TIMER_OVERFLOW_ST_S 30
/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S)
#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31
/** RTC_TIMER_INT_ENA_REG register
* need_des
*/
#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30)
/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_OVERFLOW_ENA (BIT(30))
#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S)
#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U
#define RTC_TIMER_OVERFLOW_ENA_S 30
/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S)
#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** RTC_TIMER_INT_CLR_REG register
* need_des
*/
#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34)
/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_OVERFLOW_CLR (BIT(30))
#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S)
#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U
#define RTC_TIMER_OVERFLOW_CLR_S 30
/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S)
#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** RTC_TIMER_LP_INT_RAW_REG register
* need_des
*/
#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38)
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** RTC_TIMER_LP_INT_ST_REG register
* need_des
*/
#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c)
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** RTC_TIMER_LP_INT_ENA_REG register
* need_des
*/
#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40)
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** RTC_TIMER_LP_INT_CLR_REG register
* need_des
*/
#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44)
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** RTC_TIMER_DATE_REG register
* need_des
*/
#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc)
/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
#define RTC_TIMER_DATE 0x7FFFFFFFU
#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S)
#define RTC_TIMER_DATE_V 0x7FFFFFFFU
#define RTC_TIMER_DATE_S 0
/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_TIMER_CLK_EN (BIT(31))
#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S)
#define RTC_TIMER_CLK_EN_V 0x00000001U
#define RTC_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

362
components/soc/esp32p4/include/soc/rtc_timer_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} rtc_timer_tar0_low_reg_t;
/** Type of tar0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en0:1;
};
uint32_t val;
} rtc_timer_tar0_high_reg_t;
/** Type of tar1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low1:32;
};
uint32_t val;
} rtc_timer_tar1_low_reg_t;
/** Type of tar1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high1:16;
uint32_t reserved_16:15;
/** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en1:1;
};
uint32_t val;
} rtc_timer_tar1_high_reg_t;
/** Type of update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** main_timer_update : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t main_timer_update:1;
/** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t main_timer_xtal_off:1;
/** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_sys_stall:1;
/** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_sys_rst:1;
};
uint32_t val;
} rtc_timer_update_reg_t;
/** Type of main_buf0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_low:32;
};
uint32_t val;
} rtc_timer_main_buf0_low_reg_t;
/** Type of main_buf0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} rtc_timer_main_buf0_high_reg_t;
/** Type of main_buf1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_low:32;
};
uint32_t val;
} rtc_timer_main_buf1_low_reg_t;
/** Type of main_buf1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} rtc_timer_main_buf1_high_reg_t;
/** Type of main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_alarm_load:1;
};
uint32_t val;
} rtc_timer_main_overflow_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_raw:1;
/** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_raw:1;
};
uint32_t val;
} rtc_timer_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_st:1;
/** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_st:1;
};
uint32_t val;
} rtc_timer_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_ena:1;
/** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_ena:1;
};
uint32_t val;
} rtc_timer_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_clr:1;
/** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_clr:1;
};
uint32_t val;
} rtc_timer_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_raw:1;
/** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_raw:1;
};
uint32_t val;
} rtc_timer_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_st:1;
/** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_st:1;
};
uint32_t val;
} rtc_timer_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_ena:1;
/** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_ena:1;
};
uint32_t val;
} rtc_timer_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_clr:1;
/** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_clr:1;
};
uint32_t val;
} rtc_timer_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} rtc_timer_date_reg_t;
typedef struct {
volatile rtc_timer_tar0_low_reg_t tar0_low;
volatile rtc_timer_tar0_high_reg_t tar0_high;
volatile rtc_timer_tar1_low_reg_t tar1_low;
volatile rtc_timer_tar1_high_reg_t tar1_high;
volatile rtc_timer_update_reg_t update;
volatile rtc_timer_main_buf0_low_reg_t main_buf0_low;
volatile rtc_timer_main_buf0_high_reg_t main_buf0_high;
volatile rtc_timer_main_buf1_low_reg_t main_buf1_low;
volatile rtc_timer_main_buf1_high_reg_t main_buf1_high;
volatile rtc_timer_main_overflow_reg_t main_overflow;
volatile rtc_timer_int_raw_reg_t int_raw;
volatile rtc_timer_int_st_reg_t int_st;
volatile rtc_timer_int_ena_reg_t int_ena;
volatile rtc_timer_int_clr_reg_t int_clr;
volatile rtc_timer_lp_int_raw_reg_t lp_int_raw;
volatile rtc_timer_lp_int_st_reg_t lp_int_st;
volatile rtc_timer_lp_int_ena_reg_t lp_int_ena;
volatile rtc_timer_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_048[237];
volatile rtc_timer_date_reg_t date;
} rtc_timer_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(rtc_timer_dev_t) == 0x400, "Invalid size of rtc_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

324
components/soc/esp32p4/include/soc/rtc_wdt_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RTC_WDT_CONFIG0_REG register
* need_des
*/
#define RTC_WDT_CONFIG0_REG (DR_REG_RTC_WDT_BASE + 0x0)
/** RTC_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define RTC_WDT_WDT_PAUSE_IN_SLP (BIT(9))
#define RTC_WDT_WDT_PAUSE_IN_SLP_M (RTC_WDT_WDT_PAUSE_IN_SLP_V << RTC_WDT_WDT_PAUSE_IN_SLP_S)
#define RTC_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
#define RTC_WDT_WDT_PAUSE_IN_SLP_S 9
/** RTC_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_APPCPU_RESET_EN (BIT(10))
#define RTC_WDT_WDT_APPCPU_RESET_EN_M (RTC_WDT_WDT_APPCPU_RESET_EN_V << RTC_WDT_WDT_APPCPU_RESET_EN_S)
#define RTC_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
#define RTC_WDT_WDT_APPCPU_RESET_EN_S 10
/** RTC_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_PROCPU_RESET_EN (BIT(11))
#define RTC_WDT_WDT_PROCPU_RESET_EN_M (RTC_WDT_WDT_PROCPU_RESET_EN_V << RTC_WDT_WDT_PROCPU_RESET_EN_S)
#define RTC_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
#define RTC_WDT_WDT_PROCPU_RESET_EN_S 11
/** RTC_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
* need_des
*/
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_M (RTC_WDT_WDT_FLASHBOOT_MOD_EN_V << RTC_WDT_WDT_FLASHBOOT_MOD_EN_S)
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/** RTC_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
* need_des
*/
#define RTC_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
#define RTC_WDT_WDT_SYS_RESET_LENGTH_M (RTC_WDT_WDT_SYS_RESET_LENGTH_V << RTC_WDT_WDT_SYS_RESET_LENGTH_S)
#define RTC_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define RTC_WDT_WDT_SYS_RESET_LENGTH_S 13
/** RTC_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
* need_des
*/
#define RTC_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
#define RTC_WDT_WDT_CPU_RESET_LENGTH_M (RTC_WDT_WDT_CPU_RESET_LENGTH_V << RTC_WDT_WDT_CPU_RESET_LENGTH_S)
#define RTC_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define RTC_WDT_WDT_CPU_RESET_LENGTH_S 16
/** RTC_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_STG3 0x00000007U
#define RTC_WDT_WDT_STG3_M (RTC_WDT_WDT_STG3_V << RTC_WDT_WDT_STG3_S)
#define RTC_WDT_WDT_STG3_V 0x00000007U
#define RTC_WDT_WDT_STG3_S 19
/** RTC_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_STG2 0x00000007U
#define RTC_WDT_WDT_STG2_M (RTC_WDT_WDT_STG2_V << RTC_WDT_WDT_STG2_S)
#define RTC_WDT_WDT_STG2_V 0x00000007U
#define RTC_WDT_WDT_STG2_S 22
/** RTC_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_STG1 0x00000007U
#define RTC_WDT_WDT_STG1_M (RTC_WDT_WDT_STG1_V << RTC_WDT_WDT_STG1_S)
#define RTC_WDT_WDT_STG1_V 0x00000007U
#define RTC_WDT_WDT_STG1_S 25
/** RTC_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_STG0 0x00000007U
#define RTC_WDT_WDT_STG0_M (RTC_WDT_WDT_STG0_V << RTC_WDT_WDT_STG0_S)
#define RTC_WDT_WDT_STG0_V 0x00000007U
#define RTC_WDT_WDT_STG0_S 28
/** RTC_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_EN (BIT(31))
#define RTC_WDT_WDT_EN_M (RTC_WDT_WDT_EN_V << RTC_WDT_WDT_EN_S)
#define RTC_WDT_WDT_EN_V 0x00000001U
#define RTC_WDT_WDT_EN_S 31
/** RTC_WDT_CONFIG1_REG register
* need_des
*/
#define RTC_WDT_CONFIG1_REG (DR_REG_RTC_WDT_BASE + 0x4)
/** RTC_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
* need_des
*/
#define RTC_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
#define RTC_WDT_WDT_STG0_HOLD_M (RTC_WDT_WDT_STG0_HOLD_V << RTC_WDT_WDT_STG0_HOLD_S)
#define RTC_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define RTC_WDT_WDT_STG0_HOLD_S 0
/** RTC_WDT_CONFIG2_REG register
* need_des
*/
#define RTC_WDT_CONFIG2_REG (DR_REG_RTC_WDT_BASE + 0x8)
/** RTC_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
* need_des
*/
#define RTC_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
#define RTC_WDT_WDT_STG1_HOLD_M (RTC_WDT_WDT_STG1_HOLD_V << RTC_WDT_WDT_STG1_HOLD_S)
#define RTC_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define RTC_WDT_WDT_STG1_HOLD_S 0
/** RTC_WDT_CONFIG3_REG register
* need_des
*/
#define RTC_WDT_CONFIG3_REG (DR_REG_RTC_WDT_BASE + 0xc)
/** RTC_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
#define RTC_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
#define RTC_WDT_WDT_STG2_HOLD_M (RTC_WDT_WDT_STG2_HOLD_V << RTC_WDT_WDT_STG2_HOLD_S)
#define RTC_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define RTC_WDT_WDT_STG2_HOLD_S 0
/** RTC_WDT_CONFIG4_REG register
* need_des
*/
#define RTC_WDT_CONFIG4_REG (DR_REG_RTC_WDT_BASE + 0x10)
/** RTC_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
#define RTC_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
#define RTC_WDT_WDT_STG3_HOLD_M (RTC_WDT_WDT_STG3_HOLD_V << RTC_WDT_WDT_STG3_HOLD_S)
#define RTC_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define RTC_WDT_WDT_STG3_HOLD_S 0
/** RTC_WDT_FEED_REG register
* need_des
*/
#define RTC_WDT_FEED_REG (DR_REG_RTC_WDT_BASE + 0x14)
/** RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_FEED (BIT(31))
#define RTC_WDT_FEED_M (RTC_WDT_FEED_V << RTC_WDT_FEED_S)
#define RTC_WDT_FEED_V 0x00000001U
#define RTC_WDT_FEED_S 31
/** RTC_WDT_WPROTECT_REG register
* need_des
*/
#define RTC_WDT_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x18)
/** RTC_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define RTC_WDT_WDT_WKEY 0xFFFFFFFFU
#define RTC_WDT_WDT_WKEY_M (RTC_WDT_WDT_WKEY_V << RTC_WDT_WDT_WKEY_S)
#define RTC_WDT_WDT_WKEY_V 0xFFFFFFFFU
#define RTC_WDT_WDT_WKEY_S 0
/** RTC_WDT_SWD_CONFIG_REG register
* need_des
*/
#define RTC_WDT_SWD_CONFIG_REG (DR_REG_RTC_WDT_BASE + 0x1c)
/** RTC_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
* need_des
*/
#define RTC_WDT_SWD_RESET_FLAG (BIT(0))
#define RTC_WDT_SWD_RESET_FLAG_M (RTC_WDT_SWD_RESET_FLAG_V << RTC_WDT_SWD_RESET_FLAG_S)
#define RTC_WDT_SWD_RESET_FLAG_V 0x00000001U
#define RTC_WDT_SWD_RESET_FLAG_S 0
/** RTC_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
* need_des
*/
#define RTC_WDT_SWD_AUTO_FEED_EN (BIT(18))
#define RTC_WDT_SWD_AUTO_FEED_EN_M (RTC_WDT_SWD_AUTO_FEED_EN_V << RTC_WDT_SWD_AUTO_FEED_EN_S)
#define RTC_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
#define RTC_WDT_SWD_AUTO_FEED_EN_S 18
/** RTC_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
* need_des
*/
#define RTC_WDT_SWD_RST_FLAG_CLR (BIT(19))
#define RTC_WDT_SWD_RST_FLAG_CLR_M (RTC_WDT_SWD_RST_FLAG_CLR_V << RTC_WDT_SWD_RST_FLAG_CLR_S)
#define RTC_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
#define RTC_WDT_SWD_RST_FLAG_CLR_S 19
/** RTC_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
* need_des
*/
#define RTC_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
#define RTC_WDT_SWD_SIGNAL_WIDTH_M (RTC_WDT_SWD_SIGNAL_WIDTH_V << RTC_WDT_SWD_SIGNAL_WIDTH_S)
#define RTC_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
#define RTC_WDT_SWD_SIGNAL_WIDTH_S 20
/** RTC_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_WDT_SWD_DISABLE (BIT(30))
#define RTC_WDT_SWD_DISABLE_M (RTC_WDT_SWD_DISABLE_V << RTC_WDT_SWD_DISABLE_S)
#define RTC_WDT_SWD_DISABLE_V 0x00000001U
#define RTC_WDT_SWD_DISABLE_S 30
/** RTC_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_SWD_FEED (BIT(31))
#define RTC_WDT_SWD_FEED_M (RTC_WDT_SWD_FEED_V << RTC_WDT_SWD_FEED_S)
#define RTC_WDT_SWD_FEED_V 0x00000001U
#define RTC_WDT_SWD_FEED_S 31
/** RTC_WDT_SWD_WPROTECT_REG register
* need_des
*/
#define RTC_WDT_SWD_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x20)
/** RTC_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define RTC_WDT_SWD_WKEY 0xFFFFFFFFU
#define RTC_WDT_SWD_WKEY_M (RTC_WDT_SWD_WKEY_V << RTC_WDT_SWD_WKEY_S)
#define RTC_WDT_SWD_WKEY_V 0xFFFFFFFFU
#define RTC_WDT_SWD_WKEY_S 0
/** RTC_WDT_INT_RAW_REG register
* need_des
*/
#define RTC_WDT_INT_RAW_REG (DR_REG_RTC_WDT_BASE + 0x24)
/** RTC_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_WDT_SUPER_WDT_INT_RAW (BIT(30))
#define RTC_WDT_SUPER_WDT_INT_RAW_M (RTC_WDT_SUPER_WDT_INT_RAW_V << RTC_WDT_SUPER_WDT_INT_RAW_S)
#define RTC_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
#define RTC_WDT_SUPER_WDT_INT_RAW_S 30
/** RTC_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_LP_WDT_INT_RAW (BIT(31))
#define RTC_WDT_LP_WDT_INT_RAW_M (RTC_WDT_LP_WDT_INT_RAW_V << RTC_WDT_LP_WDT_INT_RAW_S)
#define RTC_WDT_LP_WDT_INT_RAW_V 0x00000001U
#define RTC_WDT_LP_WDT_INT_RAW_S 31
/** RTC_WDT_INT_ST_REG register
* need_des
*/
#define RTC_WDT_INT_ST_REG (DR_REG_RTC_WDT_BASE + 0x28)
/** RTC_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_WDT_SUPER_WDT_INT_ST (BIT(30))
#define RTC_WDT_SUPER_WDT_INT_ST_M (RTC_WDT_SUPER_WDT_INT_ST_V << RTC_WDT_SUPER_WDT_INT_ST_S)
#define RTC_WDT_SUPER_WDT_INT_ST_V 0x00000001U
#define RTC_WDT_SUPER_WDT_INT_ST_S 30
/** RTC_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_LP_WDT_INT_ST (BIT(31))
#define RTC_WDT_LP_WDT_INT_ST_M (RTC_WDT_LP_WDT_INT_ST_V << RTC_WDT_LP_WDT_INT_ST_S)
#define RTC_WDT_LP_WDT_INT_ST_V 0x00000001U
#define RTC_WDT_LP_WDT_INT_ST_S 31
/** RTC_WDT_INT_ENA_REG register
* need_des
*/
#define RTC_WDT_INT_ENA_REG (DR_REG_RTC_WDT_BASE + 0x2c)
/** RTC_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_WDT_SUPER_WDT_INT_ENA (BIT(30))
#define RTC_WDT_SUPER_WDT_INT_ENA_M (RTC_WDT_SUPER_WDT_INT_ENA_V << RTC_WDT_SUPER_WDT_INT_ENA_S)
#define RTC_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
#define RTC_WDT_SUPER_WDT_INT_ENA_S 30
/** RTC_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_LP_WDT_INT_ENA (BIT(31))
#define RTC_WDT_LP_WDT_INT_ENA_M (RTC_WDT_LP_WDT_INT_ENA_V << RTC_WDT_LP_WDT_INT_ENA_S)
#define RTC_WDT_LP_WDT_INT_ENA_V 0x00000001U
#define RTC_WDT_LP_WDT_INT_ENA_S 31
/** RTC_WDT_INT_CLR_REG register
* need_des
*/
#define RTC_WDT_INT_CLR_REG (DR_REG_RTC_WDT_BASE + 0x30)
/** RTC_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define RTC_WDT_SUPER_WDT_INT_CLR (BIT(30))
#define RTC_WDT_SUPER_WDT_INT_CLR_M (RTC_WDT_SUPER_WDT_INT_CLR_V << RTC_WDT_SUPER_WDT_INT_CLR_S)
#define RTC_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
#define RTC_WDT_SUPER_WDT_INT_CLR_S 30
/** RTC_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_LP_WDT_INT_CLR (BIT(31))
#define RTC_WDT_LP_WDT_INT_CLR_M (RTC_WDT_LP_WDT_INT_CLR_V << RTC_WDT_LP_WDT_INT_CLR_S)
#define RTC_WDT_LP_WDT_INT_CLR_V 0x00000001U
#define RTC_WDT_LP_WDT_INT_CLR_S 31
/** RTC_WDT_DATE_REG register
* need_des
*/
#define RTC_WDT_DATE_REG (DR_REG_RTC_WDT_BASE + 0x3fc)
/** RTC_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
* need_des
*/
#define RTC_WDT_LP_WDT_DATE 0x7FFFFFFFU
#define RTC_WDT_LP_WDT_DATE_M (RTC_WDT_LP_WDT_DATE_V << RTC_WDT_LP_WDT_DATE_S)
#define RTC_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
#define RTC_WDT_LP_WDT_DATE_S 0
/** RTC_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTC_WDT_CLK_EN (BIT(31))
#define RTC_WDT_CLK_EN_M (RTC_WDT_CLK_EN_V << RTC_WDT_CLK_EN_S)
#define RTC_WDT_CLK_EN_V 0x00000001U
#define RTC_WDT_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/rtc_wdt_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t wdt_pause_in_slp:1;
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
* need_des
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
* need_des
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
* need_des
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
* need_des
*/
uint32_t wdt_stg3:3;
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
* need_des
*/
uint32_t wdt_stg2:3;
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
* need_des
*/
uint32_t wdt_stg1:3;
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
uint32_t wdt_stg0:3;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t wdt_en:1;
};
uint32_t val;
} rtc_wdt_config0_reg_t;
/** Type of config1 register
* need_des
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
* need_des
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} rtc_wdt_config1_reg_t;
/** Type of config2 register
* need_des
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
* need_des
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} rtc_wdt_config2_reg_t;
/** Type of config3 register
* need_des
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} rtc_wdt_config3_reg_t;
/** Type of config4 register
* need_des
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} rtc_wdt_config4_reg_t;
/** Type of feed register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** feed : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t feed:1;
};
uint32_t val;
} rtc_wdt_feed_reg_t;
/** Type of wprotect register
* need_des
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} rtc_wdt_wprotect_reg_t;
/** Type of swd_config register
* need_des
*/
typedef union {
struct {
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t swd_reset_flag:1;
uint32_t reserved_1:17;
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
* need_des
*/
uint32_t swd_auto_feed_en:1;
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
* need_des
*/
uint32_t swd_rst_flag_clr:1;
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
* need_des
*/
uint32_t swd_signal_width:10;
/** swd_disable : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t swd_disable:1;
/** swd_feed : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t swd_feed:1;
};
uint32_t val;
} rtc_wdt_swd_config_reg_t;
/** Type of swd_wprotect register
* need_des
*/
typedef union {
struct {
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t swd_wkey:32;
};
uint32_t val;
} rtc_wdt_swd_wprotect_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_raw:1;
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_raw:1;
};
uint32_t val;
} rtc_wdt_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_st:1;
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_st:1;
};
uint32_t val;
} rtc_wdt_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_ena:1;
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_ena:1;
};
uint32_t val;
} rtc_wdt_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_clr:1;
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_clr:1;
};
uint32_t val;
} rtc_wdt_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
* need_des
*/
uint32_t lp_wdt_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} rtc_wdt_date_reg_t;
typedef struct {
volatile rtc_wdt_config0_reg_t config0;
volatile rtc_wdt_config1_reg_t config1;
volatile rtc_wdt_config2_reg_t config2;
volatile rtc_wdt_config3_reg_t config3;
volatile rtc_wdt_config4_reg_t config4;
volatile rtc_wdt_feed_reg_t feed;
volatile rtc_wdt_wprotect_reg_t wprotect;
volatile rtc_wdt_swd_config_reg_t swd_config;
volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect;
volatile rtc_wdt_int_raw_reg_t int_raw;
volatile rtc_wdt_int_st_reg_t int_st;
volatile rtc_wdt_int_ena_reg_t int_ena;
volatile rtc_wdt_int_clr_reg_t int_clr;
uint32_t reserved_034[242];
volatile rtc_wdt_date_reg_t date;
} rtc_wdt_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(rtc_wdt_dev_t) == 0x400, "Invalid size of rtc_wdt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

704
components/soc/esp32p4/include/soc/rtcadc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RTCADC_READER1_CTRL_REG register
* Control the read operation of ADC1.
*/
#define RTCADC_READER1_CTRL_REG (DR_REG_RTCADC_BASE + 0x0)
/** RTCADC_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
* Clock divider.
*/
#define RTCADC_SAR1_CLK_DIV 0x000000FFU
#define RTCADC_SAR1_CLK_DIV_M (RTCADC_SAR1_CLK_DIV_V << RTCADC_SAR1_CLK_DIV_S)
#define RTCADC_SAR1_CLK_DIV_V 0x000000FFU
#define RTCADC_SAR1_CLK_DIV_S 0
/** RTCADC_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0;
* Invert SAR ADC1 data.
*/
#define RTCADC_SAR1_DATA_INV (BIT(28))
#define RTCADC_SAR1_DATA_INV_M (RTCADC_SAR1_DATA_INV_V << RTCADC_SAR1_DATA_INV_S)
#define RTCADC_SAR1_DATA_INV_V 0x00000001U
#define RTCADC_SAR1_DATA_INV_S 28
/** RTCADC_SAR1_INT_EN : R/W; bitpos: [29]; default: 1;
* Enable saradc1 to send out interrupt.
*/
#define RTCADC_SAR1_INT_EN (BIT(29))
#define RTCADC_SAR1_INT_EN_M (RTCADC_SAR1_INT_EN_V << RTCADC_SAR1_INT_EN_S)
#define RTCADC_SAR1_INT_EN_V 0x00000001U
#define RTCADC_SAR1_INT_EN_S 29
/** RTCADC_SAR1_EN_PAD_FORCE_ENABLE : R/W; bitpos: [31:30]; default: 0;
* Force enable adc en_pad to analog circuit 2'b11: force enable .
*/
#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE 0x00000003U
#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_M (RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S)
#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V 0x00000003U
#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S 30
/** RTCADC_MEAS1_CTRL2_REG register
* ADC1 configuration registers.
*/
#define RTCADC_MEAS1_CTRL2_REG (DR_REG_RTCADC_BASE + 0xc)
/** RTCADC_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0;
* SAR ADC1 data.
*/
#define RTCADC_MEAS1_DATA_SAR 0x0000FFFFU
#define RTCADC_MEAS1_DATA_SAR_M (RTCADC_MEAS1_DATA_SAR_V << RTCADC_MEAS1_DATA_SAR_S)
#define RTCADC_MEAS1_DATA_SAR_V 0x0000FFFFU
#define RTCADC_MEAS1_DATA_SAR_S 0
/** RTCADC_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0;
* SAR ADC1 conversion done indication.
*/
#define RTCADC_MEAS1_DONE_SAR (BIT(16))
#define RTCADC_MEAS1_DONE_SAR_M (RTCADC_MEAS1_DONE_SAR_V << RTCADC_MEAS1_DONE_SAR_S)
#define RTCADC_MEAS1_DONE_SAR_V 0x00000001U
#define RTCADC_MEAS1_DONE_SAR_S 16
/** RTCADC_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0;
* SAR ADC1 controller (in RTC) starts conversion.
*/
#define RTCADC_MEAS1_START_SAR (BIT(17))
#define RTCADC_MEAS1_START_SAR_M (RTCADC_MEAS1_START_SAR_V << RTCADC_MEAS1_START_SAR_S)
#define RTCADC_MEAS1_START_SAR_V 0x00000001U
#define RTCADC_MEAS1_START_SAR_S 17
/** RTCADC_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0;
* 1: SAR ADC1 controller (in RTC) is started by SW.
*/
#define RTCADC_MEAS1_START_FORCE (BIT(18))
#define RTCADC_MEAS1_START_FORCE_M (RTCADC_MEAS1_START_FORCE_V << RTCADC_MEAS1_START_FORCE_S)
#define RTCADC_MEAS1_START_FORCE_V 0x00000001U
#define RTCADC_MEAS1_START_FORCE_S 18
/** RTCADC_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0;
* SAR ADC1 pad enable bitmap.
*/
#define RTCADC_SAR1_EN_PAD 0x00000FFFU
#define RTCADC_SAR1_EN_PAD_M (RTCADC_SAR1_EN_PAD_V << RTCADC_SAR1_EN_PAD_S)
#define RTCADC_SAR1_EN_PAD_V 0x00000FFFU
#define RTCADC_SAR1_EN_PAD_S 19
/** RTCADC_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
* 1: SAR ADC1 pad enable bitmap is controlled by SW.
*/
#define RTCADC_SAR1_EN_PAD_FORCE (BIT(31))
#define RTCADC_SAR1_EN_PAD_FORCE_M (RTCADC_SAR1_EN_PAD_FORCE_V << RTCADC_SAR1_EN_PAD_FORCE_S)
#define RTCADC_SAR1_EN_PAD_FORCE_V 0x00000001U
#define RTCADC_SAR1_EN_PAD_FORCE_S 31
/** RTCADC_MEAS1_MUX_REG register
* SAR ADC1 MUX register.
*/
#define RTCADC_MEAS1_MUX_REG (DR_REG_RTCADC_BASE + 0x10)
/** RTCADC_SAR1_DIG_FORCE : R/W; bitpos: [31]; default: 0;
* 1: SAR ADC1 controlled by DIG ADC1 CTRL.
*/
#define RTCADC_SAR1_DIG_FORCE (BIT(31))
#define RTCADC_SAR1_DIG_FORCE_M (RTCADC_SAR1_DIG_FORCE_V << RTCADC_SAR1_DIG_FORCE_S)
#define RTCADC_SAR1_DIG_FORCE_V 0x00000001U
#define RTCADC_SAR1_DIG_FORCE_S 31
/** RTCADC_ATTEN1_REG register
* ADC1 attenuation registers.
*/
#define RTCADC_ATTEN1_REG (DR_REG_RTCADC_BASE + 0x14)
/** RTCADC_SAR1_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
* 2-bit attenuation for each pad.
*/
#define RTCADC_SAR1_ATTEN 0xFFFFFFFFU
#define RTCADC_SAR1_ATTEN_M (RTCADC_SAR1_ATTEN_V << RTCADC_SAR1_ATTEN_S)
#define RTCADC_SAR1_ATTEN_V 0xFFFFFFFFU
#define RTCADC_SAR1_ATTEN_S 0
/** RTCADC_READER2_CTRL_REG register
* Control the read operation of ADC2.
*/
#define RTCADC_READER2_CTRL_REG (DR_REG_RTCADC_BASE + 0x24)
/** RTCADC_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
* Clock divider.
*/
#define RTCADC_SAR2_CLK_DIV 0x000000FFU
#define RTCADC_SAR2_CLK_DIV_M (RTCADC_SAR2_CLK_DIV_V << RTCADC_SAR2_CLK_DIV_S)
#define RTCADC_SAR2_CLK_DIV_V 0x000000FFU
#define RTCADC_SAR2_CLK_DIV_S 0
/** RTCADC_SAR2_WAIT_ARB_CYCLE : R/W; bitpos: [17:16]; default: 1;
* Wait arbit stable after sar_done.
*/
#define RTCADC_SAR2_WAIT_ARB_CYCLE 0x00000003U
#define RTCADC_SAR2_WAIT_ARB_CYCLE_M (RTCADC_SAR2_WAIT_ARB_CYCLE_V << RTCADC_SAR2_WAIT_ARB_CYCLE_S)
#define RTCADC_SAR2_WAIT_ARB_CYCLE_V 0x00000003U
#define RTCADC_SAR2_WAIT_ARB_CYCLE_S 16
/** RTCADC_SAR2_EN_PAD_FORCE_ENABLE : R/W; bitpos: [28:27]; default: 0;
* Force enable adc en_pad to analog circuit 2'b11: force enable .
*/
#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE 0x00000003U
#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_M (RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S)
#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V 0x00000003U
#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S 27
/** RTCADC_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0;
* Invert SAR ADC2 data.
*/
#define RTCADC_SAR2_DATA_INV (BIT(29))
#define RTCADC_SAR2_DATA_INV_M (RTCADC_SAR2_DATA_INV_V << RTCADC_SAR2_DATA_INV_S)
#define RTCADC_SAR2_DATA_INV_V 0x00000001U
#define RTCADC_SAR2_DATA_INV_S 29
/** RTCADC_SAR2_INT_EN : R/W; bitpos: [30]; default: 1;
* Enable saradc2 to send out interrupt.
*/
#define RTCADC_SAR2_INT_EN (BIT(30))
#define RTCADC_SAR2_INT_EN_M (RTCADC_SAR2_INT_EN_V << RTCADC_SAR2_INT_EN_S)
#define RTCADC_SAR2_INT_EN_V 0x00000001U
#define RTCADC_SAR2_INT_EN_S 30
/** RTCADC_MEAS2_CTRL1_REG register
* ADC2 configuration registers.
*/
#define RTCADC_MEAS2_CTRL1_REG (DR_REG_RTCADC_BASE + 0x2c)
/** RTCADC_SAR2_CNTL_STATE : RO; bitpos: [2:0]; default: 0;
* saradc2_cntl_fsm.
*/
#define RTCADC_SAR2_CNTL_STATE 0x00000007U
#define RTCADC_SAR2_CNTL_STATE_M (RTCADC_SAR2_CNTL_STATE_V << RTCADC_SAR2_CNTL_STATE_S)
#define RTCADC_SAR2_CNTL_STATE_V 0x00000007U
#define RTCADC_SAR2_CNTL_STATE_S 0
/** RTCADC_SAR2_PWDET_CAL_EN : R/W; bitpos: [3]; default: 0;
* RTC control pwdet enable.
*/
#define RTCADC_SAR2_PWDET_CAL_EN (BIT(3))
#define RTCADC_SAR2_PWDET_CAL_EN_M (RTCADC_SAR2_PWDET_CAL_EN_V << RTCADC_SAR2_PWDET_CAL_EN_S)
#define RTCADC_SAR2_PWDET_CAL_EN_V 0x00000001U
#define RTCADC_SAR2_PWDET_CAL_EN_S 3
/** RTCADC_SAR2_PKDET_CAL_EN : R/W; bitpos: [4]; default: 0;
* RTC control pkdet enable.
*/
#define RTCADC_SAR2_PKDET_CAL_EN (BIT(4))
#define RTCADC_SAR2_PKDET_CAL_EN_M (RTCADC_SAR2_PKDET_CAL_EN_V << RTCADC_SAR2_PKDET_CAL_EN_S)
#define RTCADC_SAR2_PKDET_CAL_EN_V 0x00000001U
#define RTCADC_SAR2_PKDET_CAL_EN_S 4
/** RTCADC_SAR2_EN_TEST : R/W; bitpos: [5]; default: 0;
* SAR2_EN_TEST.
*/
#define RTCADC_SAR2_EN_TEST (BIT(5))
#define RTCADC_SAR2_EN_TEST_M (RTCADC_SAR2_EN_TEST_V << RTCADC_SAR2_EN_TEST_S)
#define RTCADC_SAR2_EN_TEST_V 0x00000001U
#define RTCADC_SAR2_EN_TEST_S 5
/** RTCADC_MEAS2_CTRL2_REG register
* ADC2 configuration registers.
*/
#define RTCADC_MEAS2_CTRL2_REG (DR_REG_RTCADC_BASE + 0x30)
/** RTCADC_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0;
* SAR ADC2 data.
*/
#define RTCADC_MEAS2_DATA_SAR 0x0000FFFFU
#define RTCADC_MEAS2_DATA_SAR_M (RTCADC_MEAS2_DATA_SAR_V << RTCADC_MEAS2_DATA_SAR_S)
#define RTCADC_MEAS2_DATA_SAR_V 0x0000FFFFU
#define RTCADC_MEAS2_DATA_SAR_S 0
/** RTCADC_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0;
* SAR ADC2 conversion done indication.
*/
#define RTCADC_MEAS2_DONE_SAR (BIT(16))
#define RTCADC_MEAS2_DONE_SAR_M (RTCADC_MEAS2_DONE_SAR_V << RTCADC_MEAS2_DONE_SAR_S)
#define RTCADC_MEAS2_DONE_SAR_V 0x00000001U
#define RTCADC_MEAS2_DONE_SAR_S 16
/** RTCADC_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0;
* SAR ADC2 controller (in RTC) starts conversion.
*/
#define RTCADC_MEAS2_START_SAR (BIT(17))
#define RTCADC_MEAS2_START_SAR_M (RTCADC_MEAS2_START_SAR_V << RTCADC_MEAS2_START_SAR_S)
#define RTCADC_MEAS2_START_SAR_V 0x00000001U
#define RTCADC_MEAS2_START_SAR_S 17
/** RTCADC_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0;
* 1: SAR ADC2 controller (in RTC) is started by SW.
*/
#define RTCADC_MEAS2_START_FORCE (BIT(18))
#define RTCADC_MEAS2_START_FORCE_M (RTCADC_MEAS2_START_FORCE_V << RTCADC_MEAS2_START_FORCE_S)
#define RTCADC_MEAS2_START_FORCE_V 0x00000001U
#define RTCADC_MEAS2_START_FORCE_S 18
/** RTCADC_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0;
* SAR ADC2 pad enable bitmap.
*/
#define RTCADC_SAR2_EN_PAD 0x00000FFFU
#define RTCADC_SAR2_EN_PAD_M (RTCADC_SAR2_EN_PAD_V << RTCADC_SAR2_EN_PAD_S)
#define RTCADC_SAR2_EN_PAD_V 0x00000FFFU
#define RTCADC_SAR2_EN_PAD_S 19
/** RTCADC_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
* 1: SAR ADC2 pad enable bitmap is controlled by SW.
*/
#define RTCADC_SAR2_EN_PAD_FORCE (BIT(31))
#define RTCADC_SAR2_EN_PAD_FORCE_M (RTCADC_SAR2_EN_PAD_FORCE_V << RTCADC_SAR2_EN_PAD_FORCE_S)
#define RTCADC_SAR2_EN_PAD_FORCE_V 0x00000001U
#define RTCADC_SAR2_EN_PAD_FORCE_S 31
/** RTCADC_MEAS2_MUX_REG register
* SAR ADC2 MUX register.
*/
#define RTCADC_MEAS2_MUX_REG (DR_REG_RTCADC_BASE + 0x34)
/** RTCADC_SAR2_PWDET_CCT : R/W; bitpos: [30:28]; default: 0;
* SAR2_PWDET_CCT.
*/
#define RTCADC_SAR2_PWDET_CCT 0x00000007U
#define RTCADC_SAR2_PWDET_CCT_M (RTCADC_SAR2_PWDET_CCT_V << RTCADC_SAR2_PWDET_CCT_S)
#define RTCADC_SAR2_PWDET_CCT_V 0x00000007U
#define RTCADC_SAR2_PWDET_CCT_S 28
/** RTCADC_SAR2_RTC_FORCE : R/W; bitpos: [31]; default: 0;
* In sleep, force to use rtc to control ADC.
*/
#define RTCADC_SAR2_RTC_FORCE (BIT(31))
#define RTCADC_SAR2_RTC_FORCE_M (RTCADC_SAR2_RTC_FORCE_V << RTCADC_SAR2_RTC_FORCE_S)
#define RTCADC_SAR2_RTC_FORCE_V 0x00000001U
#define RTCADC_SAR2_RTC_FORCE_S 31
/** RTCADC_ATTEN2_REG register
* ADC1 attenuation registers.
*/
#define RTCADC_ATTEN2_REG (DR_REG_RTCADC_BASE + 0x38)
/** RTCADC_SAR2_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
* 2-bit attenuation for each pad.
*/
#define RTCADC_SAR2_ATTEN 0xFFFFFFFFU
#define RTCADC_SAR2_ATTEN_M (RTCADC_SAR2_ATTEN_V << RTCADC_SAR2_ATTEN_S)
#define RTCADC_SAR2_ATTEN_V 0xFFFFFFFFU
#define RTCADC_SAR2_ATTEN_S 0
/** RTCADC_FORCE_WPD_SAR_REG register
* In sleep, force to use rtc to control ADC
*/
#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_RTCADC_BASE + 0x3c)
/** RTCADC_FORCE_XPD_SAR1 : R/W; bitpos: [1:0]; default: 0;
* 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
* control.
*/
#define RTCADC_FORCE_XPD_SAR1 0x00000003U
#define RTCADC_FORCE_XPD_SAR1_M (RTCADC_FORCE_XPD_SAR1_V << RTCADC_FORCE_XPD_SAR1_S)
#define RTCADC_FORCE_XPD_SAR1_V 0x00000003U
#define RTCADC_FORCE_XPD_SAR1_S 0
/** RTCADC_FORCE_XPD_SAR2 : R/W; bitpos: [3:2]; default: 0;
* 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
* control.
*/
#define RTCADC_FORCE_XPD_SAR2 0x00000003U
#define RTCADC_FORCE_XPD_SAR2_M (RTCADC_FORCE_XPD_SAR2_V << RTCADC_FORCE_XPD_SAR2_S)
#define RTCADC_FORCE_XPD_SAR2_V 0x00000003U
#define RTCADC_FORCE_XPD_SAR2_S 2
/** RTCADC_COCPU_INT_RAW_REG register
* Interrupt raw registers.
*/
#define RTCADC_COCPU_INT_RAW_REG (DR_REG_RTCADC_BASE + 0x48)
/** RTCADC_COCPU_SARADC1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int raw.
*/
#define RTCADC_COCPU_SARADC1_INT_RAW (BIT(0))
#define RTCADC_COCPU_SARADC1_INT_RAW_M (RTCADC_COCPU_SARADC1_INT_RAW_V << RTCADC_COCPU_SARADC1_INT_RAW_S)
#define RTCADC_COCPU_SARADC1_INT_RAW_V 0x00000001U
#define RTCADC_COCPU_SARADC1_INT_RAW_S 0
/** RTCADC_COCPU_SARADC2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int raw.
*/
#define RTCADC_COCPU_SARADC2_INT_RAW (BIT(1))
#define RTCADC_COCPU_SARADC2_INT_RAW_M (RTCADC_COCPU_SARADC2_INT_RAW_V << RTCADC_COCPU_SARADC2_INT_RAW_S)
#define RTCADC_COCPU_SARADC2_INT_RAW_V 0x00000001U
#define RTCADC_COCPU_SARADC2_INT_RAW_S 1
/** RTCADC_COCPU_SARADC1_ERROR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int raw.
*/
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW (BIT(2))
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_M (RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S)
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V 0x00000001U
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S 2
/** RTCADC_COCPU_SARADC2_ERROR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int raw.
*/
#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW (BIT(3))
#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_M (RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S)
#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V 0x00000001U
#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S 3
/** RTCADC_COCPU_SARADC1_WAKE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int raw.
*/
#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW (BIT(4))
#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_M (RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S)
#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V 0x00000001U
#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S 4
/** RTCADC_COCPU_SARADC2_WAKE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int raw.
*/
#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW (BIT(5))
#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_M (RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S)
#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V 0x00000001U
#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S 5
/** RTCADC_INT_ENA_REG register
* Interrupt enable registers.
*/
#define RTCADC_INT_ENA_REG (DR_REG_RTCADC_BASE + 0x4c)
/** RTCADC_COCPU_SARADC1_INT_ENA : R/WTC; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int enable.
*/
#define RTCADC_COCPU_SARADC1_INT_ENA (BIT(0))
#define RTCADC_COCPU_SARADC1_INT_ENA_M (RTCADC_COCPU_SARADC1_INT_ENA_V << RTCADC_COCPU_SARADC1_INT_ENA_S)
#define RTCADC_COCPU_SARADC1_INT_ENA_V 0x00000001U
#define RTCADC_COCPU_SARADC1_INT_ENA_S 0
/** RTCADC_COCPU_SARADC2_INT_ENA : R/WTC; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int enable.
*/
#define RTCADC_COCPU_SARADC2_INT_ENA (BIT(1))
#define RTCADC_COCPU_SARADC2_INT_ENA_M (RTCADC_COCPU_SARADC2_INT_ENA_V << RTCADC_COCPU_SARADC2_INT_ENA_S)
#define RTCADC_COCPU_SARADC2_INT_ENA_V 0x00000001U
#define RTCADC_COCPU_SARADC2_INT_ENA_S 1
/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA : R/WTC; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int enable.
*/
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA (BIT(2))
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S)
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V 0x00000001U
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S 2
/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA : R/WTC; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int enable.
*/
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA (BIT(3))
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S)
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V 0x00000001U
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S 3
/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA : R/WTC; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int enable.
*/
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA (BIT(4))
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_M (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S)
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V 0x00000001U
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S 4
/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA : R/WTC; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int enable.
*/
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA (BIT(5))
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_M (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S)
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V 0x00000001U
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S 5
/** RTCADC_INT_ST_REG register
* Interrupt status registers.
*/
#define RTCADC_INT_ST_REG (DR_REG_RTCADC_BASE + 0x50)
/** RTCADC_COCPU_SARADC1_INT_ST : RO; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int status.
*/
#define RTCADC_COCPU_SARADC1_INT_ST (BIT(0))
#define RTCADC_COCPU_SARADC1_INT_ST_M (RTCADC_COCPU_SARADC1_INT_ST_V << RTCADC_COCPU_SARADC1_INT_ST_S)
#define RTCADC_COCPU_SARADC1_INT_ST_V 0x00000001U
#define RTCADC_COCPU_SARADC1_INT_ST_S 0
/** RTCADC_COCPU_SARADC2_INT_ST : RO; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int status.
*/
#define RTCADC_COCPU_SARADC2_INT_ST (BIT(1))
#define RTCADC_COCPU_SARADC2_INT_ST_M (RTCADC_COCPU_SARADC2_INT_ST_V << RTCADC_COCPU_SARADC2_INT_ST_S)
#define RTCADC_COCPU_SARADC2_INT_ST_V 0x00000001U
#define RTCADC_COCPU_SARADC2_INT_ST_S 1
/** RTCADC_COCPU_SARADC1_ERROR_INT_ST : RO; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int status.
*/
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST (BIT(2))
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_M (RTCADC_COCPU_SARADC1_ERROR_INT_ST_V << RTCADC_COCPU_SARADC1_ERROR_INT_ST_S)
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_V 0x00000001U
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_S 2
/** RTCADC_COCPU_SARADC2_ERROR_INT_ST : RO; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int status.
*/
#define RTCADC_COCPU_SARADC2_ERROR_INT_ST (BIT(3))
#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_M (RTCADC_COCPU_SARADC2_ERROR_INT_ST_V << RTCADC_COCPU_SARADC2_ERROR_INT_ST_S)
#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_V 0x00000001U
#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_S 3
/** RTCADC_COCPU_SARADC1_WAKE_INT_ST : RO; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int status.
*/
#define RTCADC_COCPU_SARADC1_WAKE_INT_ST (BIT(4))
#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_M (RTCADC_COCPU_SARADC1_WAKE_INT_ST_V << RTCADC_COCPU_SARADC1_WAKE_INT_ST_S)
#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_V 0x00000001U
#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_S 4
/** RTCADC_COCPU_SARADC2_WAKE_INT_ST : RO; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int status.
*/
#define RTCADC_COCPU_SARADC2_WAKE_INT_ST (BIT(5))
#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_M (RTCADC_COCPU_SARADC2_WAKE_INT_ST_V << RTCADC_COCPU_SARADC2_WAKE_INT_ST_S)
#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_V 0x00000001U
#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_S 5
/** RTCADC_INT_CLR_REG register
* Interrupt clear registers.
*/
#define RTCADC_INT_CLR_REG (DR_REG_RTCADC_BASE + 0x54)
/** RTCADC_COCPU_SARADC1_INT_CLR : WT; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int clear.
*/
#define RTCADC_COCPU_SARADC1_INT_CLR (BIT(0))
#define RTCADC_COCPU_SARADC1_INT_CLR_M (RTCADC_COCPU_SARADC1_INT_CLR_V << RTCADC_COCPU_SARADC1_INT_CLR_S)
#define RTCADC_COCPU_SARADC1_INT_CLR_V 0x00000001U
#define RTCADC_COCPU_SARADC1_INT_CLR_S 0
/** RTCADC_COCPU_SARADC2_INT_CLR : WT; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int clear.
*/
#define RTCADC_COCPU_SARADC2_INT_CLR (BIT(1))
#define RTCADC_COCPU_SARADC2_INT_CLR_M (RTCADC_COCPU_SARADC2_INT_CLR_V << RTCADC_COCPU_SARADC2_INT_CLR_S)
#define RTCADC_COCPU_SARADC2_INT_CLR_V 0x00000001U
#define RTCADC_COCPU_SARADC2_INT_CLR_S 1
/** RTCADC_COCPU_SARADC1_ERROR_INT_CLR : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int clear.
*/
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR (BIT(2))
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_M (RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S)
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V 0x00000001U
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S 2
/** RTCADC_COCPU_SARADC2_ERROR_INT_CLR : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int clear.
*/
#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR (BIT(3))
#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_M (RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S)
#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V 0x00000001U
#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S 3
/** RTCADC_COCPU_SARADC1_WAKE_INT_CLR : WT; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int clear.
*/
#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR (BIT(4))
#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_M (RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S)
#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V 0x00000001U
#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S 4
/** RTCADC_COCPU_SARADC2_WAKE_INT_CLR : WT; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int clear.
*/
#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR (BIT(5))
#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_M (RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S)
#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V 0x00000001U
#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S 5
/** RTCADC_INT_ENA_W1TS_REG register
* Interrupt enable assert registers.
*/
#define RTCADC_INT_ENA_W1TS_REG (DR_REG_RTCADC_BASE + 0x58)
/** RTCADC_COCPU_SARADC1_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
* ADC1 Conversion is done, write 1 to assert int enable.
*/
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS (BIT(0))
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S)
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V 0x00000001U
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S 0
/** RTCADC_COCPU_SARADC2_INT_ENA_W1TS : WT; bitpos: [1]; default: 0;
* ADC2 Conversion is done, write 1 to assert int enable.
*/
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS (BIT(1))
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S)
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V 0x00000001U
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S 1
/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, write 1 to assert int enable.
*/
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS (BIT(2))
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S)
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V 0x00000001U
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S 2
/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, write 1 to assert int enable.
*/
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS (BIT(3))
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S)
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V 0x00000001U
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S 3
/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS : WT; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, write 1 to assert int enable.
*/
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS (BIT(4))
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S)
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V 0x00000001U
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S 4
/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS : WT; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, write 1 to assert int enable.
*/
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS (BIT(5))
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S)
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V 0x00000001U
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S 5
/** RTCADC_INT_ENA_W1TC_REG register
* Interrupt enable deassert registers.
*/
#define RTCADC_INT_ENA_W1TC_REG (DR_REG_RTCADC_BASE + 0x5c)
/** RTCADC_COCPU_SARADC1_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
* ADC1 Conversion is done, write 1 to deassert int enable.
*/
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC (BIT(0))
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S)
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V 0x00000001U
#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S 0
/** RTCADC_COCPU_SARADC2_INT_ENA_W1TC : WT; bitpos: [1]; default: 0;
* ADC2 Conversion is done, write 1 to deassert int enable.
*/
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC (BIT(1))
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S)
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V 0x00000001U
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S 1
/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, write 1 to deassert int enable.
*/
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC (BIT(2))
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S)
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V 0x00000001U
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S 2
/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, write 1 to deassert int enable.
*/
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC (BIT(3))
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S)
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V 0x00000001U
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S 3
/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC : WT; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, write 1 to deassert int enable.
*/
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC (BIT(4))
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S)
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V 0x00000001U
#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S 4
/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC : WT; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, write 1 to deassert int enable.
*/
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC (BIT(5))
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S)
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V 0x00000001U
#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S 5
/** RTCADC_WAKEUP1_REG register
* ADC1 wakeup configuration registers.
*/
#define RTCADC_WAKEUP1_REG (DR_REG_RTCADC_BASE + 0x60)
/** RTCADC_SAR1_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
* Lower threshold.
*/
#define RTCADC_SAR1_WAKEUP_TH_LOW 0x00000FFFU
#define RTCADC_SAR1_WAKEUP_TH_LOW_M (RTCADC_SAR1_WAKEUP_TH_LOW_V << RTCADC_SAR1_WAKEUP_TH_LOW_S)
#define RTCADC_SAR1_WAKEUP_TH_LOW_V 0x00000FFFU
#define RTCADC_SAR1_WAKEUP_TH_LOW_S 0
/** RTCADC_SAR1_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
* Upper threshold.
*/
#define RTCADC_SAR1_WAKEUP_TH_HIGH 0x00000FFFU
#define RTCADC_SAR1_WAKEUP_TH_HIGH_M (RTCADC_SAR1_WAKEUP_TH_HIGH_V << RTCADC_SAR1_WAKEUP_TH_HIGH_S)
#define RTCADC_SAR1_WAKEUP_TH_HIGH_V 0x00000FFFU
#define RTCADC_SAR1_WAKEUP_TH_HIGH_S 14
/** RTCADC_SAR1_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
* Indicates that this wakeup event arose from exceeding upper threshold.
*/
#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH (BIT(29))
#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_M (RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S)
#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S 29
/** RTCADC_SAR1_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
* Wakeup function enable.
*/
#define RTCADC_SAR1_WAKEUP_EN (BIT(30))
#define RTCADC_SAR1_WAKEUP_EN_M (RTCADC_SAR1_WAKEUP_EN_V << RTCADC_SAR1_WAKEUP_EN_S)
#define RTCADC_SAR1_WAKEUP_EN_V 0x00000001U
#define RTCADC_SAR1_WAKEUP_EN_S 30
/** RTCADC_SAR1_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
* 0:absolute value comparison mode. 1: relative value comparison mode.
*/
#define RTCADC_SAR1_WAKEUP_MODE (BIT(31))
#define RTCADC_SAR1_WAKEUP_MODE_M (RTCADC_SAR1_WAKEUP_MODE_V << RTCADC_SAR1_WAKEUP_MODE_S)
#define RTCADC_SAR1_WAKEUP_MODE_V 0x00000001U
#define RTCADC_SAR1_WAKEUP_MODE_S 31
/** RTCADC_WAKEUP2_REG register
* ADC2 wakeup configuration registers.
*/
#define RTCADC_WAKEUP2_REG (DR_REG_RTCADC_BASE + 0x64)
/** RTCADC_SAR2_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
* Lower threshold.
*/
#define RTCADC_SAR2_WAKEUP_TH_LOW 0x00000FFFU
#define RTCADC_SAR2_WAKEUP_TH_LOW_M (RTCADC_SAR2_WAKEUP_TH_LOW_V << RTCADC_SAR2_WAKEUP_TH_LOW_S)
#define RTCADC_SAR2_WAKEUP_TH_LOW_V 0x00000FFFU
#define RTCADC_SAR2_WAKEUP_TH_LOW_S 0
/** RTCADC_SAR2_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
* Upper threshold.
*/
#define RTCADC_SAR2_WAKEUP_TH_HIGH 0x00000FFFU
#define RTCADC_SAR2_WAKEUP_TH_HIGH_M (RTCADC_SAR2_WAKEUP_TH_HIGH_V << RTCADC_SAR2_WAKEUP_TH_HIGH_S)
#define RTCADC_SAR2_WAKEUP_TH_HIGH_V 0x00000FFFU
#define RTCADC_SAR2_WAKEUP_TH_HIGH_S 14
/** RTCADC_SAR2_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
* Indicates that this wakeup event arose from exceeding upper threshold.
*/
#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH (BIT(29))
#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_M (RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S)
#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S 29
/** RTCADC_SAR2_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
* Wakeup function enable.
*/
#define RTCADC_SAR2_WAKEUP_EN (BIT(30))
#define RTCADC_SAR2_WAKEUP_EN_M (RTCADC_SAR2_WAKEUP_EN_V << RTCADC_SAR2_WAKEUP_EN_S)
#define RTCADC_SAR2_WAKEUP_EN_V 0x00000001U
#define RTCADC_SAR2_WAKEUP_EN_S 30
/** RTCADC_SAR2_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
* 0:absolute value comparison mode. 1: relative value comparison mode.
*/
#define RTCADC_SAR2_WAKEUP_MODE (BIT(31))
#define RTCADC_SAR2_WAKEUP_MODE_M (RTCADC_SAR2_WAKEUP_MODE_V << RTCADC_SAR2_WAKEUP_MODE_S)
#define RTCADC_SAR2_WAKEUP_MODE_V 0x00000001U
#define RTCADC_SAR2_WAKEUP_MODE_S 31
/** RTCADC_WAKEUP_SEL_REG register
* Wakeup source select register.
*/
#define RTCADC_WAKEUP_SEL_REG (DR_REG_RTCADC_BASE + 0x68)
/** RTCADC_SAR_WAKEUP_SEL : R/W; bitpos: [0]; default: 0;
* 0: ADC1. 1: ADC2.
*/
#define RTCADC_SAR_WAKEUP_SEL (BIT(0))
#define RTCADC_SAR_WAKEUP_SEL_M (RTCADC_SAR_WAKEUP_SEL_V << RTCADC_SAR_WAKEUP_SEL_S)
#define RTCADC_SAR_WAKEUP_SEL_V 0x00000001U
#define RTCADC_SAR_WAKEUP_SEL_S 0
/** RTCADC_SAR1_HW_WAKEUP_REG register
* Hardware automatic sampling registers for wakeup function.
*/
#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x6c)
/** RTCADC_ADC1_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
* Enable hardware automatic sampling.
*/
#define RTCADC_ADC1_HW_READ_EN_I (BIT(0))
#define RTCADC_ADC1_HW_READ_EN_I_M (RTCADC_ADC1_HW_READ_EN_I_V << RTCADC_ADC1_HW_READ_EN_I_S)
#define RTCADC_ADC1_HW_READ_EN_I_V 0x00000001U
#define RTCADC_ADC1_HW_READ_EN_I_S 0
/** RTCADC_ADC1_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
* Hardware automatic sampling rate.
*/
#define RTCADC_ADC1_HW_READ_RATE_I 0x0000FFFFU
#define RTCADC_ADC1_HW_READ_RATE_I_M (RTCADC_ADC1_HW_READ_RATE_I_V << RTCADC_ADC1_HW_READ_RATE_I_S)
#define RTCADC_ADC1_HW_READ_RATE_I_V 0x0000FFFFU
#define RTCADC_ADC1_HW_READ_RATE_I_S 1
/** RTCADC_SAR2_HW_WAKEUP_REG register
* Hardware automatic sampling registers for wakeup function.
*/
#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x70)
/** RTCADC_ADC2_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
* Enable hardware automatic sampling.
*/
#define RTCADC_ADC2_HW_READ_EN_I (BIT(0))
#define RTCADC_ADC2_HW_READ_EN_I_M (RTCADC_ADC2_HW_READ_EN_I_V << RTCADC_ADC2_HW_READ_EN_I_S)
#define RTCADC_ADC2_HW_READ_EN_I_V 0x00000001U
#define RTCADC_ADC2_HW_READ_EN_I_S 0
/** RTCADC_ADC2_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
* Hardware automatic sampling rate.
*/
#define RTCADC_ADC2_HW_READ_RATE_I 0x0000FFFFU
#define RTCADC_ADC2_HW_READ_RATE_I_M (RTCADC_ADC2_HW_READ_RATE_I_V << RTCADC_ADC2_HW_READ_RATE_I_S)
#define RTCADC_ADC2_HW_READ_RATE_I_V 0x0000FFFFU
#define RTCADC_ADC2_HW_READ_RATE_I_S 1
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/rtcadc_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ADC1 control registers. */
/** Type of reader1_ctrl register
* Control the read operation of ADC1.
*/
typedef union {
struct {
/** sar1_clk_div : R/W; bitpos: [7:0]; default: 2;
* Clock divider.
*/
uint32_t sar1_clk_div:8;
uint32_t reserved_8:20;
/** sar1_data_inv : R/W; bitpos: [28]; default: 0;
* Invert SAR ADC1 data.
*/
uint32_t sar1_data_inv:1;
/** sar1_int_en : R/W; bitpos: [29]; default: 1;
* Enable saradc1 to send out interrupt.
*/
uint32_t sar1_int_en:1;
/** sar1_en_pad_force_enable : R/W; bitpos: [31:30]; default: 0;
* Force enable adc en_pad to analog circuit 2'b11: force enable .
*/
uint32_t sar1_en_pad_force_enable:2;
};
uint32_t val;
} rtcadc_reader1_ctrl_reg_t;
/** Type of meas1_ctrl2 register
* ADC1 configuration registers.
*/
typedef union {
struct {
/** meas1_data_sar : RO; bitpos: [15:0]; default: 0;
* SAR ADC1 data.
*/
uint32_t meas1_data_sar:16;
/** meas1_done_sar : RO; bitpos: [16]; default: 0;
* SAR ADC1 conversion done indication.
*/
uint32_t meas1_done_sar:1;
/** meas1_start_sar : R/W; bitpos: [17]; default: 0;
* SAR ADC1 controller (in RTC) starts conversion.
*/
uint32_t meas1_start_sar:1;
/** meas1_start_force : R/W; bitpos: [18]; default: 0;
* 1: SAR ADC1 controller (in RTC) is started by SW.
*/
uint32_t meas1_start_force:1;
/** sar1_en_pad : R/W; bitpos: [30:19]; default: 0;
* SAR ADC1 pad enable bitmap.
*/
uint32_t sar1_en_pad:12;
/** sar1_en_pad_force : R/W; bitpos: [31]; default: 0;
* 1: SAR ADC1 pad enable bitmap is controlled by SW.
*/
uint32_t sar1_en_pad_force:1;
};
uint32_t val;
} rtcadc_meas1_ctrl2_reg_t;
/** Type of meas1_mux register
* SAR ADC1 MUX register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** sar1_dig_force : R/W; bitpos: [31]; default: 0;
* 1: SAR ADC1 controlled by DIG ADC1 CTRL.
*/
uint32_t sar1_dig_force:1;
};
uint32_t val;
} rtcadc_meas1_mux_reg_t;
/** Type of atten1 register
* ADC1 attenuation registers.
*/
typedef union {
struct {
/** sar1_atten : R/W; bitpos: [31:0]; default: 4294967295;
* 2-bit attenuation for each pad.
*/
uint32_t sar1_atten:32;
};
uint32_t val;
} rtcadc_atten1_reg_t;
/** Group: ADC2 control registers. */
/** Type of reader2_ctrl register
* Control the read operation of ADC2.
*/
typedef union {
struct {
/** sar2_clk_div : R/W; bitpos: [7:0]; default: 2;
* Clock divider.
*/
uint32_t sar2_clk_div:8;
uint32_t reserved_8:8;
/** sar2_wait_arb_cycle : R/W; bitpos: [17:16]; default: 1;
* Wait arbit stable after sar_done.
*/
uint32_t sar2_wait_arb_cycle:2;
uint32_t reserved_18:9;
/** sar2_en_pad_force_enable : R/W; bitpos: [28:27]; default: 0;
* Force enable adc en_pad to analog circuit 2'b11: force enable .
*/
uint32_t sar2_en_pad_force_enable:2;
/** sar2_data_inv : R/W; bitpos: [29]; default: 0;
* Invert SAR ADC2 data.
*/
uint32_t sar2_data_inv:1;
/** sar2_int_en : R/W; bitpos: [30]; default: 1;
* Enable saradc2 to send out interrupt.
*/
uint32_t sar2_int_en:1;
uint32_t reserved_31:1;
};
uint32_t val;
} rtcadc_reader2_ctrl_reg_t;
/** Type of meas2_ctrl1 register
* ADC2 configuration registers.
*/
typedef union {
struct {
/** sar2_cntl_state : RO; bitpos: [2:0]; default: 0;
* saradc2_cntl_fsm.
*/
uint32_t sar2_cntl_state:3;
/** sar2_pwdet_cal_en : R/W; bitpos: [3]; default: 0;
* RTC control pwdet enable.
*/
uint32_t sar2_pwdet_cal_en:1;
/** sar2_pkdet_cal_en : R/W; bitpos: [4]; default: 0;
* RTC control pkdet enable.
*/
uint32_t sar2_pkdet_cal_en:1;
/** sar2_en_test : R/W; bitpos: [5]; default: 0;
* SAR2_EN_TEST.
*/
uint32_t sar2_en_test:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_meas2_ctrl1_reg_t;
/** Type of meas2_ctrl2 register
* ADC2 configuration registers.
*/
typedef union {
struct {
/** meas2_data_sar : RO; bitpos: [15:0]; default: 0;
* SAR ADC2 data.
*/
uint32_t meas2_data_sar:16;
/** meas2_done_sar : RO; bitpos: [16]; default: 0;
* SAR ADC2 conversion done indication.
*/
uint32_t meas2_done_sar:1;
/** meas2_start_sar : R/W; bitpos: [17]; default: 0;
* SAR ADC2 controller (in RTC) starts conversion.
*/
uint32_t meas2_start_sar:1;
/** meas2_start_force : R/W; bitpos: [18]; default: 0;
* 1: SAR ADC2 controller (in RTC) is started by SW.
*/
uint32_t meas2_start_force:1;
/** sar2_en_pad : R/W; bitpos: [30:19]; default: 0;
* SAR ADC2 pad enable bitmap.
*/
uint32_t sar2_en_pad:12;
/** sar2_en_pad_force : R/W; bitpos: [31]; default: 0;
* 1: SAR ADC2 pad enable bitmap is controlled by SW.
*/
uint32_t sar2_en_pad_force:1;
};
uint32_t val;
} rtcadc_meas2_ctrl2_reg_t;
/** Type of meas2_mux register
* SAR ADC2 MUX register.
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** sar2_pwdet_cct : R/W; bitpos: [30:28]; default: 0;
* SAR2_PWDET_CCT.
*/
uint32_t sar2_pwdet_cct:3;
/** sar2_rtc_force : R/W; bitpos: [31]; default: 0;
* In sleep, force to use rtc to control ADC.
*/
uint32_t sar2_rtc_force:1;
};
uint32_t val;
} rtcadc_meas2_mux_reg_t;
/** Type of atten2 register
* ADC1 attenuation registers.
*/
typedef union {
struct {
/** sar2_atten : R/W; bitpos: [31:0]; default: 4294967295;
* 2-bit attenuation for each pad.
*/
uint32_t sar2_atten:32;
};
uint32_t val;
} rtcadc_atten2_reg_t;
/** Group: ADC XPD control. */
/** Type of force_wpd_sar register
* In sleep, force to use rtc to control ADC
*/
typedef union {
struct {
/** force_xpd_sar1 : R/W; bitpos: [1:0]; default: 0;
* 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
* control.
*/
uint32_t force_xpd_sar1:2;
/** force_xpd_sar2 : R/W; bitpos: [3:2]; default: 0;
* 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
* control.
*/
uint32_t force_xpd_sar2:2;
uint32_t reserved_4:28;
};
uint32_t val;
} rtcadc_force_wpd_sar_reg_t;
/** Group: RTCADC interrupt registers. */
/** Type of cocpu_int_raw register
* Interrupt raw registers.
*/
typedef union {
struct {
/** cocpu_saradc1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int raw.
*/
uint32_t cocpu_saradc1_int_raw:1;
/** cocpu_saradc2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int raw.
*/
uint32_t cocpu_saradc2_int_raw:1;
/** cocpu_saradc1_error_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int raw.
*/
uint32_t cocpu_saradc1_error_int_raw:1;
/** cocpu_saradc2_error_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int raw.
*/
uint32_t cocpu_saradc2_error_int_raw:1;
/** cocpu_saradc1_wake_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int raw.
*/
uint32_t cocpu_saradc1_wake_int_raw:1;
/** cocpu_saradc2_wake_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int raw.
*/
uint32_t cocpu_saradc2_wake_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_cocpu_int_raw_reg_t;
/** Type of int_ena register
* Interrupt enable registers.
*/
typedef union {
struct {
/** cocpu_saradc1_int_ena : R/WTC; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int enable.
*/
uint32_t cocpu_saradc1_int_ena:1;
/** cocpu_saradc2_int_ena : R/WTC; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int enable.
*/
uint32_t cocpu_saradc2_int_ena:1;
/** cocpu_saradc1_error_int_ena : R/WTC; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int enable.
*/
uint32_t cocpu_saradc1_error_int_ena:1;
/** cocpu_saradc2_error_int_ena : R/WTC; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int enable.
*/
uint32_t cocpu_saradc2_error_int_ena:1;
/** cocpu_saradc1_wake_int_ena : R/WTC; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int enable.
*/
uint32_t cocpu_saradc1_wake_int_ena:1;
/** cocpu_saradc2_wake_int_ena : R/WTC; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int enable.
*/
uint32_t cocpu_saradc2_wake_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_int_ena_reg_t;
/** Type of int_st register
* Interrupt status registers.
*/
typedef union {
struct {
/** cocpu_saradc1_int_st : RO; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int status.
*/
uint32_t cocpu_saradc1_int_st:1;
/** cocpu_saradc2_int_st : RO; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int status.
*/
uint32_t cocpu_saradc2_int_st:1;
/** cocpu_saradc1_error_int_st : RO; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int status.
*/
uint32_t cocpu_saradc1_error_int_st:1;
/** cocpu_saradc2_error_int_st : RO; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int status.
*/
uint32_t cocpu_saradc2_error_int_st:1;
/** cocpu_saradc1_wake_int_st : RO; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int status.
*/
uint32_t cocpu_saradc1_wake_int_st:1;
/** cocpu_saradc2_wake_int_st : RO; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int status.
*/
uint32_t cocpu_saradc2_wake_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_int_st_reg_t;
/** Type of int_clr register
* Interrupt clear registers.
*/
typedef union {
struct {
/** cocpu_saradc1_int_clr : WT; bitpos: [0]; default: 0;
* ADC1 Conversion is done, int clear.
*/
uint32_t cocpu_saradc1_int_clr:1;
/** cocpu_saradc2_int_clr : WT; bitpos: [1]; default: 0;
* ADC2 Conversion is done, int clear.
*/
uint32_t cocpu_saradc2_int_clr:1;
/** cocpu_saradc1_error_int_clr : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int clear.
*/
uint32_t cocpu_saradc1_error_int_clr:1;
/** cocpu_saradc2_error_int_clr : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int clear.
*/
uint32_t cocpu_saradc2_error_int_clr:1;
/** cocpu_saradc1_wake_int_clr : WT; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, int clear.
*/
uint32_t cocpu_saradc1_wake_int_clr:1;
/** cocpu_saradc2_wake_int_clr : WT; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, int clear.
*/
uint32_t cocpu_saradc2_wake_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_int_clr_reg_t;
/** Type of int_ena_w1ts register
* Interrupt enable assert registers.
*/
typedef union {
struct {
/** cocpu_saradc1_int_ena_w1ts : WT; bitpos: [0]; default: 0;
* ADC1 Conversion is done, write 1 to assert int enable.
*/
uint32_t cocpu_saradc1_int_ena_w1ts:1;
/** cocpu_saradc2_int_ena_w1ts : WT; bitpos: [1]; default: 0;
* ADC2 Conversion is done, write 1 to assert int enable.
*/
uint32_t cocpu_saradc2_int_ena_w1ts:1;
/** cocpu_saradc1_error_int_ena_w1ts : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, write 1 to assert int enable.
*/
uint32_t cocpu_saradc1_error_int_ena_w1ts:1;
/** cocpu_saradc2_error_int_ena_w1ts : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, write 1 to assert int enable.
*/
uint32_t cocpu_saradc2_error_int_ena_w1ts:1;
/** cocpu_saradc1_wake_int_ena_w1ts : WT; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, write 1 to assert int enable.
*/
uint32_t cocpu_saradc1_wake_int_ena_w1ts:1;
/** cocpu_saradc2_wake_int_ena_w1ts : WT; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, write 1 to assert int enable.
*/
uint32_t cocpu_saradc2_wake_int_ena_w1ts:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_int_ena_w1ts_reg_t;
/** Type of int_ena_w1tc register
* Interrupt enable deassert registers.
*/
typedef union {
struct {
/** cocpu_saradc1_int_ena_w1tc : WT; bitpos: [0]; default: 0;
* ADC1 Conversion is done, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc1_int_ena_w1tc:1;
/** cocpu_saradc2_int_ena_w1tc : WT; bitpos: [1]; default: 0;
* ADC2 Conversion is done, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc2_int_ena_w1tc:1;
/** cocpu_saradc1_error_int_ena_w1tc : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc1_error_int_ena_w1tc:1;
/** cocpu_saradc2_error_int_ena_w1tc : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc2_error_int_ena_w1tc:1;
/** cocpu_saradc1_wake_int_ena_w1tc : WT; bitpos: [4]; default: 0;
* A wakeup event is triggered from ADC1, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc1_wake_int_ena_w1tc:1;
/** cocpu_saradc2_wake_int_ena_w1tc : WT; bitpos: [5]; default: 0;
* A wakeup event is triggered from ADC2, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc2_wake_int_ena_w1tc:1;
uint32_t reserved_6:26;
};
uint32_t val;
} rtcadc_int_ena_w1tc_reg_t;
/** Group: RTCADC wakeup control registers. */
/** Type of wakeup1 register
* ADC1 wakeup configuration registers.
*/
typedef union {
struct {
/** sar1_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
* Lower threshold.
*/
uint32_t sar1_wakeup_th_low:12;
uint32_t reserved_12:2;
/** sar1_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
* Upper threshold.
*/
uint32_t sar1_wakeup_th_high:12;
uint32_t reserved_26:3;
/** sar1_wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
* Indicates that this wakeup event arose from exceeding upper threshold.
*/
uint32_t sar1_wakeup_over_upper_th:1;
/** sar1_wakeup_en : R/W; bitpos: [30]; default: 0;
* Wakeup function enable.
*/
uint32_t sar1_wakeup_en:1;
/** sar1_wakeup_mode : R/W; bitpos: [31]; default: 0;
* 0:absolute value comparison mode. 1: relative value comparison mode.
*/
uint32_t sar1_wakeup_mode:1;
};
uint32_t val;
} rtcadc_wakeup1_reg_t;
/** Type of wakeup2 register
* ADC2 wakeup configuration registers.
*/
typedef union {
struct {
/** sar2_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
* Lower threshold.
*/
uint32_t sar2_wakeup_th_low:12;
uint32_t reserved_12:2;
/** sar2_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
* Upper threshold.
*/
uint32_t sar2_wakeup_th_high:12;
uint32_t reserved_26:3;
/** sar2_wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
* Indicates that this wakeup event arose from exceeding upper threshold.
*/
uint32_t sar2_wakeup_over_upper_th:1;
/** sar2_wakeup_en : R/W; bitpos: [30]; default: 0;
* Wakeup function enable.
*/
uint32_t sar2_wakeup_en:1;
/** sar2_wakeup_mode : R/W; bitpos: [31]; default: 0;
* 0:absolute value comparison mode. 1: relative value comparison mode.
*/
uint32_t sar2_wakeup_mode:1;
};
uint32_t val;
} rtcadc_wakeup2_reg_t;
/** Type of wakeup_sel register
* Wakeup source select register.
*/
typedef union {
struct {
/** sar_wakeup_sel : R/W; bitpos: [0]; default: 0;
* 0: ADC1. 1: ADC2.
*/
uint32_t sar_wakeup_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rtcadc_wakeup_sel_reg_t;
/** Type of sar1_hw_wakeup register
* Hardware automatic sampling registers for wakeup function.
*/
typedef union {
struct {
/** adc1_hw_read_en_i : R/W; bitpos: [0]; default: 0;
* Enable hardware automatic sampling.
*/
uint32_t adc1_hw_read_en_i:1;
/** adc1_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100;
* Hardware automatic sampling rate.
*/
uint32_t adc1_hw_read_rate_i:16;
uint32_t reserved_17:15;
};
uint32_t val;
} rtcadc_sar1_hw_wakeup_reg_t;
/** Type of sar2_hw_wakeup register
* Hardware automatic sampling registers for wakeup function.
*/
typedef union {
struct {
/** adc2_hw_read_en_i : R/W; bitpos: [0]; default: 0;
* Enable hardware automatic sampling.
*/
uint32_t adc2_hw_read_en_i:1;
/** adc2_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100;
* Hardware automatic sampling rate.
*/
uint32_t adc2_hw_read_rate_i:16;
uint32_t reserved_17:15;
};
uint32_t val;
} rtcadc_sar2_hw_wakeup_reg_t;
typedef struct {
volatile rtcadc_reader1_ctrl_reg_t reader1_ctrl;
uint32_t reserved_004[2];
volatile rtcadc_meas1_ctrl2_reg_t meas1_ctrl2;
volatile rtcadc_meas1_mux_reg_t meas1_mux;
volatile rtcadc_atten1_reg_t atten1;
uint32_t reserved_018[3];
volatile rtcadc_reader2_ctrl_reg_t reader2_ctrl;
uint32_t reserved_028;
volatile rtcadc_meas2_ctrl1_reg_t meas2_ctrl1;
volatile rtcadc_meas2_ctrl2_reg_t meas2_ctrl2;
volatile rtcadc_meas2_mux_reg_t meas2_mux;
volatile rtcadc_atten2_reg_t atten2;
volatile rtcadc_force_wpd_sar_reg_t force_wpd_sar;
uint32_t reserved_040[2];
volatile rtcadc_cocpu_int_raw_reg_t cocpu_int_raw;
volatile rtcadc_int_ena_reg_t int_ena;
volatile rtcadc_int_st_reg_t int_st;
volatile rtcadc_int_clr_reg_t int_clr;
volatile rtcadc_int_ena_w1ts_reg_t int_ena_w1ts;
volatile rtcadc_int_ena_w1tc_reg_t int_ena_w1tc;
volatile rtcadc_wakeup1_reg_t wakeup1;
volatile rtcadc_wakeup2_reg_t wakeup2;
volatile rtcadc_wakeup_sel_reg_t wakeup_sel;
volatile rtcadc_sar1_hw_wakeup_reg_t sar1_hw_wakeup;
volatile rtcadc_sar2_hw_wakeup_reg_t sar2_hw_wakeup;
} rtcadc_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(rtcadc_dev_t) == 0x74, "Invalid size of rtcadc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/rtclockcali_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RTCLOCKCALI_LP_CALI_TIMER_REG register
* need_des
*/
#define RTCLOCKCALI_LP_CALI_TIMER_REG (DR_REG_RTCLOCKCALI_BASE + 0x0)
/** RTCLOCKCALI_TIMER_TARGET : R/W; bitpos: [29:0]; default: 4095;
* need_des
*/
#define RTCLOCKCALI_TIMER_TARGET 0x3FFFFFFFU
#define RTCLOCKCALI_TIMER_TARGET_M (RTCLOCKCALI_TIMER_TARGET_V << RTCLOCKCALI_TIMER_TARGET_S)
#define RTCLOCKCALI_TIMER_TARGET_V 0x3FFFFFFFU
#define RTCLOCKCALI_TIMER_TARGET_S 0
/** RTCLOCKCALI_TIMER_STOP : WT; bitpos: [30]; default: 0;
* need_des
*/
#define RTCLOCKCALI_TIMER_STOP (BIT(30))
#define RTCLOCKCALI_TIMER_STOP_M (RTCLOCKCALI_TIMER_STOP_V << RTCLOCKCALI_TIMER_STOP_S)
#define RTCLOCKCALI_TIMER_STOP_V 0x00000001U
#define RTCLOCKCALI_TIMER_STOP_S 30
/** RTCLOCKCALI_TIMER_START : WT; bitpos: [31]; default: 0;
* need_des
*/
#define RTCLOCKCALI_TIMER_START (BIT(31))
#define RTCLOCKCALI_TIMER_START_M (RTCLOCKCALI_TIMER_START_V << RTCLOCKCALI_TIMER_START_S)
#define RTCLOCKCALI_TIMER_START_V 0x00000001U
#define RTCLOCKCALI_TIMER_START_S 31
/** RTCLOCKCALI_RTCCALICFG_SLOW_REG register
* RTC calibration configure register
*/
#define RTCLOCKCALI_RTCCALICFG_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x4)
/** RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW (BIT(12))
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_M (RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S 12
/** RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW 0x00000003U
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_M (RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V 0x00000003U
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S 13
/** RTCLOCKCALI_RTC_CALI_RDY_SLOW : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
#define RTCLOCKCALI_RTC_CALI_RDY_SLOW (BIT(15))
#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_M (RTCLOCKCALI_RTC_CALI_RDY_SLOW_V << RTCLOCKCALI_RTC_CALI_RDY_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_S 15
/** RTCLOCKCALI_RTC_CALI_MAX_SLOW : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
#define RTCLOCKCALI_RTC_CALI_MAX_SLOW 0x00007FFFU
#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_M (RTCLOCKCALI_RTC_CALI_MAX_SLOW_V << RTCLOCKCALI_RTC_CALI_MAX_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_V 0x00007FFFU
#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_S 16
/** RTCLOCKCALI_RTC_CALI_START_SLOW : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
#define RTCLOCKCALI_RTC_CALI_START_SLOW (BIT(31))
#define RTCLOCKCALI_RTC_CALI_START_SLOW_M (RTCLOCKCALI_RTC_CALI_START_SLOW_V << RTCLOCKCALI_RTC_CALI_START_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_START_SLOW_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_START_SLOW_S 31
/** RTCLOCKCALI_RTCCALICFG_FAST_REG register
* RTC calibration configure register
*/
#define RTCLOCKCALI_RTCCALICFG_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x8)
/** RTCLOCKCALI_FOSC_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
* fosc clock divider number
*/
#define RTCLOCKCALI_FOSC_DIV_NUM 0x000000FFU
#define RTCLOCKCALI_FOSC_DIV_NUM_M (RTCLOCKCALI_FOSC_DIV_NUM_V << RTCLOCKCALI_FOSC_DIV_NUM_S)
#define RTCLOCKCALI_FOSC_DIV_NUM_V 0x000000FFU
#define RTCLOCKCALI_FOSC_DIV_NUM_S 4
/** RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST (BIT(12))
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_M (RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S)
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S 12
/** RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST 0x00000003U
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_M (RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S)
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V 0x00000003U
#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S 13
/** RTCLOCKCALI_RTC_CALI_RDY_FAST : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
#define RTCLOCKCALI_RTC_CALI_RDY_FAST (BIT(15))
#define RTCLOCKCALI_RTC_CALI_RDY_FAST_M (RTCLOCKCALI_RTC_CALI_RDY_FAST_V << RTCLOCKCALI_RTC_CALI_RDY_FAST_S)
#define RTCLOCKCALI_RTC_CALI_RDY_FAST_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_RDY_FAST_S 15
/** RTCLOCKCALI_RTC_CALI_MAX_FAST : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
#define RTCLOCKCALI_RTC_CALI_MAX_FAST 0x00007FFFU
#define RTCLOCKCALI_RTC_CALI_MAX_FAST_M (RTCLOCKCALI_RTC_CALI_MAX_FAST_V << RTCLOCKCALI_RTC_CALI_MAX_FAST_S)
#define RTCLOCKCALI_RTC_CALI_MAX_FAST_V 0x00007FFFU
#define RTCLOCKCALI_RTC_CALI_MAX_FAST_S 16
/** RTCLOCKCALI_RTC_CALI_START_FAST : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
#define RTCLOCKCALI_RTC_CALI_START_FAST (BIT(31))
#define RTCLOCKCALI_RTC_CALI_START_FAST_M (RTCLOCKCALI_RTC_CALI_START_FAST_V << RTCLOCKCALI_RTC_CALI_START_FAST_S)
#define RTCLOCKCALI_RTC_CALI_START_FAST_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_START_FAST_S 31
/** RTCLOCKCALI_RTCCALICFG1_SLOW_REG register
* RTC calibration configure1 register
*/
#define RTCLOCKCALI_RTCCALICFG1_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0xc)
/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW (BIT(0))
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_M (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S 0
/** RTCLOCKCALI_RTC_CALI_VALUE_SLOW : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW 0x01FFFFFFU
#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_M (RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V << RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S)
#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V 0x01FFFFFFU
#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S 7
/** RTCLOCKCALI_RTCCALICFG1_FAST_REG register
* RTC calibration configure1 register
*/
#define RTCLOCKCALI_RTCCALICFG1_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x10)
/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST (BIT(0))
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_M (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S)
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S 0
/** RTCLOCKCALI_RTC_CALI_VALUE_FAST : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
#define RTCLOCKCALI_RTC_CALI_VALUE_FAST 0x01FFFFFFU
#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_M (RTCLOCKCALI_RTC_CALI_VALUE_FAST_V << RTCLOCKCALI_RTC_CALI_VALUE_FAST_S)
#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_V 0x01FFFFFFU
#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_S 7
/** RTCLOCKCALI_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define RTCLOCKCALI_RTCCALICFG2_REG (DR_REG_RTCLOCKCALI_BASE + 0x14)
/** RTCLOCKCALI_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define RTCLOCKCALI_RTC_CALI_TIMEOUT (BIT(0))
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_M (RTCLOCKCALI_RTC_CALI_TIMEOUT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_S)
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_V 0x00000001U
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_S 0
/** RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_M (RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S)
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_M (RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S)
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S 7
/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG register
* RTC slow clock dfreq high limit.
*/
#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x18)
/** RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW : R/W; bitpos: [7:0]; default: 16;
* When rtc_cali_value upper/lower than reg_high/low_limit +/-
* reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
*/
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW 0x000000FFU
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_M (RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S)
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V 0x000000FFU
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S 0
/** RTCLOCKCALI_HIGH_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 267;
* when rtc_cali_value upper than reg_high_limit,frequency of osc will increase .
*/
#define RTCLOCKCALI_HIGH_LIMIT_SLOW 0x00FFFFFFU
#define RTCLOCKCALI_HIGH_LIMIT_SLOW_M (RTCLOCKCALI_HIGH_LIMIT_SLOW_V << RTCLOCKCALI_HIGH_LIMIT_SLOW_S)
#define RTCLOCKCALI_HIGH_LIMIT_SLOW_V 0x00FFFFFFU
#define RTCLOCKCALI_HIGH_LIMIT_SLOW_S 8
/** RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG register
* RTC slow clock dfreq low limit.
*/
#define RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x1c)
/** RTCLOCKCALI_LOW_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 266;
* when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease .
*/
#define RTCLOCKCALI_LOW_LIMIT_SLOW 0x00FFFFFFU
#define RTCLOCKCALI_LOW_LIMIT_SLOW_M (RTCLOCKCALI_LOW_LIMIT_SLOW_V << RTCLOCKCALI_LOW_LIMIT_SLOW_S)
#define RTCLOCKCALI_LOW_LIMIT_SLOW_V 0x00FFFFFFU
#define RTCLOCKCALI_LOW_LIMIT_SLOW_S 8
/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG register
* RTC fast clock dfreq high limit.
*/
#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x20)
/** RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST : R/W; bitpos: [7:0]; default: 16;
* When rtc_cali_value upper/lower than reg_high/low_limit +/-
* reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
*/
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST 0x000000FFU
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_M (RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S)
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V 0x000000FFU
#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S 0
/** RTCLOCKCALI_HIGH_LIMIT_FAST : R/W; bitpos: [31:8]; default: 267;
* when rtc_cali_value upper than reg_high_limit,frequency of osc will increase .
*/
#define RTCLOCKCALI_HIGH_LIMIT_FAST 0x00FFFFFFU
#define RTCLOCKCALI_HIGH_LIMIT_FAST_M (RTCLOCKCALI_HIGH_LIMIT_FAST_V << RTCLOCKCALI_HIGH_LIMIT_FAST_S)
#define RTCLOCKCALI_HIGH_LIMIT_FAST_V 0x00FFFFFFU
#define RTCLOCKCALI_HIGH_LIMIT_FAST_S 8
/** RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG register
* RTC fast clock dfreq low limit.
*/
#define RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x24)
/** RTCLOCKCALI_LOW_LIMIT_FAST : R/W; bitpos: [31:8]; default: 266;
* when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease .
*/
#define RTCLOCKCALI_LOW_LIMIT_FAST 0x00FFFFFFU
#define RTCLOCKCALI_LOW_LIMIT_FAST_M (RTCLOCKCALI_LOW_LIMIT_FAST_V << RTCLOCKCALI_LOW_LIMIT_FAST_S)
#define RTCLOCKCALI_LOW_LIMIT_FAST_V 0x00FFFFFFU
#define RTCLOCKCALI_LOW_LIMIT_FAST_S 8
/** RTCLOCKCALI_DFREQ_CONF2_REG register
* RTC DFREQ CONF2
*/
#define RTCLOCKCALI_DFREQ_CONF2_REG (DR_REG_RTCLOCKCALI_BASE + 0x28)
/** RTCLOCKCALI_DREQ_UPDATE : WT; bitpos: [0]; default: 0;
* need_des
*/
#define RTCLOCKCALI_DREQ_UPDATE (BIT(0))
#define RTCLOCKCALI_DREQ_UPDATE_M (RTCLOCKCALI_DREQ_UPDATE_V << RTCLOCKCALI_DREQ_UPDATE_S)
#define RTCLOCKCALI_DREQ_UPDATE_V 0x00000001U
#define RTCLOCKCALI_DREQ_UPDATE_S 0
/** RTCLOCKCALI_DREQ_INIT_32K : WT; bitpos: [2]; default: 0;
* Initialize the vaule of 32K OSC dfreq setting.
*/
#define RTCLOCKCALI_DREQ_INIT_32K (BIT(2))
#define RTCLOCKCALI_DREQ_INIT_32K_M (RTCLOCKCALI_DREQ_INIT_32K_V << RTCLOCKCALI_DREQ_INIT_32K_S)
#define RTCLOCKCALI_DREQ_INIT_32K_V 0x00000001U
#define RTCLOCKCALI_DREQ_INIT_32K_S 2
/** RTCLOCKCALI_DREQ_INIT_FOSC : WT; bitpos: [3]; default: 0;
* Initialize the vaule of FOSC dfreq setting.
*/
#define RTCLOCKCALI_DREQ_INIT_FOSC (BIT(3))
#define RTCLOCKCALI_DREQ_INIT_FOSC_M (RTCLOCKCALI_DREQ_INIT_FOSC_V << RTCLOCKCALI_DREQ_INIT_FOSC_S)
#define RTCLOCKCALI_DREQ_INIT_FOSC_V 0x00000001U
#define RTCLOCKCALI_DREQ_INIT_FOSC_S 3
/** RTCLOCKCALI_DREQ_INIT_SOSC : WT; bitpos: [4]; default: 0;
* Initialize the vaule of SOSC dfreq setting.
*/
#define RTCLOCKCALI_DREQ_INIT_SOSC (BIT(4))
#define RTCLOCKCALI_DREQ_INIT_SOSC_M (RTCLOCKCALI_DREQ_INIT_SOSC_V << RTCLOCKCALI_DREQ_INIT_SOSC_S)
#define RTCLOCKCALI_DREQ_INIT_SOSC_V 0x00000001U
#define RTCLOCKCALI_DREQ_INIT_SOSC_S 4
/** RTCLOCKCALI_32K_DFREQ_SEL : R/W; bitpos: [5]; default: 0;
* 1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled
* by register from system-register bank
*/
#define RTCLOCKCALI_32K_DFREQ_SEL (BIT(5))
#define RTCLOCKCALI_32K_DFREQ_SEL_M (RTCLOCKCALI_32K_DFREQ_SEL_V << RTCLOCKCALI_32K_DFREQ_SEL_S)
#define RTCLOCKCALI_32K_DFREQ_SEL_V 0x00000001U
#define RTCLOCKCALI_32K_DFREQ_SEL_S 5
/** RTCLOCKCALI_FOSC_DFREQ_SEL : R/W; bitpos: [6]; default: 0;
* 1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled
* by register from system-register bank
*/
#define RTCLOCKCALI_FOSC_DFREQ_SEL (BIT(6))
#define RTCLOCKCALI_FOSC_DFREQ_SEL_M (RTCLOCKCALI_FOSC_DFREQ_SEL_V << RTCLOCKCALI_FOSC_DFREQ_SEL_S)
#define RTCLOCKCALI_FOSC_DFREQ_SEL_V 0x00000001U
#define RTCLOCKCALI_FOSC_DFREQ_SEL_S 6
/** RTCLOCKCALI_SOSC_DFREQ_SEL : R/W; bitpos: [7]; default: 0;
* 1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled
* by register from system-register bank
*/
#define RTCLOCKCALI_SOSC_DFREQ_SEL (BIT(7))
#define RTCLOCKCALI_SOSC_DFREQ_SEL_M (RTCLOCKCALI_SOSC_DFREQ_SEL_V << RTCLOCKCALI_SOSC_DFREQ_SEL_S)
#define RTCLOCKCALI_SOSC_DFREQ_SEL_V 0x00000001U
#define RTCLOCKCALI_SOSC_DFREQ_SEL_S 7
/** RTCLOCKCALI_FINE_STEP : R/W; bitpos: [15:8]; default: 1;
* Frequncy fine step.
*/
#define RTCLOCKCALI_FINE_STEP 0x000000FFU
#define RTCLOCKCALI_FINE_STEP_M (RTCLOCKCALI_FINE_STEP_V << RTCLOCKCALI_FINE_STEP_S)
#define RTCLOCKCALI_FINE_STEP_V 0x000000FFU
#define RTCLOCKCALI_FINE_STEP_S 8
/** RTCLOCKCALI_COARSE_STEP_FAST : R/W; bitpos: [23:16]; default: 8;
* Frequncy coarse step,use to decrease calibration time.
*/
#define RTCLOCKCALI_COARSE_STEP_FAST 0x000000FFU
#define RTCLOCKCALI_COARSE_STEP_FAST_M (RTCLOCKCALI_COARSE_STEP_FAST_V << RTCLOCKCALI_COARSE_STEP_FAST_S)
#define RTCLOCKCALI_COARSE_STEP_FAST_V 0x000000FFU
#define RTCLOCKCALI_COARSE_STEP_FAST_S 16
/** RTCLOCKCALI_COARSE_STEP_SLOW : R/W; bitpos: [31:24]; default: 8;
* Frequncy coarse step,use to decrease calibration time.
*/
#define RTCLOCKCALI_COARSE_STEP_SLOW 0x000000FFU
#define RTCLOCKCALI_COARSE_STEP_SLOW_M (RTCLOCKCALI_COARSE_STEP_SLOW_V << RTCLOCKCALI_COARSE_STEP_SLOW_S)
#define RTCLOCKCALI_COARSE_STEP_SLOW_V 0x000000FFU
#define RTCLOCKCALI_COARSE_STEP_SLOW_S 24
/** RTCLOCKCALI_CALI_EN_REG register
* Configure register.
*/
#define RTCLOCKCALI_CALI_EN_REG (DR_REG_RTCLOCKCALI_BASE + 0x2c)
/** RTCLOCKCALI_CALI_EN_32K : R/W; bitpos: [0]; default: 1;
* need_des
*/
#define RTCLOCKCALI_CALI_EN_32K (BIT(0))
#define RTCLOCKCALI_CALI_EN_32K_M (RTCLOCKCALI_CALI_EN_32K_V << RTCLOCKCALI_CALI_EN_32K_S)
#define RTCLOCKCALI_CALI_EN_32K_V 0x00000001U
#define RTCLOCKCALI_CALI_EN_32K_S 0
/** RTCLOCKCALI_CALI_EN_FOSC : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define RTCLOCKCALI_CALI_EN_FOSC (BIT(1))
#define RTCLOCKCALI_CALI_EN_FOSC_M (RTCLOCKCALI_CALI_EN_FOSC_V << RTCLOCKCALI_CALI_EN_FOSC_S)
#define RTCLOCKCALI_CALI_EN_FOSC_V 0x00000001U
#define RTCLOCKCALI_CALI_EN_FOSC_S 1
/** RTCLOCKCALI_CALI_EN_SOSC : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define RTCLOCKCALI_CALI_EN_SOSC (BIT(2))
#define RTCLOCKCALI_CALI_EN_SOSC_M (RTCLOCKCALI_CALI_EN_SOSC_V << RTCLOCKCALI_CALI_EN_SOSC_S)
#define RTCLOCKCALI_CALI_EN_SOSC_V 0x00000001U
#define RTCLOCKCALI_CALI_EN_SOSC_S 2
/** RTCLOCKCALI_DFREQ_VALUE_REG register
* Configure register.
*/
#define RTCLOCKCALI_DFREQ_VALUE_REG (DR_REG_RTCLOCKCALI_BASE + 0x30)
/** RTCLOCKCALI_DREQ_32K : RO; bitpos: [11:2]; default: 172;
* The value of dfreq num of 32k.
*/
#define RTCLOCKCALI_DREQ_32K 0x000003FFU
#define RTCLOCKCALI_DREQ_32K_M (RTCLOCKCALI_DREQ_32K_V << RTCLOCKCALI_DREQ_32K_S)
#define RTCLOCKCALI_DREQ_32K_V 0x000003FFU
#define RTCLOCKCALI_DREQ_32K_S 2
/** RTCLOCKCALI_DREQ_FOSC : RO; bitpos: [21:12]; default: 172;
* The value of dfreq num of FOSC.
*/
#define RTCLOCKCALI_DREQ_FOSC 0x000003FFU
#define RTCLOCKCALI_DREQ_FOSC_M (RTCLOCKCALI_DREQ_FOSC_V << RTCLOCKCALI_DREQ_FOSC_S)
#define RTCLOCKCALI_DREQ_FOSC_V 0x000003FFU
#define RTCLOCKCALI_DREQ_FOSC_S 12
/** RTCLOCKCALI_DREQ_SOSC : RO; bitpos: [31:22]; default: 172;
* The value of dfreq num of SOSC.
*/
#define RTCLOCKCALI_DREQ_SOSC 0x000003FFU
#define RTCLOCKCALI_DREQ_SOSC_M (RTCLOCKCALI_DREQ_SOSC_V << RTCLOCKCALI_DREQ_SOSC_S)
#define RTCLOCKCALI_DREQ_SOSC_V 0x000003FFU
#define RTCLOCKCALI_DREQ_SOSC_S 22
/** RTCLOCKCALI_BYPASS_REG register
* Configure register.
*/
#define RTCLOCKCALI_BYPASS_REG (DR_REG_RTCLOCKCALI_BASE + 0x34)
/** RTCLOCKCALI_HP_SLEEP_AUTOCALI : R/W; bitpos: [30]; default: 0;
* 1:Chip begin to calibrating,when into hp_sleep.0:Disable this function.
*/
#define RTCLOCKCALI_HP_SLEEP_AUTOCALI (BIT(30))
#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_M (RTCLOCKCALI_HP_SLEEP_AUTOCALI_V << RTCLOCKCALI_HP_SLEEP_AUTOCALI_S)
#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_V 0x00000001U
#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_S 30
/** RTCLOCKCALI_LP_SLEEP_AUTOCALI : R/W; bitpos: [31]; default: 0;
* 1:Chip begin to calibrating,when into lp_sleep.0:Disable this function.
*/
#define RTCLOCKCALI_LP_SLEEP_AUTOCALI (BIT(31))
#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_M (RTCLOCKCALI_LP_SLEEP_AUTOCALI_V << RTCLOCKCALI_LP_SLEEP_AUTOCALI_S)
#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_V 0x00000001U
#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_S 31
/** RTCLOCKCALI_INT_RAW_REG register
* Configure register.
*/
#define RTCLOCKCALI_INT_RAW_REG (DR_REG_RTCLOCKCALI_BASE + 0x38)
/** RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* Indicate the xtal timeout once happend .
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW (BIT(29))
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V 0x00000001U
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S 29
/** RTCLOCKCALI_CALI_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Indicate the calibration timeout once happend .
*/
#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW (BIT(30))
#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_M (RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V << RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S)
#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V 0x00000001U
#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S 30
/** RTCLOCKCALI_CALI_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Indicate the finish of once calibration .
*/
#define RTCLOCKCALI_CALI_DONE_INT_RAW (BIT(31))
#define RTCLOCKCALI_CALI_DONE_INT_RAW_M (RTCLOCKCALI_CALI_DONE_INT_RAW_V << RTCLOCKCALI_CALI_DONE_INT_RAW_S)
#define RTCLOCKCALI_CALI_DONE_INT_RAW_V 0x00000001U
#define RTCLOCKCALI_CALI_DONE_INT_RAW_S 31
/** RTCLOCKCALI_INT_ST_REG register
* Interrupt state register.
*/
#define RTCLOCKCALI_INT_ST_REG (DR_REG_RTCLOCKCALI_BASE + 0x3c)
/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ST : RO; bitpos: [29]; default: 0;
* Interrupt state register.
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST (BIT(29))
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V 0x00000001U
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S 29
/** RTCLOCKCALI_CALI_TIMEOUT_INT_ST : RO; bitpos: [30]; default: 0;
* Interrupt state register.
*/
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST (BIT(30))
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_M (RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S)
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V 0x00000001U
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S 30
/** RTCLOCKCALI_CALI_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* Interrupt state register.
*/
#define RTCLOCKCALI_CALI_DONE_INT_ST (BIT(31))
#define RTCLOCKCALI_CALI_DONE_INT_ST_M (RTCLOCKCALI_CALI_DONE_INT_ST_V << RTCLOCKCALI_CALI_DONE_INT_ST_S)
#define RTCLOCKCALI_CALI_DONE_INT_ST_V 0x00000001U
#define RTCLOCKCALI_CALI_DONE_INT_ST_S 31
/** RTCLOCKCALI_INT_ENA_REG register
* Configure register.
*/
#define RTCLOCKCALI_INT_ENA_REG (DR_REG_RTCLOCKCALI_BASE + 0x40)
/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA : R/W; bitpos: [29]; default: 0;
* Interrupt enable signal.
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA (BIT(29))
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V 0x00000001U
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S 29
/** RTCLOCKCALI_CALI_TIMEOUT_INT_ENA : R/W; bitpos: [30]; default: 0;
* Interrupt enable signal.
*/
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA (BIT(30))
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_M (RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S)
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V 0x00000001U
#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S 30
/** RTCLOCKCALI_CALI_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* Interrupt enable signal.
*/
#define RTCLOCKCALI_CALI_DONE_INT_ENA (BIT(31))
#define RTCLOCKCALI_CALI_DONE_INT_ENA_M (RTCLOCKCALI_CALI_DONE_INT_ENA_V << RTCLOCKCALI_CALI_DONE_INT_ENA_S)
#define RTCLOCKCALI_CALI_DONE_INT_ENA_V 0x00000001U
#define RTCLOCKCALI_CALI_DONE_INT_ENA_S 31
/** RTCLOCKCALI_INT_CLR_REG register
* Configure register.
*/
#define RTCLOCKCALI_INT_CLR_REG (DR_REG_RTCLOCKCALI_BASE + 0x44)
/** RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR : WT; bitpos: [29]; default: 0;
* interrupt clear signal.
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR (BIT(29))
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V 0x00000001U
#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S 29
/** RTCLOCKCALI_CALI_TIMEOUT_INT_CLR : WT; bitpos: [30]; default: 0;
* interrupt clear signal.
*/
#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR (BIT(30))
#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_M (RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V << RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S)
#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V 0x00000001U
#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S 30
/** RTCLOCKCALI_CALI_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* interrupt clear signal.
*/
#define RTCLOCKCALI_CALI_DONE_INT_CLR (BIT(31))
#define RTCLOCKCALI_CALI_DONE_INT_CLR_M (RTCLOCKCALI_CALI_DONE_INT_CLR_V << RTCLOCKCALI_CALI_DONE_INT_CLR_S)
#define RTCLOCKCALI_CALI_DONE_INT_CLR_V 0x00000001U
#define RTCLOCKCALI_CALI_DONE_INT_CLR_S 31
/** RTCLOCKCALI_TIMEOUT_REG register
* Configure register.
*/
#define RTCLOCKCALI_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x48)
/** RTCLOCKCALI_TIMEOUT_TARGET : R/W; bitpos: [29:0]; default: 0;
* use to setting max calibration time .
*/
#define RTCLOCKCALI_TIMEOUT_TARGET 0x3FFFFFFFU
#define RTCLOCKCALI_TIMEOUT_TARGET_M (RTCLOCKCALI_TIMEOUT_TARGET_V << RTCLOCKCALI_TIMEOUT_TARGET_S)
#define RTCLOCKCALI_TIMEOUT_TARGET_V 0x3FFFFFFFU
#define RTCLOCKCALI_TIMEOUT_TARGET_S 0
/** RTCLOCKCALI_TIMEOUT_EN : R/W; bitpos: [31]; default: 0;
* use to enable calibration time-out function ,the calibration force stopping,when
* timeout.
*/
#define RTCLOCKCALI_TIMEOUT_EN (BIT(31))
#define RTCLOCKCALI_TIMEOUT_EN_M (RTCLOCKCALI_TIMEOUT_EN_V << RTCLOCKCALI_TIMEOUT_EN_S)
#define RTCLOCKCALI_TIMEOUT_EN_V 0x00000001U
#define RTCLOCKCALI_TIMEOUT_EN_S 31
/** RTCLOCKCALI_XTAL_TIMEOUT_REG register
* Configure register.
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x4c)
/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET : R/W; bitpos: [29:14]; default: 65535;
* use to setting max xtal monitor time .
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET 0x0000FFFFU
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_M (RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V 0x0000FFFFU
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S 14
/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP : WT; bitpos: [30]; default: 0;
* use to stop XTAL time-out function ,timeout happened when xtal invalid.
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP (BIT(30))
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_M (RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V 0x00000001U
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S 30
/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_START : WT; bitpos: [31]; default: 0;
* use to start XTAL time-out function ,timeout happened when xtal invalid.
*/
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START (BIT(31))
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_M (RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S)
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V 0x00000001U
#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S 31
/** RTCLOCKCALI_DATE_REG register
* Configure register.
*/
#define RTCLOCKCALI_DATE_REG (DR_REG_RTCLOCKCALI_BASE + 0x3fc)
/** RTCLOCKCALI_RTCLOCKCALI_DATE : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
#define RTCLOCKCALI_RTCLOCKCALI_DATE 0x7FFFFFFFU
#define RTCLOCKCALI_RTCLOCKCALI_DATE_M (RTCLOCKCALI_RTCLOCKCALI_DATE_V << RTCLOCKCALI_RTCLOCKCALI_DATE_S)
#define RTCLOCKCALI_RTCLOCKCALI_DATE_V 0x7FFFFFFFU
#define RTCLOCKCALI_RTCLOCKCALI_DATE_S 0
/** RTCLOCKCALI_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define RTCLOCKCALI_CLK_EN (BIT(31))
#define RTCLOCKCALI_CLK_EN_M (RTCLOCKCALI_CLK_EN_V << RTCLOCKCALI_CLK_EN_S)
#define RTCLOCKCALI_CLK_EN_V 0x00000001U
#define RTCLOCKCALI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_cali_timer register
* need_des
*/
typedef union {
struct {
/** timer_target : R/W; bitpos: [29:0]; default: 4095;
* need_des
*/
uint32_t timer_target:30;
/** timer_stop : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_stop:1;
/** timer_start : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_start:1;
};
uint32_t val;
} rtclockcali_lp_cali_timer_reg_t;
/** Type of dfreq_high_limit_slow register
* RTC slow clock dfreq high limit.
*/
typedef union {
struct {
/** coarse_limit_diff_slow : R/W; bitpos: [7:0]; default: 16;
* When rtc_cali_value upper/lower than reg_high/low_limit +/-
* reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
*/
uint32_t coarse_limit_diff_slow:8;
/** high_limit_slow : R/W; bitpos: [31:8]; default: 267;
* when rtc_cali_value upper than reg_high_limit,frequency of osc will increase .
*/
uint32_t high_limit_slow:24;
};
uint32_t val;
} rtclockcali_dfreq_high_limit_slow_reg_t;
/** Type of dfreq_low_limit_slow register
* RTC slow clock dfreq low limit.
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** low_limit_slow : R/W; bitpos: [31:8]; default: 266;
* when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease .
*/
uint32_t low_limit_slow:24;
};
uint32_t val;
} rtclockcali_dfreq_low_limit_slow_reg_t;
/** Type of dfreq_high_limit_fast register
* RTC fast clock dfreq high limit.
*/
typedef union {
struct {
/** coarse_limit_diff_fast : R/W; bitpos: [7:0]; default: 16;
* When rtc_cali_value upper/lower than reg_high/low_limit +/-
* reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
*/
uint32_t coarse_limit_diff_fast:8;
/** high_limit_fast : R/W; bitpos: [31:8]; default: 267;
* when rtc_cali_value upper than reg_high_limit,frequency of osc will increase .
*/
uint32_t high_limit_fast:24;
};
uint32_t val;
} rtclockcali_dfreq_high_limit_fast_reg_t;
/** Type of dfreq_low_limit_fast register
* RTC fast clock dfreq low limit.
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** low_limit_fast : R/W; bitpos: [31:8]; default: 266;
* when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease .
*/
uint32_t low_limit_fast:24;
};
uint32_t val;
} rtclockcali_dfreq_low_limit_fast_reg_t;
/** Type of dfreq_conf2 register
* RTC DFREQ CONF2
*/
typedef union {
struct {
/** dreq_update : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t dreq_update:1;
uint32_t reserved_1:1;
/** dreq_init_32k : WT; bitpos: [2]; default: 0;
* Initialize the vaule of 32K OSC dfreq setting.
*/
uint32_t dreq_init_32k:1;
/** dreq_init_fosc : WT; bitpos: [3]; default: 0;
* Initialize the vaule of FOSC dfreq setting.
*/
uint32_t dreq_init_fosc:1;
/** dreq_init_sosc : WT; bitpos: [4]; default: 0;
* Initialize the vaule of SOSC dfreq setting.
*/
uint32_t dreq_init_sosc:1;
/** rc32k_dfreq_sel : R/W; bitpos: [5]; default: 0;
* 1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled
* by register from system-register bank
*/
uint32_t rc32k_dfreq_sel:1;
/** fosc_dfreq_sel : R/W; bitpos: [6]; default: 0;
* 1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled
* by register from system-register bank
*/
uint32_t fosc_dfreq_sel:1;
/** sosc_dfreq_sel : R/W; bitpos: [7]; default: 0;
* 1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled
* by register from system-register bank
*/
uint32_t sosc_dfreq_sel:1;
/** fine_step : R/W; bitpos: [15:8]; default: 1;
* Frequncy fine step.
*/
uint32_t fine_step:8;
/** coarse_step_fast : R/W; bitpos: [23:16]; default: 8;
* Frequncy coarse step,use to decrease calibration time.
*/
uint32_t coarse_step_fast:8;
/** coarse_step_slow : R/W; bitpos: [31:24]; default: 8;
* Frequncy coarse step,use to decrease calibration time.
*/
uint32_t coarse_step_slow:8;
};
uint32_t val;
} rtclockcali_dfreq_conf2_reg_t;
/** Type of cali_en register
* Configure register.
*/
typedef union {
struct {
/** cali_en_32k : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t cali_en_32k:1;
/** cali_en_fosc : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t cali_en_fosc:1;
/** cali_en_sosc : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t cali_en_sosc:1;
uint32_t reserved_3:29;
};
uint32_t val;
} rtclockcali_cali_en_reg_t;
/** Type of dfreq_value register
* Configure register.
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** dreq_32k : RO; bitpos: [11:2]; default: 172;
* The value of dfreq num of 32k.
*/
uint32_t dreq_32k:10;
/** dreq_fosc : RO; bitpos: [21:12]; default: 172;
* The value of dfreq num of FOSC.
*/
uint32_t dreq_fosc:10;
/** dreq_sosc : RO; bitpos: [31:22]; default: 172;
* The value of dfreq num of SOSC.
*/
uint32_t dreq_sosc:10;
};
uint32_t val;
} rtclockcali_dfreq_value_reg_t;
/** Type of bypass register
* Configure register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** hp_sleep_autocali : R/W; bitpos: [30]; default: 0;
* 1:Chip begin to calibrating,when into hp_sleep.0:Disable this function.
*/
uint32_t hp_sleep_autocali:1;
/** lp_sleep_autocali : R/W; bitpos: [31]; default: 0;
* 1:Chip begin to calibrating,when into lp_sleep.0:Disable this function.
*/
uint32_t lp_sleep_autocali:1;
};
uint32_t val;
} rtclockcali_bypass_reg_t;
/** Type of int_raw register
* Configure register.
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** xtal_timeout_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* Indicate the xtal timeout once happend .
*/
uint32_t xtal_timeout_int_raw:1;
/** cali_timeout_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Indicate the calibration timeout once happend .
*/
uint32_t cali_timeout_int_raw:1;
/** cali_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Indicate the finish of once calibration .
*/
uint32_t cali_done_int_raw:1;
};
uint32_t val;
} rtclockcali_int_raw_reg_t;
/** Type of int_st register
* Interrupt state register.
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** xtal_timeout_int_st : RO; bitpos: [29]; default: 0;
* Interrupt state register.
*/
uint32_t xtal_timeout_int_st:1;
/** cali_timeout_int_st : RO; bitpos: [30]; default: 0;
* Interrupt state register.
*/
uint32_t cali_timeout_int_st:1;
/** cali_done_int_st : RO; bitpos: [31]; default: 0;
* Interrupt state register.
*/
uint32_t cali_done_int_st:1;
};
uint32_t val;
} rtclockcali_int_st_reg_t;
/** Type of int_ena register
* Configure register.
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** xtal_timeout_int_ena : R/W; bitpos: [29]; default: 0;
* Interrupt enable signal.
*/
uint32_t xtal_timeout_int_ena:1;
/** cali_timeout_int_ena : R/W; bitpos: [30]; default: 0;
* Interrupt enable signal.
*/
uint32_t cali_timeout_int_ena:1;
/** cali_done_int_ena : R/W; bitpos: [31]; default: 0;
* Interrupt enable signal.
*/
uint32_t cali_done_int_ena:1;
};
uint32_t val;
} rtclockcali_int_ena_reg_t;
/** Type of int_clr register
* Configure register.
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** xtal_timeout_int_clr : WT; bitpos: [29]; default: 0;
* interrupt clear signal.
*/
uint32_t xtal_timeout_int_clr:1;
/** cali_timeout_int_clr : WT; bitpos: [30]; default: 0;
* interrupt clear signal.
*/
uint32_t cali_timeout_int_clr:1;
/** cali_done_int_clr : WT; bitpos: [31]; default: 0;
* interrupt clear signal.
*/
uint32_t cali_done_int_clr:1;
};
uint32_t val;
} rtclockcali_int_clr_reg_t;
/** Type of timeout register
* Configure register.
*/
typedef union {
struct {
/** timeout_target : R/W; bitpos: [29:0]; default: 0;
* use to setting max calibration time .
*/
uint32_t timeout_target:30;
uint32_t reserved_30:1;
/** timeout_en : R/W; bitpos: [31]; default: 0;
* use to enable calibration time-out function ,the calibration force stopping,when
* timeout.
*/
uint32_t timeout_en:1;
};
uint32_t val;
} rtclockcali_timeout_reg_t;
/** Type of xtal_timeout register
* Configure register.
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** xtal_timeout_cnt_target : R/W; bitpos: [29:14]; default: 65535;
* use to setting max xtal monitor time .
*/
uint32_t xtal_timeout_cnt_target:16;
/** xtal_timeout_cnt_stop : WT; bitpos: [30]; default: 0;
* use to stop XTAL time-out function ,timeout happened when xtal invalid.
*/
uint32_t xtal_timeout_cnt_stop:1;
/** xtal_timeout_cnt_start : WT; bitpos: [31]; default: 0;
* use to start XTAL time-out function ,timeout happened when xtal invalid.
*/
uint32_t xtal_timeout_cnt_start:1;
};
uint32_t val;
} rtclockcali_xtal_timeout_reg_t;
/** Type of date register
* Configure register.
*/
typedef union {
struct {
/** rtclockcali_date : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
uint32_t rtclockcali_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} rtclockcali_date_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg_slow register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling_slow : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
uint32_t rtc_cali_start_cycling_slow:1;
/** rtc_cali_clk_sel_slow : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel_slow:2;
/** rtc_cali_rdy_slow : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
uint32_t rtc_cali_rdy_slow:1;
/** rtc_cali_max_slow : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_max_slow:15;
/** rtc_cali_start_slow : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
uint32_t rtc_cali_start_slow:1;
};
uint32_t val;
} rtclockcali_rtccalicfg_slow_reg_t;
/** Type of rtccalicfg_fast register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:4;
/** fosc_div_num : R/W; bitpos: [11:4]; default: 0;
* fosc clock divider number
*/
uint32_t fosc_div_num:8;
/** rtc_cali_start_cycling_fast : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
uint32_t rtc_cali_start_cycling_fast:1;
/** rtc_cali_clk_sel_fast : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel_fast:2;
/** rtc_cali_rdy_fast : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
uint32_t rtc_cali_rdy_fast:1;
/** rtc_cali_max_fast : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_max_fast:15;
/** rtc_cali_start_fast : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
uint32_t rtc_cali_start_fast:1;
};
uint32_t val;
} rtclockcali_rtccalicfg_fast_reg_t;
/** Type of rtccalicfg1_slow register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld_slow : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
uint32_t rtc_cali_cycling_data_vld_slow:1;
uint32_t reserved_1:6;
/** rtc_cali_value_slow : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value_slow:25;
};
uint32_t val;
} rtclockcali_rtccalicfg1_slow_reg_t;
/** Type of rtccalicfg1_fast register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld_fast : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
uint32_t rtc_cali_cycling_data_vld_fast:1;
uint32_t reserved_1:6;
/** rtc_cali_value_fast : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value_fast:25;
};
uint32_t val;
} rtclockcali_rtccalicfg1_fast_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} rtclockcali_rtccalicfg2_reg_t;
typedef struct {
volatile rtclockcali_lp_cali_timer_reg_t lp_cali_timer;
volatile rtclockcali_rtccalicfg_slow_reg_t rtccalicfg_slow;
volatile rtclockcali_rtccalicfg_fast_reg_t rtccalicfg_fast;
volatile rtclockcali_rtccalicfg1_slow_reg_t rtccalicfg1_slow;
volatile rtclockcali_rtccalicfg1_fast_reg_t rtccalicfg1_fast;
volatile rtclockcali_rtccalicfg2_reg_t rtccalicfg2;
volatile rtclockcali_dfreq_high_limit_slow_reg_t dfreq_high_limit_slow;
volatile rtclockcali_dfreq_low_limit_slow_reg_t dfreq_low_limit_slow;
volatile rtclockcali_dfreq_high_limit_fast_reg_t dfreq_high_limit_fast;
volatile rtclockcali_dfreq_low_limit_fast_reg_t dfreq_low_limit_fast;
volatile rtclockcali_dfreq_conf2_reg_t dfreq_conf2;
volatile rtclockcali_cali_en_reg_t cali_en;
volatile rtclockcali_dfreq_value_reg_t dfreq_value;
volatile rtclockcali_bypass_reg_t bypass;
volatile rtclockcali_int_raw_reg_t int_raw;
volatile rtclockcali_int_st_reg_t int_st;
volatile rtclockcali_int_ena_reg_t int_ena;
volatile rtclockcali_int_clr_reg_t int_clr;
volatile rtclockcali_timeout_reg_t timeout;
volatile rtclockcali_xtal_timeout_reg_t xtal_timeout;
uint32_t reserved_050[235];
volatile rtclockcali_date_reg_t date;
} rtclockcali_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(rtclockcali_dev_t) == 0x400, "Invalid size of rtclockcali_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
* Initial configuration register.
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* Sha mode.
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x00000007U
#define SHA_MODE_S 0
/** SHA_DMA_BLOCK_NUM_REG register
* DMA configuration register 0.
*/
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
* Dma-sha block number.
*/
#define SHA_DMA_BLOCK_NUM 0x0000003FU
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
#define SHA_DMA_BLOCK_NUM_S 0
/** SHA_START_REG register
* Typical SHA configuration register 0.
*/
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
/** SHA_START : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
#define SHA_START 0x7FFFFFFFU
#define SHA_START_M (SHA_START_V << SHA_START_S)
#define SHA_START_V 0x7FFFFFFFU
#define SHA_START_S 1
/** SHA_CONTINUE_REG register
* Typical SHA configuration register 1.
*/
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
#define SHA_CONTINUE 0x7FFFFFFFU
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
#define SHA_CONTINUE_V 0x7FFFFFFFU
#define SHA_CONTINUE_S 1
/** SHA_BUSY_REG register
* Busy register.
*/
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Sha busy state. 1'b0: idle. 1'b1: busy.
*/
#define SHA_BUSY_STATE (BIT(0))
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
#define SHA_BUSY_STATE_V 0x00000001U
#define SHA_BUSY_STATE_S 0
/** SHA_DMA_START_REG register
* DMA configuration register 1.
*/
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
* Start dma-sha.
*/
#define SHA_DMA_START (BIT(0))
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
#define SHA_DMA_START_V 0x00000001U
#define SHA_DMA_START_S 0
/** SHA_DMA_CONTINUE_REG register
* DMA configuration register 2.
*/
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue dma-sha.
*/
#define SHA_DMA_CONTINUE (BIT(0))
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
#define SHA_DMA_CONTINUE_V 0x00000001U
#define SHA_DMA_CONTINUE_S 0
/** SHA_CLEAR_IRQ_REG register
* Interrupt clear register.
*/
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Clear sha interrupt.
*/
#define SHA_CLEAR_INTERRUPT (BIT(0))
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
#define SHA_CLEAR_INTERRUPT_S 0
/** SHA_IRQ_ENA_REG register
* Interrupt enable register.
*/
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
*/
#define SHA_INTERRUPT_ENA (BIT(0))
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
#define SHA_INTERRUPT_ENA_V 0x00000001U
#define SHA_INTERRUPT_ENA_S 0
/** SHA_DATE_REG register
* Date register.
*/
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
* Sha date information/ sha version information.
*/
#define SHA_DATE 0x3FFFFFFFU
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
#define SHA_DATE_V 0x3FFFFFFFU
#define SHA_DATE_S 0
/** SHA_H_MEM register
* Sha H memory which contains intermediate hash or finial hash.
*/
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
#define SHA_H_MEM_SIZE_BYTES 64
/** SHA_M_MEM register
* Sha M memory which contains message.
*/
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
#define SHA_M_MEM_SIZE_BYTES 64
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
* Initial configuration register.
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Sha mode.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_mode_reg_t;
/** Type of dma_block_num register
* DMA configuration register 0.
*/
typedef union {
struct {
/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
* Dma-sha block number.
*/
uint32_t dma_block_num:6;
uint32_t reserved_6:26;
};
uint32_t val;
} sha_dma_block_num_reg_t;
/** Type of start register
* Typical SHA configuration register 0.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** start : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t start:31;
};
uint32_t val;
} sha_start_reg_t;
/** Type of continue register
* Typical SHA configuration register 1.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** continue : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t conti:31;
};
uint32_t val;
} sha_continue_reg_t;
/** Type of dma_start register
* DMA configuration register 1.
*/
typedef union {
struct {
/** dma_start : WO; bitpos: [0]; default: 0;
* Start dma-sha.
*/
uint32_t dma_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_start_reg_t;
/** Type of dma_continue register
* DMA configuration register 2.
*/
typedef union {
struct {
/** dma_continue : WO; bitpos: [0]; default: 0;
* Continue dma-sha.
*/
uint32_t dma_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_continue_reg_t;
/** Group: Status Register */
/** Type of busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Sha busy state. 1'b0: idle. 1'b1: busy.
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_busy_reg_t;
/** Group: Interrupt Register */
/** Type of clear_irq register
* Interrupt clear register.
*/
typedef union {
struct {
/** clear_interrupt : WO; bitpos: [0]; default: 0;
* Clear sha interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_clear_irq_reg_t;
/** Type of irq_ena register
* Interrupt enable register.
*/
typedef union {
struct {
/** interrupt_ena : R/W; bitpos: [0]; default: 0;
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
*/
uint32_t interrupt_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_irq_ena_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538972713;
* Sha date information/ sha version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} sha_date_reg_t;
/** Group: memory type */
typedef struct {
volatile sha_mode_reg_t mode;
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
volatile sha_clear_irq_reg_t clear_irq;
volatile sha_irq_ena_reg_t irq_ena;
volatile sha_date_reg_t date;
uint32_t reserved_030[4];
volatile uint32_t h[16];
volatile uint32_t m[16];
} sha_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SYSTIMER_CONF_REG register
* Configure system timer clock
*/
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
* enable systimer's etm task and event
*/
#define SYSTIMER_ETM_EN (BIT(1))
#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
#define SYSTIMER_ETM_EN_V 0x00000001U
#define SYSTIMER_ETM_EN_S 1
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET2_WORK_EN_S 22
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET1_WORK_EN_S 23
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET0_WORK_EN_S 24
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
#define SYSTIMER_CLK_EN_V 0x00000001U
#define SYSTIMER_CLK_EN_S 31
/** SYSTIMER_UNIT0_OP_REG register
* system timer unit0 value update register
*/
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
/** SYSTIMER_UNIT1_OP_REG register
* system timer unit1 value update register
*/
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
/** SYSTIMER_UNIT0_LOAD_HI_REG register
* system timer unit0 value high load register
*/
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 20 bits
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
/** SYSTIMER_UNIT0_LOAD_LO_REG register
* system timer unit0 value low load register
*/
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bits
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
/** SYSTIMER_UNIT1_LOAD_HI_REG register
* system timer unit1 value high load register
*/
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 20 bits
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
/** SYSTIMER_UNIT1_LOAD_LO_REG register
* system timer unit1 value low load register
*/
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bits
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
/** SYSTIMER_TARGET0_HI_REG register
* system timer comp0 value high register
*/
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET0_HI_S 0
/** SYSTIMER_TARGET0_LO_REG register
* system timer comp0 value low register
*/
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET0_LO_S 0
/** SYSTIMER_TARGET1_HI_REG register
* system timer comp1 value high register
*/
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET1_HI_S 0
/** SYSTIMER_TARGET1_LO_REG register
* system timer comp1 value low register
*/
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET1_LO_S 0
/** SYSTIMER_TARGET2_HI_REG register
* system timer comp2 value high register
*/
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET2_HI_S 0
/** SYSTIMER_TARGET2_LO_REG register
* system timer comp2 value low register
*/
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET2_LO_S 0
/** SYSTIMER_TARGET0_CONF_REG register
* system timer comp0 target mode register
*/
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
/** SYSTIMER_TARGET1_CONF_REG register
* system timer comp1 target mode register
*/
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
/** SYSTIMER_TARGET2_CONF_REG register
* system timer comp2 target mode register
*/
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
/** SYSTIMER_UNIT0_VALUE_HI_REG register
* system timer unit0 value high register
*/
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
/** SYSTIMER_UNIT0_VALUE_LO_REG register
* system timer unit0 value low register
*/
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
/** SYSTIMER_UNIT1_VALUE_HI_REG register
* system timer unit1 value high register
*/
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
/** SYSTIMER_UNIT1_VALUE_LO_REG register
* system timer unit1 value low register
*/
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
/** SYSTIMER_COMP0_LOAD_REG register
* system timer comp0 conf sync register
*/
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
* timer comp0 sync enable signal
*/
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
/** SYSTIMER_COMP1_LOAD_REG register
* system timer comp1 conf sync register
*/
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
* timer comp1 sync enable signal
*/
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
/** SYSTIMER_COMP2_LOAD_REG register
* system timer comp2 conf sync register
*/
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
* timer comp2 sync enable signal
*/
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
/** SYSTIMER_UNIT0_LOAD_REG register
* system timer unit0 conf sync register
*/
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
* timer unit0 sync enable signal
*/
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
/** SYSTIMER_UNIT1_LOAD_REG register
* system timer unit1 conf sync register
*/
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
* timer unit1 sync enable signal
*/
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
/** SYSTIMER_INT_ENA_REG register
* systimer interrupt enable register
*/
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET1_INT_ENA_S 1
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET2_INT_ENA_S 2
/** SYSTIMER_INT_RAW_REG register
* systimer interrupt raw register
*/
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET1_INT_RAW_S 1
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET2_INT_RAW_S 2
/** SYSTIMER_INT_CLR_REG register
* systimer interrupt clear register
*/
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET1_INT_CLR_S 1
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET2_INT_CLR_S 2
/** SYSTIMER_INT_ST_REG register
* systimer interrupt status register
*/
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
* interupt0 status
*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
* interupt1 status
*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET1_INT_ST_S 1
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
* interupt2 status
*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET2_INT_ST_S 2
/** SYSTIMER_REAL_TARGET0_LO_REG register
* system timer comp0 actual target value low register
*/
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET0_LO_RO_S 0
/** SYSTIMER_REAL_TARGET0_HI_REG register
* system timer comp0 actual target value high register
*/
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET0_HI_RO_S 0
/** SYSTIMER_REAL_TARGET1_LO_REG register
* system timer comp1 actual target value low register
*/
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET1_LO_RO_S 0
/** SYSTIMER_REAL_TARGET1_HI_REG register
* system timer comp1 actual target value high register
*/
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET1_HI_RO_S 0
/** SYSTIMER_REAL_TARGET2_LO_REG register
* system timer comp2 actual target value low register
*/
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET2_LO_RO_S 0
/** SYSTIMER_REAL_TARGET2_HI_REG register
* system timer comp2 actual target value high register
*/
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET2_HI_RO_S 0
/** SYSTIMER_DATE_REG register
* system timer version control register
*/
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
* systimer register version
*/
#define SYSTIMER_DATE 0xFFFFFFFFU
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
#define SYSTIMER_DATE_V 0xFFFFFFFFU
#define SYSTIMER_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
* Configure system timer clock
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** etm_en : R/W; bitpos: [1]; default: 0;
* enable systimer's etm task and event
*/
uint32_t etm_en:1;
uint32_t reserved_2:20;
/** target2_work_en : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
uint32_t target2_work_en:1;
/** target1_work_en : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
uint32_t target1_work_en:1;
/** target0_work_en : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
uint32_t target0_work_en:1;
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
uint32_t timer_unit1_core1_stall_en:1;
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
uint32_t timer_unit1_core0_stall_en:1;
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
uint32_t timer_unit0_core1_stall_en:1;
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
uint32_t timer_unit0_core0_stall_en:1;
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
uint32_t timer_unit1_work_en:1;
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
uint32_t timer_unit0_work_en:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
uint32_t clk_en:1;
};
uint32_t val;
} systimer_conf_reg_t;
/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */
/** Type of unit0_op register
* system timer unit0 value update register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
uint32_t timer_unit0_value_valid:1;
/** timer_unit0_update : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
uint32_t timer_unit0_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit0_op_reg_t;
/** Type of unit0_load_hi register
* system timer unit0 value high load register
*/
typedef union {
struct {
/** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 20 bits
*/
uint32_t timer_unit0_load_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit0_load_hi_reg_t;
/** Type of unit0_load_lo register
* system timer unit0 value low load register
*/
typedef union {
struct {
/** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bits
*/
uint32_t timer_unit0_load_lo:32;
};
uint32_t val;
} systimer_unit0_load_lo_reg_t;
/** Type of unit0_value_hi register
* system timer unit0 value high register
*/
typedef union {
struct {
/** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
uint32_t timer_unit0_value_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit0_value_hi_reg_t;
/** Type of unit0_value_lo register
* system timer unit0 value low register
*/
typedef union {
struct {
/** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
uint32_t timer_unit0_value_lo:32;
};
uint32_t val;
} systimer_unit0_value_lo_reg_t;
/** Type of unit0_load register
* system timer unit0 conf sync register
*/
typedef union {
struct {
/** timer_unit0_load : WT; bitpos: [0]; default: 0;
* timer unit0 sync enable signal
*/
uint32_t timer_unit0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit0_load_reg_t;
/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
/** Type of unit1_op register
* system timer unit1 value update register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
uint32_t timer_unit1_value_valid:1;
/** timer_unit1_update : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
uint32_t timer_unit1_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit1_op_reg_t;
/** Type of unit1_load_hi register
* system timer unit1 value high load register
*/
typedef union {
struct {
/** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 20 bits
*/
uint32_t timer_unit1_load_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit1_load_hi_reg_t;
/** Type of unit1_load_lo register
* system timer unit1 value low load register
*/
typedef union {
struct {
/** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bits
*/
uint32_t timer_unit1_load_lo:32;
};
uint32_t val;
} systimer_unit1_load_lo_reg_t;
/** Type of unit1_value_hi register
* system timer unit1 value high register
*/
typedef union {
struct {
/** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
uint32_t timer_unit1_value_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit1_value_hi_reg_t;
/** Type of unit1_value_lo register
* system timer unit1 value low register
*/
typedef union {
struct {
/** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
uint32_t timer_unit1_value_lo:32;
};
uint32_t val;
} systimer_unit1_value_lo_reg_t;
/** Type of unit1_load register
* system timer unit1 conf sync register
*/
typedef union {
struct {
/** timer_unit1_load : WT; bitpos: [0]; default: 0;
* timer unit1 sync enable signal
*/
uint32_t timer_unit1_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit1_load_reg_t;
/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
/** Type of target0_hi register
* system timer comp0 value high register
*/
typedef union {
struct {
/** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 20 bits
*/
uint32_t timer_target0_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target0_hi_reg_t;
/** Type of target0_lo register
* system timer comp0 value low register
*/
typedef union {
struct {
/** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bits
*/
uint32_t timer_target0_lo:32;
};
uint32_t val;
} systimer_target0_lo_reg_t;
/** Type of target0_conf register
* system timer comp0 target mode register
*/
typedef union {
struct {
/** target0_period : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
uint32_t target0_period:26;
uint32_t reserved_26:4;
/** target0_period_mode : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
uint32_t target0_period_mode:1;
/** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target0_timer_unit_sel:1;
};
uint32_t val;
} systimer_target0_conf_reg_t;
/** Type of comp0_load register
* system timer comp0 conf sync register
*/
typedef union {
struct {
/** timer_comp0_load : WT; bitpos: [0]; default: 0;
* timer comp0 sync enable signal
*/
uint32_t timer_comp0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp0_load_reg_t;
/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
/** Type of target1_hi register
* system timer comp1 value high register
*/
typedef union {
struct {
/** timer_target1_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 20 bits
*/
uint32_t timer_target1_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target1_hi_reg_t;
/** Type of target1_lo register
* system timer comp1 value low register
*/
typedef union {
struct {
/** timer_target1_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bits
*/
uint32_t timer_target1_lo:32;
};
uint32_t val;
} systimer_target1_lo_reg_t;
/** Type of target1_conf register
* system timer comp1 target mode register
*/
typedef union {
struct {
/** target1_period : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
uint32_t target1_period:26;
uint32_t reserved_26:4;
/** target1_period_mode : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
uint32_t target1_period_mode:1;
/** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target1_timer_unit_sel:1;
};
uint32_t val;
} systimer_target1_conf_reg_t;
/** Type of comp1_load register
* system timer comp1 conf sync register
*/
typedef union {
struct {
/** timer_comp1_load : WT; bitpos: [0]; default: 0;
* timer comp1 sync enable signal
*/
uint32_t timer_comp1_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp1_load_reg_t;
/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */
/** Type of target2_hi register
* system timer comp2 value high register
*/
typedef union {
struct {
/** timer_target2_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 20 bits
*/
uint32_t timer_target2_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target2_hi_reg_t;
/** Type of target2_lo register
* system timer comp2 value low register
*/
typedef union {
struct {
/** timer_target2_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bits
*/
uint32_t timer_target2_lo:32;
};
uint32_t val;
} systimer_target2_lo_reg_t;
/** Type of target2_conf register
* system timer comp2 target mode register
*/
typedef union {
struct {
/** target2_period : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
uint32_t target2_period:26;
uint32_t reserved_26:4;
/** target2_period_mode : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
uint32_t target2_period_mode:1;
/** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target2_timer_unit_sel:1;
};
uint32_t val;
} systimer_target2_conf_reg_t;
/** Type of comp2_load register
* system timer comp2 conf sync register
*/
typedef union {
struct {
/** timer_comp2_load : WT; bitpos: [0]; default: 0;
* timer comp2 sync enable signal
*/
uint32_t timer_comp2_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp2_load_reg_t;
/** Group: SYSTEM TIMER INTERRUPT REGISTER */
/** Type of int_ena register
* systimer interrupt enable register
*/
typedef union {
struct {
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
uint32_t target0_int_ena:1;
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
uint32_t target1_int_ena:1;
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
uint32_t target2_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_ena_reg_t;
/** Type of int_raw register
* systimer interrupt raw register
*/
typedef union {
struct {
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
uint32_t target0_int_raw:1;
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
uint32_t target1_int_raw:1;
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
uint32_t target2_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_raw_reg_t;
/** Type of int_clr register
* systimer interrupt clear register
*/
typedef union {
struct {
/** target0_int_clr : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
uint32_t target0_int_clr:1;
/** target1_int_clr : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
uint32_t target1_int_clr:1;
/** target2_int_clr : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
uint32_t target2_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_clr_reg_t;
/** Type of int_st register
* systimer interrupt status register
*/
typedef union {
struct {
/** target0_int_st : RO; bitpos: [0]; default: 0;
* interupt0 status
*/
uint32_t target0_int_st:1;
/** target1_int_st : RO; bitpos: [1]; default: 0;
* interupt1 status
*/
uint32_t target1_int_st:1;
/** target2_int_st : RO; bitpos: [2]; default: 0;
* interupt2 status
*/
uint32_t target2_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_st_reg_t;
/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */
/** Type of real_target0_lo register
* system timer comp0 actual target value low register
*/
typedef union {
struct {
/** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
uint32_t target0_lo_ro:32;
};
uint32_t val;
} systimer_real_target0_lo_reg_t;
/** Type of real_target0_hi register
* system timer comp0 actual target value high register
*/
typedef union {
struct {
/** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
uint32_t target0_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target0_hi_reg_t;
/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */
/** Type of real_target1_lo register
* system timer comp1 actual target value low register
*/
typedef union {
struct {
/** target1_lo_ro : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
uint32_t target1_lo_ro:32;
};
uint32_t val;
} systimer_real_target1_lo_reg_t;
/** Type of real_target1_hi register
* system timer comp1 actual target value high register
*/
typedef union {
struct {
/** target1_hi_ro : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
uint32_t target1_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target1_hi_reg_t;
/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */
/** Type of real_target2_lo register
* system timer comp2 actual target value low register
*/
typedef union {
struct {
/** target2_lo_ro : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
uint32_t target2_lo_ro:32;
};
uint32_t val;
} systimer_real_target2_lo_reg_t;
/** Type of real_target2_hi register
* system timer comp2 actual target value high register
*/
typedef union {
struct {
/** target2_hi_ro : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
uint32_t target2_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target2_hi_reg_t;
/** Group: VERSION REGISTER */
/** Type of date register
* system timer version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 35655795;
* systimer register version
*/
uint32_t date:32;
};
uint32_t val;
} systimer_date_reg_t;
typedef struct {
volatile systimer_conf_reg_t conf;
volatile systimer_unit0_op_reg_t unit0_op;
volatile systimer_unit1_op_reg_t unit1_op;
volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
volatile systimer_target0_hi_reg_t target0_hi;
volatile systimer_target0_lo_reg_t target0_lo;
volatile systimer_target1_hi_reg_t target1_hi;
volatile systimer_target1_lo_reg_t target1_lo;
volatile systimer_target2_hi_reg_t target2_hi;
volatile systimer_target2_lo_reg_t target2_lo;
volatile systimer_target0_conf_reg_t target0_conf;
volatile systimer_target1_conf_reg_t target1_conf;
volatile systimer_target2_conf_reg_t target2_conf;
volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
volatile systimer_comp0_load_reg_t comp0_load;
volatile systimer_comp1_load_reg_t comp1_load;
volatile systimer_comp2_load_reg_t comp2_load;
volatile systimer_unit0_load_reg_t unit0_load;
volatile systimer_unit1_load_reg_t unit1_load;
volatile systimer_int_ena_reg_t int_ena;
volatile systimer_int_raw_reg_t int_raw;
volatile systimer_int_clr_reg_t int_clr;
volatile systimer_int_st_reg_t int_st;
volatile systimer_real_target0_lo_reg_t real_target0_lo;
volatile systimer_real_target0_hi_reg_t real_target0_hi;
volatile systimer_real_target1_lo_reg_t real_target1_lo;
volatile systimer_real_target1_hi_reg_t real_target1_hi;
volatile systimer_real_target2_lo_reg_t real_target2_lo;
volatile systimer_real_target2_hi_reg_t real_target2_hi;
uint32_t reserved_08c[28];
volatile systimer_date_reg_t date;
} systimer_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* log config regsiter
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
* Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
* monitor
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 0
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
* enable core log
*/
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_S 8
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
* enable dma_0 log
*/
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
* enable dma_1 log
*/
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
/** MEM_MONITOR_LOG_SETTING1_REG register
* log config regsiter
*/
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
* enable dma_2 log
*/
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
* enable dma_3 log
*/
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* check data regsiter
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* check data mask register
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MEM_START_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* current writing address.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* writing address update
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* full flag status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* clock gate force on register
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* version register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36708896;
* version register
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/tcm_monitor_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
* log config regsiter
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
* Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
* monitor
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_5:3;
/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
* enable core log
*/
uint32_t log_core_ena:8;
/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
* enable dma_0 log
*/
uint32_t log_dma_0_ena:8;
/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
* enable dma_1 log
*/
uint32_t log_dma_1_ena:8;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of log_setting1 register
* log config regsiter
*/
typedef union {
struct {
/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
* enable dma_2 log
*/
uint32_t log_dma_2_ena:8;
/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
* enable dma_3 log
*/
uint32_t log_dma_3_ena:8;
uint32_t reserved_16:16;
};
uint32_t val;
} mem_monitor_log_setting1_reg_t;
/** Type of log_check_data register
* check data regsiter
*/
typedef union {
struct {
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
uint32_t log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of log_data_mask register
* check data mask register
*/
typedef union {
struct {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of log_min register
* log boundary regsiter
*/
typedef union {
struct {
/** log_min : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
uint32_t log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of log_max register
* log boundary regsiter
*/
typedef union {
struct {
/** log_max : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
uint32_t log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of log_mem_start register
* log message store range register
*/
typedef union {
struct {
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
uint32_t log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of log_mem_end register
* log message store range register
*/
typedef union {
struct {
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
uint32_t log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of log_mem_current_addr register
* current writing address.
*/
typedef union {
struct {
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
uint32_t log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of log_mem_addr_update register
* writing address update
*/
typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of log_mem_full_flag register
* full flag status register
*/
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of clock_gate register
* clock gate force on register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36708896;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_setting1_reg_t log_setting1;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
volatile mem_monitor_log_min_reg_t log_min;
volatile mem_monitor_log_max_reg_t log_max;
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_030[243];
volatile mem_monitor_date_reg_t date;
} mem_monitor_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
/** TIMG_T0HI_REG register
* Timer 0 current value, high 22 bits
*/
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
/** TIMG_T0ALARMLO_REG register
* Timer 0 alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
/** TIMG_T0ALARMHI_REG register
* Timer 0 alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
/** TIMG_T0LOADLO_REG register
* Timer 0 reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer 0 time-base
* Counter.
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
/** TIMG_T0LOADHI_REG register
* Timer 0 reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer 0 time-base counter reload.
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
/** TIMG_T1CONFIG_REG register
* Timer 1 configuration register
*/
#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24)
/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
#define TIMG_T1_ALARM_EN_V 0x00000001U
#define TIMG_T1_ALARM_EN_S 10
/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 1 's clock divider counter will be reset.
*/
#define TIMG_T1_DIVCNT_RST (BIT(12))
#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
#define TIMG_T1_DIVCNT_RST_V 0x00000001U
#define TIMG_T1_DIVCNT_RST_S 12
/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 1 clock (T1_clk) prescaler value.
*/
#define TIMG_T1_DIVIDER 0x0000FFFFU
#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
#define TIMG_T1_DIVIDER_V 0x0000FFFFU
#define TIMG_T1_DIVIDER_S 13
/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 1 auto-reload at alarm is enabled.
*/
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
#define TIMG_T1_AUTORELOAD_V 0x00000001U
#define TIMG_T1_AUTORELOAD_S 29
/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 1 time-base counter will increment every clock tick. When
* cleared, the timer 1 time-base counter will decrement.
*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
#define TIMG_T1_INCREASE_V 0x00000001U
#define TIMG_T1_INCREASE_S 30
/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer 1 time-base counter is enabled.
*/
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S)
#define TIMG_T1_EN_V 0x00000001U
#define TIMG_T1_EN_S 31
/** TIMG_T1LO_REG register
* Timer 1 current value, low 32 bits
*/
#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28)
/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
* of timer 1 can be read here.
*/
#define TIMG_T1_LO 0xFFFFFFFFU
#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S)
#define TIMG_T1_LO_V 0xFFFFFFFFU
#define TIMG_T1_LO_S 0
/** TIMG_T1HI_REG register
* Timer 1 current value, high 22 bits
*/
#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c)
/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
* of timer 1 can be read here.
*/
#define TIMG_T1_HI 0x003FFFFFU
#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S)
#define TIMG_T1_HI_V 0x003FFFFFU
#define TIMG_T1_HI_S 0
/** TIMG_T1UPDATE_REG register
* Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
*/
#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30)
/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
*/
#define TIMG_T1_UPDATE (BIT(31))
#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
#define TIMG_T1_UPDATE_V 0x00000001U
#define TIMG_T1_UPDATE_S 31
/** TIMG_T1ALARMLO_REG register
* Timer 1 alarm value, low 32 bits
*/
#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34)
/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer 1 alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T1_ALARM_LO 0xFFFFFFFFU
#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T1_ALARM_LO_S 0
/** TIMG_T1ALARMHI_REG register
* Timer 1 alarm value, high bits
*/
#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38)
/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer 1 alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T1_ALARM_HI 0x003FFFFFU
#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
#define TIMG_T1_ALARM_HI_V 0x003FFFFFU
#define TIMG_T1_ALARM_HI_S 0
/** TIMG_T1LOADLO_REG register
* Timer 1 reload value, low 32 bits
*/
#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c)
/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer 1 time-base
* Counter.
*/
#define TIMG_T1_LOAD_LO 0xFFFFFFFFU
#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T1_LOAD_LO_S 0
/** TIMG_T1LOADHI_REG register
* Timer 1 reload value, high 22 bits
*/
#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40)
/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer 1 time-base
* counter.
*/
#define TIMG_T1_LOAD_HI 0x003FFFFFU
#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
#define TIMG_T1_LOAD_HI_V 0x003FFFFFU
#define TIMG_T1_LOAD_HI_S 0
/** TIMG_T1LOAD_REG register
* Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
*/
#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44)
/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer 1 time-base counter reload.
*/
#define TIMG_T1_LOAD 0xFFFFFFFFU
#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
#define TIMG_T1_LOAD_V 0xFFFFFFFFU
#define TIMG_T1_LOAD_S 0
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
#define TIMG_T1_INT_ENA_V 0x00000001U
#define TIMG_T1_INT_ENA_S 1
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 2
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
#define TIMG_T1_INT_RAW_V 0x00000001U
#define TIMG_T1_INT_RAW_S 1
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 2
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
#define TIMG_T1_INT_ST_V 0x00000001U
#define TIMG_T1_INT_ST_S 1
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 2
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
#define TIMG_T1_INT_CLR_V 0x00000001U
#define TIMG_T1_INT_CLR_S 1
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 2
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
* Timer version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
*/
#define TIMG_ETM_EN (BIT(28))
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
#define TIMG_ETM_EN_V 0x00000001U
#define TIMG_ETM_EN_S 28
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/timers_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer x current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer x alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer x alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer x alarm trigger time-base counter value, high 22 bits.
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer x reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer x time-base
* Counter.
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer x reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer x time-base
* counter.
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer x time-base counter reload.
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
uint32_t reserved_21:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_ena:1;
/** t1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_ena:1;
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_raw:1;
/** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_raw:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_st:1;
/** t1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_st:1;
/** wdt_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_clr:1;
/** t1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t1_int_clr:1;
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
* Timer version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** etm_en : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
*/
uint32_t etm_en:1;
uint32_t reserved_29:2;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t t0config;
volatile timg_txlo_reg_t t0lo;
volatile timg_txhi_reg_t t0hi;
volatile timg_txupdate_reg_t t0update;
volatile timg_txalarmlo_reg_t t0alarmlo;
volatile timg_txalarmhi_reg_t t0alarmhi;
volatile timg_txloadlo_reg_t t0loadlo;
volatile timg_txloadhi_reg_t t0loadhi;
volatile timg_txload_reg_t t0load;
volatile timg_txconfig_reg_t t1config;
volatile timg_txlo_reg_t t1lo;
volatile timg_txhi_reg_t t1hi;
volatile timg_txupdate_reg_t t1update;
volatile timg_txalarmlo_reg_t t1alarmlo;
volatile timg_txalarmhi_reg_t t1alarmhi;
volatile timg_txloadlo_reg_t t1loadlo;
volatile timg_txloadhi_reg_t t1loadhi;
volatile timg_txload_reg_t t1load;
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif