From 983cca8b274d2fcb88063cc457bb1b20833003b9 Mon Sep 17 00:00:00 2001 From: Shu Chen Date: Thu, 10 Jun 2021 10:22:35 +0800 Subject: [PATCH] esp32h2: copy driver/hal/soc components from esp32c3 Copy the esp32c3 code without any change: * components/driver/esp32h2 * components/esp32h2 * components/hal/esp32h2 * components/soc/esp32h2 --- components/driver/esp32h2/adc.c | 717 +++ components/driver/esp32h2/adc2_init_cal.c | 31 + .../driver/esp32h2/include/driver/adc.h | 93 + .../esp32h2/include/driver/temp_sensor.h | 91 + components/driver/esp32h2/rtc_tempsensor.c | 151 + components/esp32h2/CMakeLists.txt | 66 + components/esp32h2/Kconfig | 212 + components/esp32h2/Makefile.projbuild | 1 + components/esp32h2/component.mk | 4 + components/esp32h2/dport_access.c | 25 + components/esp32h2/esp_crypto_lock.c | 83 + components/esp32h2/esp_ds.c | 232 + components/esp32h2/esp_hmac.c | 132 + .../esp32h2/include/esp32h2/dport_access.h | 42 + components/esp32h2/include/esp32h2/memprot.h | 455 ++ components/esp32h2/include/esp32h2/rtc.h | 40 + components/esp32h2/include/esp_crypto_lock.h | 76 + components/esp32h2/include/esp_ds.h | 218 + components/esp32h2/include/esp_hmac.h | 67 + components/esp32h2/ld/esp32h2.ld | 118 + components/esp32h2/ld/esp32h2.peripherals.ld | 30 + components/esp32h2/ld/esp32h2.project.ld.in | 392 ++ components/esp32h2/memprot.c | 616 +++ components/esp32h2/project_include.cmake | 5 + components/esp32h2/test/CMakeLists.txt | 9 + components/esp32h2/test/component.mk | 4 + .../test/digital_signature_test_cases.h | 166 + components/esp32h2/test/test_ds.c | 382 ++ components/esp32h2/test/test_sha.c | 80 + components/hal/esp32h2/adc_hal.c | 165 + components/hal/esp32h2/brownout_hal.c | 45 + components/hal/esp32h2/hmac_hal.c | 83 + components/hal/esp32h2/include/hal/adc_hal.h | 119 + .../hal/esp32h2/include/hal/adc_hal_conf.h | 31 + components/hal/esp32h2/include/hal/adc_ll.h | 801 +++ components/hal/esp32h2/include/hal/aes_ll.h | 235 + .../hal/esp32h2/include/hal/clk_gate_ll.h | 252 + components/hal/esp32h2/include/hal/cpu_ll.h | 161 + components/hal/esp32h2/include/hal/ds_ll.h | 175 + components/hal/esp32h2/include/hal/gdma_ll.h | 456 ++ components/hal/esp32h2/include/hal/gpio_ll.h | 586 +++ .../hal/esp32h2/include/hal/gpspi_flash_ll.h | 394 ++ components/hal/esp32h2/include/hal/hmac_hal.h | 109 + components/hal/esp32h2/include/hal/hmac_ll.h | 199 + components/hal/esp32h2/include/hal/i2c_ll.h | 914 ++++ components/hal/esp32h2/include/hal/i2s_ll.h | 912 ++++ .../include/hal/interrupt_controller_ll.h | 132 + components/hal/esp32h2/include/hal/ledc_ll.h | 518 ++ .../hal/esp32h2/include/hal/memprot_ll.h | 571 ++ components/hal/esp32h2/include/hal/mpu_ll.h | 53 + components/hal/esp32h2/include/hal/mwdt_ll.h | 254 + components/hal/esp32h2/include/hal/rmt_ll.h | 502 ++ .../hal/esp32h2/include/hal/rtc_cntl_ll.h | 67 + components/hal/esp32h2/include/hal/rwdt_ll.h | 311 ++ components/hal/esp32h2/include/hal/sha_ll.h | 157 + .../hal/esp32h2/include/hal/sigmadelta_ll.h | 73 + components/hal/esp32h2/include/hal/soc_ll.h | 52 + .../include/hal/spi_flash_encrypted_ll.h | 157 + .../hal/esp32h2/include/hal/spi_flash_ll.h | 111 + components/hal/esp32h2/include/hal/spi_ll.h | 1090 ++++ .../hal/esp32h2/include/hal/spimem_flash_ll.h | 560 ++ .../hal/esp32h2/include/hal/systimer_ll.h | 164 + components/hal/esp32h2/include/hal/timer_ll.h | 430 ++ components/hal/esp32h2/include/hal/twai_ll.h | 667 +++ components/hal/esp32h2/include/hal/uart_ll.h | 937 ++++ components/hal/esp32h2/include/hal/uhci_ll.h | 130 + .../hal/esp32h2/include/hal/uhci_types.h | 54 + .../esp32h2/include/hal/usb_serial_jtag_ll.h | 169 + components/hal/esp32h2/rtc_cntl_hal.c | 61 + components/soc/esp32h2/CMakeLists.txt | 20 + components/soc/esp32h2/adc_periph.c | 27 + components/soc/esp32h2/gdma_periph.c | 37 + components/soc/esp32h2/gpio_periph.c | 65 + components/soc/esp32h2/i2c_bbpll.h | 183 + components/soc/esp32h2/i2c_periph.c | 30 + components/soc/esp32h2/i2s_periph.c | 38 + .../soc/esp32h2/include/soc/adc_channel.h | 36 + .../soc/esp32h2/include/soc/apb_ctrl_reg.h | 576 +++ .../soc/esp32h2/include/soc/apb_ctrl_struct.h | 482 ++ .../soc/esp32h2/include/soc/apb_saradc_reg.h | 631 +++ .../esp32h2/include/soc/apb_saradc_struct.h | 490 ++ .../esp32h2/include/soc/assist_debug_reg.h | 691 +++ components/soc/esp32h2/include/soc/bb_reg.h | 37 + .../soc/esp32h2/include/soc/boot_mode.h | 101 + .../soc/esp32h2/include/soc/cache_memory.h | 100 + .../soc/esp32h2/include/soc/clkout_channel.h | 26 + .../soc/esp32h2/include/soc/dport_access.h | 111 + .../soc/esp32h2/include/soc/efuse_reg.h | 2061 ++++++++ .../soc/esp32h2/include/soc/efuse_struct.h | 514 ++ .../soc/esp32h2/include/soc/extmem_reg.h | 992 ++++ components/soc/esp32h2/include/soc/fe_reg.h | 41 + .../soc/esp32h2/include/soc/gdma_channel.h | 24 + components/soc/esp32h2/include/soc/gdma_reg.h | 2419 +++++++++ .../soc/esp32h2/include/soc/gdma_struct.h | 331 ++ .../soc/esp32h2/include/soc/gpio_pins.h | 27 + components/soc/esp32h2/include/soc/gpio_reg.h | 4588 +++++++++++++++++ .../soc/esp32h2/include/soc/gpio_sd_reg.h | 114 + .../soc/esp32h2/include/soc/gpio_sd_struct.h | 61 + .../soc/esp32h2/include/soc/gpio_sig_map.h | 184 + .../soc/esp32h2/include/soc/gpio_struct.h | 437 ++ .../soc/esp32h2/include/soc/hwcrypto_reg.h | 186 + components/soc/esp32h2/include/soc/i2c_reg.h | 1062 ++++ .../soc/esp32h2/include/soc/i2c_struct.h | 407 ++ components/soc/esp32h2/include/soc/i2s_reg.h | 1051 ++++ .../soc/esp32h2/include/soc/i2s_struct.h | 336 ++ .../esp32h2/include/soc/interrupt_core0_reg.h | 856 +++ .../soc/esp32h2/include/soc/interrupt_reg.h | 1 + .../soc/esp32h2/include/soc/io_mux_reg.h | 274 + components/soc/esp32h2/include/soc/ledc_reg.h | 1226 +++++ .../soc/esp32h2/include/soc/ledc_struct.h | 220 + components/soc/esp32h2/include/soc/mmu.h | 42 + components/soc/esp32h2/include/soc/nrx_reg.h | 55 + .../soc/esp32h2/include/soc/periph_defs.h | 120 + components/soc/esp32h2/include/soc/rmt_reg.h | 1144 ++++ .../soc/esp32h2/include/soc/rmt_struct.h | 308 ++ components/soc/esp32h2/include/soc/rtc.h | 861 ++++ .../soc/esp32h2/include/soc/rtc_cntl_reg.h | 2647 ++++++++++ .../soc/esp32h2/include/soc/rtc_cntl_struct.h | 843 +++ .../soc/esp32h2/include/soc/rtc_i2c_reg.h | 684 +++ .../soc/esp32h2/include/soc/rtc_i2c_struct.h | 227 + .../soc/esp32h2/include/soc/sensitive_reg.h | 2304 +++++++++ .../esp32h2/include/soc/sensitive_struct.h | 1912 +++++++ components/soc/esp32h2/include/soc/soc.h | 340 ++ components/soc/esp32h2/include/soc/soc_caps.h | 271 + components/soc/esp32h2/include/soc/soc_pins.h | 24 + components/soc/esp32h2/include/soc/soc_ulp.h | 0 .../soc/esp32h2/include/soc/spi_mem_reg.h | 1220 +++++ .../soc/esp32h2/include/soc/spi_mem_struct.h | 569 ++ components/soc/esp32h2/include/soc/spi_pins.h | 34 + components/soc/esp32h2/include/soc/spi_reg.h | 1443 ++++++ .../soc/esp32h2/include/soc/spi_struct.h | 381 ++ .../soc/esp32h2/include/soc/syscon_reg.h | 628 +++ .../soc/esp32h2/include/soc/syscon_struct.h | 482 ++ .../soc/esp32h2/include/soc/system_reg.h | 1050 ++++ .../soc/esp32h2/include/soc/system_struct.h | 1412 +++++ .../soc/esp32h2/include/soc/systimer_reg.h | 567 ++ .../soc/esp32h2/include/soc/systimer_struct.h | 370 ++ .../soc/esp32h2/include/soc/timer_group_reg.h | 441 ++ .../esp32h2/include/soc/timer_group_struct.h | 222 + .../soc/esp32h2/include/soc/twai_struct.h | 209 + .../soc/esp32h2/include/soc/uart_channel.h | 61 + components/soc/esp32h2/include/soc/uart_reg.h | 1258 +++++ .../soc/esp32h2/include/soc/uart_struct.h | 406 ++ components/soc/esp32h2/include/soc/uhci_reg.h | 748 +++ .../soc/esp32h2/include/soc/uhci_struct.h | 230 + .../esp32h2/include/soc/usb_serial_jtag_reg.h | 993 ++++ .../include/soc/usb_serial_jtag_struct.h | 263 + components/soc/esp32h2/include/soc/wdev_reg.h | 20 + components/soc/esp32h2/interrupts.c | 80 + components/soc/esp32h2/ledc_periph.c | 25 + components/soc/esp32h2/rmt_periph.c | 39 + components/soc/esp32h2/sigmadelta_periph.c | 33 + components/soc/esp32h2/soc_memory_layout.c | 99 + components/soc/esp32h2/spi_periph.c | 71 + components/soc/esp32h2/timer_periph.c | 28 + components/soc/esp32h2/uart_periph.c | 37 + 156 files changed, 63689 insertions(+) create mode 100644 components/driver/esp32h2/adc.c create mode 100644 components/driver/esp32h2/adc2_init_cal.c create mode 100644 components/driver/esp32h2/include/driver/adc.h create mode 100644 components/driver/esp32h2/include/driver/temp_sensor.h create mode 100644 components/driver/esp32h2/rtc_tempsensor.c create mode 100644 components/esp32h2/CMakeLists.txt create mode 100644 components/esp32h2/Kconfig create mode 100644 components/esp32h2/Makefile.projbuild create mode 100644 components/esp32h2/component.mk create mode 100644 components/esp32h2/dport_access.c create mode 100644 components/esp32h2/esp_crypto_lock.c create mode 100644 components/esp32h2/esp_ds.c create mode 100644 components/esp32h2/esp_hmac.c create mode 100644 components/esp32h2/include/esp32h2/dport_access.h create mode 100644 components/esp32h2/include/esp32h2/memprot.h create mode 100644 components/esp32h2/include/esp32h2/rtc.h create mode 100644 components/esp32h2/include/esp_crypto_lock.h create mode 100644 components/esp32h2/include/esp_ds.h create mode 100644 components/esp32h2/include/esp_hmac.h create mode 100644 components/esp32h2/ld/esp32h2.ld create mode 100644 components/esp32h2/ld/esp32h2.peripherals.ld create mode 100644 components/esp32h2/ld/esp32h2.project.ld.in create mode 100644 components/esp32h2/memprot.c create mode 100644 components/esp32h2/project_include.cmake create mode 100644 components/esp32h2/test/CMakeLists.txt create mode 100644 components/esp32h2/test/component.mk create mode 100644 components/esp32h2/test/digital_signature_test_cases.h create mode 100644 components/esp32h2/test/test_ds.c create mode 100644 components/esp32h2/test/test_sha.c create mode 100644 components/hal/esp32h2/adc_hal.c create mode 100644 components/hal/esp32h2/brownout_hal.c create mode 100644 components/hal/esp32h2/hmac_hal.c create mode 100644 components/hal/esp32h2/include/hal/adc_hal.h create mode 100644 components/hal/esp32h2/include/hal/adc_hal_conf.h create mode 100644 components/hal/esp32h2/include/hal/adc_ll.h create mode 100644 components/hal/esp32h2/include/hal/aes_ll.h create mode 100644 components/hal/esp32h2/include/hal/clk_gate_ll.h create mode 100644 components/hal/esp32h2/include/hal/cpu_ll.h create mode 100644 components/hal/esp32h2/include/hal/ds_ll.h create mode 100644 components/hal/esp32h2/include/hal/gdma_ll.h create mode 100644 components/hal/esp32h2/include/hal/gpio_ll.h create mode 100644 components/hal/esp32h2/include/hal/gpspi_flash_ll.h create mode 100644 components/hal/esp32h2/include/hal/hmac_hal.h create mode 100644 components/hal/esp32h2/include/hal/hmac_ll.h create mode 100644 components/hal/esp32h2/include/hal/i2c_ll.h create mode 100644 components/hal/esp32h2/include/hal/i2s_ll.h create mode 100644 components/hal/esp32h2/include/hal/interrupt_controller_ll.h create mode 100644 components/hal/esp32h2/include/hal/ledc_ll.h create mode 100644 components/hal/esp32h2/include/hal/memprot_ll.h create mode 100644 components/hal/esp32h2/include/hal/mpu_ll.h create mode 100644 components/hal/esp32h2/include/hal/mwdt_ll.h create mode 100644 components/hal/esp32h2/include/hal/rmt_ll.h create mode 100644 components/hal/esp32h2/include/hal/rtc_cntl_ll.h create mode 100644 components/hal/esp32h2/include/hal/rwdt_ll.h create mode 100644 components/hal/esp32h2/include/hal/sha_ll.h create mode 100644 components/hal/esp32h2/include/hal/sigmadelta_ll.h create mode 100644 components/hal/esp32h2/include/hal/soc_ll.h create mode 100644 components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h create mode 100644 components/hal/esp32h2/include/hal/spi_flash_ll.h create mode 100644 components/hal/esp32h2/include/hal/spi_ll.h create mode 100644 components/hal/esp32h2/include/hal/spimem_flash_ll.h create mode 100644 components/hal/esp32h2/include/hal/systimer_ll.h create mode 100644 components/hal/esp32h2/include/hal/timer_ll.h create mode 100644 components/hal/esp32h2/include/hal/twai_ll.h create mode 100644 components/hal/esp32h2/include/hal/uart_ll.h create mode 100644 components/hal/esp32h2/include/hal/uhci_ll.h create mode 100644 components/hal/esp32h2/include/hal/uhci_types.h create mode 100644 components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h create mode 100644 components/hal/esp32h2/rtc_cntl_hal.c create mode 100644 components/soc/esp32h2/CMakeLists.txt create mode 100644 components/soc/esp32h2/adc_periph.c create mode 100644 components/soc/esp32h2/gdma_periph.c create mode 100644 components/soc/esp32h2/gpio_periph.c create mode 100644 components/soc/esp32h2/i2c_bbpll.h create mode 100644 components/soc/esp32h2/i2c_periph.c create mode 100644 components/soc/esp32h2/i2s_periph.c create mode 100644 components/soc/esp32h2/include/soc/adc_channel.h create mode 100644 components/soc/esp32h2/include/soc/apb_ctrl_reg.h create mode 100644 components/soc/esp32h2/include/soc/apb_ctrl_struct.h create mode 100644 components/soc/esp32h2/include/soc/apb_saradc_reg.h create mode 100644 components/soc/esp32h2/include/soc/apb_saradc_struct.h create mode 100644 components/soc/esp32h2/include/soc/assist_debug_reg.h create mode 100644 components/soc/esp32h2/include/soc/bb_reg.h create mode 100644 components/soc/esp32h2/include/soc/boot_mode.h create mode 100644 components/soc/esp32h2/include/soc/cache_memory.h create mode 100644 components/soc/esp32h2/include/soc/clkout_channel.h create mode 100644 components/soc/esp32h2/include/soc/dport_access.h create mode 100644 components/soc/esp32h2/include/soc/efuse_reg.h create mode 100644 components/soc/esp32h2/include/soc/efuse_struct.h create mode 100644 components/soc/esp32h2/include/soc/extmem_reg.h create mode 100644 components/soc/esp32h2/include/soc/fe_reg.h create mode 100644 components/soc/esp32h2/include/soc/gdma_channel.h create mode 100644 components/soc/esp32h2/include/soc/gdma_reg.h create mode 100644 components/soc/esp32h2/include/soc/gdma_struct.h create mode 100644 components/soc/esp32h2/include/soc/gpio_pins.h create mode 100644 components/soc/esp32h2/include/soc/gpio_reg.h create mode 100644 components/soc/esp32h2/include/soc/gpio_sd_reg.h create mode 100644 components/soc/esp32h2/include/soc/gpio_sd_struct.h create mode 100644 components/soc/esp32h2/include/soc/gpio_sig_map.h create mode 100644 components/soc/esp32h2/include/soc/gpio_struct.h create mode 100644 components/soc/esp32h2/include/soc/hwcrypto_reg.h create mode 100644 components/soc/esp32h2/include/soc/i2c_reg.h create mode 100644 components/soc/esp32h2/include/soc/i2c_struct.h create mode 100644 components/soc/esp32h2/include/soc/i2s_reg.h create mode 100644 components/soc/esp32h2/include/soc/i2s_struct.h create mode 100644 components/soc/esp32h2/include/soc/interrupt_core0_reg.h create mode 100644 components/soc/esp32h2/include/soc/interrupt_reg.h create mode 100644 components/soc/esp32h2/include/soc/io_mux_reg.h create mode 100644 components/soc/esp32h2/include/soc/ledc_reg.h create mode 100644 components/soc/esp32h2/include/soc/ledc_struct.h create mode 100644 components/soc/esp32h2/include/soc/mmu.h create mode 100644 components/soc/esp32h2/include/soc/nrx_reg.h create mode 100644 components/soc/esp32h2/include/soc/periph_defs.h create mode 100644 components/soc/esp32h2/include/soc/rmt_reg.h create mode 100644 components/soc/esp32h2/include/soc/rmt_struct.h create mode 100644 components/soc/esp32h2/include/soc/rtc.h create mode 100644 components/soc/esp32h2/include/soc/rtc_cntl_reg.h create mode 100644 components/soc/esp32h2/include/soc/rtc_cntl_struct.h create mode 100644 components/soc/esp32h2/include/soc/rtc_i2c_reg.h create mode 100644 components/soc/esp32h2/include/soc/rtc_i2c_struct.h create mode 100644 components/soc/esp32h2/include/soc/sensitive_reg.h create mode 100644 components/soc/esp32h2/include/soc/sensitive_struct.h create mode 100644 components/soc/esp32h2/include/soc/soc.h create mode 100644 components/soc/esp32h2/include/soc/soc_caps.h create mode 100644 components/soc/esp32h2/include/soc/soc_pins.h create mode 100644 components/soc/esp32h2/include/soc/soc_ulp.h create mode 100644 components/soc/esp32h2/include/soc/spi_mem_reg.h create mode 100644 components/soc/esp32h2/include/soc/spi_mem_struct.h create mode 100644 components/soc/esp32h2/include/soc/spi_pins.h create mode 100644 components/soc/esp32h2/include/soc/spi_reg.h create mode 100644 components/soc/esp32h2/include/soc/spi_struct.h create mode 100644 components/soc/esp32h2/include/soc/syscon_reg.h create mode 100644 components/soc/esp32h2/include/soc/syscon_struct.h create mode 100644 components/soc/esp32h2/include/soc/system_reg.h create mode 100644 components/soc/esp32h2/include/soc/system_struct.h create mode 100644 components/soc/esp32h2/include/soc/systimer_reg.h create mode 100644 components/soc/esp32h2/include/soc/systimer_struct.h create mode 100644 components/soc/esp32h2/include/soc/timer_group_reg.h create mode 100644 components/soc/esp32h2/include/soc/timer_group_struct.h create mode 100644 components/soc/esp32h2/include/soc/twai_struct.h create mode 100644 components/soc/esp32h2/include/soc/uart_channel.h create mode 100644 components/soc/esp32h2/include/soc/uart_reg.h create mode 100644 components/soc/esp32h2/include/soc/uart_struct.h create mode 100644 components/soc/esp32h2/include/soc/uhci_reg.h create mode 100644 components/soc/esp32h2/include/soc/uhci_struct.h create mode 100644 components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h create mode 100644 components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h create mode 100644 components/soc/esp32h2/include/soc/wdev_reg.h create mode 100644 components/soc/esp32h2/interrupts.c create mode 100644 components/soc/esp32h2/ledc_periph.c create mode 100644 components/soc/esp32h2/rmt_periph.c create mode 100644 components/soc/esp32h2/sigmadelta_periph.c create mode 100644 components/soc/esp32h2/soc_memory_layout.c create mode 100644 components/soc/esp32h2/spi_periph.c create mode 100644 components/soc/esp32h2/timer_periph.c create mode 100644 components/soc/esp32h2/uart_periph.c diff --git a/components/driver/esp32h2/adc.c b/components/driver/esp32h2/adc.c new file mode 100644 index 0000000000..693810da4a --- /dev/null +++ b/components/driver/esp32h2/adc.c @@ -0,0 +1,717 @@ +/* + * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp_intr_alloc.h" +#include "esp_log.h" +#include "esp_pm.h" +#include "sys/lock.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/timers.h" +#include "freertos/ringbuf.h" +#include "esp32c3/rom/ets_sys.h" +#include "driver/periph_ctrl.h" +#include "driver/gpio.h" +#include "driver/adc.h" +#include "hal/adc_types.h" +#include "hal/adc_hal.h" +#include "hal/dma_types.h" +#include "esp_efuse_rtc_calib.h" +#include "esp_private/gdma.h" + +#define ADC_CHECK_RET(fun_ret) ({ \ + if (fun_ret != ESP_OK) { \ + ESP_LOGE(ADC_TAG,"%s(%d)",__FUNCTION__,__LINE__); \ + return ESP_FAIL; \ + } \ +}) + +static const char *ADC_TAG = "ADC"; + +#define ADC_CHECK(a, str, ret_val) ({ \ + if (!(a)) { \ + ESP_LOGE(ADC_TAG,"%s(%d) :%s", __FUNCTION__, __LINE__, str); \ + return (ret_val); \ + } \ +}) + +#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel]) + +#define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG) + +extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished. +#define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock) +#define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock) + +/** + * 1. sar_adc1_lock: this mutex lock is to protect the SARADC1 module. + * 2. sar_adc2_lock: this mutex lock is to protect the SARADC2 module. On C3, it is controlled by the digital controller + * and PWDET controller. + * 3. adc_reg_lock: this spin lock is to protect the shared registers used by ADC1 / ADC2 single read mode. + */ +static _lock_t sar_adc1_lock; +#define SAR_ADC1_LOCK_ACQUIRE() _lock_acquire(&sar_adc1_lock) +#define SAR_ADC1_LOCK_RELEASE() _lock_release(&sar_adc1_lock) +static _lock_t sar_adc2_lock; +#define SAR_ADC2_LOCK_ACQUIRE() _lock_acquire(&sar_adc2_lock) +#define SAR_ADC2_LOCK_RELEASE() _lock_release(&sar_adc2_lock) +portMUX_TYPE adc_reg_lock = portMUX_INITIALIZER_UNLOCKED; +#define ADC_REG_LOCK_ENTER() portENTER_CRITICAL(&adc_reg_lock) +#define ADC_REG_LOCK_EXIT() portEXIT_CRITICAL(&adc_reg_lock) + +#define INTERNAL_BUF_NUM 5 +#define IN_SUC_EOF_BIT GDMA_LL_EVENT_RX_SUC_EOF + +/*--------------------------------------------------------------- + Digital Controller Context +---------------------------------------------------------------*/ +typedef struct adc_digi_context_t { + uint8_t *rx_dma_buf; //dma buffer + adc_hal_context_t hal; //hal context + gdma_channel_handle_t rx_dma_channel; //dma rx channel handle + RingbufHandle_t ringbuf_hdl; //RX ringbuffer handler + intptr_t rx_eof_desc_addr; //eof descriptor address of RX channel + bool ringbuf_overflow_flag; //1: ringbuffer overflow + bool driver_start_flag; //1: driver is started; 0: driver is stoped + bool use_adc1; //1: ADC unit1 will be used; 0: ADC unit1 won't be used. + bool use_adc2; //1: ADC unit2 will be used; 0: ADC unit2 won't be used. This determines whether to acquire sar_adc2_mutex lock or not. + adc_atten_t adc1_atten; //Attenuation for ADC1. On this chip each ADC can only support one attenuation. + adc_atten_t adc2_atten; //Attenuation for ADC2. On this chip each ADC can only support one attenuation. + adc_digi_config_t digi_controller_config; //Digital Controller Configuration + esp_pm_lock_handle_t pm_lock; //For power management +} adc_digi_context_t; + +static adc_digi_context_t *s_adc_digi_ctx = NULL; + +static uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan, adc_atten_t atten); + +/*--------------------------------------------------------------- + ADC Continuous Read Mode (via DMA) +---------------------------------------------------------------*/ +static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); + +static int8_t adc_digi_get_io_num(uint8_t adc_unit, uint8_t adc_channel) +{ + return adc_channel_io_map[adc_unit][adc_channel]; +} + +static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask) +{ + esp_err_t ret = ESP_OK; + uint64_t gpio_mask = 0; + uint32_t n = 0; + int8_t io = 0; + + while (channel_mask) { + if (channel_mask & 0x1) { + io = adc_digi_get_io_num(adc_unit, n); + if (io < 0) { + return ESP_ERR_INVALID_ARG; + } + gpio_mask |= BIT64(io); + } + channel_mask = channel_mask >> 1; + n++; + } + + gpio_config_t cfg = { + .pin_bit_mask = gpio_mask, + .mode = GPIO_MODE_DISABLE, + }; + ret = gpio_config(&cfg); + + return ret; +} + +esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) +{ + esp_err_t ret = ESP_OK; + + s_adc_digi_ctx = calloc(1, sizeof(adc_digi_context_t)); + if (s_adc_digi_ctx == NULL) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + + //ringbuffer + s_adc_digi_ctx->ringbuf_hdl = xRingbufferCreate(init_config->max_store_buf_size, RINGBUF_TYPE_BYTEBUF); + if (!s_adc_digi_ctx->ringbuf_hdl) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + + //malloc internal buffer used by DMA + s_adc_digi_ctx->rx_dma_buf = heap_caps_calloc(1, init_config->conv_num_each_intr * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL); + if (!s_adc_digi_ctx->rx_dma_buf) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + + //malloc dma descriptor + s_adc_digi_ctx->hal.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * INTERNAL_BUF_NUM, MALLOC_CAP_DMA); + if (!s_adc_digi_ctx->hal.rx_desc) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + + //malloc pattern table + s_adc_digi_ctx->digi_controller_config.adc_pattern = calloc(1, SOC_ADC_PATT_LEN_MAX * sizeof(adc_digi_pattern_table_t)); + if (!s_adc_digi_ctx->digi_controller_config.adc_pattern) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + +#if CONFIG_PM_ENABLE + ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc_dma", &s_adc_digi_ctx->pm_lock); + if (ret != ESP_OK) { + goto cleanup; + } +#endif //CONFIG_PM_ENABLE + + //init gpio pins + if (init_config->adc1_chan_mask) { + ret = adc_digi_gpio_init(ADC_NUM_1, init_config->adc1_chan_mask); + if (ret != ESP_OK) { + goto cleanup; + } + } + if (init_config->adc2_chan_mask) { + ret = adc_digi_gpio_init(ADC_NUM_2, init_config->adc2_chan_mask); + if (ret != ESP_OK) { + goto cleanup; + } + } + + //alloc rx gdma channel + gdma_channel_alloc_config_t rx_alloc_config = { + .direction = GDMA_CHANNEL_DIRECTION_RX, + }; + ret = gdma_new_channel(&rx_alloc_config, &s_adc_digi_ctx->rx_dma_channel); + if (ret != ESP_OK) { + goto cleanup; + } + gdma_connect(s_adc_digi_ctx->rx_dma_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_ADC, 0)); + + gdma_strategy_config_t strategy_config = { + .auto_update_desc = true, + .owner_check = true + }; + gdma_apply_strategy(s_adc_digi_ctx->rx_dma_channel, &strategy_config); + + gdma_rx_event_callbacks_t cbs = { + .on_recv_eof = adc_dma_in_suc_eof_callback + }; + gdma_register_rx_event_callbacks(s_adc_digi_ctx->rx_dma_channel, &cbs, s_adc_digi_ctx); + + int dma_chan; + gdma_get_channel_id(s_adc_digi_ctx->rx_dma_channel, &dma_chan); + + adc_hal_config_t config = { + .desc_max_num = INTERNAL_BUF_NUM, + .dma_chan = dma_chan, + .eof_num = init_config->conv_num_each_intr / ADC_HAL_DATA_LEN_PER_CONV + }; + adc_hal_context_config(&s_adc_digi_ctx->hal, &config); + + //enable SARADC module clock + periph_module_enable(PERIPH_SARADC_MODULE); + + adc_hal_calibration_init(ADC_NUM_1); + adc_hal_calibration_init(ADC_NUM_2); + + return ret; + +cleanup: + adc_digi_deinitialize(); + return ret; + +} + +static IRAM_ATTR bool adc_dma_intr(adc_digi_context_t *adc_digi_ctx); + +static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +{ + assert(event_data); + adc_digi_context_t *adc_digi_ctx = (adc_digi_context_t *)user_data; + adc_digi_ctx->rx_eof_desc_addr = event_data->rx_eof_desc_addr; + return adc_dma_intr(adc_digi_ctx); +} + +static IRAM_ATTR bool adc_dma_intr(adc_digi_context_t *adc_digi_ctx) +{ + portBASE_TYPE taskAwoken = 0; + BaseType_t ret; + adc_hal_dma_desc_status_t status = false; + dma_descriptor_t *current_desc = NULL; + + while (1) { + status = adc_hal_get_reading_result(&adc_digi_ctx->hal, adc_digi_ctx->rx_eof_desc_addr, ¤t_desc); + if (status != ADC_HAL_DMA_DESC_VALID) { + break; + } + + ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, current_desc->buffer, current_desc->dw0.length, &taskAwoken); + if (ret == pdFALSE) { + //ringbuffer overflow + adc_digi_ctx->ringbuf_overflow_flag = 1; + } + } + + if (status == ADC_HAL_DMA_DESC_NULL) { + //start next turns of dma operation + adc_hal_digi_rxdma_start(&adc_digi_ctx->hal, adc_digi_ctx->rx_dma_buf); + } + + return (taskAwoken == pdTRUE); +} + +esp_err_t adc_digi_start(void) +{ + if (s_adc_digi_ctx->driver_start_flag != 0) { + ESP_LOGE(ADC_TAG, "The driver is already started"); + return ESP_ERR_INVALID_STATE; + } + adc_power_acquire(); + //reset flags + s_adc_digi_ctx->ringbuf_overflow_flag = 0; + s_adc_digi_ctx->driver_start_flag = 1; + if (s_adc_digi_ctx->use_adc1) { + SAR_ADC1_LOCK_ACQUIRE(); + } + if (s_adc_digi_ctx->use_adc2) { + SAR_ADC2_LOCK_ACQUIRE(); + } + +#if CONFIG_PM_ENABLE + // Lock APB frequency while ADC driver is in use + esp_pm_lock_acquire(s_adc_digi_ctx->pm_lock); +#endif + + adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); + if (s_adc_digi_ctx->use_adc1) { + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc1_atten); + adc_hal_set_calibration_param(ADC_NUM_1, cal_val); + } + if (s_adc_digi_ctx->use_adc2) { + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc2_atten); + adc_hal_set_calibration_param(ADC_NUM_2, cal_val); + } + + adc_hal_init(); + adc_hal_arbiter_config(&config); + adc_hal_digi_init(&s_adc_digi_ctx->hal); + adc_hal_digi_controller_config(&s_adc_digi_ctx->digi_controller_config); + + //reset ADC and DMA + adc_hal_fifo_reset(&s_adc_digi_ctx->hal); + //start DMA + adc_hal_digi_rxdma_start(&s_adc_digi_ctx->hal, s_adc_digi_ctx->rx_dma_buf); + //start ADC + adc_hal_digi_start(&s_adc_digi_ctx->hal); + + return ESP_OK; +} + +esp_err_t adc_digi_stop(void) +{ + if (s_adc_digi_ctx->driver_start_flag != 1) { + ESP_LOGE(ADC_TAG, "The driver is already stopped"); + return ESP_ERR_INVALID_STATE; + } + s_adc_digi_ctx->driver_start_flag = 0; + + //disable the in suc eof intrrupt + adc_hal_digi_dis_intr(&s_adc_digi_ctx->hal, IN_SUC_EOF_BIT); + //clear the in suc eof interrupt + adc_hal_digi_clr_intr(&s_adc_digi_ctx->hal, IN_SUC_EOF_BIT); + //stop ADC + adc_hal_digi_stop(&s_adc_digi_ctx->hal); + //stop DMA + adc_hal_digi_rxdma_stop(&s_adc_digi_ctx->hal); + adc_hal_digi_deinit(); +#if CONFIG_PM_ENABLE + if (s_adc_digi_ctx->pm_lock) { + esp_pm_lock_release(s_adc_digi_ctx->pm_lock); + } +#endif //CONFIG_PM_ENABLE + + if (s_adc_digi_ctx->use_adc1) { + SAR_ADC1_LOCK_RELEASE(); + } + if (s_adc_digi_ctx->use_adc2) { + SAR_ADC2_LOCK_RELEASE(); + } + adc_power_release(); + + return ESP_OK; +} + +esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_length, uint32_t timeout_ms) +{ + TickType_t ticks_to_wait; + esp_err_t ret = ESP_OK; + uint8_t *data = NULL; + size_t size = 0; + + ticks_to_wait = timeout_ms / portTICK_RATE_MS; + if (timeout_ms == ADC_MAX_DELAY) { + ticks_to_wait = portMAX_DELAY; + } + + data = xRingbufferReceiveUpTo(s_adc_digi_ctx->ringbuf_hdl, &size, ticks_to_wait, length_max); + if (!data) { + ESP_LOGV(ADC_TAG, "No data, increase timeout or reduce conv_num_each_intr"); + ret = ESP_ERR_TIMEOUT; + *out_length = 0; + return ret; + } + + memcpy(buf, data, size); + vRingbufferReturnItem(s_adc_digi_ctx->ringbuf_hdl, data); + assert((size % 4) == 0); + *out_length = size; + + if (s_adc_digi_ctx->ringbuf_overflow_flag) { + ret = ESP_ERR_INVALID_STATE; + } + + return ret; +} + +esp_err_t adc_digi_deinitialize(void) +{ + if (!s_adc_digi_ctx) { + return ESP_ERR_INVALID_STATE; + } + + if (s_adc_digi_ctx->driver_start_flag != 0) { + ESP_LOGE(ADC_TAG, "The driver is not stopped"); + return ESP_ERR_INVALID_STATE; + } + + if (s_adc_digi_ctx->ringbuf_hdl) { + vRingbufferDelete(s_adc_digi_ctx->ringbuf_hdl); + s_adc_digi_ctx->ringbuf_hdl = NULL; + } + +#if CONFIG_PM_ENABLE + if (s_adc_digi_ctx->pm_lock) { + esp_pm_lock_delete(s_adc_digi_ctx->pm_lock); + } +#endif //CONFIG_PM_ENABLE + + free(s_adc_digi_ctx->rx_dma_buf); + free(s_adc_digi_ctx->hal.rx_desc); + free(s_adc_digi_ctx->digi_controller_config.adc_pattern); + gdma_disconnect(s_adc_digi_ctx->rx_dma_channel); + gdma_del_channel(s_adc_digi_ctx->rx_dma_channel); + + free(s_adc_digi_ctx); + s_adc_digi_ctx = NULL; + + periph_module_disable(PERIPH_SARADC_MODULE); + + return ESP_OK; +} + +/*--------------------------------------------------------------- + ADC Single Read Mode +---------------------------------------------------------------*/ +static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC1, used by single read API +static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC2, used by single read API + +esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio) +{ + esp_err_t ret; + uint32_t channel = ADC2_CHANNEL_MAX; + if (adc_unit == ADC_UNIT_2) { + for (int i = 0; i < ADC2_CHANNEL_MAX; i++) { + if (gpio == ADC_GET_IO_NUM(ADC_NUM_2, i)) { + channel = i; + break; + } + } + if (channel == ADC2_CHANNEL_MAX) { + return ESP_ERR_INVALID_ARG; + } + } + + adc_power_acquire(); + if (adc_unit & ADC_UNIT_1) { + ADC_ENTER_CRITICAL(); + adc_hal_vref_output(ADC_NUM_1, channel, true); + ADC_EXIT_CRITICAL() + } else if (adc_unit & ADC_UNIT_2) { + ADC_ENTER_CRITICAL(); + adc_hal_vref_output(ADC_NUM_2, channel, true); + ADC_EXIT_CRITICAL() + } + + ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel)); + + return ret; +} + +esp_err_t adc1_config_width(adc_bits_width_t width_bit) +{ + //On ESP32C3, the data width is always 12-bits. + if (width_bit != ADC_WIDTH_BIT_12) { + return ESP_ERR_INVALID_ARG; + } + + return ESP_OK; +} + +esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) +{ + ADC_CHANNEL_CHECK(ADC_NUM_1, channel); + ADC_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG); + + esp_err_t ret = ESP_OK; + s_atten1_single[channel] = atten; + ret = adc_digi_gpio_init(ADC_NUM_1, BIT(channel)); + + adc_hal_calibration_init(ADC_NUM_1); + + return ret; +} + +int adc1_get_raw(adc1_channel_t channel) +{ + int raw_out = 0; + + periph_module_enable(PERIPH_SARADC_MODULE); + adc_power_acquire(); + + SAR_ADC1_LOCK_ACQUIRE(); + + adc_atten_t atten = s_atten1_single[channel]; + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, channel, atten); + adc_hal_set_calibration_param(ADC_NUM_1, cal_val); + + ADC_REG_LOCK_ENTER(); + adc_hal_set_atten(ADC_NUM_2, channel, atten); + adc_hal_convert(ADC_NUM_1, channel, &raw_out); + ADC_REG_LOCK_EXIT(); + + SAR_ADC1_LOCK_RELEASE(); + + adc_power_release(); + periph_module_disable(PERIPH_SARADC_MODULE); + + return raw_out; +} + +esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) +{ + ADC_CHANNEL_CHECK(ADC_NUM_2, channel); + ADC_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG); + + esp_err_t ret = ESP_OK; + s_atten2_single[channel] = atten; + ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel)); + + adc_hal_calibration_init(ADC_NUM_2); + + return ret; +} + +esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out) +{ + //On ESP32C3, the data width is always 12-bits. + if (width_bit != ADC_WIDTH_BIT_12) { + return ESP_ERR_INVALID_ARG; + } + + esp_err_t ret = ESP_OK; + + periph_module_enable(PERIPH_SARADC_MODULE); + adc_power_acquire(); + + SAR_ADC2_LOCK_ACQUIRE(); + + adc_atten_t atten = s_atten2_single[channel]; + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten); + adc_hal_set_calibration_param(ADC_NUM_2, cal_val); + + ADC_REG_LOCK_ENTER(); + adc_hal_set_atten(ADC_NUM_2, channel, atten); + ret = adc_hal_convert(ADC_NUM_2, channel, raw_out); + ADC_REG_LOCK_EXIT(); + + SAR_ADC2_LOCK_RELEASE(); + + adc_power_release(); + periph_module_disable(PERIPH_SARADC_MODULE); + + return ret; +} + + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ +esp_err_t adc_digi_controller_config(const adc_digi_config_t *config) +{ + if (!s_adc_digi_ctx) { + return ESP_ERR_INVALID_STATE; + } + ADC_CHECK(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, "ADC sampling frequency out of range", ESP_ERR_INVALID_ARG); + + s_adc_digi_ctx->digi_controller_config.conv_limit_en = config->conv_limit_en; + s_adc_digi_ctx->digi_controller_config.conv_limit_num = config->conv_limit_num; + s_adc_digi_ctx->digi_controller_config.adc_pattern_len = config->adc_pattern_len; + s_adc_digi_ctx->digi_controller_config.sample_freq_hz = config->sample_freq_hz; + memcpy(s_adc_digi_ctx->digi_controller_config.adc_pattern, config->adc_pattern, config->adc_pattern_len * sizeof(adc_digi_pattern_table_t)); + + const int atten_uninitialised = 999; + s_adc_digi_ctx->adc1_atten = atten_uninitialised; + s_adc_digi_ctx->adc2_atten = atten_uninitialised; + s_adc_digi_ctx->use_adc1 = 0; + s_adc_digi_ctx->use_adc2 = 0; + for (int i = 0; i < config->adc_pattern_len; i++) { + const adc_digi_pattern_table_t *pat = &config->adc_pattern[i]; + if (pat->unit == ADC_NUM_1) { + s_adc_digi_ctx->use_adc1 = 1; + + if (s_adc_digi_ctx->adc1_atten == atten_uninitialised) { + s_adc_digi_ctx->adc1_atten = pat->atten; + } else if (s_adc_digi_ctx->adc1_atten != pat->atten) { + return ESP_ERR_INVALID_ARG; + } + } else if (pat->unit == ADC_NUM_2) { + //See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver + s_adc_digi_ctx->use_adc2 = 1; + + if (s_adc_digi_ctx->adc2_atten == atten_uninitialised) { + s_adc_digi_ctx->adc2_atten = pat->atten; + } else if (s_adc_digi_ctx->adc2_atten != pat->atten) { + return ESP_ERR_INVALID_ARG; + } + } + } + + return ESP_OK; +} + +/*************************************/ +/* Digital controller filter setting */ +/*************************************/ + +esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx) +{ + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_reset(idx); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} + +esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config) +{ + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_set_factor(idx, config); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} + +esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config) +{ + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_get_factor(idx, config); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} + +esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable) +{ + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_enable(idx, enable); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} + +/**************************************/ +/* Digital controller monitor setting */ +/**************************************/ + +esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config) +{ + ADC_ENTER_CRITICAL(); + adc_hal_digi_monitor_config(idx, config); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} + +esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable) +{ + + ADC_ENTER_CRITICAL(); + adc_hal_digi_monitor_enable(idx, enable); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} + +/*--------------------------------------------------------------- + RTC controller setting +---------------------------------------------------------------*/ + +static uint16_t s_adc_cali_param[ADC_UNIT_MAX][ADC_ATTEN_MAX] = {}; + +//NOTE: according to calibration version, different types of lock may be taken during the process: +// 1. Semaphore when reading efuse +// 2. Lock (Spinlock, or Mutex) if we actually do ADC calibration in the future +//This function shoudn't be called inside critical section or ISR +static uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + const bool no_cal = false; + if (s_adc_cali_param[adc_n][atten]) { + return (uint32_t)s_adc_cali_param[adc_n][atten]; + } + + if (no_cal) { + return 0; //indicating failure + } + + // check if we can fetch the values from eFuse. + int version = esp_efuse_rtc_calib_get_ver(); + + uint32_t init_code = 0; + if (version == 1) { + //for calibration v1, both ADC units use the same init code (calibrated by ADC1) + init_code = esp_efuse_rtc_calib_get_init_code(version, atten); + ESP_LOGD(ADC_TAG, "Calib(V%d) ADC0, 1 atten=%d: %04X", version, atten, init_code); + s_adc_cali_param[0][atten] = init_code; + s_adc_cali_param[1][atten] = init_code; + } else { + adc_power_acquire(); + ADC_ENTER_CRITICAL(); + const bool internal_gnd = true; + init_code = adc_hal_self_calibration(adc_n, channel, atten, internal_gnd); + ADC_EXIT_CRITICAL(); + adc_power_release(); + + ESP_LOGD(ADC_TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n, atten, init_code); + s_adc_cali_param[adc_n][atten] = init_code; + } + + return init_code; +} + +// Internal function to calibrate PWDET for WiFi +esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + adc_hal_calibration_init(adc_n); + uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten); + ADC_ENTER_CRITICAL(); + adc_hal_set_calibration_param(adc_n, cal_val); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} diff --git a/components/driver/esp32h2/adc2_init_cal.c b/components/driver/esp32h2/adc2_init_cal.c new file mode 100644 index 0000000000..351e795024 --- /dev/null +++ b/components/driver/esp32h2/adc2_init_cal.c @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is used to get `adc2_init_code_calibration` executed before the APP when the ADC2 is used by Wi-Fi or other drivers. +The linker will link constructor (adc2_init_code_calibration) only when any sections inside the same file (adc2_cal_include) is used. +Don't put any other code into this file. */ + +#include "adc2_wifi_private.h" +#include "hal/adc_hal.h" +#include "esp_private/adc_cali.h" + +/** + * @brief Set initial code to ADC2 after calibration. ADC2 RTC and ADC2 PWDET controller share the initial code. + * This API be called in before `app_main()`. + */ +static __attribute__((constructor)) void adc2_init_code_calibration(void) +{ + const adc_ll_num_t adc_n = ADC_NUM_2; + const adc_atten_t atten = ADC_ATTEN_DB_11; + const adc_channel_t channel = 0; + adc_cal_offset(adc_n, channel, atten); +} + +/** Don't call `adc2_cal_include` in user code. */ +void adc2_cal_include(void) +{ + /* When this empty function is called, the `adc2_init_code_calibration` constructor will be linked and executed before the app.*/ +} diff --git a/components/driver/esp32h2/include/driver/adc.h b/components/driver/esp32h2/include/driver/adc.h new file mode 100644 index 0000000000..7567c7b2a1 --- /dev/null +++ b/components/driver/esp32h2/include/driver/adc.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "driver/adc_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ +/*************************************/ +/* Digital controller filter setting */ +/*************************************/ +/** + * @brief Reset adc digital controller filter. + * + * @param idx Filter index. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx); + +/** + * @brief Set adc digital controller filter configuration. + * + * @param idx Filter index. + * @param config See ``adc_digi_filter_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config); + +/** + * @brief Get adc digital controller filter configuration. + * + * @param idx Filter index. + * @param config See ``adc_digi_filter_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config); + +/** + * @brief Enable/disable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @param idx Filter index. + * @param enable Enable/Disable filter. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable); + +/**************************************/ +/* Digital controller monitor setting */ +/**************************************/ + +/** + * @brief Config monitor of adc digital controller. + * + * @param idx Monitor index. + * @param config See ``adc_digi_monitor_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config); + +/** + * @brief Enable/disable monitor of adc digital controller. + * + * @param idx Monitor index. + * @param enable True or false enable monitor. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable); + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/esp32h2/include/driver/temp_sensor.h b/components/driver/esp32h2/include/driver/temp_sensor.h new file mode 100644 index 0000000000..9e227c71d6 --- /dev/null +++ b/components/driver/esp32h2/include/driver/temp_sensor.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + TSENS_DAC_L0 = 0, /*!< offset = -2, measure range: 50℃ ~ 125℃, error < 3℃. */ + TSENS_DAC_L1, /*!< offset = -1, measure range: 20℃ ~ 100℃, error < 2℃. */ + TSENS_DAC_L2, /*!< offset = 0, measure range:-10℃ ~ 80℃, error < 1℃. */ + TSENS_DAC_L3, /*!< offset = 1, measure range:-30℃ ~ 50℃, error < 2℃. */ + TSENS_DAC_L4, /*!< offset = 2, measure range:-40℃ ~ 20℃, error < 3℃. */ + TSENS_DAC_MAX, + TSENS_DAC_DEFAULT = TSENS_DAC_L2, +} temp_sensor_dac_offset_t; + +/** + * @brief Configuration for temperature sensor reading + */ +typedef struct { + temp_sensor_dac_offset_t dac_offset; /*!< The temperature measurement range is configured with a built-in temperature offset DAC. */ + uint8_t clk_div; /*!< Default: 6 */ +} temp_sensor_config_t; + +#define TSENS_CONFIG_DEFAULT() {.dac_offset = TSENS_DAC_L2, \ + .clk_div = 6} + +/** + * @brief Set parameter of temperature sensor. + * @param tsens + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens); + +/** + * @brief Get parameter of temperature sensor. + * @param tsens + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens); + +/** + * @brief Start temperature sensor measure. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG + */ +esp_err_t temp_sensor_start(void); + +/** + * @brief Stop temperature sensor measure. + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_stop(void); + +/** + * @brief Read temperature sensor raw data. + * @param tsens_out Pointer to raw data, Range: 0 ~ 255 + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG `tsens_out` is NULL + * - ESP_ERR_INVALID_STATE temperature sensor dont start + */ +esp_err_t temp_sensor_read_raw(uint32_t *tsens_out); + +/** + * @brief Read temperature sensor data that is converted to degrees Celsius. + * @note Should not be called from interrupt. + * @param celsius The measure output value. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG ARG is NULL. + * - ESP_ERR_INVALID_STATE The ambient temperature is out of range. + */ +esp_err_t temp_sensor_read_celsius(float *celsius); + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/esp32h2/rtc_tempsensor.c b/components/driver/esp32h2/rtc_tempsensor.c new file mode 100644 index 0000000000..7d03401eee --- /dev/null +++ b/components/driver/esp32h2/rtc_tempsensor.c @@ -0,0 +1,151 @@ +/* + * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "esp_log.h" +#include "hal/adc_ll.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/apb_saradc_struct.h" +#include "soc/apb_saradc_reg.h" +#include "soc/system_reg.h" +#include "driver/temp_sensor.h" +#include "regi2c_ctrl.h" +#include "esp32c3/rom/ets_sys.h" +#include "esp_efuse_rtc_calib.h" + +static const char *TAG = "tsens"; + +#define TSENS_CHECK(res, ret_val) ({ \ + if (!(res)) { \ + ESP_LOGE(TAG, "%s(%d)", __FUNCTION__, __LINE__); \ + return (ret_val); \ + } \ +}) +#define TSENS_XPD_WAIT_DEFAULT 0xFF /* Set wait cycle time(8MHz) from power up to reset enable. */ +#define TSENS_ADC_FACTOR (0.4386) +#define TSENS_DAC_FACTOR (27.88) +#define TSENS_SYS_OFFSET (20.52) + +typedef struct { + int index; + int offset; + int set_val; + int range_min; + int range_max; + int error_max; +} tsens_dac_offset_t; + +static const tsens_dac_offset_t dac_offset[TSENS_DAC_MAX] = { + /* DAC Offset reg_val min max error */ + {TSENS_DAC_L0, -2, 5, 50, 125, 3}, + {TSENS_DAC_L1, -1, 7, 20, 100, 2}, + {TSENS_DAC_L2, 0, 15, -10, 80, 1}, + {TSENS_DAC_L3, 1, 11, -30, 50, 2}, + {TSENS_DAC_L4, 2, 10, -40, 20, 3}, +}; + +static float s_deltaT = NAN; // unused number + +esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens) +{ + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset[tsens.dac_offset].set_val); + APB_SARADC.apb_tsens_ctrl.tsens_clk_div = tsens.clk_div; + APB_SARADC.apb_tsens_ctrl2.tsens_xpd_wait = TSENS_XPD_WAIT_DEFAULT; + APB_SARADC.apb_tsens_ctrl2.tsens_xpd_force = 1; + ESP_LOGD(TAG, "Config temperature range [%d°C ~ %d°C], error < %d°C", + dac_offset[tsens.dac_offset].range_min, + dac_offset[tsens.dac_offset].range_max, + dac_offset[tsens.dac_offset].error_max); + return ESP_OK; +} + +esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens) +{ + TSENS_CHECK(tsens != NULL, ESP_ERR_INVALID_ARG); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); + tsens->dac_offset = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); + for (int i = TSENS_DAC_L0; i < TSENS_DAC_MAX; i++) { + if (tsens->dac_offset == dac_offset[i].set_val) { + tsens->dac_offset = dac_offset[i].index; + break; + } + } + tsens->clk_div = APB_SARADC.apb_tsens_ctrl.tsens_clk_div; + return ESP_OK; +} + +esp_err_t temp_sensor_start(void) +{ + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); + APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = 1; + APB_SARADC.apb_tsens_ctrl.tsens_pu = 1; + return ESP_OK; +} + +esp_err_t temp_sensor_stop(void) +{ + APB_SARADC.apb_tsens_ctrl.tsens_pu = 0; + APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = 0; + return ESP_OK; +} + +esp_err_t temp_sensor_read_raw(uint32_t *tsens_out) +{ + TSENS_CHECK(tsens_out != NULL, ESP_ERR_INVALID_ARG); + *tsens_out = APB_SARADC.apb_tsens_ctrl.tsens_out; + return ESP_OK; +} + +static void read_delta_t_from_efuse(void) +{ + uint32_t version = esp_efuse_rtc_calib_get_ver(); + if (version == 1) { + // fetch calibration value for temp sensor from eFuse + s_deltaT = esp_efuse_rtc_calib_get_cal_temp(version); + } else { + // no value to fetch, use 0. + s_deltaT = 0; + } + ESP_LOGD(TAG, "s_deltaT = %f", s_deltaT); +} + +static float parse_temp_sensor_raw_value(uint32_t tsens_raw, const int dac_offset) +{ + if (isnan(s_deltaT)) { //suggests that the value is not initialized + read_delta_t_from_efuse(); + } + float result = (TSENS_ADC_FACTOR * (float)tsens_raw - TSENS_DAC_FACTOR * dac_offset - TSENS_SYS_OFFSET) - s_deltaT / 10.0; + return result; +} + +esp_err_t temp_sensor_read_celsius(float *celsius) +{ + TSENS_CHECK(celsius != NULL, ESP_ERR_INVALID_ARG); + temp_sensor_config_t tsens; + uint32_t tsens_out = 0; + esp_err_t ret = temp_sensor_get_config(&tsens); + if (ret == ESP_OK) { + ret = temp_sensor_read_raw(&tsens_out); + printf("tsens_out %d\r\n", tsens_out); + TSENS_CHECK(ret == ESP_OK, ret); + const tsens_dac_offset_t *dac = &dac_offset[tsens.dac_offset]; + *celsius = parse_temp_sensor_raw_value(tsens_out, dac->offset); + if (*celsius < dac->range_min || *celsius > dac->range_max) { + ESP_LOGW(TAG, "Exceeding the temperature range!"); + ret = ESP_ERR_INVALID_STATE; + } + } + return ret; +} diff --git a/components/esp32h2/CMakeLists.txt b/components/esp32h2/CMakeLists.txt new file mode 100644 index 0000000000..a785c520dc --- /dev/null +++ b/components/esp32h2/CMakeLists.txt @@ -0,0 +1,66 @@ +idf_build_get_property(target IDF_TARGET) +idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER) +if(NOT "${target}" STREQUAL "esp32c3") + return() +endif() + +if(BOOTLOADER_BUILD) + # For bootloader, all we need from esp32c3 is headers + idf_component_register(INCLUDE_DIRS include REQUIRES riscv) + target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32c3.peripherals.ld") +else() + # Regular app build + + set(srcs "dport_access.c" + "esp_hmac.c" + "esp_ds.c" + "esp_crypto_lock.c" + "memprot.c") + set(include_dirs "include") + + set(requires driver efuse soc riscv) #unfortunately rom/uart uses SOC registers directly + + # driver is a public requirement because esp_sleep.h uses gpio_num_t & touch_pad_t + # app_update is added here because cpu_start.c uses esp_ota_get_app_description() function. + # esp_timer is added here because cpu_start.c uses esp_timer + set(priv_requires + app_trace app_update bootloader_support log mbedtls nvs_flash + pthread spi_flash vfs espcoredump esp_common esp_timer) + + idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS "${include_dirs}" + REQUIRES "${requires}" + PRIV_REQUIRES "${priv_requires}" + REQUIRED_IDF_TARGETS esp32c3) + + target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_BINARY_DIR}/esp32c3_out.ld") + + # Process the template file through the linker script generation mechanism, and use the output for linking the + # final binary + target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/ld/esp32c3.project.ld.in" + PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32c3.project.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32c3.peripherals.ld") + + target_link_libraries(${COMPONENT_LIB} PUBLIC gcc) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0") + + idf_build_get_property(config_dir CONFIG_DIR) + # Preprocess esp32c3.ld linker script to include configuration, becomes esp32c3_out.ld + set(LD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/ld) + add_custom_command( + OUTPUT esp32c3_out.ld + COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32c3_out.ld -I ${config_dir} ${LD_DIR}/esp32c3.ld + MAIN_DEPENDENCY ${LD_DIR}/esp32c3.ld + DEPENDS ${sdkconfig_header} + COMMENT "Generating linker script..." + VERBATIM) + + add_custom_target(esp32c3_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32c3_out.ld) + add_dependencies(${COMPONENT_LIB} esp32c3_linker_script) + + # disable stack protection in files which are involved in initialization of that feature + set_source_files_properties( + cpu_start.c + PROPERTIES COMPILE_FLAGS + -fno-stack-protector) +endif() diff --git a/components/esp32h2/Kconfig b/components/esp32h2/Kconfig new file mode 100644 index 0000000000..26d4bacfb9 --- /dev/null +++ b/components/esp32h2/Kconfig @@ -0,0 +1,212 @@ +menu "ESP32C3-Specific" + visible if IDF_TARGET_ESP32C3 + + choice ESP32C3_DEFAULT_CPU_FREQ_MHZ + prompt "CPU frequency" + default ESP32C3_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA + default ESP32C3_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA + help + CPU frequency to be set on application startup. + + config ESP32C3_DEFAULT_CPU_FREQ_40 + bool "40 MHz" + depends on IDF_ENV_FPGA + config ESP32C3_DEFAULT_CPU_FREQ_80 + bool "80 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_160 + bool "160 MHz" + endchoice + + config ESP32C3_DEFAULT_CPU_FREQ_MHZ + int + default 40 if ESP32C3_DEFAULT_CPU_FREQ_40 + default 80 if ESP32C3_DEFAULT_CPU_FREQ_80 + default 160 if ESP32C3_DEFAULT_CPU_FREQ_160 + + choice ESP32C3_REV_MIN + prompt "Minimum Supported ESP32-C3 Revision" + default ESP32C3_REV_MIN_3 + help + Minimum revision that ESP-IDF would support. + + Only supporting higher chip revisions can reduce binary size. + + config ESP32C3_REV_MIN_0 + bool "Rev 0" + config ESP32C3_REV_MIN_1 + bool "Rev 1" + config ESP32C3_REV_MIN_2 + bool "Rev 2" + config ESP32C3_REV_MIN_3 + bool "Rev 3" + endchoice + + config ESP32C3_REV_MIN + int + default 0 if ESP32C3_REV_MIN_0 + default 1 if ESP32C3_REV_MIN_1 + default 2 if ESP32C3_REV_MIN_2 + default 3 if ESP32C3_REV_MIN_3 + + config ESP32C3_DEBUG_OCDAWARE + bool "Make exception and panic handlers JTAG/OCD aware" + default y + select FREERTOS_DEBUG_OCDAWARE + help + The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and + instead of panicking, have the debugger stop on the offending instruction. + + config ESP32C3_DEBUG_STUBS_ENABLE + bool "OpenOCD debug stubs" + default COMPILER_OPTIMIZATION_LEVEL_DEBUG + depends on !ESP32C3_TRAX + help + Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging, + e.g. GCOV data dump. + + config ESP32C3_BROWNOUT_DET + bool "Hardware brownout detect & reset" + default y + help + The ESP32-C3 has a built-in brownout detector which can detect if the voltage is lower than + a specific value. If this happens, it will reset the chip in order to prevent unintended + behaviour. + + choice ESP32C3_BROWNOUT_DET_LVL_SEL + prompt "Brownout voltage level" + depends on ESP32C3_BROWNOUT_DET + default ESP32C3_BROWNOUT_DET_LVL_SEL_7 + help + The brownout detector will reset the chip when the supply voltage is approximately + below this level. Note that there may be some variation of brownout voltage level + between each chip. + + #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages + #of the brownout threshold levels. + config ESP32C3_BROWNOUT_DET_LVL_SEL_7 + bool "2.51V" + config ESP32C3_BROWNOUT_DET_LVL_SEL_6 + bool "2.64V" + config ESP32C3_BROWNOUT_DET_LVL_SEL_5 + bool "2.76V" + config ESP32C3_BROWNOUT_DET_LVL_SEL_4 + bool "2.92V" + config ESP32C3_BROWNOUT_DET_LVL_SEL_3 + bool "3.10V" + config ESP32C3_BROWNOUT_DET_LVL_SEL_2 + bool "3.27V" + endchoice + + config ESP32C3_BROWNOUT_DET_LVL + int + default 2 if ESP32C3_BROWNOUT_DET_LVL_SEL_2 + default 3 if ESP32C3_BROWNOUT_DET_LVL_SEL_3 + default 4 if ESP32C3_BROWNOUT_DET_LVL_SEL_4 + default 5 if ESP32C3_BROWNOUT_DET_LVL_SEL_5 + default 6 if ESP32C3_BROWNOUT_DET_LVL_SEL_6 + default 7 if ESP32C3_BROWNOUT_DET_LVL_SEL_7 + + choice ESP32C3_TIME_SYSCALL + prompt "Timers used for gettimeofday function" + default ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER + help + This setting defines which hardware timers are used to + implement 'gettimeofday' and 'time' functions in C library. + + - If both high-resolution (systimer) and RTC timers are used, timekeeping will + continue in deep sleep. Time will be reported at 1 microsecond + resolution. This is the default, and the recommended option. + - If only high-resolution timer (systimer) is used, gettimeofday will + provide time at microsecond resolution. + Time will not be preserved when going into deep sleep mode. + - If only RTC timer is used, timekeeping will continue in + deep sleep, but time will be measured at 6.(6) microsecond + resolution. Also the gettimeofday function itself may take + longer to run. + - If no timers are used, gettimeofday and time functions + return -1 and set errno to ENOSYS. + - When RTC is used for timekeeping, two RTC_STORE registers are + used to keep time in deep sleep mode. + + config ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER + bool "RTC and high-resolution timer" + select ESP_TIME_FUNCS_USE_RTC_TIMER + select ESP_TIME_FUNCS_USE_ESP_TIMER + config ESP32C3_TIME_SYSCALL_USE_RTC + bool "RTC" + select ESP_TIME_FUNCS_USE_RTC_TIMER + config ESP32C3_TIME_SYSCALL_USE_SYSTIMER + bool "High-resolution timer" + select ESP_TIME_FUNCS_USE_ESP_TIMER + config ESP32C3_TIME_SYSCALL_USE_NONE + bool "None" + select ESP_TIME_FUNCS_USE_NONE + endchoice + + choice ESP32C3_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32C3_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config ESP32C3_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + config ESP32C3_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config ESP32C3_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + config ESP32C3_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + endchoice + + config ESP32C3_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + + config ESP32C3_NO_BLOBS + bool "No Binary Blobs" + depends on !BT_ENABLED + default n + help + If enabled, this disables the linking of binary libraries in the application build. Note + that after enabling this Wi-Fi/Bluetooth will not work. + + config ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND + bool "light sleep GPIO reset workaround" + default y + select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE + help + ESP32C3 will reset at wake-up if GPIO is received a small electrostatic pulse during + light sleep, with specific condition + + - GPIO needs to be configured as input-mode only + - The pin receives a small electrostatic pulse, and reset occurs when the pulse + voltage is higher than 6 V + + For GPIO set to input mode only, it is not a good practice to leave it open/floating, + The hardware design needs to controlled it with determined supply or ground voltage + is necessary. + + This option provides a software workaround for this issue. Configure to isolate all + GPIO pins in sleep state. + +endmenu # ESP32C3-Specific diff --git a/components/esp32h2/Makefile.projbuild b/components/esp32h2/Makefile.projbuild new file mode 100644 index 0000000000..cb10139573 --- /dev/null +++ b/components/esp32h2/Makefile.projbuild @@ -0,0 +1 @@ +# ESP32-C3 is not supported in the GNU Make build system. diff --git a/components/esp32h2/component.mk b/components/esp32h2/component.mk new file mode 100644 index 0000000000..a2f7dc1797 --- /dev/null +++ b/components/esp32h2/component.mk @@ -0,0 +1,4 @@ +# +# Component Makefile +# +COMPONENT_CONFIG_ONLY := 1 diff --git a/components/esp32h2/dport_access.c b/components/esp32h2/dport_access.c new file mode 100644 index 0000000000..08b55a96fb --- /dev/null +++ b/components/esp32h2/dport_access.c @@ -0,0 +1,25 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include "soc/dport_access.h" + +// Read a sequence of DPORT registers to the buffer. +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words) +{ + for (uint32_t i = 0; i < num_words; ++i) { + buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4); + } +} diff --git a/components/esp32h2/esp_crypto_lock.c b/components/esp32h2/esp_crypto_lock.c new file mode 100644 index 0000000000..46a90ca08b --- /dev/null +++ b/components/esp32h2/esp_crypto_lock.c @@ -0,0 +1,83 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include "esp_crypto_lock.h" + +/* Lock overview: +SHA: peripheral independent, but DMA is shared with AES +AES: peripheral independent, but DMA is shared with SHA +MPI/RSA: independent +HMAC: needs SHA +DS: needs HMAC (which needs SHA), AES and MPI +*/ + +/* Lock for DS peripheral */ +static _lock_t s_crypto_ds_lock; + +/* Lock for HMAC peripheral */ +static _lock_t s_crypto_hmac_lock; + +/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */ +static _lock_t s_crypto_mpi_lock; + +/* Single lock for SHA and AES, sharing a reserved GDMA channel */ +static _lock_t s_crypto_sha_aes_lock; + +void esp_crypto_hmac_lock_acquire(void) +{ + _lock_acquire(&s_crypto_hmac_lock); + esp_crypto_sha_aes_lock_acquire(); +} + +void esp_crypto_hmac_lock_release(void) +{ + esp_crypto_sha_aes_lock_release(); + _lock_release(&s_crypto_hmac_lock); +} + +void esp_crypto_ds_lock_acquire(void) +{ + _lock_acquire(&s_crypto_ds_lock); + esp_crypto_hmac_lock_acquire(); + esp_crypto_mpi_lock_acquire(); +} + +void esp_crypto_ds_lock_release(void) +{ + esp_crypto_mpi_lock_release(); + esp_crypto_hmac_lock_release(); + _lock_release(&s_crypto_ds_lock); +} + +void esp_crypto_sha_aes_lock_acquire(void) +{ + _lock_acquire(&s_crypto_sha_aes_lock); +} + +void esp_crypto_sha_aes_lock_release(void) +{ + _lock_release(&s_crypto_sha_aes_lock); +} + +void esp_crypto_mpi_lock_acquire(void) +{ + _lock_acquire(&s_crypto_mpi_lock); +} + +void esp_crypto_mpi_lock_release(void) +{ + _lock_release(&s_crypto_mpi_lock); +} diff --git a/components/esp32h2/esp_ds.c b/components/esp32h2/esp_ds.c new file mode 100644 index 0000000000..3dbaa79dc5 --- /dev/null +++ b/components/esp32h2/esp_ds.c @@ -0,0 +1,232 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/periph_ctrl.h" +#include "esp_crypto_lock.h" +#include "hal/ds_hal.h" +#include "hal/ds_ll.h" +#include "hal/hmac_hal.h" +#include "esp32c3/rom/digital_signature.h" +#include "esp_timer.h" +#include "esp_ds.h" + +struct esp_ds_context { + const esp_ds_data_t *data; +}; + +/** + * The vtask delay \c esp_ds_sign() is using while waiting for completion of the signing operation. + */ +#define ESP_DS_SIGN_TASK_DELAY_MS 10 + +#define RSA_LEN_MAX 127 + +/* + * esp_digital_signature_length_t is used in esp_ds_data_t in contrast to ets_ds_data_t, where unsigned is used. + * Check esp_digital_signature_length_t's width here because it's converted to unsigned using raw casts. + */ +_Static_assert(sizeof(esp_digital_signature_length_t) == sizeof(unsigned), + "The size of esp_digital_signature_length_t and unsigned has to be the same"); + +/* + * esp_ds_data_t is used in the encryption function but casted to ets_ds_data_t. + * Check esp_ds_data_t's width here because it's converted using raw casts. + */ +_Static_assert(sizeof(esp_ds_data_t) == sizeof(ets_ds_data_t), + "The size of esp_ds_data_t and ets_ds_data_t has to be the same"); + +static void ds_acquire_enable(void) +{ + esp_crypto_ds_lock_acquire(); + + // We also enable SHA and HMAC here. SHA is used by HMAC, HMAC is used by DS. + periph_module_enable(PERIPH_HMAC_MODULE); + periph_module_enable(PERIPH_SHA_MODULE); + periph_module_enable(PERIPH_DS_MODULE); + + hmac_hal_start(); +} + +static void ds_disable_release(void) +{ + ds_hal_finish(); + + periph_module_disable(PERIPH_DS_MODULE); + periph_module_disable(PERIPH_SHA_MODULE); + periph_module_disable(PERIPH_HMAC_MODULE); + + esp_crypto_ds_lock_release(); +} + +esp_err_t esp_ds_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + void *signature) +{ + // Need to check signature here, otherwise the signature is only checked when the signing has finished and fails + // but the signing isn't uninitialized and the mutex is still locked. + if (!signature) { + return ESP_ERR_INVALID_ARG; + } + + esp_ds_context_t *context; + esp_err_t result = esp_ds_start_sign(message, data, key_id, &context); + if (result != ESP_OK) { + return result; + } + + while (esp_ds_is_busy()) + vTaskDelay(ESP_DS_SIGN_TASK_DELAY_MS / portTICK_PERIOD_MS); + + return esp_ds_finish_sign(signature, context); +} + +esp_err_t esp_ds_start_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + esp_ds_context_t **esp_ds_ctx) +{ + if (!message || !data || !esp_ds_ctx) { + return ESP_ERR_INVALID_ARG; + } + + if (key_id >= HMAC_KEY_MAX) { + return ESP_ERR_INVALID_ARG; + } + + if (!(data->rsa_length == ESP_DS_RSA_1024 + || data->rsa_length == ESP_DS_RSA_2048 + || data->rsa_length == ESP_DS_RSA_3072)) { + return ESP_ERR_INVALID_ARG; + } + + ds_acquire_enable(); + + // initiate hmac + uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); + if (conf_error) { + ds_disable_release(); + return ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL; + } + + ds_hal_start(); + + // check encryption key from HMAC + int64_t start_time = esp_timer_get_time(); + while (ds_ll_busy() != 0) { + if ((esp_timer_get_time() - start_time) > SOC_DS_KEY_CHECK_MAX_WAIT_US) { + ds_disable_release(); + return ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY; + } + } + + esp_ds_context_t *context = malloc(sizeof(esp_ds_context_t)); + if (!context) { + ds_disable_release(); + return ESP_ERR_NO_MEM; + } + + size_t rsa_len = (data->rsa_length + 1) * 4; + ds_hal_write_private_key_params(data->c); + ds_hal_configure_iv(data->iv); + ds_hal_write_message(message, rsa_len); + + // initiate signing + ds_hal_start_sign(); + + context->data = data; + *esp_ds_ctx = context; + + return ESP_OK; +} + +bool esp_ds_is_busy(void) +{ + return ds_hal_busy(); +} + +esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx) +{ + if (!signature || !esp_ds_ctx) { + return ESP_ERR_INVALID_ARG; + } + + const esp_ds_data_t *data = esp_ds_ctx->data; + unsigned rsa_len = (data->rsa_length + 1) * 4; + + while (ds_hal_busy()) { } + + ds_signature_check_t sig_check_result = ds_hal_read_result((uint8_t*) signature, (size_t) rsa_len); + + esp_err_t return_value = ESP_OK; + + if (sig_check_result == DS_SIGNATURE_MD_FAIL || sig_check_result == DS_SIGNATURE_PADDING_AND_MD_FAIL) { + return_value = ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST; + } + + if (sig_check_result == DS_SIGNATURE_PADDING_FAIL) { + return_value = ESP32C3_ERR_HW_CRYPTO_DS_INVALID_PADDING; + } + + free(esp_ds_ctx); + + hmac_hal_clean(); + + ds_disable_release(); + + return return_value; +} + +esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data, + const void *iv, + const esp_ds_p_data_t *p_data, + const void *key) +{ + if (!p_data) { + return ESP_ERR_INVALID_ARG; + } + + esp_err_t result = ESP_OK; + + esp_crypto_ds_lock_acquire(); + periph_module_enable(PERIPH_AES_MODULE); + periph_module_enable(PERIPH_DS_MODULE); + periph_module_enable(PERIPH_SHA_MODULE); + periph_module_enable(PERIPH_HMAC_MODULE); + periph_module_enable(PERIPH_RSA_MODULE); + + ets_ds_data_t *ds_data = (ets_ds_data_t*) data; + const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t*) p_data; + + ets_ds_result_t ets_result = ets_ds_encrypt_params(ds_data, iv, ds_plain_data, key, ETS_DS_KEY_HMAC); + + if (ets_result == ETS_DS_INVALID_PARAM) { + result = ESP_ERR_INVALID_ARG; + } + + periph_module_disable(PERIPH_RSA_MODULE); + periph_module_disable(PERIPH_HMAC_MODULE); + periph_module_disable(PERIPH_SHA_MODULE); + periph_module_disable(PERIPH_DS_MODULE); + periph_module_disable(PERIPH_AES_MODULE); + esp_crypto_ds_lock_release(); + + return result; +} diff --git a/components/esp32h2/esp_hmac.c b/components/esp32h2/esp_hmac.c new file mode 100644 index 0000000000..9f71353e30 --- /dev/null +++ b/components/esp32h2/esp_hmac.c @@ -0,0 +1,132 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "driver/periph_ctrl.h" +#include "esp32c3/rom/hmac.h" +#include "esp32c3/rom/ets_sys.h" +#include "esp_hmac.h" +#include "esp_crypto_lock.h" + +#include "hal/hmac_hal.h" + +#define SHA256_BLOCK_SZ 64 +#define SHA256_PAD_SZ 8 + +/** + * @brief Apply the HMAC padding without the embedded length. + * + * @note This function does not check the data length, it is the responsibility of the other functions in this + * module to make sure that \c data_len is at most SHA256_BLOCK_SZ - 1 so the padding fits in. + * Otherwise, this function has undefined behavior. + * Note however, that for the actual HMAC implementation on ESP32C3, the length also needs to be applied at the end + * of the block. This function alone deosn't do that. + */ +static void write_and_padd(uint8_t *block, const uint8_t *data, uint16_t data_len) +{ + memcpy(block, data, data_len); + // Apply a one bit, followed by zero bits (refer to the ESP32C3 TRM). + block[data_len] = 0x80; + bzero(block + data_len + 1, SHA256_BLOCK_SZ - data_len - 1); +} + +esp_err_t esp_hmac_calculate(hmac_key_id_t key_id, + const void *message, + size_t message_len, + uint8_t *hmac) +{ + const uint8_t *message_bytes = (const uint8_t *)message; + + if (!message || !hmac) { + return ESP_ERR_INVALID_ARG; + } + if (key_id >= HMAC_KEY_MAX) { + return ESP_ERR_INVALID_ARG; + } + + esp_crypto_hmac_lock_acquire(); + + // We also enable SHA and DS here. SHA is used by HMAC, DS will otherwise hold SHA in reset state. + periph_module_enable(PERIPH_HMAC_MODULE); + periph_module_enable(PERIPH_SHA_MODULE); + periph_module_enable(PERIPH_DS_MODULE); + + hmac_hal_start(); + + uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_USER, key_id); + if (conf_error) { + esp_crypto_hmac_lock_release(); + return ESP_FAIL; + } + + if (message_len + 1 + SHA256_PAD_SZ <= SHA256_BLOCK_SZ) { + // If message including padding is only one block... + // Last message block, so apply SHA-256 padding rules in software + uint8_t block[SHA256_BLOCK_SZ]; + uint64_t bit_len = __builtin_bswap64(message_len * 8 + 512); + + write_and_padd(block, message_bytes, message_len); + // Final block: append the bit length in this block and signal padding to peripheral + memcpy(block + SHA256_BLOCK_SZ - sizeof(bit_len), + &bit_len, sizeof(bit_len)); + hmac_hal_write_one_block_512(block); + } else { + // If message including padding is needs more than one block + + // write all blocks without padding except the last one + size_t remaining_blocks = message_len / SHA256_BLOCK_SZ; + for (int i = 1; i < remaining_blocks; i++) { + hmac_hal_write_block_512(message_bytes); + message_bytes += SHA256_BLOCK_SZ; + hmac_hal_next_block_normal(); + } + + // If message fits into one block but without padding, we must not write another block. + if (remaining_blocks) { + hmac_hal_write_block_512(message_bytes); + message_bytes += SHA256_BLOCK_SZ; + } + + size_t remaining = message_len % SHA256_BLOCK_SZ; + // Last message block, so apply SHA-256 padding rules in software + uint8_t block[SHA256_BLOCK_SZ]; + uint64_t bit_len = __builtin_bswap64(message_len * 8 + 512); + + // If the remaining message and appended padding doesn't fit into a single block, we have to write an + // extra block with the rest of the message and potential padding first. + if (remaining >= SHA256_BLOCK_SZ - SHA256_PAD_SZ) { + write_and_padd(block, message_bytes, remaining); + hmac_hal_next_block_normal(); + hmac_hal_write_block_512(block); + bzero(block, SHA256_BLOCK_SZ); + } else { + write_and_padd(block, message_bytes, remaining); + } + memcpy(block + SHA256_BLOCK_SZ - sizeof(bit_len), + &bit_len, sizeof(bit_len)); + hmac_hal_next_block_padding(); + hmac_hal_write_block_512(block); + } + + // Read back result (bit swapped) + hmac_hal_read_result_256(hmac); + + periph_module_disable(PERIPH_DS_MODULE); + periph_module_disable(PERIPH_SHA_MODULE); + periph_module_disable(PERIPH_HMAC_MODULE); + + esp_crypto_hmac_lock_release(); + + return ESP_OK; +} diff --git a/components/esp32h2/include/esp32h2/dport_access.h b/components/esp32h2/include/esp32h2/dport_access.h new file mode 100644 index 0000000000..f3f7007a9c --- /dev/null +++ b/components/esp32h2/include/esp32h2/dport_access.h @@ -0,0 +1,42 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_DPORT_ACCESS_H_ +#define _ESP_DPORT_ACCESS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +#define DPORT_STALL_OTHER_CPU_START() +#define DPORT_STALL_OTHER_CPU_END() +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP_DPORT_ACCESS_H_ */ diff --git a/components/esp32h2/include/esp32h2/memprot.h b/components/esp32h2/include/esp32h2/memprot.h new file mode 100644 index 0000000000..094f28f42e --- /dev/null +++ b/components/esp32h2/include/esp32h2/memprot.h @@ -0,0 +1,455 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +/* INTERNAL API + * generic interface to PMS memory protection features + */ + +#pragma once + +#include +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef IRAM_SRAM_START +#define IRAM_SRAM_START 0x4037C000 +#endif + +#ifndef DRAM_SRAM_START +#define DRAM_SRAM_START 0x3FC7C000 +#endif + +#ifndef MAP_DRAM_TO_IRAM +#define MAP_DRAM_TO_IRAM(addr) (addr - DRAM_SRAM_START + IRAM_SRAM_START) +#endif + +#ifndef MAP_IRAM_TO_DRAM +#define MAP_IRAM_TO_DRAM(addr) (addr - IRAM_SRAM_START + DRAM_SRAM_START) +#endif + +typedef enum { + MEMPROT_NONE = 0x00000000, + MEMPROT_IRAM0_SRAM = 0x00000001, + MEMPROT_DRAM0_SRAM = 0x00000002, + MEMPROT_ALL = 0xFFFFFFFF +} mem_type_prot_t; + +typedef enum { + MEMPROT_SPLITLINE_NONE = 0, + MEMPROT_IRAM0_DRAM0_SPLITLINE, + MEMPROT_IRAM0_LINE_0_SPLITLINE, + MEMPROT_IRAM0_LINE_1_SPLITLINE, + MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, + MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE +} split_line_t; + +typedef enum { + MEMPROT_PMS_AREA_NONE = 0, + MEMPROT_IRAM0_PMS_AREA_0, + MEMPROT_IRAM0_PMS_AREA_1, + MEMPROT_IRAM0_PMS_AREA_2, + MEMPROT_IRAM0_PMS_AREA_3, + MEMPROT_DRAM0_PMS_AREA_0, + MEMPROT_DRAM0_PMS_AREA_1, + MEMPROT_DRAM0_PMS_AREA_2, + MEMPROT_DRAM0_PMS_AREA_3 +} pms_area_t; + +typedef enum +{ + MEMPROT_PMS_WORLD_0 = 0, + MEMPROT_PMS_WORLD_1, + MEMPROT_PMS_WORLD_2, + MEMPROT_PMS_WORLD_INVALID = 0xFFFFFFFF +} pms_world_t; + +typedef enum +{ + MEMPROT_PMS_OP_READ = 0, + MEMPROT_PMS_OP_WRITE, + MEMPROT_PMS_OP_FETCH, + MEMPROT_PMS_OP_INVALID = 0xFFFFFFFF +} pms_operation_type_t; + +/** + * @brief Converts Memory protection type to string + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + */ +const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type); + +/** + * @brief Converts Split line type to string + * + * @param line_type Split line type (see split_line_t enum) + */ +const char *esp_memprot_split_line_to_str(split_line_t line_type); + +/** + * @brief Converts PMS Area type to string + * + * @param area_type PMS Area type (see pms_area_t enum) + */ +const char *esp_memprot_pms_to_str(pms_area_t area_type); + +/** + * @brief Returns PMS splitting address for given Split line type + * + * The value is taken from PMS configuration registers (IRam0 range) + * For details on split lines see 'esp_memprot_set_prot_int' function description + * + * @param line_type Split line type (see split_line_t enum) + * + * @return appropriate split line address + */ +uint32_t *esp_memprot_get_split_addr(split_line_t line_type); + +/** + * @brief Returns default main IRAM/DRAM splitting address + * + * The address value is given by _iram_text_end global (IRam0 range) + + * @return Main I/D split line (IRam0_DRam0_Split_Addr) + */ +void *esp_memprot_get_default_main_split_addr(void); + +/** + * @brief Sets a lock for the main IRAM/DRAM splitting address + * + * Locks can be unlocked only by digital system reset + */ +void esp_memprot_set_split_line_lock(void); + +/** + * @brief Gets a lock status for the main IRAM/DRAM splitting address + * + * @return true/false (locked/unlocked) + */ +bool esp_memprot_get_split_line_lock(void); + +/** + * @brief Sets required split line address + * + * @param line_type Split line type (see split_line_t enum) + * @param line_addr target address from a memory range relevant to given line_type (IRAM/DRAM) + */ +void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr); + +/** + * @brief Sets a lock for PMS Area settings of required Memory type + * + * Locks can be unlocked only by digital system reset + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + */ +void esp_memprot_set_pms_lock(mem_type_prot_t mem_type); + +/** + * @brief Gets a lock status for PMS Area settings of required Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return true/false (locked/unlocked) + */ +bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type); + +/** + * @brief Sets permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) + * + * @param area_type IRam0 PMS Area type (see pms_area_t enum) + * @param r Read permission flag + * @param w Write permission flag + * @param x Execute permission flag + */ +void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x); + +/** + * @brief Gets current permissions for given PMS Area in IRam0 memory range (MEMPROT_IRAM0_SRAM) + * + * @param area_type IRam0 PMS Area type (see pms_area_t enum) + * @param r Read permission flag holder + * @param w Write permission flag holder + * @param x Execute permission flag holder + */ +void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x); + +/** + * @brief Sets permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) + * + * @param area_type DRam0 PMS Area type (see pms_area_t enum) + * @param r Read permission flag + * @param w Write permission flag + */ +void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w); + +/** + * @brief Gets current permissions for given PMS Area in DRam0 memory range (MEMPROT_DRAM0_SRAM) + * + * @param area_type DRam0 PMS Area type (see pms_area_t enum) + * @param r Read permission flag holder + * @param w Write permission flag holder + */ +void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w); + +/** + * @brief Sets a lock for PMS interrupt monitor settings of required Memory type + * + * Locks can be unlocked only by digital system reset + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + */ +void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type); + +/** + * @brief Gets a lock status for PMS interrupt monitor settings of required Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return true/false (locked/unlocked) + */ +bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type); + +/** + * @brief Enable PMS violation interrupt monitoring of required Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * @param enable/disable + */ +void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable); + +/** + * @brief Gets enable/disable status for PMS interrupt monitor settings of required Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return true/false (enabled/disabled) + */ +bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type); + +/** + * @brief Gets CPU ID for currently active PMS violation interrupt + * + * @return CPU ID (CPU_PRO for ESP32C3) + */ +int IRAM_ATTR esp_memprot_intr_get_cpuid(void); + +/** + * @brief Clears current interrupt ON flag for given Memory type + * + * Interrupt clearing happens in two steps: + * 1. Interrupt CLR flag is set (to clear the interrupt ON status) + * 2. Interrupt CLR flag is reset (to allow further monitoring) + * This operation is non-atomic by PMS module design + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + */ +void IRAM_ATTR esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type); + +/** + * @brief Returns active PMS violation interrupt (if any) + * + * This function iterates through supported Memory type status registers + * and returns the first interrupt-on flag. If none is found active, + * MEMPROT_NONE is returned. + * Order of checking (in current version): + * 1. MEMPROT_IRAM0_SRAM + * 2. MEMPROT_DRAM0_SRAM + * + * @return mem_type Memory protection type related to active interrupt found (see mem_type_prot_t enum) + */ +mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); + +/** + * @brief Checks whether any violation interrupt is active + * + * @return true/false (yes/no) + */ +bool IRAM_ATTR esp_memprot_is_locked_any(void); + +/** + * @brief Checks whether any violation interrupt is enabled + * + * @return true/false (yes/no) + */ +bool IRAM_ATTR esp_memprot_is_intr_ena_any(void); + +/** + * @brief Checks whether any violation interrupt is enabled + * + * @return true/false (yes/no) + */ +bool IRAM_ATTR esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type); + +/** + * @brief Returns the address which caused the violation interrupt (if any) + * + * The address is taken from appropriate PMS violation status register, based given Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return faulting address + */ +uint32_t IRAM_ATTR esp_memprot_get_violate_addr(mem_type_prot_t mem_type); + +/** + * @brief Returns the World identifier of the code causing the violation interrupt (if any) + * + * The value is taken from appropriate PMS violation status register, based given Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return World identifier (see pms_world_t enum) + */ +pms_world_t IRAM_ATTR esp_memprot_get_violate_world(mem_type_prot_t mem_type); + +/** + * @brief Returns Read or Write operation type which caused the violation interrupt (if any) + * + * The value (bit) is taken from appropriate PMS violation status register, based given Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return PMS operation type relevant to mem_type parameter (se pms_operation_type_t) + */ +pms_operation_type_t IRAM_ATTR esp_memprot_get_violate_wr(mem_type_prot_t mem_type); + +/** + * @brief Returns LoadStore flag of the operation type which caused the violation interrupt (if any) + * + * The value (bit) is taken from appropriate PMS violation status register, based given Memory type + * Effective only on IRam0 access + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return true/false (LoadStore bit on/off) + */ +bool IRAM_ATTR esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type); + +/** + * @brief Returns byte-enables for the address which caused the violation interrupt (if any) + * + * The value is taken from appropriate PMS violation status register, based given Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return byte-enables + */ +uint32_t IRAM_ATTR esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type); + +/** + * @brief Returns raw contents of DRam0 status register 1 + * + * @return 32-bit register value + */ +uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_1(void); + +/** + * @brief Returns raw contents of DRam0 status register 2 + * + * @return 32-bit register value + */ +uint32_t IRAM_ATTR esp_memprot_get_dram_status_reg_2(void); + +/** + * @brief Returns raw contents of IRam0 status register + * + * @return 32-bit register value + */ +uint32_t IRAM_ATTR esp_memprot_get_iram_status_reg(void); + +/** + * @brief Register PMS violation interrupt in global interrupt matrix for given Memory type + * + * Memory protection components uses specific interrupt number, see ETS_MEMPROT_ERR_INUM + * The registration makes the panic-handler routine being called when the interrupt appears + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + */ +void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type); + +/** + * @brief Convenient routine for setting the PMS defaults + * + * Called on application startup, depending on CONFIG_ESP_SYSTEM_MEMPROT_FEATURE Kconfig settings + * For implementation details see 'esp_memprot_set_prot_int' description + * + * @param invoke_panic_handler register all interrupts for panic handling (true/false) + * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) + * @param mem_type_mask 32-bit field of specific PMS parts to configure (see 'esp_memprot_set_prot_int') + */ +void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask); + +/** + * @brief Internal routine for setting the PMS defaults + * + * Called on application startup from within 'esp_memprot_set_prot'. Allows setting a specific splitting address + * (main I/D split line) - see the parameter 'split_addr'. If the 'split_addr' equals to NULL, default I/D split line + * is used (&_iram_text_end) and all the remaining lines share the same address. + * The function sets all the split lines and PMS areas to the same space, + * ie there is a single instruction space and single data space at the end. + * The PMS split lines and permission areas scheme described below: + * + * DRam0/DMA IRam0 + * ----------------------------------------------- + * ... | IRam0_PMS_0 | + * DRam0_PMS_0 ----------------------------------------------- IRam0_line1_Split_addr + * ... | IRam0_PMS_1 | + * ... ----------------------------------------------- IRam0_line0_Split_addr + * | IRam0_PMS_2 | + * =============================================== IRam0_DRam0_Split_addr (main I/D) + * | DRam0_PMS_1 | + * DRam0_DMA_line0_Split_addr ----------------------------------------------- ... + * | DRam0_PMS_2 | ... + * DRam0_DMA_line1_Split_addr ----------------------------------------------- IRam0_PMS_3 + * | DRam0_PMS_3 | ... + * ----------------------------------------------- + * + * Default settings provided by 'esp_memprot_set_prot_int' are as follows: + * + * DRam0/DMA IRam0 + * ----------------------------------------------- + * | IRam0_PMS_0 = IRam0_PMS_1 = IRam0_PMS_2 | + * | DRam0_PMS_0 | IRam0_line1_Split_addr + * DRam0_DMA_line0_Split_addr | | = + * = =============================================== IRam0_line0_Split_addr + * DRam0_DMA_line1_Split_addr | | = + * | DRam0_PMS_1 = DRam0_PMS_2 = DRam0_PMS_3 | IRam0_DRam0_Split_addr (main I/D) + * | IRam0_PMS_3 | + * ----------------------------------------------- + * + * Once the memprot feature is locked, it can be unlocked only by digital system reset + * + * @param invoke_panic_handler register all the violation interrupts for panic handling (true/false) + * @param lock_feature lock the defaults to prevent further PMS settings changes (true/false) + * @param split_addr specific main I/D adrees or NULL to use default ($_iram_text_end) + * @param mem_type_mask 32-bit field of specific PMS parts to configure (members of mem_type_prot_t) + */ +void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask); + +/** + * @brief Returns raw contents of PMS interrupt monitor register for given Memory type + * + * @param mem_type Memory protection type (see mem_type_prot_t enum) + * + * @return 32-bit register value + */ +uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp32h2/include/esp32h2/rtc.h b/components/esp32h2/include/esp32h2/rtc.h new file mode 100644 index 0000000000..b090ae5cfb --- /dev/null +++ b/components/esp32h2/include/esp32h2/rtc.h @@ -0,0 +1,40 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp32c3/rtc.h + * + * This file contains declarations of rtc related functions. + */ + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +uint64_t esp_rtc_get_time_us(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp32h2/include/esp_crypto_lock.h b/components/esp32h2/include/esp_crypto_lock.h new file mode 100644 index 0000000000..3149d34692 --- /dev/null +++ b/components/esp32h2/include/esp_crypto_lock.h @@ -0,0 +1,76 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Acquire lock for HMAC cryptography peripheral + * + * Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral + */ +void esp_crypto_hmac_lock_acquire(void); + +/** + * @brief Release lock for HMAC cryptography peripheral + * + * Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral + */ +void esp_crypto_hmac_lock_release(void); + +/** + * @brief Acquire lock for DS cryptography peripheral + * + * Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals + */ +void esp_crypto_ds_lock_acquire(void); + +/** + * @brief Release lock for DS cryptography peripheral + * + * Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals + */ +void esp_crypto_ds_lock_release(void); + +/** + * @brief Acquire lock for the SHA and AES cryptography peripheral. + * + */ +void esp_crypto_sha_aes_lock_acquire(void); + +/** + * @brief Release lock for the SHA and AES cryptography peripheral. + * + */ +void esp_crypto_sha_aes_lock_release(void); + + +/** + * @brief Acquire lock for the mpi cryptography peripheral. + * + */ +void esp_crypto_mpi_lock_acquire(void); + +/** + * @brief Release lock for the mpi/rsa cryptography peripheral. + * + */ +void esp_crypto_mpi_lock_release(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp32h2/include/esp_ds.h b/components/esp32h2/include/esp_ds.h new file mode 100644 index 0000000000..911e44c837 --- /dev/null +++ b/components/esp32h2/include/esp_ds.h @@ -0,0 +1,218 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_hmac.h" +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL ESP_ERR_HW_CRYPTO_BASE + 0x1 /*!< HMAC peripheral problem */ +#define ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY ESP_ERR_HW_CRYPTO_BASE + 0x2 /*!< given HMAC key isn't correct, + HMAC peripheral problem */ +#define ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST ESP_ERR_HW_CRYPTO_BASE + 0x4 /*!< message digest check failed, + result is invalid */ +#define ESP32C3_ERR_HW_CRYPTO_DS_INVALID_PADDING ESP_ERR_HW_CRYPTO_BASE + 0x5 /*!< padding check failed, but result + is produced anyway and can be read*/ + +#define ESP_DS_IV_BIT_LEN 128 +#define ESP_DS_IV_LEN (ESP_DS_IV_BIT_LEN / 8) +#define ESP_DS_SIGNATURE_MAX_BIT_LEN 3072 +#define ESP_DS_SIGNATURE_MD_BIT_LEN 256 +#define ESP_DS_SIGNATURE_M_PRIME_BIT_LEN 32 +#define ESP_DS_SIGNATURE_L_BIT_LEN 32 +#define ESP_DS_SIGNATURE_PADDING_BIT_LEN 64 + +/* Length of parameter 'C' stored in flash, in bytes + - Operands Y, M and r_bar; each 3072 bits + - Operand MD (message digest); 256 bits + - Operands M' and L; each 32 bits + - Operand beta (padding value; 64 bits +*/ +#define ESP_DS_C_LEN (((ESP_DS_SIGNATURE_MAX_BIT_LEN * 3 \ + + ESP_DS_SIGNATURE_MD_BIT_LEN \ + + ESP_DS_SIGNATURE_M_PRIME_BIT_LEN \ + + ESP_DS_SIGNATURE_L_BIT_LEN \ + + ESP_DS_SIGNATURE_PADDING_BIT_LEN) / 8)) + +typedef struct esp_ds_context esp_ds_context_t; + +typedef enum { + ESP_DS_RSA_1024 = (1024 / 32) - 1, + ESP_DS_RSA_2048 = (2048 / 32) - 1, + ESP_DS_RSA_3072 = (3072 / 32) - 1 +} esp_digital_signature_length_t; + +/** + * Encrypted private key data. Recommended to store in flash in this format. + * + * @note This struct has to match to one from the ROM code! This documentation is mostly taken from there. + */ +typedef struct esp_digital_signature_data { + /** + * RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * Max value 127 (for RSA 3072). + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + * + * @note In IDF, the enum type length is the same as of type unsigned, so they can be used interchangably. + * See the ROM code for the original declaration of struct \c ets_ds_data_t. + */ + esp_digital_signature_length_t rsa_length; + + /** + * IV value used to encrypt 'c' + */ + uint32_t iv[ESP_DS_IV_BIT_LEN / 32]; + + /** + * Encrypted Digital Signature parameters. Result of AES-CBC encryption + * of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ESP_DS_C_LEN]; +} esp_ds_data_t; + +/** + * Plaintext parameters used by Digital Signature. + * + * This is only used for encrypting the RSA parameters by calling esp_ds_encrypt_params(). + * Afterwards, the result can be stored in flash or in other persistent memory. + * The encryption is a prerequisite step before any signature operation can be done. + */ +typedef struct { + uint32_t Y[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA exponent + uint32_t M[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA modulus + uint32_t Rb[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA r inverse operand + uint32_t M_prime; //!< RSA M prime operand + uint32_t length; //!< RSA length in words (32 bit) +} esp_ds_p_data_t; + +/** + * @brief Sign the message with a hardware key from specific key slot. + * + * This function is a wrapper around \c esp_ds_finish_sign() and \c esp_ds_start_sign(), so do not use them + * in parallel. + * It blocks until the signing is finished and then returns the signature. + * + * @note This function locks the HMAC, SHA, AES and RSA components during its entire execution time. + * + * @param message the message to be signed; its length is determined by data->rsa_length + * @param data the encrypted signing key data (AES encrypted RSA key + IV) + * @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the + * signing key data + * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long + * + * @return + * - ESP_OK if successful, the signature was written to the parameter \c signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0 + * - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key + * - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object + * - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component + * - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid. + * - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though + * since the message digest matches. + */ +esp_err_t esp_ds_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + void *signature); + +/** + * @brief Start the signing process. + * + * This function yields a context object which needs to be passed to \c esp_ds_finish_sign() to finish the signing + * process. + * + * @note This function locks the HMAC, SHA, AES and RSA components, so the user has to ensure to call + * \c esp_ds_finish_sign() in a timely manner. + * + * @param message the message to be signed; its length is determined by data->rsa_length + * @param data the encrypted signing key data (AES encrypted RSA key + IV) + * @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the + * signing key data + * @param esp_ds_ctx the context object which is needed for finishing the signing process later + * + * @return + * - ESP_OK if successful, the ds operation was started now and has to be finished with \c esp_ds_finish_sign() + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0 + * - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key + * - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object + * - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component + */ +esp_err_t esp_ds_start_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + esp_ds_context_t **esp_ds_ctx); + +/** + * Return true if the DS peripheral is busy, otherwise false. + * + * @note Only valid if \c esp_ds_start_sign() was called before. + */ +bool esp_ds_is_busy(void); + +/** + * @brief Finish the signing process. + * + * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long + * @param esp_ds_ctx the context object retreived by \c esp_ds_start_sign() + * + * @return + * - ESP_OK if successful, the ds operation has been finished and the result is written to signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL + * - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid. + * This means that the encrypted RSA key parameters are invalid, indicating that they may have been tampered + * with or indicating a flash error, etc. + * - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though + * since the message digest matches (see TRM for more details). + */ +esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx); + +/** + * @brief Encrypt the private key parameters. + * + * The encryption is a prerequisite step before any signature operation can be done. + * It is not strictly necessary to use this encryption function, the encryption could also happen on an external + * device. + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * The allocated memory must be in internal memory and word aligned since it's filled by DMA. Both is asserted + * at run time. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process + * is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the + * corresponding HMAC key will be stored to efuse and then permanently erased. + * + * @return + * - ESP_OK if successful, the ds operation has been finished and the result is written to signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or p_data->rsa_length is too long + */ +esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data, + const void *iv, + const esp_ds_p_data_t *p_data, + const void *key); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp32h2/include/esp_hmac.h b/components/esp32h2/include/esp_hmac.h new file mode 100644 index 0000000000..391ba12fe1 --- /dev/null +++ b/components/esp32h2/include/esp_hmac.h @@ -0,0 +1,67 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_HMAC_H_ +#define _ESP_HMAC_H_ + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The possible efuse keys for the HMAC peripheral + */ +typedef enum { + HMAC_KEY0 = 0, + HMAC_KEY1, + HMAC_KEY2, + HMAC_KEY3, + HMAC_KEY4, + HMAC_KEY5, + HMAC_KEY_MAX +} hmac_key_id_t; + +/** + * @brief + * Calculate the HMAC of a given message. + * + * Calculate the HMAC \c hmac of a given message \c message with length \c message_len. + * SHA256 is used for the calculation (fixed on ESP32S2). + * + * @note Uses the HMAC peripheral in "upstream" mode. + * + * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calcuation. + * The corresponding purpose field of the key block in the efuse must be set to the HMAC upstream purpose value. + * @param message the message for which to calculate the HMAC + * @param message_len message length + * return ESP_ERR_INVALID_STATE if unsuccessful + * @param [out] hmac the hmac result; the buffer behind the provided pointer must be 32 bytes long + * + * @return + * * ESP_OK, if the calculation was successful, + * * ESP_FAIL, if the hmac calculation failed + */ +esp_err_t esp_hmac_calculate(hmac_key_id_t key_id, + const void *message, + size_t message_len, + uint8_t *hmac); + +#ifdef __cplusplus +} +#endif + +#endif // _ESP_HMAC_H_ diff --git a/components/esp32h2/ld/esp32h2.ld b/components/esp32h2/ld/esp32h2.ld new file mode 100644 index 0000000000..63a26c4276 --- /dev/null +++ b/components/esp32h2/ld/esp32h2.ld @@ -0,0 +1,118 @@ +/** + * ESP32-C3 Linker Script Memory Layout + * This file describes the memory layout (memory blocks) by virtual memory addresses. + * This linker script is passed through the C preprocessor to include configuration options. + * Please use preprocessor features sparingly! + * Restrict to simple macros with numeric values, and/or #if/#endif blocks. + */ + +#include "sdkconfig.h" + +#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC +#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) +#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) +#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) +#else +#define ESP_BOOTLOADER_RESERVE_RTC 0 +#endif + +#define SRAM_IRAM_START 0x4037C000 +#define SRAM_DRAM_START 0x3FC7C000 +#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ +#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) +#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ + +#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) +#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) + +#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG + +#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE +ASSERT((CONFIG_ESP32C3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.") +#define DRAM0_0_SEG_LEN CONFIG_ESP3C3_FIXED_STATIC_RAM_SIZE +#else +#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE +#endif // CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE +MEMORY +{ + /** + * All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + * of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + * are connected to the data port of the CPU and eg allow byte-wise access. + */ + + /* IRAM for PRO CPU. */ + iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + /* Flash mapped instruction data */ + iram0_2_seg (RX) : org = 0x42000020, len = 0x8000000-0x20 + + /** + * (0x20 offset above is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB).) + */ +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + + /** + * Shared data RAM, excluding memory reserved for ROM bss/data/stack. + * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. + */ + dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + /* Flash mapped constant data */ + drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20 + + /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + + /** + * RTC fast memory (executable). Persists over deep sleep. + */ + rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC +} + +#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE +/* static data ends at defined address */ +_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN; +#else +_static_data_end = _bss_end; +#endif // CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE + +/* Heap ends at top of dram0_0_seg */ +_heap_end = 0x40000000; + +_data_seg_org = ORIGIN(rtc_data_seg); + +/** + * The lines below define location alias for .rtc.data section + * As C3 only has RTC fast memory, this is not configurable like on other targets + */ +REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_data_location", rtc_iram_seg ); + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + REGION_ALIAS("default_code_seg", iram0_2_seg); +#else + REGION_ALIAS("default_code_seg", iram0_0_seg); +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + REGION_ALIAS("default_rodata_seg", drom0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", dram0_0_seg); +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + +/** + * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must + * also be first in the segment. + */ +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), + ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") +#endif diff --git a/components/esp32h2/ld/esp32h2.peripherals.ld b/components/esp32h2/ld/esp32h2.peripherals.ld new file mode 100644 index 0000000000..49a57408c3 --- /dev/null +++ b/components/esp32h2/ld/esp32h2.peripherals.ld @@ -0,0 +1,30 @@ +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60010000 ); +PROVIDE ( SPIMEM1 = 0x60002000 ); +PROVIDE ( SPIMEM0 = 0x60003000 ); +PROVIDE ( GPIO = 0x60004000 ); +PROVIDE ( SIGMADELTA = 0x60004f00 ); +PROVIDE ( RTCCNTL = 0x60008000 ); +PROVIDE ( RTCIO = 0x60008400 ); +PROVIDE ( HINF = 0x6000B000 ); +PROVIDE ( I2S1 = 0x6002d000 ); +PROVIDE ( I2C0 = 0x60013000 ); +PROVIDE ( UHCI0 = 0x60014000 ); +PROVIDE ( UHCI1 = 0x6000c000 ); +PROVIDE ( HOST = 0x60015000 ); +PROVIDE ( RMT = 0x60016000 ); +PROVIDE ( RMTMEM = 0x60016400 ); +PROVIDE ( PCNT = 0x60017000 ); +PROVIDE ( SLC = 0x60018000 ); +PROVIDE ( LEDC = 0x60019000 ); +PROVIDE ( TIMERG0 = 0x6001F000 ); +PROVIDE ( TIMERG1 = 0x60020000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); +PROVIDE ( GPSPI2 = 0x60024000 ); +PROVIDE ( GPSPI3 = 0x60025000 ); +PROVIDE ( SYSCON = 0x60026000 ); +PROVIDE ( TWAI = 0x6002B000 ); +PROVIDE ( GPSPI4 = 0x60037000 ); +PROVIDE ( APB_SARADC = 0x60040000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x60043000 ); +PROVIDE ( GDMA = 0x6003F000 ); diff --git a/components/esp32h2/ld/esp32h2.project.ld.in b/components/esp32h2/ld/esp32h2.project.ld.in new file mode 100644 index 0000000000..58f27c9e19 --- /dev/null +++ b/components/esp32h2/ld/esp32h2.project.ld.in @@ -0,0 +1,392 @@ +/* Default entry point */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + /** + * RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + + mapping[rtc_text] + + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_text_end = ABSOLUTE(.); + } > rtc_iram_seg + + /** + * This section is required to skip rtc.text area because rtc_iram_seg and + * rtc_data_seg are reflect the same address space on different buses. + */ + .rtc.dummy : + { + _rtc_dummy_start = ABSOLUTE(.); + _rtc_fast_start = ABSOLUTE(.); + . = SIZEOF(.rtc.text); + _rtc_dummy_end = ABSOLUTE(.); + } > rtc_data_seg + + /** + * This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + mapping[rtc_force_fast] + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } > rtc_data_seg + + /** + * RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + * The memory location of the data is dependent on + * CONFIG_ESP32C3_RTCDATA_IN_FAST_MEM option. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + + mapping[rtc_data] + + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } > rtc_data_location + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + mapping[rtc_bss] + + _rtc_bss_end = ABSOLUTE(.); + } > rtc_data_location + + /** + * This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + * The memory location of the data is dependent on CONFIG_ESP32C3_RTCDATA_IN_FAST_MEM option. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } > rtc_data_location + + /** + * This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_slow_end - _rtc_data_start) + : (_rtc_force_slow_end - _rtc_force_slow_start); + + _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_fast_end - _rtc_fast_start) + : (_rtc_noinit_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), + "RTC_SLOW segment data does not fit.") + + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), + "RTC_FAST segment data does not fit.") + + .iram0.text : + { + _iram_start = ABSOLUTE(.); + /* Vectors go to start of IRAM */ + ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + _invalid_pc_placeholder = ABSOLUTE(.); + + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + + mapping[iram0_text] + + } > iram0_0_seg + + /** + * This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } > dram0_0_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + + _esp_system_init_fn_array_start = ABSOLUTE(.); + KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); + + mapping[dram0_data] + + _data_end = ABSOLUTE(.); + . = ALIGN(4); + } > dram0_0_seg + + /** + * This section holds data that should not be initialized at power up. + * The section located in Internal SRAM memory region. The macro _NOINIT + * can be used as attribute to place data into this section. + * See the "esp_attr.h" file for more information. + */ + .noinit (NOLOAD): + { + . = ALIGN(4); + _noinit_start = ABSOLUTE(.); + *(.noinit .noinit.*) + . = ALIGN(4) ; + _noinit_end = ABSOLUTE(.); + } > dram0_0_seg + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + + mapping[dram0_bss] + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } > dram0_0_seg + + ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + .flash.text : + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + _text_start = ABSOLUTE(.); + + mapping[flash_text] + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); + _etext = .; + + /** + * Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > default_code_seg + + /** + * This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignement and (at least) its size. + */ + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = .; + /* Start at the same alignement constraint than .flash.text */ + . = ALIGN(ALIGNOF(.flash.text)); + /* Create an empty gap as big as .flash.text section */ + . = . + SIZEOF(.flash.text); + /* Prepare the alignement of the section above. Few bytes (0x20) must be + * added for the mapping header. */ + . = ALIGN(0x10000) + 0x20; + _rodata_reserved_start = .; + } > default_rodata_seg + + .flash.appdesc : ALIGN(0x10) + { + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + + .flash.rodata : ALIGN(0x10) + { + _flash_rodata_start = ABSOLUTE(.); + + mapping[flash_rodata] + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + /* + * C++ constructor and destructor tables + * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt. + * + * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead. + * But the init_priority sections will be sorted for iteration in ascending order during startup. + * The rest of the init_array sections is sorted for iteration in descending order during startup, however. + * Hence a different section is generated for the init_priority functions which is iterated in + * ascending order during startup. The corresponding code can be found in startup.c. + */ + __init_priority_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + __init_priority_array_end = ABSOLUTE(.); + __init_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ + soc_reserved_memory_region_start = ABSOLUTE(.); + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + *(.srodata) + *(.srodata.*) + _thread_local_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN(4); + } > default_rodata_seg + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* C3 memprot requires 512 B alignment for split lines */ + . = ALIGN (0x200); + /* iram_end_test section exists for use by memprot unit tests only */ + *(.iram_end_test) + _iram_text_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + _iram_data_start = ABSOLUTE(.); + + mapping[iram0_data] + + _iram_data_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + _iram_bss_start = ABSOLUTE(.); + + mapping[iram0_bss] + + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } > iram0_0_seg + + /* Marks the end of data, bss and possibly rodata */ + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (16); + _heap_start = ABSOLUTE(.); + } > dram0_0_seg +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") diff --git a/components/esp32h2/memprot.c b/components/esp32h2/memprot.c new file mode 100644 index 0000000000..20cc054ad5 --- /dev/null +++ b/components/esp32h2/memprot.c @@ -0,0 +1,616 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* INTERNAL API + * implementation of PMS memory protection features + */ + +#include +#include "sdkconfig.h" +#include "soc/sensitive_reg.h" +#include "soc/dport_access.h" +#include "soc/periph_defs.h" +#include "esp_intr_alloc.h" +#include "hal/memprot_ll.h" +#include "esp32c3/memprot.h" +#include "riscv/interrupt.h" +#include "esp32c3/rom/ets_sys.h" +#include "esp_log.h" + +extern int _iram_text_end; +static const char *TAG = "memprot"; + +const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type) +{ + switch (mem_type) { + case MEMPROT_NONE: + return "NONE"; + case MEMPROT_IRAM0_SRAM: + return "IRAM0_SRAM"; + case MEMPROT_DRAM0_SRAM: + return "DRAM0_SRAM"; + case MEMPROT_ALL: + return "ALL"; + default: + return "UNKNOWN"; + } +} + +const char *esp_memprot_split_line_to_str(split_line_t line_type) +{ + switch (line_type) { + case MEMPROT_IRAM0_DRAM0_SPLITLINE: + return "MEMPROT_IRAM0_DRAM0_SPLITLINE"; + case MEMPROT_IRAM0_LINE_0_SPLITLINE: + return "MEMPROT_IRAM0_LINE_0_SPLITLINE"; + case MEMPROT_IRAM0_LINE_1_SPLITLINE: + return "MEMPROT_IRAM0_LINE_1_SPLITLINE"; + case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE: + return "MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE"; + case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE: + return "MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE"; + default: + return "UNKNOWN"; + } +} + +const char *esp_memprot_pms_to_str(pms_area_t area_type) +{ + switch (area_type) { + case MEMPROT_IRAM0_PMS_AREA_0: + return "MEMPROT_IRAM0_PMS_AREA_0"; + case MEMPROT_IRAM0_PMS_AREA_1: + return "MEMPROT_IRAM0_PMS_AREA_1"; + case MEMPROT_IRAM0_PMS_AREA_2: + return "MEMPROT_IRAM0_PMS_AREA_2"; + case MEMPROT_IRAM0_PMS_AREA_3: + return "MEMPROT_IRAM0_PMS_AREA_3"; + case MEMPROT_DRAM0_PMS_AREA_0: + return "MEMPROT_DRAM0_PMS_AREA_0"; + case MEMPROT_DRAM0_PMS_AREA_1: + return "MEMPROT_DRAM0_PMS_AREA_1"; + case MEMPROT_DRAM0_PMS_AREA_2: + return "MEMPROT_DRAM0_PMS_AREA_2"; + case MEMPROT_DRAM0_PMS_AREA_3: + return "MEMPROT_DRAM0_PMS_AREA_3"; + default: + return "UNKNOWN"; + } +} + + +/* split lines */ + +void *esp_memprot_get_default_main_split_addr() +{ + return &_iram_text_end; +} + +uint32_t *esp_memprot_get_split_addr(split_line_t line_type) +{ + switch ( line_type ) { + case MEMPROT_IRAM0_DRAM0_SPLITLINE: + return memprot_ll_get_iram0_split_line_main_I_D(); + case MEMPROT_IRAM0_LINE_0_SPLITLINE: + return memprot_ll_get_iram0_split_line_I_0(); + case MEMPROT_IRAM0_LINE_1_SPLITLINE: + return memprot_ll_get_iram0_split_line_I_1(); + case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE: + return memprot_ll_get_dram0_split_line_D_0(); + case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE: + return memprot_ll_get_dram0_split_line_D_1(); + default: + abort(); + } +} + +void esp_memprot_set_split_line_lock() +{ + memprot_ll_set_iram0_dram0_split_line_lock(); +} + +bool esp_memprot_get_split_line_lock() +{ + return memprot_ll_get_iram0_dram0_split_line_lock(); +} + +void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr) +{ + ESP_EARLY_LOGD(TAG, "Setting split line %s, addr: 0x%08X", esp_memprot_split_line_to_str(line_type), (uint32_t)line_addr); + + //split-line must be divisible by 512 (PMS module restriction) + assert( ((uint32_t)line_addr) % 0x200 == 0 ); + + switch ( line_type ) { + case MEMPROT_IRAM0_DRAM0_SPLITLINE: + memprot_ll_set_iram0_split_line_main_I_D(line_addr); + break; + case MEMPROT_IRAM0_LINE_0_SPLITLINE: + memprot_ll_set_iram0_split_line_I_0(line_addr); + break; + case MEMPROT_IRAM0_LINE_1_SPLITLINE: + memprot_ll_set_iram0_split_line_I_1(line_addr); + break; + case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE: + memprot_ll_set_dram0_split_line_D_0(line_addr); + break; + case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE: + memprot_ll_set_dram0_split_line_D_1(line_addr); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid split line type, aborting: 0x%08X", (uint32_t)line_addr); + abort(); + } +} + + +/* PMS */ + +void esp_memprot_set_pms_lock(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_set_pms_lock(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + memprot_ll_iram0_set_pms_lock(); + break; + case MEMPROT_DRAM0_SRAM: + memprot_ll_dram0_set_pms_lock(); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_get_pms_lock(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_pms_lock(); + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_pms_lock(); + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_iram_set_pms_area(area:%s r:%u w:%u, x:%u)", esp_memprot_pms_to_str(area_type), r, w, x); + + switch ( area_type ) { + case MEMPROT_IRAM0_PMS_AREA_0: + memprot_ll_iram0_set_pms_area_0(r, w, x); + break; + case MEMPROT_IRAM0_PMS_AREA_1: + memprot_ll_iram0_set_pms_area_1(r, w, x); + break; + case MEMPROT_IRAM0_PMS_AREA_2: + memprot_ll_iram0_set_pms_area_2(r, w, x); + break; + case MEMPROT_IRAM0_PMS_AREA_3: + memprot_ll_iram0_set_pms_area_3(r, w, x); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid area_type %d", esp_memprot_pms_to_str(area_type)); + abort(); + } +} + +void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_iram_get_pms_area(area:%s r:%u w:%u)", esp_memprot_pms_to_str(area_type), r, w); + + switch ( area_type ) { + case MEMPROT_IRAM0_PMS_AREA_0: + memprot_ll_iram0_get_pms_area_0(r, w, x); + break; + case MEMPROT_IRAM0_PMS_AREA_1: + memprot_ll_iram0_get_pms_area_1(r, w, x); + break; + case MEMPROT_IRAM0_PMS_AREA_2: + memprot_ll_iram0_get_pms_area_2(r, w, x); + break; + case MEMPROT_IRAM0_PMS_AREA_3: + memprot_ll_iram0_get_pms_area_3(r, w, x); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid area_type %d", esp_memprot_pms_to_str(area_type)); + abort(); + } +} + +void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_dram_set_pms_area(area:%s r:%u w:%u)", esp_memprot_pms_to_str(area_type), r, w); + + switch ( area_type ) { + case MEMPROT_DRAM0_PMS_AREA_0: + memprot_ll_dram0_set_pms_area_0(r, w); + break; + case MEMPROT_DRAM0_PMS_AREA_1: + memprot_ll_dram0_set_pms_area_1(r, w); + break; + case MEMPROT_DRAM0_PMS_AREA_2: + memprot_ll_dram0_set_pms_area_2(r, w); + break; + case MEMPROT_DRAM0_PMS_AREA_3: + memprot_ll_dram0_set_pms_area_3(r, w); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid area_type %d", esp_memprot_pms_to_str(area_type)); + abort(); + } +} + +void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_dram_get_pms_area(area:%s r:%u w:%u)", esp_memprot_pms_to_str(area_type), r, w); + + switch ( area_type ) { + case MEMPROT_DRAM0_PMS_AREA_0: + memprot_ll_dram0_get_pms_area_0(r, w); + break; + case MEMPROT_DRAM0_PMS_AREA_1: + memprot_ll_dram0_get_pms_area_1(r, w); + break; + case MEMPROT_DRAM0_PMS_AREA_2: + memprot_ll_dram0_get_pms_area_2(r, w); + break; + case MEMPROT_DRAM0_PMS_AREA_3: + memprot_ll_dram0_get_pms_area_3(r, w); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid area_type %d", esp_memprot_pms_to_str(area_type)); + abort(); + } +} + + +/* monitor */ + +void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_set_monitor_lock(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + memprot_ll_iram0_set_monitor_lock(); + break; + case MEMPROT_DRAM0_SRAM: + memprot_ll_dram0_set_monitor_lock(); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_get_monitor_lock(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_lock(); + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_lock(); + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_set_monitor_en(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + memprot_ll_iram0_set_monitor_en(enable); + break; + case MEMPROT_DRAM0_SRAM: + memprot_ll_dram0_set_monitor_en(enable); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_set_monitor_en(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_en(); + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_en(); + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +bool esp_memprot_is_intr_ena_any() +{ + return esp_memprot_get_monitor_en(MEMPROT_IRAM0_SRAM) || esp_memprot_get_monitor_en(MEMPROT_DRAM0_SRAM); +} + +void esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_monitor_clear_intr(%s)", esp_memprot_mem_type_to_str(mem_type)); + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + memprot_ll_iram0_clear_monitor_intr(); + memprot_ll_iram0_reset_clear_monitor_intr(); + break; + case MEMPROT_DRAM0_SRAM: + memprot_ll_dram0_clear_monitor_intr(); + memprot_ll_dram0_reset_clear_monitor_intr(); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +mem_type_prot_t esp_memprot_get_active_intr_memtype() +{ + if ( memprot_ll_iram0_get_monitor_status_intr() > 0 ) { + return MEMPROT_IRAM0_SRAM; + } else if ( memprot_ll_dram0_get_monitor_status_intr() ) { + return MEMPROT_DRAM0_SRAM; + } + + return MEMPROT_NONE; +} + +bool esp_memprot_is_locked_any() +{ + return + esp_memprot_get_split_line_lock() || + esp_memprot_get_pms_lock(MEMPROT_IRAM0_SRAM) || + esp_memprot_get_pms_lock(MEMPROT_DRAM0_SRAM) || + esp_memprot_get_monitor_lock(MEMPROT_IRAM0_SRAM) || + esp_memprot_get_monitor_lock(MEMPROT_DRAM0_SRAM); +} + +bool esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type) +{ + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_status_intr() == 1; + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_status_intr() == 1; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +uint32_t esp_memprot_get_violate_addr(mem_type_prot_t mem_type) +{ + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_status_fault_addr(); + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_status_fault_addr(); + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +pms_world_t esp_memprot_get_violate_world(mem_type_prot_t mem_type) +{ + uint32_t world = 0; + + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + world = memprot_ll_iram0_get_monitor_status_fault_world(); + break; + case MEMPROT_DRAM0_SRAM: + world = memprot_ll_dram0_get_monitor_status_fault_world(); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } + + switch ( world ) { + case 0x01: return MEMPROT_PMS_WORLD_0; + case 0x10: return MEMPROT_PMS_WORLD_1; + default: return MEMPROT_PMS_WORLD_INVALID; + } +} + +pms_operation_type_t esp_memprot_get_violate_wr(mem_type_prot_t mem_type) +{ + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_status_fault_wr() == 1 ? MEMPROT_PMS_OP_WRITE : MEMPROT_PMS_OP_READ; + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_status_fault_wr() == 1 ? MEMPROT_PMS_OP_WRITE : MEMPROT_PMS_OP_READ; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +bool esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type) +{ + switch ( mem_type ) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_status_fault_loadstore() == 1; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +uint32_t esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type) +{ + switch ( mem_type ) { + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_status_fault_byte_en(); + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } +} + +int esp_memprot_intr_get_cpuid() +{ + return PRO_CPU_NUM; +} + +void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_set_intr_matrix(%s)", esp_memprot_mem_type_to_str(mem_type)); + + ESP_INTR_DISABLE(ETS_MEMPROT_ERR_INUM); + + switch (mem_type) { + case MEMPROT_IRAM0_SRAM: + intr_matrix_set(esp_memprot_intr_get_cpuid(), memprot_ll_iram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM); + break; + case MEMPROT_DRAM0_SRAM: + intr_matrix_set(esp_memprot_intr_get_cpuid(), memprot_ll_dram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM); + break; + default: + ESP_EARLY_LOGE(TAG, "Invalid mem_type (%s), aborting", esp_memprot_mem_type_to_str(mem_type)); + abort(); + } + + /* Set the type and priority to cache error interrupts. */ + esprv_intc_int_set_type(BIT(ETS_MEMPROT_ERR_INUM), INTR_TYPE_LEVEL); + esprv_intc_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); + + ESP_INTR_ENABLE(ETS_MEMPROT_ERR_INUM); +} + +void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask) +{ + esp_memprot_set_prot_int(invoke_panic_handler, lock_feature, NULL, mem_type_mask); +} + +void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask) +{ + ESP_EARLY_LOGD(TAG, "esp_memprot_set_prot(panic_handler: %u, lock: %u, split.addr: 0x%08X, mem.types: 0x%08X", invoke_panic_handler, lock_feature, (uint32_t)split_addr, (uint32_t)mem_type_mask); + + uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask; + bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM; + bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM; + + if (required_mem_prot == MEMPROT_NONE) { + return; + } + + //disable protection + if (use_iram0) { + esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, false); + } + if (use_dram0) { + esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, false); + } + + //panic handling + if (invoke_panic_handler) { + if (use_iram0) { + esp_memprot_set_intr_matrix(MEMPROT_IRAM0_SRAM); + } + if (use_dram0) { + esp_memprot_set_intr_matrix(MEMPROT_DRAM0_SRAM); + } + } + + //set split lines (must-have for all mem_types) + const void *line_addr = split_addr == NULL ? esp_memprot_get_default_main_split_addr() : split_addr; + esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_1_SPLITLINE, line_addr); + esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_0_SPLITLINE, line_addr); + esp_memprot_set_split_line(MEMPROT_IRAM0_DRAM0_SPLITLINE, line_addr); + esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr))); + esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr))); + + //set permissions + if (required_mem_prot & MEMPROT_IRAM0_SRAM) { + esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, true, false, true); + esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, true, false, true); + esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, true, false, true); + esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, true, true, false); + } + if (required_mem_prot & MEMPROT_DRAM0_SRAM) { + esp_memprot_dram_set_pms_area( MEMPROT_DRAM0_PMS_AREA_0, true, false ); + esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, true, true); + esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, true, true); + esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, true, true); + } + + //reenable protection + if (use_iram0) { + esp_memprot_monitor_clear_intr(MEMPROT_IRAM0_SRAM); + esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, true); + } + if (use_dram0) { + esp_memprot_monitor_clear_intr(MEMPROT_DRAM0_SRAM); + esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, true); + } + + //lock if required + if (lock_feature) { + esp_memprot_set_split_line_lock(); + if (use_iram0) { + esp_memprot_set_pms_lock(MEMPROT_IRAM0_SRAM); + esp_memprot_set_monitor_lock(MEMPROT_IRAM0_SRAM); + } + if (use_dram0) { + esp_memprot_set_pms_lock(MEMPROT_DRAM0_SRAM); + esp_memprot_set_monitor_lock(MEMPROT_DRAM0_SRAM); + } + } +} + +uint32_t esp_memprot_get_dram_status_reg_1() +{ + return memprot_ll_dram0_get_monitor_status_register_1(); +} + +uint32_t esp_memprot_get_dram_status_reg_2() +{ + return memprot_ll_dram0_get_monitor_status_register_2(); +} + +uint32_t esp_memprot_get_iram_status_reg() +{ + return memprot_ll_iram0_get_monitor_status_register(); +} + +uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type) +{ + switch (mem_type) { + case MEMPROT_IRAM0_SRAM: + return memprot_ll_iram0_get_monitor_enable_register(); + case MEMPROT_DRAM0_SRAM: + return memprot_ll_dram0_get_monitor_enable_register(); + default: + abort(); + } +} diff --git a/components/esp32h2/project_include.cmake b/components/esp32h2/project_include.cmake new file mode 100644 index 0000000000..98d8425094 --- /dev/null +++ b/components/esp32h2/project_include.cmake @@ -0,0 +1,5 @@ +set(compile_options "-Wno-error=format=" + "-nostartfiles" + "-Wno-format") + +idf_build_set_property(COMPILE_OPTIONS "${compile_options}" APPEND) diff --git a/components/esp32h2/test/CMakeLists.txt b/components/esp32h2/test/CMakeLists.txt new file mode 100644 index 0000000000..068a0a8549 --- /dev/null +++ b/components/esp32h2/test/CMakeLists.txt @@ -0,0 +1,9 @@ +if(IDF_TARGET STREQUAL "esp32c3") + idf_component_register(SRC_DIRS . + INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR} + REQUIRES unity test_utils esp_common mbedtls + ) + + idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5") +endif() diff --git a/components/esp32h2/test/component.mk b/components/esp32h2/test/component.mk new file mode 100644 index 0000000000..d2183390cc --- /dev/null +++ b/components/esp32h2/test/component.mk @@ -0,0 +1,4 @@ +# +# Component Makefile (not used for tests, but CI checks test parity between GNU Make & CMake) +# +COMPONENT_CONFIG_ONLY := 1 diff --git a/components/esp32h2/test/digital_signature_test_cases.h b/components/esp32h2/test/digital_signature_test_cases.h new file mode 100644 index 0000000000..c3f792a703 --- /dev/null +++ b/components/esp32h2/test/digital_signature_test_cases.h @@ -0,0 +1,166 @@ +/* File generated by gen_digital_signature_tests.py */ + +#define NUM_HMAC_KEYS 3 + +static const uint8_t test_hmac_keys[NUM_HMAC_KEYS][32] = { + { 0xe9, 0x6b, 0xb6, 0x8c, 0xdf, 0x02, 0xb3, 0xbb, 0x30, 0x6e, 0x3e, 0xde, 0x4d, 0x06, 0xd5, 0xa6, 0x5a, 0x1e, 0x22, 0x72, 0x60, 0x51, 0xf2, 0xdc, 0x3e, 0x1a, 0x97, 0xbd, 0x85, 0x9e, 0x1f, 0x4b }, + { 0x2a, 0x0d, 0x2e, 0x90, 0xd3, 0xd8, 0xb5, 0x90, 0xbb, 0xad, 0xc1, 0x4b, 0x97, 0x17, 0xc8, 0xb0, 0x4a, 0x5d, 0xb0, 0x33, 0xcc, 0xcf, 0x1d, 0xb7, 0x1d, 0x54, 0x59, 0x4b, 0x65, 0x77, 0xca, 0x31 }, + { 0x17, 0xd2, 0xac, 0x49, 0xd0, 0x02, 0x4f, 0xa8, 0x50, 0x68, 0x4f, 0x26, 0x07, 0xab, 0xa4, 0xf2, 0x7a, 0x55, 0x93, 0xa9, 0xd8, 0xf3, 0xf4, 0x8d, 0x66, 0x1a, 0xd9, 0x47, 0x05, 0x8c, 0x3d, 0xc5 }, +}; + +#define NUM_MESSAGES 10 + +static const uint32_t test_messages[NUM_MESSAGES][3072/32] = { + // Message 0 + { 0x61a4307a, 0xb5212a2d, 0x8ce4edab, 0x41aee467, 0xbb0f04e1, 0xc401caba, 0xc15314af, 0xa77dd076, 0x40737bcc, 0xdc2337b4, 0x960d5e6e, 0x246f04cd, 0xa797ced0, 0xb190f869, 0x2265d916, 0xed9b5a7c, 0x8b517b85, 0xfbb2f9b6, 0x1e9dac5c, 0x1d11f51f, 0x711c4768, 0x3673409e, 0x7d53947a, 0x394b4c1e, 0xa104f8dd, 0x052b1228, 0x1d2fdf2d, 0x4adae364, 0xbe6e9af4, 0x1464ab12, 0x21b893d7, 0xa86b0b4a, 0xadd9f352, 0x7cf85150, 0x81ed50e1, 0x9f222ba3, 0x3e7c11e8, 0xd33968dd, 0xad0a2bc4, 0x99d821ba, 0x766254d6, 0x374f7b9d, 0x1b42bfc4, 0x4056202b, 0x9f99ade0, 0x64992ccf, 0x83b63a2c, 0xc258dcda, 0xdfcfba84, 0x1838733e, 0xd4ecd0f1, 0x3bce6ed0, 0xa2e9cd31, 0x4dfc7fa3, 0x2ddcf100, 0xcdb55d7f, 0x4471fc6b, 0x61bd72ce, 0xb03c1b39, 0xda9819fe, 0x24867d1e, 0x11d5f0be, 0x8dc55f04, 0xfe2324bc, 0x6baaa09a, 0x917df79b, 0xa7e15752, 0x66b2fb81, 0x35645306, 0x79e9dc02, 0x46db9117, 0x5ad04c28, 0x168399cd, 0x6f840a76, 0x9b312a32, 0x12457c89, 0x67381a7d, 0x1e6b4553, 0x2f0565c3, 0xaff56d33, 0x31b11b26, 0xc7a0a0f6, 0xe7621c2f, 0x73682d12, 0x2d66bffd, 0x0f987b3a, 0xb8e160c0, 0xc9938786, 0x10f5c069, 0x466d6b2a, 0x7707751d, 0x09a13317, 0x0b38216c, 0x357c2702, 0x992ca210, 0x6b243a1f }, + // Message 1 + { 0xd42ba4c2, 0xb72ba863, 0xf8a41113, 0x6bb4083a, 0x47f6f6de, 0x5dbe9651, 0x9d73e657, 0x81162f15, 0x09fca18e, 0xa74f5812, 0xbae98d6f, 0x2ff600dd, 0x983c0943, 0x3592cb5c, 0x81522349, 0x5641adda, 0x0207b8a7, 0xa17e00e5, 0xc826e303, 0xca0a8485, 0xb3c2998e, 0x086ff876, 0x2fcbfe2e, 0xf7089b8c, 0x8663f17d, 0x50a0387d, 0x2de358c1, 0xcfaf96d2, 0x8939037b, 0x14745d7f, 0x1ab6f3c6, 0x72dfbcfe, 0x931983a3, 0x1a336770, 0x5051932c, 0x5917b474, 0x03b7cdd9, 0x8e5d0641, 0x138881c2, 0xe369136f, 0x96281950, 0xe3c47787, 0xae0009db, 0x9b3b5127, 0x38a5189b, 0xf6ad7f13, 0x3786a34a, 0x6ef328a6, 0x3777aa66, 0x22a9bde2, 0x4e9717bb, 0xbb642837, 0x5a188508, 0x5728e9ff, 0xdce1bc9f, 0x55300b1e, 0x64820e38, 0xa21607d0, 0x7c7745f2, 0xdfb33bdf, 0xef386298, 0x0ba814ac, 0xb6a14369, 0x810f036e, 0xe78a321b, 0x23d4a745, 0x73a99f61, 0x2638d9b6, 0x11ab8653, 0x75c6739b, 0x1a8dcd5a, 0x7d7c168b, 0x7e2da09c, 0x84c82b0a, 0x7db3fad2, 0xb253751e, 0x1b5c5741, 0xb76c407a, 0xdeadf688, 0x47844f16, 0x42de3462, 0x462feadb, 0xeadf6987, 0x86a75e14, 0xcc225702, 0x746a1aa9, 0x879d526e, 0x93bfce3e, 0xa5ce21dc, 0xf7339d30, 0xe2a5ef53, 0xaff1baf1, 0x5990e0c4, 0xa3469c61, 0x0a6955d2, 0x9e4c5662 }, + // Message 2 + { 0x2f4095ca, 0x8efe451c, 0x7da3dfb1, 0x7345ee0e, 0xec6f3731, 0x7a0c52c1, 0xba9fdd4c, 0x6c92569c, 0x908189ce, 0x57a5d1ab, 0xacde22f1, 0x4e142237, 0xcbad527c, 0x82285cf2, 0x465e0d1b, 0xe1da157a, 0x9d97cecc, 0x99aee64c, 0xe5bb298b, 0x1e92985c, 0xb6cff476, 0x80249bf9, 0x96cf733d, 0x282a6055, 0x550d73b2, 0x7bb152fb, 0x9b408e06, 0x959a573f, 0x8d0cd0b6, 0x9fd0bf0f, 0xdcdc263b, 0xab2dd3c0, 0xf11ade9f, 0x5b9cad6c, 0x7b97b69c, 0xa794737f, 0x479259b6, 0x137703df, 0x6579045d, 0x66836a98, 0xf53ab66f, 0x6c94f3ac, 0x4d809db5, 0x42c875d4, 0x3a4fb6ce, 0x712bb0ce, 0xf4c70c20, 0xfb637da4, 0xb8bc930c, 0x7aec739a, 0x7e12fa26, 0x693409b4, 0xd677a39d, 0x75f1d20d, 0xd02599fb, 0x12c66e6e, 0x40fc6f76, 0x8680a9e2, 0xa634cbe1, 0x84315b4f, 0x552af83c, 0x2e03d541, 0x209487ca, 0x232acc4e, 0x625cbae5, 0x96671538, 0x9a93a5ee, 0x4e3f94c4, 0x5e10627d, 0x427738b7, 0xc3de7dce, 0x52d78deb, 0x28c0542b, 0x2b806fff, 0xf378ea2c, 0xde81e1a1, 0x505bdd67, 0xc59decea, 0xdbc2be17, 0x2ac69402, 0xb61bd2f2, 0x77b8e289, 0xf2183444, 0x6d2000a9, 0xaadd9a42, 0x31d5779f, 0xf5f2d425, 0x7d40e97f, 0xf7856359, 0x7e470cdc, 0x24734042, 0x12e2ddf4, 0xf01a797c, 0xdc4baefc, 0x4a7c042b, 0x7396067e }, + // Message 3 + { 0x917e5082, 0x13f64a35, 0x5e2270c2, 0xef2f8a79, 0xd210f3ba, 0x726f0e6b, 0x9dfe4069, 0xc1a11cc4, 0x1abd4ee9, 0xd7838339, 0xcccb8ad0, 0xaf3c82f1, 0x7f472e18, 0x9a8d8c28, 0x63aee513, 0xb4a33ddd, 0xc87813b9, 0xe88dc9f7, 0x681226c2, 0x5faa8a1a, 0xbaec0aac, 0xf47933f7, 0x784083d2, 0x12e06efc, 0xc57e7cc5, 0x16574609, 0x3ce4e167, 0x3e78f75e, 0xdb9dce1b, 0xaf865934, 0x610268f4, 0xce4279d3, 0xb51e6d56, 0x9738e007, 0xc2206e8f, 0x0c536b7e, 0x6fd1f9ea, 0x248eeb3c, 0x2bae513e, 0x8e8dd6fd, 0xd954c182, 0xae05b6a6, 0x9db3cc95, 0x8275bfdb, 0xf2727628, 0x24772152, 0x8e66cebc, 0x99846119, 0x09769bc5, 0xf097c12d, 0x5895ae15, 0x77113cde, 0x1ecdbe69, 0x62368adb, 0x715239ab, 0x4f33390c, 0xe73ba79c, 0x433c7b9f, 0xb994555f, 0x9dd7d3d7, 0x30e166c5, 0x42c1a712, 0x213376b6, 0x909eb93c, 0x428e8cc7, 0xdf0a4d1c, 0xf3c1564a, 0xd564bdda, 0xb43d7bfc, 0x2e5c60b2, 0x3ea8aa24, 0xfb3cf719, 0x78a57cf0, 0x60ed7608, 0x5ebbc190, 0x131216dc, 0x838b7b71, 0x03b95f01, 0x0ff925b3, 0x4a2cd710, 0xdcbe06b5, 0x2b5ec2d3, 0xdb0d240c, 0x8a1cdeaf, 0xed4de87c, 0x60479fdb, 0xf09531e0, 0x71c379eb, 0xb1d1218d, 0xeb732ba7, 0x7288e278, 0x3a02ee89, 0xd0165697, 0xc191ba5e, 0xe7453137, 0x488a087f }, + // Message 4 + { 0xdb9ccaa7, 0x101c5cff, 0xefc0eea1, 0xf9e22fd6, 0x2c09bc6d, 0x66520e52, 0x7da40463, 0x70de90ba, 0xa62ce3e1, 0x9a3fdb72, 0x067d95f1, 0x88ee7925, 0xfd393999, 0x08caf7ca, 0x06b09412, 0xe91e79f3, 0xf5e1357a, 0x3517bf29, 0x23f7bbc0, 0xa91489a8, 0x6b2de727, 0x9fcf3874, 0x04bd8abe, 0xf2db587e, 0x441d949a, 0x3cf2117e, 0x89b0f140, 0x8e669231, 0x2b303ce4, 0x9da0b7e8, 0x70b544ac, 0x99184be5, 0x8faa6790, 0x68a74c57, 0x4dfbf323, 0x8ad801ab, 0x2e01aefa, 0x6f18867c, 0x8cdc221a, 0x96d9441f, 0xb0d24aaf, 0xb757fb28, 0x1b6fc477, 0x8a995bf3, 0x2479ca42, 0x7592128f, 0x2c7cd48a, 0xc5234043, 0x9f74abc8, 0x0c97652a, 0x3607328c, 0xe83532d8, 0xb8f6f974, 0x6c31a52a, 0x3cd0c8d3, 0xe1589046, 0xa6c89031, 0xa49bf26b, 0x44042d46, 0xb04ebfb3, 0x4b7b9c89, 0xfada8863, 0xce3efd26, 0x3853508a, 0x10950750, 0x414342e0, 0x06aaacc7, 0xf272f1eb, 0x8edc53ae, 0xea5ecd67, 0x0eed9fa1, 0x847cc975, 0x2297295c, 0x9b2bcd4b, 0x7a4bf31f, 0x15052c86, 0x02d3df12, 0x31f26ec6, 0xd4211f29, 0x1a971126, 0x078fe6b0, 0xffc2a7f8, 0x662718dd, 0xc443497c, 0xb68ae26b, 0x71ebc3b6, 0xf3b01818, 0x6a0a1081, 0xdae6fd77, 0xb2378d84, 0x3b5a6f5a, 0xe4eee13c, 0x6aec9bcd, 0xabf2f290, 0x811d26f7, 0xcddf9619 }, + // Message 5 + { 0x514bc7ba, 0xec9e2313, 0x9009fa0f, 0x3f6b2d80, 0x4269ea0b, 0xe3c94974, 0xda55e172, 0x2dbdef26, 0x8b51ccf8, 0xa38ea841, 0x90277332, 0xd1324248, 0xb27d4f19, 0xd42fb058, 0x57365f75, 0x223269b4, 0x0ddf88a6, 0x7b34dfd5, 0xf68e657a, 0x1b48e3f6, 0x978ebb87, 0x47cbe8a8, 0xd43465d0, 0x26e98bd3, 0x2b8cd579, 0x40457d8b, 0x98ece830, 0xac71ecc2, 0xabd77ae2, 0x23d7189f, 0x0cb3f24e, 0xfb5410e9, 0x363da25c, 0xcf07f7b6, 0xf19d26ab, 0xcf014f57, 0xa7b5be5a, 0xb63eecb8, 0xb0e91511, 0x3d21a5b3, 0x1113fb8f, 0x0dcb9293, 0xd13bcfd9, 0xdfddc856, 0xdb5265b8, 0xa0eceb45, 0xfa3ae3ed, 0xef940ebb, 0x5509e00b, 0x7d5cefc2, 0xb2377a00, 0x91459512, 0xb20dd7b7, 0x13c62ff0, 0x65c0293d, 0x0a2b320e, 0x3309dac7, 0x2de3c065, 0x6c16078e, 0xf7087e94, 0x8eae3339, 0xf044f4fb, 0x71a5e6a5, 0xc7345dad, 0xf5b284ec, 0xf6e64f4f, 0xd3ef5c6a, 0x0d051a21, 0xef8d2222, 0xd65a3862, 0xdfaed1b7, 0x10845a98, 0x121580b3, 0x3683ff2f, 0x718b6645, 0x29b8ad40, 0xb32c397a, 0x243e0c99, 0x016110d6, 0x82fcc51c, 0x7ee093d1, 0xba24cbb6, 0x294d9a43, 0xa4c672d1, 0xe199d6bb, 0xb828606f, 0x799521b8, 0xe63bd4c3, 0xca8bc401, 0xc1129f2a, 0xbbd59b4a, 0xf62dccc3, 0xd087a72b, 0x916f8bad, 0x05f80a48, 0xa9480b32 }, + // Message 6 + { 0x494c801a, 0xa09ccda5, 0xfd5cb1c2, 0x88a8c119, 0x1852fb99, 0x19c3e694, 0xb770300c, 0x81093aa0, 0xb987a3ab, 0x3672c0a9, 0xd8872294, 0xcd50e454, 0xd1e9e591, 0x0778a92c, 0xbada7e07, 0x730e6259, 0xadae6a0d, 0x440e2070, 0x08dad2fc, 0xf1a96af7, 0xe428b615, 0xd23e850a, 0xc7f9a60e, 0xd869daa0, 0x2b3c5fb8, 0x6664cbec, 0xd536e058, 0x2d377701, 0xe0e0e61e, 0x013c8780, 0xd2ba05f3, 0x9bc986cc, 0xf53bede9, 0x94f90e30, 0x9078cd05, 0x77c3fe5b, 0x38b2524b, 0xfc08a5ad, 0x43c2472c, 0x08e7091a, 0xfb00cdc5, 0xf57f7940, 0x54a949d1, 0xae121dea, 0x7a4d34a6, 0xc846b5d0, 0x107f5048, 0x2d813cd4, 0x751763ca, 0xf0d5beb8, 0x5f3ad34c, 0x20e8fc89, 0x522c0565, 0xb194d078, 0xd51ac55e, 0xee2985b0, 0x953eefec, 0x132f3a42, 0xa14f85e4, 0x46d27a84, 0x9790f7cd, 0x8aae4363, 0xe75f0459, 0xeb0b52d0, 0xd7dfcc60, 0xf8c1ea78, 0x195f61a0, 0x0f2218cd, 0xcf17bab6, 0x9c722da1, 0xf1f17460, 0x20f46606, 0x57223ec4, 0x449d58ca, 0xff071cb1, 0x50d0edf4, 0x2ed1158e, 0x99a06dcf, 0x4daaba52, 0x573a0d0d, 0x6c2fdd8b, 0xef355b86, 0x36745f16, 0x75c42a43, 0x566d8af8, 0x413ebf65, 0x5de5ea4d, 0xeaa02349, 0x0ea60c11, 0x3a779ea5, 0xdafe3ce0, 0xf28e6fb9, 0xba7e6fa2, 0x22c925fa, 0xb63e84fb, 0x74d93772 }, + // Message 7 + { 0x69f9ffe8, 0xd22f7c25, 0x79065655, 0xf09506f0, 0x0dcaada3, 0x190d979d, 0xa9e3d839, 0x56a52414, 0x48e21087, 0xf690f111, 0xd8e93abc, 0xbe911856, 0xe3b33a9a, 0x59035a1f, 0x59ba75db, 0x107e7069, 0x4dc0194c, 0x73a51c6b, 0x31cae97f, 0x31ba2b36, 0x9858ea6f, 0xc02382ff, 0x78ef5e5f, 0x540bc7e2, 0x46124c1c, 0x133cd8f3, 0x4268cf6f, 0xd03cc223, 0xf1369f9d, 0x5c2871ed, 0xa54c7a14, 0x06060e04, 0x0753412c, 0x89930b2c, 0xc3ea6dd3, 0xc2bef1aa, 0x9d6e1712, 0x9dfb04c2, 0xffc4f029, 0x844b9259, 0x61e085f8, 0x93489ab8, 0xc9179a28, 0x91aefe31, 0x440cce1b, 0xaffdb58c, 0xdd4c2396, 0x129bbc33, 0x1197fb6d, 0x71591bcc, 0x3c34583f, 0xfb7bcb45, 0x6a4b7055, 0x9439edcd, 0x403b8265, 0xf82a62ce, 0xe818f724, 0xd3bee15a, 0xeefde890, 0xc67633d4, 0xd5aee450, 0x4f2531ba, 0xbd9ae480, 0x676d8974, 0x7a6c66a5, 0x94c11dbd, 0x96185d05, 0xc8240d13, 0x3e2f71a8, 0xc0f48541, 0x58657c9c, 0x7117c02c, 0x81f97568, 0x3b9f9324, 0x126b1eec, 0x9c6afa89, 0xb7e0c2b0, 0x066a98b4, 0xa044889a, 0x37d75335, 0x4c4af22d, 0x13a966ef, 0xb2c9f746, 0x6a0238e8, 0x2f3650ea, 0x15255ebe, 0xcdc9219f, 0x57cc4731, 0x45b418dc, 0x689b83e6, 0x1f698a54, 0xf00fe258, 0xe665c56a, 0xb8913b96, 0x479bc689, 0xdbc22e55 }, + // Message 8 + { 0xf6276e70, 0x66175bff, 0x5352db45, 0x589ce506, 0x0f8821f5, 0xf08a7087, 0x508979d4, 0x5915500d, 0x96630de6, 0x014cd96f, 0xd48782dd, 0x5494ce5e, 0x2ee1fcfb, 0xab5ae079, 0x329ae541, 0xe09c757b, 0x74cb7c3d, 0x559bc3a7, 0x899be412, 0xb42bd267, 0x4fe60b17, 0x6acc9548, 0x571fcc95, 0x0420fab0, 0x982c7e9b, 0x204b3e31, 0x6e49f901, 0x66f66051, 0x0dcf227e, 0x54ca1e05, 0x2ece5977, 0xc98c4c54, 0x1999905b, 0x46a76b16, 0x9cce2830, 0x5fbd426f, 0x4aa54653, 0x559e5562, 0x9a484b54, 0x964e2b62, 0x1f2ce639, 0x7c308105, 0x483dfe3d, 0x5e8278d5, 0x9bfde6ab, 0x58a466e3, 0xcd3c33e2, 0xc5c68cd5, 0x8076bac7, 0x75d7ce6e, 0x01314880, 0x6a3ab61e, 0x09507c04, 0x2aad35f7, 0xe69895bf, 0x36b0e62c, 0x1534c2e1, 0xa192c033, 0x0534d073, 0xa26b9b81, 0xa776054b, 0xcf85a32a, 0xf2f76ef6, 0x3e9e5459, 0xb9073de2, 0x19b00868, 0x66fa788e, 0xaa151666, 0x2a1f9770, 0x45febf07, 0x35dfa9d2, 0x2c2c2364, 0x3d0f30e3, 0xa277a43d, 0xfa1d0296, 0x92a74586, 0x93234057, 0x34c73d7d, 0x48666cde, 0x8211d309, 0xad94ff6c, 0x182e45fb, 0xcfa79f8a, 0x2bc42037, 0x7ae67f1d, 0xacaeb046, 0x864dd151, 0x6520b840, 0x5eec3d72, 0x14e72fbd, 0x5baa6f5f, 0x27e4b1bc, 0x41aad9c0, 0x141a142f, 0xfd93c63d, 0xcfc1535a }, + // Message 9 + { 0x8dd5880e, 0x371a498f, 0x9c9add0d, 0xe0ea7d41, 0x4e681a70, 0xd89e0df2, 0x9514abee, 0xfae87315, 0xe837bca6, 0xefb89823, 0xfbd03997, 0x72ad1146, 0xd85eeaf1, 0x3e5937c4, 0xb289f36b, 0xe5ba0477, 0x941170c2, 0x29c4617e, 0x91a045b3, 0x8a39d1e1, 0x3bc8eccb, 0xf99a1c51, 0xf0a1013f, 0xa9c84292, 0xd1e408b9, 0x4da26c40, 0x6c779e64, 0x18d53c20, 0xea79910c, 0xe3f0e389, 0xfd5e7594, 0xf924df1a, 0x8fab41a1, 0xb33600c9, 0x27ceeefb, 0x05a78307, 0x9df2d704, 0x9532c917, 0xfefa2582, 0x08e96dd8, 0xd1c5d4f6, 0x27bef73f, 0x508bc2d6, 0xd60a4f64, 0xc1622da0, 0xbcbb3aeb, 0x46c744e7, 0xb5af204a, 0x737c5613, 0xcb0e4acd, 0xa87b8965, 0x7e9f690d, 0xe6ab511c, 0xd78db0ef, 0x8d2a1884, 0xf95e5133, 0x390da241, 0x3bc7d270, 0xbf649fe2, 0xfd7f7260, 0xd7bd94e2, 0x2d48ceef, 0xfa003bc0, 0xd2402937, 0x3086edd9, 0x87ac55e7, 0x2e222391, 0x6b46026e, 0xc565a1ad, 0x8a661112, 0xdda0ca66, 0x1ec8dd90, 0x471ad908, 0x72cc1e54, 0x35f4ba32, 0x0d6d07bf, 0xe71cdea3, 0x0f3620c3, 0x4132109c, 0xd768ec23, 0x4305a50f, 0xf4ed7e87, 0x8feded34, 0x806768cd, 0x36ab3075, 0xf857b88c, 0x75a2b697, 0xbdce1b38, 0x1155c510, 0x7c9d47ec, 0x2da88b4e, 0x8f255163, 0xc4e89a53, 0x99f8a3f9, 0xc14c117c, 0x8d432198 }, + }; + + + +#define NUM_CASES 5 + +static const encrypt_testcase_t test_cases[NUM_CASES] = { + { /* Case 0 */ + .iv = { 0x8c, 0x1e, 0x77, 0x16, 0x72, 0xde, 0x6d, 0x20, 0xc8, 0x7f, 0xaf, 0x73, 0xe0, 0x37, 0xc0, 0xfa }, + .p_data = { + .Y = { 0xcb5c62bd, 0xd53c02b1, 0x3ff33d74, 0x1200c344, 0x1d108bb7, 0x8ce3b02b, 0xd13c8ca8, 0x37f0a4d2, 0xbd5e2ba7, 0x16140ed0, 0x97e0e6d4, 0xc836e5d2, 0x09df3eb2, 0xf75921b9, 0x60c424b2, 0x5f29ac5f, 0x49b8713d, 0x4342a66a, 0x1bbc6329, 0x8f865f04, 0x5f5f6cd6, 0x1b233a09, 0x3d3d4b7f, 0x938e5a81, 0x02c343f6, 0x71c002c4, 0x4ad10fbf, 0x4f68429f, 0x68ea660c, 0xe4e9bfc8, 0x9a885e24, 0x22dc593a, 0x123509bd, 0xa8d8036c, 0x5a1ee67a, 0x577524cc, 0x1578f6e9, 0xac7b122a, 0x45e75817, 0xd33d73bd, 0xfd8caa5f, 0x3dd84eac, 0xcb21e71c, 0xb6df0faa, 0xb7c2b2cb, 0x5a35badc, 0x506a1282, 0xa23779cc, 0x1939e0d8, 0x89ac87f8, 0x396cc952, 0x21102ece, 0x1e84e5e3, 0x0dedaa06, 0xc6a0cac1, 0x35f934c8, 0xc139d9de, 0x8db949b9, 0xd26fbd54, 0x866c7375, 0xc542b4ca, 0x9de85700, 0x47ceb667, 0x9048c459, 0x2d60f706, 0xff980fe9, 0xb2bc5851, 0x14233375, 0x78e4a2b1, 0xc4503859, 0x6abe5255, 0xcca9ea15, 0x9f9f3377, 0xa0ecf4bf, 0x8c93078f, 0x6585711a, 0x2f3a0069, 0xb419fa34, 0xafadcf0b, 0xe575d179, 0xf865674c, 0x762cc0ba, 0xee40bf05, 0x196a5562, 0xd46fa34e, 0xeb7169da, 0x6893b021, 0x7a4ba5e4, 0x17acd406, 0x29ee794a, 0x6d097841, 0x34833d52, 0xaba7728c, 0xa2b178b2, 0x572415e2, 0xae9d2ed6 }, + .M = { 0xa7c8dae9, 0x71a084ba, 0xc46ffe34, 0x8c4ce331, 0x3f8606aa, 0x13823ea1, 0x79b9b2d6, 0x7fb2ed35, 0x1c75a92a, 0x76cbdbe2, 0xa00a4b52, 0xbbbd1697, 0x42b94063, 0xf5729322, 0xc836cdc0, 0x5a102597, 0x28dd02bd, 0x6d1649f2, 0x6374b255, 0x87f5d4d5, 0xd982d456, 0x6805284d, 0x90e3dfa0, 0xc14ea883, 0x369118c1, 0x12d6dbb0, 0x1bd106c8, 0xe9c145e2, 0x55574baf, 0x7fae64cb, 0x7c7829d7, 0xf19706f6, 0x9d7cd9a0, 0xfe5d7592, 0xf5057fe5, 0x3c24c781, 0x6d71749d, 0x0f4b3737, 0xc1136ea8, 0x15d3a3e0, 0xec5b80b3, 0x77973840, 0xb32dfcc1, 0x7f9dabf3, 0xa06a36dd, 0xa9a03bef, 0x7a606b52, 0xebd0936e, 0xabe211e7, 0x28b6df1f, 0x6f9b2092, 0x1be829fd, 0x3694097c, 0x0dc7cf28, 0xb73bf1df, 0xe6fb9628, 0x37351f75, 0xa61d0558, 0xba4c504c, 0x99196a13, 0x66b9ab4f, 0xabf2f08b, 0x4690e911, 0x86f7eeb0, 0x7986318a, 0xee525553, 0x8add40d6, 0x39d97958, 0x9bf0ebf8, 0x6f22c0f9, 0x9598e2a0, 0xf4709b61, 0x5016506a, 0x97d8127e, 0x023ff5d9, 0x71ace674, 0xc4e8333f, 0x99229a97, 0x80b48469, 0xb7687043, 0x5c0e7f79, 0xb7bc5d93, 0x5e504759, 0xffcfe533, 0xf254e419, 0x97212c42, 0x84fad815, 0xc8f7fcff, 0x9afbce0c, 0x898d1dd8, 0xe0ef661c, 0x5bf211b6, 0x76957689, 0xf58f1cfa, 0xeed49187, 0xb8572ec1 }, + .Rb = { 0x0b0c0a87, 0x07b0c5bc, 0x7be65940, 0xca7a734a, 0xbfc8755c, 0xa60e7eda, 0xd51cf3a5, 0x72d93c93, 0x72b0b01b, 0x6edc70c5, 0x192bdc52, 0xece987d8, 0xf3bd040f, 0x6f207f51, 0x50fb8317, 0xde12f201, 0xc5c4d0e5, 0x9a10baec, 0x13346985, 0xac32b264, 0x26db361b, 0xd9a19acc, 0x4ba7c94c, 0xde1ed00f, 0xaebf5e7e, 0xba0f20cd, 0x72f98543, 0x46f58f13, 0x0256c157, 0x1061058a, 0x17fcf0b0, 0x6ed62849, 0x8824c840, 0x1ad89a36, 0x62d01765, 0x7a74e8b1, 0x8e9c9fc1, 0x0cd312bb, 0x8e9792a1, 0x139fca5a, 0x14244d65, 0xcf734148, 0x336ecd8d, 0x52ce8c79, 0xa0b00234, 0xeb55c35c, 0x628c54ea, 0x2f2f5422, 0x7edbfc76, 0x43648965, 0xe04dce82, 0x13571757, 0x35b910fa, 0xc6d47cb0, 0x372430a8, 0x6be40069, 0x8553cc57, 0x5ab4a818, 0x9a234115, 0xba12e97e, 0x12302dee, 0x375f38c1, 0x3f797af3, 0x7419b1ba, 0xd8a692d0, 0x17a82e77, 0x19516428, 0xfdd32e14, 0xc0ce5186, 0xb5f01ce4, 0xcba43ead, 0xb740ffea, 0x3733443e, 0x06929405, 0x402bcbbb, 0x49fb85aa, 0x0a6d4e67, 0x02e6f076, 0xdf554141, 0xdebcc8c9, 0x563c65c9, 0x76c3d2bd, 0x64accd63, 0x83b3818d, 0x56ecce2f, 0x6ab3bc17, 0x6f616fc6, 0xf6b90a98, 0x305e988d, 0xd74bde1a, 0x987e3a31, 0x02454625, 0x8e9b7930, 0x1c1e1282, 0x508abff4, 0x09156acb }, + .M_prime = 0x734c62a7, + .length = 95, // 3072 bit + }, + .expected_c = { 0x79, 0x0a, 0x62, 0xe5, 0xd4, 0x1d, 0xee, 0xc4, 0x99, 0xbf, 0xce, 0xd8, 0x89, 0x16, 0xbc, 0xa7, 0x09, 0x62, 0x48, 0xd1, 0x69, 0xbc, 0xd5, 0x0c, 0xb9, 0x62, 0x2d, 0x9f, 0x32, 0x15, 0x6f, 0xef, 0x87, 0x7b, 0xcc, 0xab, 0x6c, 0xf3, 0xd2, 0x52, 0x3d, 0x49, 0xfc, 0x99, 0x36, 0x3f, 0x61, 0xc0, 0xb4, 0x76, 0xdc, 0xd7, 0x44, 0xdf, 0x39, 0xd4, 0xe0, 0x13, 0x28, 0xf5, 0x94, 0x1e, 0xe6, 0xa7, 0xf9, 0xa5, 0x7b, 0x4f, 0xe5, 0xc0, 0x72, 0xbd, 0x20, 0xb5, 0xb4, 0x3a, 0x66, 0xdb, 0x58, 0x59, 0x58, 0x10, 0x33, 0xe1, 0x25, 0x71, 0x3f, 0x2b, 0x9f, 0xee, 0xe9, 0x3b, 0x36, 0xea, 0xd8, 0x08, 0x30, 0xcb, 0x4a, 0x85, 0x24, 0xcf, 0x54, 0x34, 0x5f, 0x6b, 0x3c, 0x44, 0x12, 0x9d, 0x30, 0x68, 0xf0, 0x26, 0xce, 0xb9, 0xe7, 0xdf, 0x31, 0x45, 0x24, 0x39, 0xdc, 0xdb, 0x17, 0xf2, 0xa1, 0x3d, 0xa9, 0x21, 0x33, 0xfb, 0x71, 0x68, 0xeb, 0x11, 0x70, 0x7b, 0x72, 0xe5, 0x79, 0x03, 0x2f, 0xdb, 0xf7, 0x71, 0xb3, 0xe8, 0x79, 0x6b, 0x25, 0x95, 0xdb, 0x91, 0x48, 0x28, 0x97, 0xbd, 0x8c, 0x4c, 0xff, 0x98, 0x56, 0x1d, 0x8e, 0xf7, 0xca, 0x0f, 0xdc, 0x51, 0x19, 0xef, 0xe8, 0xab, 0xb1, 0xea, 0x99, 0x2a, 0x04, 0xa9, 0x0a, 0x39, 0xfc, 0x8c, 0x34, 0x40, 0xa4, 0x29, 0xdc, 0x0f, 0x7c, 0x6d, 0x3e, 0xda, 0x25, 0x67, 0xbe, 0xcd, 0xe7, 0x21, 0x2a, 0xb8, 0xbb, 0x21, 0xdb, 0x45, 0x46, 0x44, 0x09, 0xe2, 0x60, 0x0f, 0x80, 0xce, 0x22, 0x88, 0x43, 0xd0, 0xf8, 0x6e, 0xd7, 0xf5, 0x0e, 0x17, 0x1c, 0x4d, 0xfd, 0xc5, 0x0a, 0xe8, 0x70, 0xed, 0x29, 0x3e, 0x56, 0x01, 0xa5, 0xd7, 0xad, 0x82, 0x03, 0x33, 0x4f, 0x8d, 0x4c, 0x58, 0x38, 0xf6, 0x82, 0xc5, 0x6e, 0x87, 0xf9, 0x22, 0x98, 0xdd, 0x32, 0x85, 0x3d, 0x2e, 0xbe, 0xfa, 0x2e, 0x1f, 0xc4, 0x3b, 0x2c, 0x30, 0x36, 0x7c, 0xa3, 0x72, 0xb9, 0xd9, 0xf5, 0x6e, 0xb9, 0x16, 0x03, 0xd6, 0x41, 0xab, 0x9c, 0x36, 0xc8, 0x1a, 0x48, 0x58, 0x94, 0xef, 0x6b, 0x2b, 0x02, 0x3a, 0x29, 0x38, 0x1f, 0xeb, 0xc8, 0x99, 0x8a, 0x86, 0xcf, 0x87, 0xe6, 0xf9, 0xb4, 0x8b, 0x54, 0xe7, 0x08, 0xc7, 0x60, 0x8a, 0xdd, 0x42, 0xe8, 0x9b, 0x8f, 0xf4, 0x47, 0x7f, 0xe9, 0x93, 0x8c, 0x6f, 0xa6, 0xeb, 0x1b, 0x64, 0x80, 0xa4, 0x1e, 0xbe, 0x03, 0x7d, 0xa4, 0x18, 0x0e, 0x79, 0xc5, 0x0f, 0xda, 0xce, 0xe0, 0xdb, 0x2c, 0xb0, 0xb5, 0x51, 0x2a, 0x70, 0x7f, 0x83, 0xd5, 0xdd, 0x0c, 0x29, 0xe8, 0x2b, 0x88, 0x6c, 0xea, 0x89, 0x85, 0x14, 0xd9, 0xfe, 0xb3, 0x01, 0x1e, 0xf3, 0x28, 0xd7, 0x9b, 0x74, 0x93, 0x7a, 0xe0, 0xdc, 0xfb, 0x24, 0x1c, 0x75, 0x61, 0x6d, 0x6e, 0x06, 0xb5, 0xfa, 0x55, 0xf2, 0x5c, 0x52, 0x32, 0xb4, 0xee, 0x45, 0x1f, 0x5d, 0x2e, 0x15, 0x31, 0xa0, 0x53, 0x4f, 0xc0, 0xbd, 0xb4, 0x7f, 0x4f, 0x70, 0x56, 0x69, 0xca, 0xc2, 0x1d, 0x74, 0xd8, 0x2f, 0xfa, 0x69, 0x52, 0x89, 0x06, 0xce, 0xc5, 0xd1, 0x71, 0x8d, 0x90, 0x11, 0x88, 0x58, 0x5e, 0x50, 0x84, 0x54, 0x5d, 0xdc, 0x6c, 0x28, 0xc8, 0x2a, 0x76, 0x71, 0x61, 0xf8, 0x9d, 0xbd, 0x99, 0xd9, 0x61, 0x44, 0xc5, 0xfd, 0x32, 0xb8, 0xd7, 0x07, 0xc9, 0x2f, 0xad, 0x4a, 0xfd, 0xcd, 0x40, 0xb8, 0x6c, 0xdd, 0xdc, 0xcf, 0xf2, 0x2a, 0x9f, 0x31, 0xf2, 0xc9, 0xa9, 0x24, 0x74, 0xa6, 0x82, 0xd1, 0xe1, 0xcb, 0xef, 0x52, 0xcf, 0x78, 0x52, 0xd9, 0x1d, 0xb5, 0x06, 0x4c, 0x0c, 0xa8, 0x86, 0xe8, 0x61, 0x7f, 0xf4, 0xaa, 0xac, 0xdc, 0x7e, 0x8c, 0x45, 0x3d, 0x4a, 0x9f, 0xee, 0xcc, 0xf9, 0x1e, 0x81, 0xb0, 0xa2, 0x3b, 0x69, 0xc8, 0x5f, 0xc8, 0xf6, 0x53, 0x10, 0xf1, 0x43, 0x70, 0x1a, 0xba, 0x27, 0x6b, 0xcf, 0x98, 0x46, 0xd7, 0xa1, 0xc3, 0x64, 0xe4, 0xc7, 0x5a, 0xea, 0x07, 0x93, 0x4c, 0xea, 0xa9, 0x54, 0x0c, 0xb5, 0x5c, 0xae, 0x24, 0xa7, 0xa2, 0xcf, 0xd1, 0x36, 0x7e, 0x95, 0x1b, 0x33, 0x73, 0xc1, 0xcd, 0x97, 0xd5, 0xab, 0x0b, 0x77, 0x26, 0xac, 0xf1, 0xef, 0x3a, 0x15, 0xc5, 0xf3, 0xff, 0xbd, 0xb7, 0xa7, 0x4d, 0x8b, 0x58, 0xaa, 0xb4, 0xf7, 0x51, 0xce, 0xfc, 0xad, 0xc5, 0x00, 0x7c, 0xea, 0xcb, 0xaa, 0xc8, 0x5a, 0x91, 0x8d, 0x8c, 0x09, 0xa3, 0x84, 0xd3, 0xfe, 0x9b, 0xe5, 0x09, 0x01, 0xea, 0x1f, 0xb1, 0x26, 0xfc, 0x9f, 0x9e, 0xfb, 0xaa, 0x47, 0x67, 0xa6, 0x11, 0x5c, 0xce, 0xfc, 0x7b, 0xb8, 0xa0, 0x41, 0x7e, 0xe2, 0x80, 0x8c, 0xe9, 0x8c, 0x1d, 0x31, 0x84, 0xc6, 0x9e, 0xd2, 0xa7, 0x8a, 0x63, 0x8b, 0xc3, 0x2f, 0x08, 0x3b, 0x2f, 0xcc, 0x2c, 0xce, 0x25, 0x81, 0x98, 0x02, 0x05, 0x38, 0x6e, 0x19, 0x3f, 0x8f, 0x6f, 0x67, 0x72, 0x0f, 0x8f, 0x75, 0x27, 0xfe, 0xad, 0xd8, 0xd2, 0xec, 0xae, 0xec, 0x25, 0x33, 0x1e, 0xf8, 0xc2, 0x59, 0xb0, 0x96, 0x05, 0x39, 0xf4, 0xf2, 0x60, 0xd9, 0xda, 0x88, 0x1e, 0x8e, 0x29, 0xed, 0xcc, 0x5b, 0xe8, 0x39, 0x57, 0xc0, 0x10, 0x20, 0x94, 0xe2, 0x22, 0x6e, 0xb5, 0x3f, 0x75, 0xe4, 0xb1, 0x1b, 0xac, 0x14, 0xf9, 0xc7, 0x55, 0x62, 0x19, 0x4b, 0x87, 0xa7, 0x20, 0x6b, 0x5a, 0x44, 0x8f, 0xc7, 0xb3, 0x98, 0x70, 0x21, 0x80, 0x10, 0x1e, 0x13, 0x05, 0xc7, 0x8c, 0x3c, 0xce, 0x56, 0xb1, 0xce, 0xfd, 0x43, 0x96, 0x27, 0xcc, 0x6a, 0xb6, 0x66, 0xcc, 0xa6, 0x41, 0x2d, 0x9a, 0x84, 0x70, 0x1f, 0xa5, 0xb1, 0x0f, 0x32, 0x20, 0x1a, 0x40, 0xd6, 0x41, 0xac, 0xa8, 0x36, 0xf0, 0x78, 0x25, 0xd3, 0xc9, 0x79, 0x9d, 0x44, 0x53, 0x4d, 0xb7, 0xf5, 0x7c, 0x15, 0xca, 0xe6, 0x58, 0x22, 0xc8, 0x53, 0xc9, 0xdb, 0x10, 0xac, 0xb3, 0xcb, 0xc6, 0x76, 0xc0, 0x76, 0x32, 0x29, 0x46, 0x14, 0xa5, 0x29, 0x88, 0x78, 0x99, 0xe5, 0x39, 0xd8, 0xde, 0x93, 0x65, 0xcb, 0x91, 0xbd, 0x88, 0xb0, 0x2f, 0xef, 0xca, 0x96, 0x02, 0x53, 0x36, 0xd6, 0xc1, 0x98, 0x24, 0x88, 0xb8, 0x7a, 0xf9, 0xe8, 0x4d, 0x36, 0xd5, 0x87, 0x43, 0x58, 0x66, 0x8e, 0x6d, 0xe7, 0x02, 0x2c, 0xdb, 0x36, 0xed, 0x85, 0x1f, 0x0b, 0x3f, 0xcc, 0x4d, 0xac, 0x17, 0x8a, 0x30, 0x61, 0x87, 0xed, 0xc1, 0xdd, 0x4a, 0x95, 0x33, 0xd8, 0x24, 0x09, 0x21, 0x92, 0x1f, 0x7b, 0x09, 0x12, 0xb5, 0xb0, 0x78, 0xa4, 0xe5, 0x52, 0x75, 0x4e, 0xcd, 0x91, 0xe6, 0xd2, 0xe2, 0x81, 0x08, 0x0b, 0xbd, 0xcb, 0xd3, 0x70, 0x2c, 0x06, 0xab, 0x06, 0x2e, 0x16, 0xd9, 0x3a, 0xcc, 0x4a, 0xa8, 0xfd, 0xbb, 0x09, 0x55, 0xd1, 0x31, 0xa2, 0x43, 0x9a, 0x76, 0xd9, 0x5c, 0x8a, 0x73, 0xb6, 0x79, 0x16, 0x35, 0x27, 0xe1, 0x3c, 0x77, 0x58, 0x8d, 0xf5, 0xb5, 0x66, 0x8a, 0xc7, 0x20, 0x7c, 0x75, 0xf1, 0x79, 0xa6, 0x1a, 0x4c, 0x55, 0x18, 0x0f, 0x28, 0x49, 0x52, 0xf1, 0x22, 0xfd, 0x24, 0xfa, 0x0a, 0x76, 0x59, 0x83, 0xf1, 0xe1, 0x04, 0x30, 0x51, 0x20, 0x09, 0xf2, 0x22, 0xe6, 0x3e, 0x5b, 0x18, 0x16, 0xfa, 0x3f, 0xce, 0x43, 0x87, 0x84, 0x76, 0xfa, 0xb6, 0xec, 0xdf, 0xfb, 0x18, 0x74, 0x89, 0x17, 0x0a, 0x73, 0x55, 0x01, 0x29, 0x31, 0xf8, 0x94, 0xe9, 0xa9, 0xc1, 0xc6, 0x97, 0x0f, 0x1c, 0x7d, 0x6e, 0x28, 0xa3, 0x64, 0xb2, 0x4b, 0x6c, 0xd4, 0xd6, 0xfe, 0x2b, 0x07, 0x68, 0xaa, 0xbb, 0xf1, 0x54, 0x8d, 0x5e, 0x6c, 0xe9, 0xda, 0x3b, 0x17, 0xe4, 0x16, 0xe8, 0x7d, 0xa5, 0xf9, 0x52, 0x73, 0x00, 0xb5, 0x34, 0xaa, 0xee, 0x76, 0xa6, 0xee, 0xd8, 0x8c, 0x59, 0x84, 0x90, 0x28, 0x42, 0x9a, 0x1f, 0x9f, 0x8e, 0x29, 0x81, 0xfd, 0x6c, 0x6b, 0xb5, 0x12, 0xa4, 0x91, 0x80, 0xa6, 0x77, 0xfd, 0xcd, 0x9f, 0x99, 0x2c, 0xb3, 0x5e, 0x35, 0x03, 0xb9, 0x03, 0xa5, 0x19, 0xb2, 0xce, 0xa4, 0x9a, 0x31, 0x9c, 0xde, 0x0f, 0xf6, 0x36, 0x54, 0x49, 0x3f, 0x52, 0xd6, 0x16, 0x3b, 0x66, 0x86, 0xa9, 0x63, 0x53, 0x28, 0x44, 0x29, 0x85, 0xe4, 0x19, 0x17, 0xc4, 0x9f, 0xc6, 0x2e, 0xc2, 0x8e, 0xb6, 0x4a, 0x44, 0x73, 0xa5, 0xe1, 0xe2, 0x12, 0x1d, 0xd3, 0x0a, 0xb2, 0xb5, 0x14, 0x08, 0xe1, 0x8a, 0x87, 0x05, 0xfa, 0x4a, 0x6c, 0xb1, 0xd1, 0xf0, 0xc2, 0xdb, 0xd0, 0x84, 0x46, 0x0d, 0x71, 0x1d, 0xb7, 0xc5, 0x42, 0x9a, 0x62, 0x76, 0xdd, 0x22, 0x7c, 0xad, 0x18, 0xc3, 0xa2, 0x8c, 0x3f, 0x53, 0xcd, 0x36, 0xa9, 0x2f, 0x00, 0x15, 0xf2, 0xb9, 0x6a, 0x19, 0x5d, 0x09, 0xe1, 0x2d, 0x39, 0x52, 0x42, 0xbf, 0xfd, 0x6a, 0xc3, 0x27 }, + .hmac_key_idx = 1, + // results of message array encrypted with these keys + .expected_results = { + // Message 0 + { 0x0152da3a, 0x762a3fb4, 0xbe18cd88, 0x3d967ed4, 0x5b51fe39, 0xd688fd48, 0x216459bb, 0xf15f9b19, 0xed7e7a43, 0xb59e8bf9, 0xddcf8efa, 0x8974a335, 0xa6d9f07d, 0xd290dfbb, 0x20fa81e5, 0xfb87a847, 0xbbf4ea09, 0xde3efe67, 0x1158d712, 0x966753a8, 0xafb2bef2, 0x969edb98, 0x379f3714, 0xbe0f2773, 0x5c044d39, 0x16b3d605, 0xc792f51a, 0xf693960a, 0xbd7417b7, 0x59f4a22e, 0xada4823d, 0x4c74246d, 0x25a5f973, 0xd7e1dbe7, 0x6e816a19, 0x7bcbb461, 0x9011a1ac, 0x2952b70b, 0xc8d8666b, 0x2a04c3f7, 0xfa147ccf, 0xe9459bd7, 0xe408d45e, 0xd468b0c0, 0xf415e1e7, 0x334447e5, 0x8bebf8a1, 0x6a63ed9b, 0x0714a200, 0x686bb29e, 0x36ff6788, 0xc1dc1d69, 0x11583bd8, 0x6c39ef9b, 0xa92fa313, 0xf550b0eb, 0xa1a156ff, 0x80d7e7b2, 0xcde26f16, 0x22efc91e, 0xdf15a305, 0x3c6f8e9d, 0xc1b917f1, 0x0a990e14, 0x1241d963, 0x84324a11, 0x293de186, 0x3397810a, 0x734a3412, 0x720cf85f, 0xdaa30a9a, 0xa9f264bf, 0xcc70302f, 0xc658df8e, 0x21ded10b, 0xee91e6ec, 0x036c322d, 0x6cbe3667, 0x5319bc7b, 0x65acbb71, 0x428909ad, 0xe5a7e82d, 0xddd4c6b7, 0x4c6386f5, 0xb9ab70c5, 0xcaea7aa7, 0xcc13e5c4, 0x7b8e2a2e, 0x1fdaac8b, 0x2705b4f2, 0xa9b52c45, 0xd48a48b3, 0xd73295ac, 0x87b8dd20, 0x1f06402b, 0x765f9413 }, // Message 1 + { 0x8077eb25, 0xc62c9c39, 0xbbcc7919, 0xfbfafb2d, 0xd982d6d4, 0x4b977932, 0x4a8b5e13, 0xbcecd12b, 0xbf5a6672, 0xdeca4148, 0xe1893c41, 0xdda9da85, 0x3e478184, 0x9347e998, 0xf91cb596, 0x9664403e, 0xa9af3d0e, 0xe8d4174a, 0x1337d4e4, 0x2f9abb33, 0xb555944e, 0xf13ed7f9, 0x0c452217, 0xe3645109, 0x700695bd, 0xff8be175, 0xa3bab12a, 0xdbbcb8a4, 0x649d8c07, 0xd893e155, 0xbee8794d, 0xd764d2e2, 0xbad59a02, 0x125b1fe4, 0x9868d2ff, 0xb566a3fe, 0x529fb57a, 0xccf451ff, 0xc9d1fbf6, 0xec04749d, 0x125fe6c8, 0x8b32df5b, 0x5b873af1, 0x70ddae64, 0xf6f2c57e, 0x6ddf32b0, 0x5f83a7d6, 0xeb398393, 0xdb51e800, 0xebff95bb, 0x6cab049d, 0xcd3f5f6b, 0x3d441da1, 0x634b1c3d, 0x4dd51125, 0xdaa05beb, 0x93463e72, 0xfac8212b, 0xf1d6c8dc, 0x8b355695, 0x4a705864, 0x3aaf7a11, 0x104d5e39, 0xc86c818d, 0x43077ee7, 0x3cbecedc, 0x2b86d315, 0xd5cbdba2, 0x45de03d0, 0xe6476a9b, 0x0155eae7, 0x96e9d7f3, 0xac879021, 0x4da64539, 0x362cf772, 0x98048ddd, 0x5d280243, 0xe9c86210, 0x07d0ba70, 0x4b64ccff, 0xaa6d6a29, 0x0900d999, 0x15930af3, 0x1278e322, 0x1f677625, 0x7a5bc43b, 0x42c7b5e3, 0x49d63815, 0xc9329722, 0xa5a64ce7, 0x64b5c1bb, 0x7d151b58, 0xebd4f665, 0x14ca6c0b, 0x819a6b2e, 0xb72dfc7c }, // Message 2 + { 0x558e22e3, 0xd8edebfb, 0x38cc66ce, 0x2e6cbd80, 0x2ec77f97, 0x6bcec9e2, 0x91661ddc, 0x80e32b38, 0x1f94bf8b, 0x6157a4a5, 0xd100e201, 0x81fffff4, 0xddbb9eee, 0x09fedb2f, 0x47fe3ee5, 0xb427bc06, 0x2d10a486, 0x12a7784d, 0xafa90127, 0x126b18ff, 0x1a050f33, 0xe499ff25, 0x746f6018, 0x803401ca, 0x3e5d290d, 0xba3f3534, 0xc881eb09, 0xf3deacd3, 0xe8da79da, 0x6ef25f62, 0x302d510b, 0x6460e529, 0x4aac9523, 0xc13f91a0, 0xbb4ff974, 0xd5c68ace, 0x1d07f6f0, 0x16caf5a9, 0xaa357735, 0x0e500544, 0xf888c7d9, 0xec671fc1, 0xb1a504bd, 0xa79ed820, 0x1ec78fed, 0x2db92ae9, 0xbe4833c5, 0x626adae7, 0x121fe1cf, 0x775a7881, 0x05cf904f, 0x1a68383b, 0xf679796d, 0x03f9a0cf, 0xd9b86d31, 0xc9112623, 0x01590134, 0xece0776d, 0xb995e4e2, 0x5f239fbd, 0xdf8d6c36, 0x80e0e042, 0xfbf57182, 0x52c264c5, 0x2f8268e2, 0xf3101f03, 0xc35237b8, 0xbe454c1d, 0xf12b7934, 0x44820788, 0xb5567721, 0x2b82b89a, 0x9025777f, 0x635a6c3d, 0x8da8efc4, 0x19ad36d6, 0xa9483b52, 0x2fe22d20, 0xd0cc5ae2, 0x799ec6ed, 0xf9c10037, 0x9056b2d3, 0xe9167d9f, 0x59e5ebf1, 0xbf1fcc16, 0x68e24b99, 0x9e514702, 0x0b1bda00, 0x8e7f26f9, 0x8a16423e, 0xf00a5c52, 0xb27420e1, 0xf7a75042, 0x28256923, 0x93a53d97, 0x593cc811 }, // Message 3 + { 0x58f14e9b, 0x3fba7d61, 0x7e56cf0a, 0x369f6bab, 0x1d562f95, 0xa5a16fc7, 0x8b8e78a4, 0x6a1fb20a, 0x427a1217, 0xe4f43fa5, 0x0bcbabea, 0x44e36fb5, 0xd7d09291, 0x8e589fa5, 0x723abb94, 0x90e765b1, 0x02a10201, 0xb4903db1, 0x0e7bcaad, 0x09a55b67, 0x7ca80a5a, 0x57856c50, 0x834a4547, 0xb5725470, 0x5d9db382, 0x6f653814, 0xa9c1d0d8, 0xc5e0972f, 0x10df3c95, 0xdac2a46e, 0x3574fe39, 0x15648781, 0x0a0784ce, 0xd14437f0, 0xebef4e4b, 0x0916cf82, 0x76d78cd9, 0x6ea3f595, 0x18b439a6, 0xb7229141, 0x5321d899, 0x34b02c77, 0x47ecdd63, 0xbc16e256, 0x360b6334, 0xe066a8b7, 0x9bede8cd, 0xe2f1bdf9, 0x9bb126cd, 0x09ac638e, 0x1ebeef58, 0x43a5d3c9, 0xfffe03ad, 0x683b60d0, 0x53f89ad4, 0x00b28ffd, 0x22a3acdc, 0xed9edac6, 0x600e298e, 0x73c8dada, 0x31f85658, 0x4acf41fa, 0x203d273d, 0x1977aa0e, 0xe7bebe57, 0x4ce59323, 0x22af2296, 0xec5b4f6a, 0x2ef02644, 0xb57f95f0, 0x4fade369, 0x8b3ccb6c, 0x859bfea0, 0x56515fbb, 0xe977fbd6, 0x4603afe6, 0xfc521d22, 0x8305f598, 0x9f53a6de, 0x9a50a8ea, 0x88904d85, 0x13a86af8, 0x92f029a1, 0x9ee876ad, 0xd731df69, 0xdf4b1f8a, 0x692c9413, 0x1d491c34, 0x28cad0fa, 0x62f6c20d, 0x2a18c38d, 0x4dc863b6, 0x59925352, 0x526cf074, 0xe00a7509, 0x4f74348d }, // Message 4 + { 0xecfe784b, 0xfa59d270, 0x5e4d4ac1, 0x0f0606f6, 0x8a99b1ee, 0x3fdfd931, 0xbfdab1ca, 0xa1b8750b, 0x213e5637, 0x0b6a3d12, 0xaab1ae85, 0x21152bba, 0x5bdfbdcb, 0x03a9fef9, 0x3c0f0cd9, 0x9325218a, 0x468cdb2a, 0x0a19b778, 0x09c9bfea, 0xb8141c74, 0xaa3746d8, 0x387a3742, 0xc0e4f644, 0x0c3e8166, 0x518aa2d1, 0x6b820e82, 0xe135a093, 0xce1aed91, 0x6ea1480f, 0x01b000dc, 0x730ee892, 0x356b8854, 0xc7129c58, 0xe1905c79, 0x149efc33, 0x1a4af6c8, 0x78efea46, 0xceeb6daa, 0xd9a93aba, 0xcf124636, 0x4681b414, 0x2dbd5a38, 0xa77427d4, 0xcd198cd4, 0x3454b3a5, 0xeaa21411, 0x5ea7f58b, 0xd24c4bcf, 0x2db53e3a, 0x95fe2f2a, 0x43f019e8, 0xbb3ab440, 0xf016ab58, 0xe44c835c, 0x0a7f26bc, 0x5c0f8b8e, 0x337f8206, 0x65071aa0, 0xd8296708, 0x499d520b, 0x20fa64fe, 0xc7edcc40, 0x32a24758, 0xde394108, 0x06bec3b0, 0xc6425bd0, 0xa839680b, 0x1638d3d1, 0x6597bbe2, 0xfc7efc5d, 0xf0799229, 0xadfdab6d, 0x687190cd, 0x40964550, 0xead3e3c7, 0x7c2a163c, 0x90410aa6, 0xb55d465a, 0xf1e02015, 0xbaec8b1c, 0xcac061ee, 0x1a5a0706, 0xf3196135, 0x86fb687d, 0x2201332d, 0xfaf7790a, 0x495c693e, 0x49f01065, 0x5c4c5f71, 0xb40e1f75, 0x2b97682d, 0xb4ea830b, 0xbbda4edf, 0xfe181687, 0x62ef95ad, 0x6b244434 }, // Message 5 + { 0x8df55d72, 0xdf8e36c2, 0xcd0a1de3, 0x90923396, 0x664c1177, 0x3f373a13, 0x84cc818c, 0xb31f28b0, 0x28107345, 0x792fde4f, 0x53392249, 0xf91d9e5b, 0x433b591e, 0xe47075e8, 0x49b7423c, 0x13543d22, 0x1010399f, 0x21dd53f5, 0x4b46fd0e, 0x8e5cb62a, 0xca52cf67, 0x029cb078, 0x3e9a66f4, 0x23c6f9a5, 0xa9bf7873, 0x9084b730, 0x6fe3b350, 0x8c0064a9, 0xc5bf52fd, 0x585902f1, 0x2f580c7f, 0x69bb7b7f, 0x463193fe, 0x1f6ddfb1, 0x0e4befaa, 0xaddd1e3a, 0xa8961706, 0xacf08696, 0x8767f45a, 0xde6407b7, 0xc5219c29, 0x441cc6ca, 0x7facd1ec, 0x1a8cd12c, 0x7dc451b4, 0xa4f4387e, 0x18156d78, 0x6376f6cc, 0xdb5727fd, 0x285753bc, 0x6cc53637, 0x421ef909, 0x7185bbc7, 0x43f0d844, 0x20e2671a, 0x620ac2f0, 0xf8e0d829, 0x03c20900, 0x9f6237a9, 0xac46cac2, 0xd320cee9, 0xe75f78e8, 0x63abf3d8, 0x5f7b5eef, 0x5c580db8, 0x00e028e4, 0x28b77df6, 0x5150b0ec, 0xbe411299, 0x844b884b, 0x2d085e38, 0x8f16bf08, 0xb082e459, 0xcf7df953, 0x52eb359c, 0x81168dca, 0xdf595d7b, 0xa99e0cc4, 0x056a9380, 0xec38d49a, 0xe88c1606, 0xce1a0687, 0x92a0a680, 0x71f3c08b, 0x4badcdf1, 0xa7ab2cd5, 0xd7c6ef1e, 0x0690bb38, 0xbf16994d, 0xec065761, 0x2293417c, 0x0cb8eb28, 0xff2a0000, 0x599367c0, 0x012dae17, 0x90ba84b4 }, // Message 6 + { 0xf5d4e9af, 0x7ddbf750, 0x161606d3, 0x552f5b5c, 0x32d54440, 0x1f1b90d9, 0x05346d53, 0x6617b470, 0xca904fab, 0xcf1600f1, 0x5c5274bb, 0xf9f511c8, 0x6f3e44b0, 0xa1431c4d, 0xd3e03362, 0x40f48092, 0x4d338cb2, 0x279e15a5, 0x164fd8d3, 0x28270914, 0x0bdedb1e, 0xe0dece47, 0x6abcd38b, 0x40562335, 0x8bc0cea0, 0x1a3d4f0a, 0x3e816741, 0x34f45381, 0x293853b1, 0xade0b447, 0xa128fec5, 0xf68152c5, 0xf8c0ebb3, 0xce11968a, 0x25d84d84, 0xe3e223ec, 0x04871f5d, 0xd6c0796b, 0xfad0cb0d, 0x2c5d77a6, 0x1e750819, 0x7a564e61, 0x9b136e13, 0xc2061d59, 0x7964bd81, 0x689fa374, 0xde1bc8f4, 0x3922f84b, 0x4581d684, 0x5b82dfe4, 0xeedef4e7, 0xc4c2f1ad, 0x4ccf4d78, 0xcdb83665, 0x4e7f1d77, 0xf139b6e8, 0x3f54c458, 0x9867e927, 0x4aada051, 0x198677f6, 0xa1cb7cb3, 0xd22e2ea9, 0xed6c6e67, 0xea940a8b, 0xc95217c0, 0x337d18e5, 0x92201215, 0xeb7c7763, 0x87af333d, 0x8cf7f049, 0x8ef96e74, 0x255c74c1, 0x857c7fb7, 0xc016a610, 0xe51cf39d, 0x5b0500f5, 0x34c4728d, 0x9abe58a2, 0x27f810a4, 0xe4bf61af, 0x35ed1d42, 0x7d724893, 0xe69c943e, 0xa163f9fd, 0xced20ee2, 0x5ba03600, 0x5d05e721, 0x185b4114, 0x43baffe6, 0x7fe34142, 0x569ca600, 0xfaad8f5c, 0xceb2ee6b, 0x7d53a97f, 0x12ee2fa2, 0x0f25ce8e }, // Message 7 + { 0x94b40b91, 0xdff655df, 0x2ff211ea, 0xbababd4a, 0x6fc2890f, 0x40092e6e, 0xc2ac8462, 0xad8842c2, 0x4c465b0b, 0x83567d09, 0xa0eed5c6, 0xbad2c5e5, 0x3a65f3d0, 0x69684a50, 0xd8326418, 0x42d686ad, 0x775bdf3d, 0x151e1248, 0x1046e45f, 0xc9175c79, 0x49164179, 0x32ca2f8e, 0x7d50c0df, 0xe4594e2d, 0x16bfc794, 0xf5817375, 0xe23780d9, 0x2d947950, 0x8934cb20, 0x63b9e631, 0xd8e94fd2, 0xbd432895, 0x7533c2a3, 0xe8e33956, 0x375c2d2b, 0xa7b8bc24, 0xb40f5a70, 0x20b35305, 0x064200e2, 0x7f84a8dc, 0x6fca1a64, 0x7c67c3be, 0x137bf864, 0x954292de, 0xc684108e, 0x203ea4b8, 0xbd04a57d, 0xe4889c98, 0x34c0ecb0, 0x5c10e181, 0x733c5e27, 0x3e034785, 0xd17c448c, 0x366addea, 0x99862929, 0x9200f99f, 0xc252cb28, 0x210a210b, 0xbb3fbf86, 0x4c1e3cf0, 0x4c286cef, 0x3069332c, 0xb47391dc, 0x300ecb50, 0xd8969893, 0x722c5a25, 0x9709b02c, 0x9ea45552, 0xe8e72472, 0xed3cd05b, 0x23d98e41, 0x85088018, 0x92053354, 0xc3dac73f, 0x3813d086, 0x4ac186e3, 0xe030cb60, 0xd04a459c, 0x9c7e660a, 0x3e16e170, 0xb878b8ff, 0x73cf3d27, 0xeb7ec0fa, 0xf7f41371, 0x148ccadc, 0xb7a50d86, 0x8f2ca973, 0xd1f4dfb1, 0xd80c3e22, 0x20293922, 0x73a01db6, 0x926f7a37, 0xf76b627a, 0x4204680e, 0x798e206d, 0x3f5b7eea }, // Message 8 + { 0x8461d479, 0x6207f011, 0xf750c7f8, 0xb16e20c0, 0x86f8c420, 0x355ca8c2, 0x3b4b8214, 0x39f89fb2, 0x06a90411, 0x460e58d0, 0x9e15bd12, 0x4fdcf3a2, 0x44c491e5, 0x9843cf61, 0x1d325991, 0x884302a5, 0x7d549362, 0xe1c956c0, 0x514bfd22, 0xd26a675b, 0xbdfe1a29, 0x04cc855c, 0x33f13004, 0xf7c4c753, 0x8c2367da, 0x0c1bebba, 0xe072fb75, 0x3b0bddb2, 0xee364509, 0xd2b11fdb, 0xd2b860ad, 0x277af197, 0xac8f4841, 0x32e0b82a, 0x667af41a, 0xb35e739a, 0x1fa78b60, 0xefe6d615, 0x92c2a7ba, 0x4fad1d19, 0xaabbc21c, 0x5141ffa3, 0x1c9d5467, 0x22221365, 0x81f7f3b7, 0x559357e6, 0x53ec3e09, 0x4bfbdf3d, 0x2d9ff612, 0x5e91c957, 0x336fae16, 0x574038b0, 0x9973a9e4, 0x877cab7b, 0xa07afcac, 0x77359195, 0x366b3335, 0xf78d3e7f, 0xe2b64afc, 0x2f474764, 0x11709fee, 0xf81efe37, 0xfafa7eb6, 0xedc06748, 0xabbb9c28, 0x2de89718, 0x720de58c, 0x74955261, 0xbaa726f3, 0xfaeb7bca, 0x36dd88c3, 0xff658280, 0x05bfdce0, 0x28c6b80c, 0xe03e296e, 0x0f0a714a, 0x5ca734e8, 0xd65036f2, 0xba994aaf, 0x1a28666c, 0x664c32ff, 0x81f4c33e, 0x1b3d92c7, 0xcdb03e43, 0x80d2e0d7, 0xedd40721, 0xb8b1235b, 0x2c60d12c, 0x8c7db652, 0xa3e70478, 0x90f39997, 0x6f9041b7, 0x130168c2, 0x89e29447, 0x7e7ecc8b, 0x718430d9 }, // Message 9 + { 0x52e547d9, 0xb170fba9, 0x04f4b83e, 0x1d4ca894, 0x2172af04, 0x2a255753, 0xc40671c5, 0xf7e2cc1e, 0x8186cb34, 0x455f51ef, 0xfb2fca8d, 0xe1bbd37e, 0x51b632b4, 0x9390ece9, 0x859aecfb, 0x295f3401, 0xe9d3e787, 0xf1c25b53, 0xa52f448f, 0x0afac83b, 0x9622a4ba, 0x0f0be543, 0xdb7f02ae, 0x8ae61d51, 0x81b9e719, 0x0082849b, 0x7e7f349c, 0xd27426e8, 0xce6f7bb3, 0xfee15619, 0x765c7b5a, 0xb63c9b36, 0xf0f683f7, 0xe45580d2, 0x87bac8ed, 0xa5da0c54, 0xecde7693, 0x449de9fa, 0x907691f7, 0x66fef5f9, 0x46aa0fc4, 0xfc8f1164, 0x07a4602e, 0x03ff47af, 0x40191395, 0x0e214f53, 0x2fc8408b, 0x07400050, 0xfced3dde, 0x7dcb6622, 0x374ee98c, 0xf8ea383d, 0x9549435c, 0x0c26d718, 0xf93c5102, 0x408ee062, 0xfa0ca7d9, 0xb98f419a, 0x2e60d6cb, 0x23bf4362, 0xda57b12c, 0xd706228e, 0x9f2b721f, 0xe1fd4168, 0xef042dcf, 0x1d0a4862, 0x6a5feb4f, 0xf05e70ae, 0x130c2065, 0xfda352f5, 0xd31b880a, 0x663ba883, 0x4b0423f0, 0x918ff7ab, 0x34a39cfd, 0xb014584b, 0x692cc10c, 0x32f7766d, 0x743ef57d, 0x4cb6c575, 0x244058c8, 0x9acfd3c6, 0xb7a9dec6, 0xa1183e73, 0xce1cee14, 0x98147360, 0xa83533e0, 0x00f33284, 0xb16439bf, 0xbb1ca5c7, 0x25040be8, 0x38b6a111, 0x2560117b, 0x7c4556fd, 0xa3983b01, 0x3db1afd2 }, }, + }, + { /* Case 1 */ + .iv = { 0x28, 0x98, 0x34, 0x8f, 0xcc, 0x04, 0x12, 0x70, 0x5c, 0x10, 0x9d, 0x34, 0x9f, 0x71, 0x14, 0xd0 }, + .p_data = { + .Y = { 0x0a7d2649, 0xff04a92e, 0x6daaab39, 0x2009f6ab, 0xd3c0506e, 0x1e37556b, 0x54948016, 0xba5bee4b, 0x069e25d1, 0x8b431099, 0x023823f7, 0xa79f1cb7, 0xff290429, 0x49c475ae, 0x46e3ffc0, 0xa2713a35, 0x2d4057fb, 0xc01d46f7, 0x2fb3cce3, 0x3f5df6fa, 0x954105cc, 0x2129c8e6, 0x5d336702, 0x65fc94b1, 0x1b8eecbc, 0x86f4ca88, 0x2fb5bd5e, 0x8ca29fa6, 0x49fa219c, 0x9c07ee09, 0x46624b31, 0x3a61868e, 0xbfff9cf3, 0x35d0fb3a, 0xc95021f9, 0x646d4730, 0xd71bd213, 0xf7715cb5, 0x0c9b452c, 0xf57e1d22, 0xe2970bfe, 0x28723bcd, 0x28960f77, 0x453af17d, 0xb1adc4a7, 0x3e5730d3, 0x42cbf974, 0xe7a81876, 0xaf42c832, 0x41b34359, 0xabdd44b2, 0xb52be073, 0x9075321b, 0xc4403990, 0x886cce4b, 0xe2f0cabb, 0xd9de1e3b, 0x5d044cbb, 0xbab20b39, 0x57799d78, 0x7984a95d, 0x0d2c0e33, 0x6d64c860, 0xa7d59473 }, + .M = { 0xd1ee431d, 0x59d19e48, 0xcc33d304, 0xfabdd511, 0x22b2406f, 0x2ce0ba09, 0x71f7ecc4, 0xa258c460, 0x6b8077c4, 0x8351d2ea, 0x1073137d, 0xb6a4ce18, 0x9a549663, 0x63da2203, 0xb3ccbe91, 0xc0e96187, 0x67996ce4, 0xe87d88d8, 0x6ed2da7a, 0xb2091f65, 0x3dab4d9c, 0xad5cd695, 0x1bea7884, 0x1d424f15, 0x3f221a5d, 0x930affca, 0x3076f5e4, 0xa3d01522, 0xa5ab37b0, 0xae88ce49, 0x857a962e, 0x80170df2, 0xe87bc96b, 0x07fa8734, 0xfd9fce7e, 0x07736dbb, 0xc8e52fc2, 0x05056744, 0xf104f851, 0xe6f66b5a, 0xe47c1638, 0x240c6fb4, 0x3cef51bb, 0xa8490acc, 0x5cb13fea, 0x70aa57be, 0x51fef53c, 0xd7daa545, 0xd867f233, 0xcb4630fe, 0xffe7f24e, 0xb5c7076b, 0x9a65ca87, 0xeb29bd00, 0x8ae68fd4, 0xfab6cdf9, 0xa17cf2d8, 0xa0de153c, 0x0019d70e, 0x84e7cf3f, 0x5c8c66fa, 0xdb7c2179, 0x1aeabaf0, 0xaf10bb23 }, + .Rb = { 0x5e4224d9, 0x34499f74, 0x1f9d96fd, 0x4fc48a10, 0x483a10e7, 0x8d701d43, 0xe707a2c1, 0x5746758c, 0x7467a20f, 0xfd605ad7, 0xcc2267d7, 0x31601983, 0x73ab70a8, 0x242271dd, 0x354229c9, 0x41801153, 0xde5694f1, 0xb35e74ad, 0xf3632e2f, 0xbcec730f, 0x95586b73, 0x3da3dfb3, 0x9746a72d, 0x3b9fd08b, 0x5c4da0f4, 0x2cbff8fc, 0x3260c9fc, 0x5095466d, 0x0abe9b44, 0xbb66ad50, 0x5d7eb466, 0xcd928a06, 0x636de21d, 0xa1725cb4, 0x9c862b88, 0x050b61c8, 0x46403bde, 0x91858baa, 0x3727331d, 0xb63e303a, 0x724aed74, 0x7abf0e8a, 0xbcdabe25, 0x3a84caf8, 0x1dfe643e, 0x4f0c286b, 0x7e285580, 0xa9ca8bd9, 0x3850f447, 0x55c662fc, 0x672582ae, 0x019bf1d9, 0x1eb3c5ec, 0x14be284d, 0x664ed150, 0x2a4b8b61, 0x5169540e, 0x25d3f0c5, 0x43f2eae0, 0x40f94130, 0x18d81099, 0x2b84ed17, 0x0c557e9c, 0x05deb5f3 }, + .M_prime = 0x017168cb, + .length = 63, // 2048 bit + }, + .expected_c = { 0xce, 0x77, 0xa8, 0x0a, 0xc8, 0x2a, 0x31, 0xe4, 0xcb, 0xb2, 0xf0, 0xef, 0xdd, 0xa8, 0xc6, 0x0d, 0x36, 0x63, 0x65, 0xe3, 0x55, 0x29, 0xf7, 0x53, 0xd2, 0xd2, 0xf2, 0xb8, 0x5d, 0x12, 0x87, 0xf7, 0x83, 0x44, 0xe0, 0xdd, 0x7d, 0x10, 0xee, 0xb6, 0x1a, 0xf7, 0xd6, 0xba, 0xc2, 0x01, 0x34, 0x00, 0xb3, 0xcc, 0xef, 0xed, 0x3a, 0xc7, 0x02, 0x12, 0x49, 0x82, 0x8e, 0xfd, 0x94, 0xd4, 0x52, 0x3f, 0x12, 0x90, 0x3e, 0x0b, 0x09, 0x1f, 0x43, 0xb4, 0xcd, 0x69, 0xb2, 0xa0, 0xa1, 0xff, 0xb9, 0x46, 0x0a, 0xc4, 0x0d, 0x54, 0xf1, 0x38, 0x1d, 0xc6, 0x64, 0x81, 0x6e, 0x49, 0x5e, 0x49, 0x28, 0xa0, 0x8a, 0xb8, 0xb2, 0x5d, 0xec, 0xb0, 0xf4, 0xa4, 0x4e, 0xfe, 0x73, 0xee, 0xb6, 0xe7, 0xcc, 0xcb, 0x0f, 0xd0, 0xbf, 0x49, 0xfd, 0xdd, 0xe3, 0xe4, 0x8e, 0xbf, 0xeb, 0xaa, 0x63, 0xe5, 0x14, 0x7a, 0xaa, 0x56, 0xa3, 0x87, 0xf7, 0xdf, 0xf4, 0x20, 0xb1, 0xdb, 0x17, 0x66, 0xff, 0x01, 0xdb, 0xb4, 0x6d, 0xcb, 0x91, 0x44, 0x41, 0x77, 0xa5, 0x85, 0xd4, 0x25, 0x6e, 0x16, 0xf2, 0xbd, 0xad, 0x1f, 0x9d, 0x4f, 0x5c, 0xe0, 0xa2, 0xb0, 0xb8, 0x7d, 0x75, 0x73, 0x55, 0x26, 0x5d, 0x23, 0x72, 0xf2, 0x99, 0x65, 0x55, 0xd4, 0x3a, 0xaa, 0xc3, 0xe0, 0x75, 0xbb, 0xb6, 0x3c, 0x50, 0xf2, 0x38, 0xc5, 0x51, 0x75, 0x67, 0xf5, 0xe3, 0xa2, 0x9c, 0x2d, 0x3f, 0x18, 0x5a, 0x32, 0x32, 0x43, 0x9e, 0x4e, 0xef, 0xab, 0x01, 0x1e, 0x1f, 0xe6, 0xb0, 0x89, 0x13, 0x3b, 0x99, 0x90, 0xbf, 0x73, 0xe4, 0xc1, 0xdd, 0x9c, 0x05, 0x69, 0x93, 0x13, 0xe4, 0xeb, 0x9e, 0x75, 0xdd, 0x32, 0xdf, 0x74, 0x66, 0xd8, 0x11, 0x0f, 0x4c, 0x36, 0xeb, 0xc4, 0x94, 0x9a, 0x34, 0x61, 0x7e, 0xe4, 0x55, 0x1c, 0x60, 0xc4, 0x3d, 0x1c, 0xa4, 0x06, 0x7a, 0xdd, 0x88, 0xe8, 0xb6, 0x79, 0x08, 0x4f, 0x42, 0xf6, 0x97, 0x5f, 0x93, 0x8c, 0x50, 0x79, 0xdd, 0x72, 0x75, 0x9c, 0xde, 0x71, 0x45, 0x13, 0x15, 0xb2, 0x24, 0x6d, 0xab, 0x21, 0x52, 0x5a, 0x81, 0xda, 0x16, 0x18, 0xd4, 0x4a, 0x1d, 0xfc, 0x78, 0xb7, 0x0c, 0xf9, 0xd9, 0x7f, 0x3f, 0xa9, 0x74, 0xd5, 0x0d, 0xe3, 0x1c, 0xd4, 0x51, 0xfe, 0xd1, 0x26, 0x6b, 0x42, 0xc2, 0x3a, 0xa2, 0x8d, 0x1b, 0x51, 0x07, 0x8d, 0xfb, 0xf5, 0x49, 0xf7, 0x94, 0xd0, 0x75, 0xf0, 0xc7, 0x7c, 0x1e, 0xfc, 0xe7, 0x61, 0xe8, 0x3f, 0x31, 0xe4, 0xf2, 0xab, 0x6e, 0x8e, 0x12, 0xc5, 0x0d, 0x63, 0xca, 0x0f, 0x02, 0x4e, 0x88, 0x5e, 0x2b, 0xc9, 0xef, 0x67, 0xc0, 0x60, 0xde, 0xb7, 0xcb, 0x51, 0xf6, 0xf0, 0x53, 0x5d, 0xd1, 0x88, 0x2d, 0x15, 0x3d, 0x8e, 0x6f, 0xee, 0x34, 0x31, 0x5a, 0xd3, 0xb3, 0x29, 0x5c, 0x55, 0x2a, 0xa1, 0x26, 0x83, 0x9c, 0x44, 0x87, 0xec, 0xbb, 0x45, 0x4c, 0xc0, 0x69, 0x91, 0x26, 0xa0, 0x54, 0x57, 0x8b, 0x62, 0x23, 0xb0, 0x71, 0x9a, 0x6d, 0x2e, 0x87, 0xb4, 0x36, 0x6d, 0x9c, 0xce, 0xdc, 0x9b, 0xe0, 0x03, 0x04, 0xbf, 0xd1, 0xdf, 0x0f, 0x05, 0xc2, 0xbb, 0xd8, 0xe5, 0x7d, 0xe9, 0xb5, 0x2d, 0x6b, 0xc2, 0x72, 0x95, 0x34, 0xa9, 0x1a, 0x5e, 0xa4, 0xfd, 0x71, 0xf5, 0x81, 0x64, 0xbc, 0xcb, 0x45, 0x9a, 0x7f, 0xdb, 0xd0, 0x09, 0xcf, 0xf2, 0x71, 0xcc, 0x54, 0xb7, 0x5e, 0x68, 0x3e, 0xa9, 0xcd, 0x4c, 0x36, 0x26, 0x75, 0x9e, 0x12, 0x6b, 0xf3, 0x4c, 0xe8, 0x09, 0x2a, 0x60, 0x13, 0x51, 0xfe, 0x31, 0xbd, 0x29, 0x3b, 0x6e, 0xb7, 0x8e, 0x9d, 0xce, 0x0d, 0x23, 0x39, 0xfd, 0xa3, 0x51, 0x48, 0x7e, 0xac, 0xbd, 0xb3, 0x28, 0x4b, 0xc8, 0x91, 0x4c, 0xc6, 0xac, 0xff, 0xc7, 0x64, 0x63, 0x11, 0xc1, 0x2c, 0x88, 0x24, 0x68, 0x75, 0x2f, 0x25, 0x1c, 0xe3, 0x08, 0x8a, 0x50, 0x39, 0xec, 0xb7, 0x78, 0x24, 0x69, 0xf3, 0x74, 0xad, 0xeb, 0xd0, 0x57, 0x02, 0x8e, 0xca, 0x6e, 0x42, 0xcf, 0xca, 0x7d, 0x58, 0x4d, 0x57, 0x28, 0xde, 0xde, 0x2b, 0x82, 0x30, 0xf0, 0x76, 0x26, 0x58, 0x50, 0x87, 0xd7, 0xdf, 0x92, 0xb1, 0x37, 0x89, 0xfb, 0xb7, 0x8e, 0x16, 0xf5, 0xef, 0x54, 0x8b, 0xab, 0x73, 0xf1, 0x61, 0xb2, 0xd2, 0x85, 0x94, 0x39, 0x39, 0x08, 0xd7, 0x12, 0x27, 0xdd, 0x2d, 0xb6, 0x74, 0x26, 0xc3, 0xd6, 0x07, 0xcb, 0x21, 0x4a, 0xeb, 0x70, 0xf1, 0x44, 0x9e, 0x85, 0x93, 0x99, 0xd2, 0x0e, 0x39, 0x4f, 0x45, 0x7e, 0x41, 0xd2, 0x2e, 0xe1, 0x9c, 0x8e, 0x03, 0x94, 0x7f, 0x6b, 0x48, 0x65, 0x25, 0x48, 0xad, 0x98, 0xf7, 0x2d, 0x3c, 0x42, 0x2f, 0x9e, 0x2f, 0x26, 0x1f, 0x04, 0xfc, 0x55, 0x4f, 0xa4, 0x43, 0xfa, 0x51, 0xd1, 0xb8, 0x93, 0x5e, 0x49, 0x21, 0x31, 0x1f, 0x98, 0x43, 0xba, 0xa7, 0xe0, 0x4e, 0x47, 0x96, 0xca, 0x75, 0x12, 0xed, 0x79, 0x4f, 0x32, 0x0b, 0x1f, 0xbe, 0xf8, 0x25, 0xca, 0x35, 0x56, 0xc5, 0x8f, 0x82, 0x3a, 0x09, 0xf4, 0x01, 0x07, 0x91, 0x7e, 0x08, 0xf8, 0xf7, 0xf1, 0x0b, 0x91, 0x2a, 0x78, 0xbd, 0xf6, 0x5c, 0x23, 0xb3, 0x47, 0x43, 0x73, 0x69, 0x14, 0x44, 0x6f, 0x1c, 0x61, 0x7b, 0x56, 0xe6, 0x0b, 0x44, 0xbd, 0x58, 0xda, 0x58, 0x2b, 0x1a, 0x98, 0x96, 0x13, 0xa0, 0x4d, 0x79, 0x44, 0x5a, 0x25, 0xdc, 0xf4, 0xc5, 0x1d, 0xc6, 0x4a, 0x63, 0x81, 0x52, 0xce, 0xd2, 0x94, 0x5f, 0x6f, 0x2b, 0xbc, 0x72, 0xdb, 0x5e, 0xed, 0x67, 0x28, 0x72, 0x2e, 0xa2, 0xa3, 0x45, 0x88, 0xd6, 0x88, 0x3d, 0xce, 0xdc, 0x23, 0x93, 0xeb, 0x1b, 0x49, 0x6b, 0x52, 0xea, 0xaa, 0x8c, 0x9c, 0xb3, 0xb9, 0x36, 0xfa, 0x00, 0x2c, 0x88, 0x9e, 0x19, 0xe0, 0x06, 0xa6, 0x1a, 0x1a, 0xda, 0x33, 0x4d, 0x61, 0x38, 0x17, 0x6c, 0x4f, 0xe8, 0xb7, 0x85, 0xb7, 0x8e, 0xac, 0x69, 0x5d, 0x65, 0x8d, 0x5e, 0x5c, 0x18, 0xdf, 0x66, 0xe1, 0x3d, 0xee, 0xe1, 0x24, 0x45, 0xdf, 0x91, 0x5a, 0x03, 0xe5, 0x57, 0x3f, 0x19, 0x06, 0x33, 0x71, 0xe3, 0xcf, 0xda, 0xc5, 0x72, 0x8e, 0x65, 0x9f, 0x4b, 0xf1, 0x43, 0x7c, 0x30, 0x34, 0xe5, 0x59, 0xda, 0x74, 0xae, 0x20, 0x51, 0x09, 0x99, 0xf2, 0xc9, 0xf2, 0xf0, 0x57, 0x3d, 0x7d, 0x3f, 0x0a, 0xa7, 0x6b, 0x0e, 0x04, 0x9e, 0xb5, 0xa6, 0x25, 0x4b, 0x33, 0xde, 0x47, 0x05, 0x4d, 0x7a, 0x1c, 0xcc, 0x0b, 0x7f, 0x9b, 0x34, 0xcb, 0xa9, 0x00, 0xa5, 0x67, 0x4e, 0xd4, 0xbd, 0x39, 0xb8, 0xe9, 0xc2, 0xaf, 0xf6, 0xed, 0xf9, 0xbb, 0x6e, 0xb4, 0xfb, 0x04, 0xcf, 0x60, 0x74, 0xfc, 0x43, 0x2c, 0xac, 0x44, 0x3f, 0xf1, 0x3a, 0x05, 0x4c, 0xd1, 0x07, 0x68, 0x18, 0xd6, 0xe4, 0x36, 0x70, 0xe8, 0xd2, 0x92, 0x1e, 0x8e, 0xe5, 0xfe, 0x3e, 0x74, 0x29, 0x49, 0x53, 0x66, 0x2c, 0x6c, 0xb3, 0xd9, 0x6e, 0x3b, 0x8c, 0xee, 0x7b, 0xbf, 0x7b, 0xe3, 0xb2, 0x91, 0x08, 0xaf, 0x7e, 0x39, 0x9a, 0xbf, 0x3d, 0xdd, 0xb9, 0xee, 0x4d, 0x5e, 0xcc, 0xed, 0x04, 0x1b, 0xbe, 0x21, 0x43, 0x67, 0xc9, 0xb1, 0x96, 0x56, 0xaa, 0x70, 0x03, 0x50, 0xe1, 0xa3, 0x19, 0x1c, 0xec, 0xa4, 0x31, 0x28, 0x96, 0x47, 0x1f, 0x28, 0xce, 0xb2, 0x8e, 0x20, 0xfc, 0x2f, 0x52, 0x14, 0x47, 0xa1, 0xca, 0x27, 0x6f, 0x00, 0xe5, 0x72, 0xfd, 0x96, 0x34, 0x02, 0xf4, 0xd8, 0xd3, 0x10, 0xa7, 0xc8, 0x36, 0xca, 0x5a, 0x27, 0xfb, 0x8a, 0x00, 0xda, 0x38, 0x1d, 0x10, 0xda, 0x26, 0xc1, 0x04, 0x02, 0x6b, 0x92, 0x7f, 0x5d, 0x2d, 0x8e, 0x2d, 0x8b, 0x31, 0x13, 0x25, 0x40, 0x47, 0xf8, 0x7e, 0xa0, 0xe1, 0x27, 0xf9, 0x0a, 0xe4, 0xb9, 0x8b, 0xa3, 0xf6, 0xd6, 0xc1, 0xb2, 0x2e, 0x8f, 0xa3, 0x9a, 0x25, 0x95, 0xfc, 0xc7, 0xa8, 0x85, 0xd1, 0x3a, 0x10, 0x65, 0xbd, 0xba, 0x5a, 0x15, 0xfd, 0x6d, 0xe7, 0x8c, 0x20, 0x9e, 0x13, 0x34, 0x52, 0x4a, 0xb3, 0x64, 0xec, 0x82, 0xc7, 0xa6, 0xc4, 0xd3, 0xdb, 0x22, 0x12, 0xee, 0x5d, 0xec, 0xbe, 0x1f, 0xda, 0xeb, 0x69, 0xca, 0xe7, 0x83, 0x8a, 0x1e, 0x03, 0x19, 0xca, 0xb3, 0x6d, 0x38, 0xfb, 0x93, 0xb3, 0x32, 0x79, 0x99, 0xaa, 0x23, 0x04, 0x49, 0x3d, 0xdb, 0x63, 0x05, 0x0f, 0x43, 0xaf, 0xb1, 0x51, 0x0e, 0xbc, 0xc7, 0x98, 0x58, 0xa2, 0x19, 0xfe, 0x1d, 0x39, 0x4a, 0x22, 0x1e, 0x7b, 0x3d, 0xe3, 0x2d, 0xf5, 0xbe, 0xe6, 0x81, 0x3c, 0xda, 0x2a, 0xf0, 0x13, 0xcd, 0x9f, 0x9f, 0x05, 0xa8, 0x0a, 0x89, 0x34, 0x98, 0xde, 0x1d, 0x3d, 0x0c, 0x7a, 0x10, 0xbc, 0xb3, 0x39, 0x04, 0x45, 0x89, 0x29, 0xd0, 0x10, 0xd3, 0x7f, 0xf9, 0x97, 0xdd }, + .hmac_key_idx = 2, + // results of message array encrypted with these keys + .expected_results = { + // Message 0 + { 0x0945b2b4, 0x054757f4, 0x8f765a17, 0x60d13fd8, 0x4589a098, 0x24c11112, 0x591fa9b2, 0x779be5c0, 0xb3b31cd7, 0x58a5a406, 0x9e99370b, 0x200af50a, 0xce16016e, 0x0d882a0f, 0x75ec7e0e, 0x25d6a694, 0x29fa562a, 0xc6504c6b, 0x3c2f0602, 0x12832577, 0x7b31685b, 0xf2e2ef3c, 0xed20276d, 0xdb765155, 0x8a68bb78, 0x87e993db, 0x29bc2857, 0x2b15c314, 0x08c616b7, 0x8e494e75, 0x21cd6e36, 0xd2450ee9, 0x85bd8d5c, 0x77d33531, 0x3e865931, 0x630a1882, 0x37c746d2, 0x9dd15386, 0x0e0367cd, 0x6976903d, 0x3908a5ae, 0xb9698ee7, 0x73143a8f, 0x690aca4a, 0xfc96ca1f, 0x90811ed8, 0x634de27e, 0x05e1499a, 0x03ddea52, 0xa736f4d0, 0xf47f60ec, 0x5150f85e, 0x45730753, 0x7086e797, 0x24ac2057, 0xd84dca26, 0x43417f70, 0x99283765, 0x1e0eed11, 0xb901ac56, 0x6b106d2b, 0x088c3e59, 0x6e93b58b, 0xa445726e }, // Message 1 + { 0x976f1acd, 0xee9d9748, 0xe8e71778, 0x158b14ff, 0x6a91e2e3, 0xb6083da2, 0x6c54e624, 0x1ad20801, 0x0eaa96ae, 0xb15cacf1, 0x6e57dd0c, 0x811a8f5f, 0xa655cd02, 0x7268a8e5, 0x7c973283, 0xb2d2edcf, 0x8199fcd1, 0xf6b40718, 0x12d8aab2, 0x0b5aa12a, 0x6f78345e, 0x3c383278, 0x26dc4a48, 0x060eb57f, 0xe22721e4, 0x16a4bf26, 0x08d431b7, 0xc833d1f5, 0x08c3f121, 0x7a8ab9df, 0xa1b3ba9f, 0x4ee9c021, 0xaafc7019, 0x524ea77e, 0x5070be2e, 0xfaaee387, 0x4f9c1869, 0xee8387ff, 0x709a38f8, 0x917f89d9, 0x95d19532, 0xfaefe80c, 0xda887d1d, 0x37501c93, 0x214c8b82, 0x8c8c4c1c, 0x9213f447, 0x97fa04d5, 0x6cc5669e, 0xf3d48973, 0xcf872c12, 0x2097382d, 0x2bde8215, 0x9d6c8250, 0x7d885fd3, 0x915e3407, 0xcd3969af, 0xfa98e7f7, 0x1975f1b2, 0xf41f0919, 0x996ed33d, 0x2d82f14f, 0x84f4483b, 0x7023639a }, // Message 2 + { 0x728f6465, 0x298bf54f, 0xfdccb8b4, 0xc7c29b2c, 0x41d3089f, 0xb0dab85d, 0x1ea8fb39, 0xf0f34e4c, 0xdd5de5eb, 0xd5dd8254, 0x829684e0, 0x5fa1cf0b, 0x2b5b3d33, 0xc05fae66, 0xf8fd70f2, 0x6b80677c, 0x2ac471ff, 0x6cbc4896, 0x834348d0, 0x4d464f3f, 0x7f52d488, 0x9358cc35, 0xa1d66d2f, 0xd901c364, 0x6cbf0166, 0x360347dc, 0xedbea94d, 0x60181101, 0x9996def9, 0x6ba0c54a, 0x173e8d6c, 0x30105b98, 0x7f1d505d, 0x96620056, 0xa16fff55, 0xd2e0ab8a, 0x589ccf44, 0xacd34cb5, 0x322615b4, 0x5e81a792, 0xd861e43f, 0x23c27a48, 0xc12656d9, 0x45313dec, 0x15d8bcde, 0xc679ffb2, 0x6523c369, 0xe2337bf5, 0x355ec371, 0xeeba8907, 0x361d806f, 0x3c67cbe5, 0x4133d02c, 0x6edb53b6, 0xc28f03f7, 0x6d0273e4, 0x46ecbdb3, 0x14e95ec5, 0xb520fc1c, 0x93c23a22, 0x56f6b92e, 0x427859a0, 0x6ffbea14, 0x2383a340 }, // Message 3 + { 0x4fdd63fb, 0x903b9d11, 0x3dee8665, 0x860fd5b7, 0x29e98634, 0xb8412dad, 0xbdd67d55, 0xaabefc04, 0x483bd926, 0x26559898, 0x2c4e31d7, 0x300dc466, 0xf8f8b2ec, 0x91f6c3f1, 0x87c2d7db, 0x65dcc837, 0xe657f513, 0xa5ca475b, 0xb33d5c4c, 0x8189ac9f, 0x968e94ae, 0xe30e687c, 0xaee961c5, 0x3bfab1c4, 0xad3738d8, 0xb24bccb0, 0x6c2ed1bd, 0xba9bf32f, 0x47ffd571, 0x92d1ef64, 0xbae9fe4c, 0x957ebf4c, 0x51a60e0d, 0x20230935, 0x3ece96b7, 0x20515d9c, 0x26be4a33, 0xf6e4c5ee, 0x8f4c0576, 0xda5497f1, 0x07026257, 0x7ad56f7f, 0xaf952734, 0x96239be4, 0x6cdc67f9, 0x120e8fa3, 0xf2b0d5e4, 0x05acc5d6, 0x52843aac, 0xac9b9e69, 0xa0b49a50, 0x24e095a2, 0xcee0be5c, 0x1a524c29, 0xfd708113, 0xe59fef24, 0x88d25a0c, 0x4883be17, 0x126edcd6, 0x629080cd, 0x2d746261, 0x29e4a53d, 0x681459dd, 0x69bf86b5 }, // Message 4 + { 0x521493f5, 0x184057aa, 0x72dbd9e7, 0x9451c2b3, 0x01a91ce0, 0xeff23076, 0x1d1ffdbd, 0x1d25f64b, 0x86b6322f, 0xc29cd86b, 0x3e166ce2, 0xbec9e422, 0x9a782d2b, 0x809109f9, 0xa9c303da, 0x5ce55dd8, 0xcb4cf002, 0xaa0d6b75, 0x9fd84600, 0x598c381d, 0x8f6f36bf, 0xe9931438, 0x91f32468, 0xf487b9a4, 0x742826a1, 0xfc94b2f8, 0x88e62c89, 0xf84d1f69, 0x7657b53e, 0x445c3067, 0xaa7b4b18, 0x3a8117a2, 0xfd919088, 0xa760a292, 0xd602c2b6, 0x7171536a, 0xf0722c15, 0xae7cb027, 0x5073e7cc, 0x5b7273b8, 0xdffe32b7, 0xcd02e42d, 0x1b9d9aab, 0x8664d51e, 0x14b741c4, 0xc82bd736, 0x52c91186, 0xec36ed9f, 0xa5640ceb, 0x8250292c, 0x6d8de316, 0x2d7d2ec8, 0x018bcf22, 0x9bbc053e, 0x2646ccf6, 0x7eec12f4, 0xc842fd06, 0xa48462d4, 0x37e3d3e6, 0x9bbcbd5a, 0x36a17aae, 0xb418b850, 0x67c8f8ce, 0x6750d407 }, // Message 5 + { 0xd02b7d24, 0x4017506b, 0x054459a9, 0x49bc64fc, 0x86ed843a, 0x354c41d8, 0x1f5b9dfa, 0x69a3321e, 0x03ca042b, 0x6fb9751c, 0xdeb0b33e, 0xaed2824a, 0x47bf7db9, 0xad5f816f, 0xacaf8c7e, 0x69e8034a, 0x4f86c368, 0xe426ec4b, 0x7e96fba2, 0x06ef68b2, 0x3327432c, 0xafeee978, 0xe4176b92, 0x90dc7e28, 0x4f2415e9, 0x26ff05db, 0xd039565c, 0x0e497ea9, 0xaf96d11f, 0x06d90a8b, 0x20727fdb, 0xc04d60e6, 0xd7486d92, 0x3fea5fb6, 0xed0d0547, 0x560f74ed, 0x488bc7de, 0xa542a5e7, 0xe892f78a, 0x610b68c9, 0xbdaacc00, 0x04192fd7, 0x1e9ddcf9, 0x1c6e8ca5, 0x80a6a17a, 0x84da4b96, 0x3c2b5282, 0x49f78f6d, 0x449782a9, 0x966df1d1, 0x80ac68da, 0x08eb61b3, 0xfd4b00e1, 0x2dc62d60, 0x9eecdc6c, 0xd562d247, 0xd919b50f, 0x89c51929, 0x64654b23, 0xbd744ae3, 0xf04059fa, 0x2825f240, 0x8083e068, 0x0454ec74 }, // Message 6 + { 0x4a00eaca, 0xbdeb2fc5, 0x7084074b, 0xa655329d, 0xb72b49db, 0x0174a93a, 0xbdc60cde, 0x63e323af, 0x3a5c3e95, 0xb648fc72, 0xe46b10be, 0xe483c3c4, 0xe61b71e7, 0x0608fc1b, 0x24f35f29, 0x165e9aa5, 0xb0d41334, 0x6d578f51, 0x5c21614d, 0x29548543, 0x543789e8, 0x731cd402, 0x116fa594, 0x01381bc4, 0x557a57ad, 0x0ab39ab4, 0x9a8617d8, 0xa2c753b4, 0xf6f4ef7f, 0x597c100b, 0xd0b58aec, 0x76619039, 0xfbe3f316, 0xffc0400d, 0x3ee89eaa, 0xe79f2ad3, 0x7399372e, 0x859877be, 0x4253e36b, 0x635b8c4c, 0xa0cb5223, 0x3c509eb1, 0x388fd2fa, 0x0e0f6b5b, 0x4fb38e90, 0x910f9d6a, 0xf4cf76a8, 0xf7bcdc96, 0xc3b76677, 0xf4aaa20e, 0x13e4470b, 0x79e7b7e3, 0xa28d5a61, 0xa1b33d0f, 0x4b23f0c1, 0xd6800659, 0xef2affba, 0xc664d556, 0xc921bf2d, 0xe70b50c4, 0x6c7aa113, 0xbe27e7f1, 0x392a892c, 0x3127539d }, // Message 7 + { 0xc8e36f8e, 0x272f2ffe, 0x7b8bda29, 0x0f183f1d, 0xc72066d5, 0x54574fb5, 0x39acb1ac, 0xa2420a0a, 0xe5de4ed3, 0xf85343fa, 0xb49eef94, 0x34826793, 0xcf309551, 0x94b349b7, 0xb21b8e9b, 0xfe84b59e, 0x8304da6b, 0x57cc10f6, 0xcd4d1a1e, 0x3e018268, 0x1b9c0e6b, 0x1a0e3d2f, 0xb046a38f, 0x2d189663, 0x01ca779a, 0x3f4a96b2, 0xa788e283, 0x88a31242, 0xa71faee8, 0xcbac9d62, 0x165acbed, 0xe6b4fc18, 0x2f4735e5, 0x8090d057, 0x1f81f973, 0xf458590a, 0x16ffcff3, 0xaa135c2e, 0xd9a9a480, 0x66a146ce, 0x4676c4d0, 0x1e6d3ac5, 0x29152f65, 0x44218661, 0x319e0216, 0xd265e3db, 0xa59e2f02, 0x9cf28d2f, 0xd81c8f7a, 0x84c0f216, 0x3f3887d7, 0xf2bca18d, 0x101cbd8d, 0x9ad60f6a, 0xc4c649fa, 0x3b328865, 0x4ccf84dd, 0x5d3d2ee5, 0xceb4175d, 0xa85c21bf, 0x899c2d62, 0x9fb19571, 0xa0287467, 0xabe9ce38 }, // Message 8 + { 0x05a9d8b6, 0x0db4c7f3, 0x476b358b, 0xa2291a8c, 0x1d003d6e, 0x27190d47, 0xeb2736b3, 0xa993dc4a, 0x3d9dfe33, 0x494f947c, 0x770b64ce, 0xa0af0083, 0x49502ad9, 0x45c8a90e, 0x65b47e45, 0x56c7f761, 0x27946a6a, 0x9cb3bd24, 0x2058c932, 0x1e66caee, 0x1231ada0, 0xbc6b8804, 0x90767ed2, 0x384f1a77, 0xa666b775, 0xce2ab541, 0x1ae561d1, 0x0e6e5c7b, 0x912d3e48, 0xe8e6216e, 0x2ca3695a, 0xb07d024a, 0x0e073ae8, 0x0dc2d346, 0x686b4b69, 0x14971211, 0xb7b15c14, 0x8d2b1569, 0x14eab77f, 0xaaa24d7a, 0x5c452889, 0x8a6be8bd, 0x5b727432, 0x72a37c1a, 0xf9614eeb, 0x5eb9d8b0, 0xb06fc403, 0xd94c11f9, 0x7b623c0f, 0xe1a477ae, 0x7c2f8d75, 0x63a631a1, 0x787a316b, 0x2244628b, 0x2faed554, 0x0baa0388, 0x4986df09, 0x494172e2, 0xb062f78a, 0x8a6936ed, 0xa65fe593, 0x81e1e6f8, 0x7dfe0ab0, 0x2be2a9b3 }, // Message 9 + { 0x19513121, 0x360ca394, 0x2c828866, 0xd45b8572, 0xadd669df, 0xb86af352, 0xa3eaffef, 0xfb4dd6cb, 0x450f1bfe, 0x0eb23f4a, 0x993bac03, 0x926f1328, 0x74bbfff6, 0xa40e0490, 0xaaf95a42, 0xfcbf937e, 0x660dbe5c, 0x920095a9, 0xdce74fc4, 0xc41af89f, 0x57e6f740, 0x2236c5dd, 0x02472152, 0x41284124, 0x06ddebd9, 0xeb56cdfb, 0x285a78a4, 0xaf914788, 0x87b93b5e, 0xeadf441f, 0x741eb3b9, 0x3806e001, 0x06ea2d79, 0x44f464b6, 0x051f1563, 0xeb545642, 0x3bf62f96, 0x363e1cc7, 0xce83eda6, 0xe20d6352, 0xd109f1d5, 0x0cedb178, 0xe29dcc9d, 0xb347a0bd, 0x851ffabc, 0x9b3d3b0c, 0x8dae1c55, 0x04a3f933, 0x9b8cf4b0, 0xda3e3a80, 0x399b36d1, 0xce6f1991, 0x58cc7322, 0xb56f5d55, 0xb5ce99c6, 0x4be7fe50, 0xdf7ccfcf, 0x8f6da12a, 0xc177c2b6, 0xbb402145, 0x0c74865b, 0x40b243c2, 0x7d9e20f5, 0x3163db75 }, }, + }, + { /* Case 2 */ + .iv = { 0x2a, 0x0c, 0x15, 0xc2, 0x39, 0x0d, 0x56, 0x37, 0xda, 0x53, 0x58, 0x8b, 0x33, 0x0d, 0xe1, 0xa0 }, + .p_data = { + .Y = { 0x42018cc1, 0x5570b4b5, 0x3b244341, 0x548e492c, 0xf45e6df0, 0x29a8427c, 0x54a4261f, 0xa639229b, 0x3a476ab9, 0x50e2e93b, 0x49bbbce5, 0xf899d452, 0xddf462bd, 0x5a1f1188, 0xcc9567fb, 0xc390b628, 0x81ca8c54, 0x66eff475, 0x2ee8fe90, 0xffb602a9, 0xecba5807, 0x47087d42, 0xb99432e5, 0xd6c8e3d3, 0x4b8c7539, 0xfd1f6865, 0xaff6074b, 0x900e756d, 0x9ea4727a, 0x1253260f, 0xa0ef53d5, 0x5edebf0a }, + .M = { 0x1183afb3, 0x49b2d855, 0xc1d6dc2e, 0xd50f7b62, 0x020e3c7a, 0x0be0bc65, 0x3e6e8f98, 0x0a732ab1, 0x90fc3e18, 0x905ba0b5, 0x799bfcaf, 0xb677eaf5, 0x56418d29, 0xa3063d0e, 0x4fd11a6e, 0x59d70a1e, 0x28ffb961, 0x5c31bf1e, 0x74ebc5e0, 0x71da91bd, 0x55552e27, 0x63ed46c3, 0xae1cffae, 0x9733c550, 0xa0af8651, 0xef5625ca, 0x6d4a1f69, 0xbf980a4e, 0xaee3e705, 0x3e0dbe5a, 0x4cce965e, 0xe043a585 }, + .Rb = { 0xc5a8b012, 0x6710ac99, 0x29a55534, 0x2d85b2cd, 0x881c0b55, 0xefa0b081, 0x93bc798b, 0x83831a0d, 0x34f7511d, 0xe5e42fb6, 0x63bd3cb9, 0x61eb9ee1, 0x176d1a7f, 0xa54904bf, 0xca532666, 0x28d312b9, 0x0b214b43, 0x2d73a77d, 0x53dcc012, 0xd6fe7785, 0xdfed3ca4, 0x19ae4a07, 0x03441d1d, 0x0767f32d, 0xd0a99fd2, 0xfd986f61, 0x30d6386e, 0x33cc9e91, 0xbd7ef5e0, 0x881a833a, 0xd344478e, 0x8650aa28 }, + .M_prime = 0xd9776885, + .length = 31, // 1024 bit + }, + .expected_c = { 0x96, 0xa4, 0x25, 0x0c, 0x43, 0x48, 0xe0, 0x6a, 0x57, 0x8a, 0xe1, 0x4d, 0xe7, 0xf6, 0x6a, 0x5e, 0xa6, 0xa9, 0x1d, 0x0c, 0x07, 0xd4, 0x44, 0xa4, 0x8e, 0xf5, 0x05, 0x4c, 0x1b, 0xa8, 0x64, 0x2a, 0x19, 0xd9, 0xf6, 0x28, 0x79, 0xf2, 0x7b, 0x38, 0x87, 0x0a, 0xc6, 0x39, 0xf4, 0xb0, 0x5f, 0x49, 0x86, 0x22, 0xe2, 0xd8, 0x8b, 0xfe, 0xc3, 0xba, 0xe9, 0xf0, 0x87, 0x60, 0x91, 0x14, 0x0a, 0xfa, 0xe3, 0x27, 0x77, 0x86, 0xb9, 0x28, 0x9b, 0x04, 0xd5, 0xd3, 0xf6, 0xd3, 0xc0, 0x57, 0x17, 0xa2, 0xc7, 0x3d, 0x29, 0x8f, 0xc9, 0x73, 0x5d, 0x86, 0xa5, 0xd3, 0x0d, 0x5c, 0x22, 0xa3, 0xd0, 0x49, 0x76, 0xe3, 0xa1, 0xe0, 0x9c, 0x4a, 0xcf, 0x69, 0xbc, 0x03, 0xc3, 0x2d, 0x18, 0x1f, 0xcf, 0xab, 0xc4, 0x5a, 0x45, 0xc8, 0xa4, 0x12, 0x64, 0x0b, 0xbc, 0xec, 0xc4, 0x10, 0xdc, 0x69, 0x83, 0xb0, 0xa9, 0x8b, 0x47, 0x01, 0x22, 0x14, 0xeb, 0x39, 0x74, 0x40, 0x91, 0x7f, 0xd7, 0x4b, 0x70, 0xb7, 0xc3, 0x68, 0xd0, 0x99, 0xdc, 0xa0, 0xe7, 0x5d, 0xae, 0xb3, 0x7f, 0xd9, 0x00, 0x8a, 0x31, 0x80, 0xaa, 0xc8, 0x14, 0xf4, 0xe6, 0xae, 0x25, 0x45, 0x46, 0x14, 0xa8, 0x7f, 0xa7, 0x86, 0xbe, 0xf5, 0x15, 0x03, 0x5e, 0xca, 0x7f, 0xc9, 0x61, 0xd1, 0x06, 0xf1, 0x79, 0x9b, 0xca, 0x2f, 0xbc, 0x3b, 0xe1, 0x86, 0xd3, 0xe9, 0x29, 0x41, 0xe4, 0x43, 0x43, 0x49, 0xee, 0x0c, 0x21, 0xb5, 0xb3, 0xbc, 0x0d, 0x93, 0x83, 0x95, 0x05, 0xfb, 0x34, 0xc8, 0x14, 0x7b, 0xfe, 0x18, 0xd7, 0x31, 0x0d, 0x4c, 0x08, 0x1d, 0x96, 0x3f, 0xbf, 0xaa, 0x6f, 0xc9, 0xc1, 0x31, 0xa4, 0xcd, 0x37, 0x3f, 0xf0, 0xc9, 0x70, 0xbb, 0x66, 0xd0, 0xaf, 0x2d, 0x3c, 0x18, 0xbb, 0xf7, 0x55, 0x84, 0xa4, 0x65, 0x3a, 0x3e, 0x69, 0x24, 0x81, 0xa7, 0xf3, 0x6f, 0xdd, 0xe2, 0x6c, 0x49, 0x9f, 0xe5, 0x2b, 0x11, 0xa6, 0xd3, 0x66, 0x26, 0x05, 0x20, 0x16, 0xd0, 0x44, 0x97, 0xe4, 0xc8, 0x73, 0x5a, 0x76, 0xfa, 0x6c, 0xe2, 0x31, 0x87, 0x90, 0xa4, 0x61, 0x46, 0x67, 0xf5, 0xcf, 0x7b, 0x9b, 0xd2, 0x4c, 0xff, 0x20, 0xa3, 0x9c, 0x44, 0x1e, 0x85, 0x4b, 0xb2, 0xc8, 0x87, 0x55, 0x78, 0xe3, 0x92, 0xb1, 0xc5, 0x9c, 0x94, 0xd1, 0x2d, 0x8c, 0x87, 0x7d, 0x66, 0xdd, 0x57, 0xee, 0x4f, 0x14, 0x7d, 0x09, 0xd7, 0x70, 0x09, 0xc1, 0x6c, 0x2f, 0xb9, 0xce, 0xb9, 0xd0, 0x14, 0x6f, 0x39, 0x57, 0xe5, 0xde, 0x37, 0x75, 0xd8, 0xd7, 0xfd, 0x66, 0xef, 0x6a, 0xe0, 0xba, 0xe0, 0xaa, 0x99, 0x9d, 0xf2, 0x34, 0xac, 0x95, 0x2b, 0x3c, 0xab, 0xd9, 0x8c, 0xcb, 0x22, 0x58, 0x54, 0x9f, 0x20, 0xb5, 0xcc, 0x66, 0xea, 0xc1, 0x47, 0x0a, 0x55, 0xc8, 0x97, 0x14, 0xd6, 0x97, 0x2d, 0x1c, 0x1b, 0xdc, 0xbb, 0xd8, 0x47, 0x24, 0xb3, 0x05, 0x82, 0x50, 0xa5, 0xa1, 0x13, 0x66, 0xd3, 0x6f, 0x23, 0x42, 0x4e, 0x40, 0x5e, 0xec, 0x6b, 0xbb, 0x5e, 0xdc, 0xc0, 0x53, 0xe5, 0x84, 0x70, 0xbb, 0x37, 0x37, 0x0b, 0x2f, 0xae, 0x17, 0x02, 0x1d, 0xf3, 0xfd, 0x4d, 0xe3, 0x86, 0xa4, 0xb6, 0x4c, 0x13, 0xfd, 0xee, 0x81, 0x32, 0x48, 0x81, 0x34, 0xbe, 0xe2, 0xa6, 0x3d, 0x3c, 0xb0, 0x8f, 0x4b, 0x91, 0xc6, 0xea, 0x6b, 0xc2, 0xa9, 0xd1, 0x77, 0x3c, 0x11, 0x4d, 0xa4, 0xde, 0xc2, 0x56, 0x36, 0xba, 0xdb, 0x39, 0xf0, 0x64, 0x97, 0x45, 0x42, 0x18, 0xfb, 0xe8, 0xec, 0x34, 0x86, 0xf0, 0x89, 0xff, 0x79, 0x67, 0xdc, 0x97, 0xe5, 0xd4, 0x09, 0xd2, 0x15, 0x4d, 0xe7, 0x5c, 0x61, 0x37, 0xdd, 0x11, 0x46, 0x10, 0x04, 0x9f, 0x77, 0xf6, 0x8c, 0xcd, 0xc0, 0xc9, 0x11, 0x34, 0xc3, 0x74, 0xdc, 0x76, 0xf3, 0x23, 0x62, 0x73, 0x44, 0xb4, 0xc9, 0x1f, 0x9a, 0xeb, 0xff, 0x09, 0x62, 0xda, 0xd3, 0x8d, 0x37, 0xda, 0xb8, 0x6b, 0xb7, 0xd2, 0x56, 0x90, 0x99, 0x97, 0x39, 0xf8, 0xb2, 0xcf, 0xbe, 0x04, 0xba, 0x37, 0x54, 0x3f, 0x78, 0x5a, 0x06, 0xde, 0x06, 0xaa, 0xcb, 0xf1, 0xba, 0xc5, 0x66, 0x3b, 0x3e, 0xca, 0x23, 0x99, 0x86, 0xee, 0x71, 0x44, 0xf7, 0x6b, 0xc2, 0xd5, 0x14, 0xc8, 0xbd, 0x11, 0x79, 0xb1, 0x79, 0xa9, 0x7a, 0xf5, 0xcf, 0xa6, 0x8f, 0x4f, 0xbd, 0x50, 0x13, 0x72, 0xf1, 0x80, 0xa3, 0x84, 0x76, 0x4b, 0xa6, 0x10, 0x83, 0x58, 0xd0, 0x1f, 0xc5, 0xfc, 0x60, 0x62, 0x8f, 0x8e, 0xe7, 0x2f, 0xf5, 0x0b, 0xce, 0xaa, 0xce, 0x34, 0x4d, 0x2f, 0x1a, 0x55, 0x2d, 0x62, 0x93, 0x69, 0x70, 0x5f, 0xbe, 0x55, 0xd0, 0x38, 0x33, 0x7a, 0x21, 0x15, 0xa2, 0xe1, 0xed, 0x87, 0x5e, 0x8e, 0xc0, 0xab, 0x08, 0x4f, 0x14, 0x74, 0x49, 0xec, 0x2d, 0xd2, 0x01, 0x3a, 0x2b, 0xba, 0xb7, 0x72, 0xb0, 0xe8, 0x8d, 0xfc, 0x25, 0x1c, 0x55, 0x85, 0x25, 0xf8, 0x53, 0x95, 0xb1, 0x38, 0xbc, 0xed, 0xfb, 0x60, 0xf4, 0xd2, 0x29, 0xd5, 0x30, 0x28, 0x59, 0xd1, 0x5c, 0x3a, 0x15, 0xee, 0x04, 0x09, 0x17, 0x9f, 0x7a, 0xb8, 0x84, 0xf4, 0x2e, 0xe5, 0x98, 0x4b, 0xb2, 0x29, 0xd6, 0x18, 0xc7, 0x3e, 0x45, 0xc0, 0x8f, 0x77, 0xb1, 0x10, 0xa6, 0xc5, 0xb1, 0x29, 0x2b, 0xbe, 0x95, 0x43, 0xa9, 0xcb, 0x0e, 0xf8, 0x71, 0xda, 0x10, 0x1d, 0x48, 0xfa, 0xdf, 0x85, 0xee, 0x9c, 0xf4, 0x03, 0x41, 0xde, 0xb6, 0x20, 0x8a, 0xd5, 0xcd, 0x41, 0xa9, 0xc5, 0xc7, 0xb6, 0xcc, 0x52, 0xec, 0x4b, 0x2f, 0xce, 0x75, 0xa2, 0x50, 0x69, 0x1e, 0x28, 0x62, 0xe8, 0x1f, 0xcf, 0x5e, 0xff, 0x5c, 0xb8, 0xdf, 0x9b, 0x9f, 0x6d, 0x43, 0x1c, 0xf6, 0x84, 0x98, 0x64, 0x1e, 0x92, 0x45, 0x73, 0xd2, 0xa5, 0x1d, 0x5d, 0x71, 0x77, 0x20, 0x74, 0x21, 0xf1, 0x8f, 0x52, 0x99, 0x16, 0x69, 0x38, 0x39, 0x69, 0xa8, 0x28, 0x59, 0x17, 0xf0, 0x51, 0xac, 0x54, 0xbd, 0x5a, 0x7b, 0x18, 0xce, 0x8c, 0x14, 0x43, 0x2f, 0xe7, 0x11, 0x72, 0xf5, 0xb7, 0xd2, 0x16, 0x58, 0xc7, 0xac, 0x43, 0x08, 0x09, 0x89, 0x4e, 0x09, 0x44, 0x89, 0x51, 0x71, 0x89, 0x44, 0x36, 0x6a, 0x2b, 0x08, 0x32, 0x08, 0xd8, 0x83, 0xc1, 0x7b, 0xf4, 0x0a, 0xf1, 0x9b, 0x98, 0xd0, 0x03, 0xd1, 0x14, 0xa2, 0x10, 0x07, 0xd4, 0x08, 0xca, 0x57, 0x85, 0xa6, 0xb5, 0xf6, 0x60, 0x04, 0x3f, 0x89, 0x02, 0x18, 0x70, 0x83, 0xc1, 0x2e, 0x8e, 0xa7, 0xfb, 0x82, 0xeb, 0xf0, 0x13, 0x5f, 0xc0, 0x60, 0x79, 0x1d, 0x01, 0xdc, 0x89, 0xa1, 0x2c, 0xb4, 0xab, 0xde, 0x0c, 0x55, 0x35, 0x3b, 0x46, 0x60, 0x80, 0x7b, 0xe8, 0xc8, 0x0d, 0xbc, 0x54, 0x0e, 0xc1, 0x12, 0x8c, 0x19, 0x52, 0x01, 0xb3, 0x8e, 0xea, 0xf6, 0xb8, 0x37, 0xad, 0x71, 0x4c, 0x2f, 0x76, 0xc2, 0xae, 0x19, 0x85, 0xe6, 0xac, 0xb2, 0xc9, 0xf9, 0x78, 0x0b, 0xe2, 0x5b, 0xd2, 0x5d, 0x41, 0x3f, 0x4f, 0xc4, 0x3b, 0x2d, 0x6a, 0xd2, 0xab, 0x38, 0x08, 0x3f, 0xbb, 0xb2, 0x8b, 0x35, 0xb7, 0xcc, 0x48, 0x10, 0x61, 0x08, 0xac, 0x88, 0xbd, 0x56, 0x8d, 0xa6, 0x47, 0x36, 0x60, 0xcd, 0xd3, 0xbb, 0xce, 0x00, 0x9e, 0x46, 0x84, 0x05, 0x85, 0x7d, 0xe8, 0x14, 0xcc, 0xf3, 0x89, 0x06, 0xe3, 0x8f, 0xca, 0xfb, 0xe6, 0x41, 0xf7, 0x09, 0xa0, 0x73, 0x59, 0x05, 0x66, 0xce, 0xc6, 0x11, 0x6e, 0x44, 0x17, 0x26, 0x90, 0xf7, 0x21, 0x22, 0xc6, 0x10, 0xc6, 0xba, 0x4f, 0x3b, 0x14, 0xec, 0xca, 0x71, 0xf6, 0x64, 0x8c, 0x9d, 0xd9, 0x80, 0x0a, 0x8a, 0x86, 0x73, 0x39, 0x49, 0xa1, 0x14, 0xf7, 0x9e, 0x89, 0x0d, 0x3b, 0x15, 0x35, 0x8a, 0x6e, 0xfb, 0x2c, 0x94, 0x29, 0x3d, 0xac, 0xe0, 0x5a, 0xdc, 0x09, 0xa7, 0xb0, 0x7a, 0x70, 0x5e, 0x60, 0xf7, 0x01, 0xe6, 0x7f, 0xef, 0x74, 0xe0, 0x26, 0x31, 0x7c, 0xe7, 0x18, 0xa2, 0x02, 0x01, 0xdd, 0x90, 0x9f, 0x65, 0xef, 0x57, 0xcf, 0x40, 0x0f, 0xab, 0x2f, 0x20, 0x33, 0x2c, 0x57, 0x91, 0xa2, 0xc4, 0x8e, 0x3d, 0xf4, 0x96, 0xe8, 0xc1, 0x06, 0x5e, 0xc5, 0x0b, 0x11, 0xf9, 0x1b, 0x12, 0xc5, 0x82, 0x3e, 0xf2, 0x26, 0xd6, 0x3a, 0xf2, 0xa9, 0x6d, 0x26, 0x69, 0xd9, 0x73, 0xd6, 0x55, 0xcb, 0x9a, 0x4a, 0x29, 0xf8, 0x6e, 0xe5, 0x53, 0x80, 0x2e, 0xb2, 0xf4, 0xff, 0xe5, 0x4d, 0x7b, 0x84, 0x2f, 0xca, 0x38, 0x21, 0x9c, 0x05, 0xbe, 0x29, 0xca, 0x23, 0x6f, 0xa7, 0x88, 0x50, 0x60, 0x7c, 0xd8, 0x74, 0xbf, 0x11, 0x78, 0x57, 0xb2, 0xa7, 0x92, 0x06, 0xb2, 0xbb, 0x8d, 0xb9, 0x4b, 0xb1, 0x08, 0x27, 0x5f, 0xfd, 0x7c, 0x2f, 0x53, 0x3f, 0x5a, 0xcb, 0x5d, 0xfc, 0x53, 0x71 }, + .hmac_key_idx = 0, + // results of message array encrypted with these keys + .expected_results = { + // Message 0 + { 0xe5edea3c, 0xe6073206, 0x7e787676, 0xb4ba3f2c, 0x3ca9db24, 0xd1b4d954, 0x8fd23a4e, 0x80875e57, 0xaa6fffeb, 0xcf55420d, 0x35f5fef9, 0x64b119e9, 0x4b0be3c5, 0xc310f010, 0x727cf9f1, 0x4913855e, 0x6ed1a0ed, 0xc2074c38, 0x43fd92a5, 0xfa4a9328, 0xd0f96e0f, 0xad69c317, 0xd089f4ca, 0xfa906ac2, 0xcfc67275, 0x04697307, 0xd9c02d65, 0xcf9e9e50, 0x41fde0eb, 0xcf80479a, 0x24bdf2c7, 0xa366c4d3 }, // Message 1 + { 0x1e97de77, 0x26832b54, 0xe6c538a1, 0x80f11ce5, 0xa8159fa2, 0xae7378b2, 0x4ce9752c, 0xffc1fe65, 0x247c79aa, 0xb5456df2, 0x2b9c64a2, 0xe6416195, 0x7650be45, 0xc9448db3, 0x5fe36775, 0x8f45b2e0, 0x54456129, 0x4e29c3ba, 0x5a21d694, 0xe9adc848, 0x160b702f, 0x6251b504, 0x846b60c4, 0x21376c1d, 0x162ad548, 0x263ded50, 0x4b31b4ee, 0xd64e875a, 0x2107bfb3, 0xc3e4632b, 0x5862265d, 0x28076cd1 }, // Message 2 + { 0xe2cbdb2a, 0x33221d10, 0xc1152dec, 0x816be649, 0x3118ad12, 0xa2f288f2, 0x077f2fff, 0x01da518a, 0xd414cba0, 0x9060d389, 0x1a2f2d53, 0x2a21fa83, 0x2ea5a907, 0xaaeb0223, 0x659186fb, 0x0de05052, 0x0c29ff9d, 0x883786e1, 0xafa38a2b, 0x12acaf99, 0xa84ac4f2, 0xcdf43354, 0xed0ffe7e, 0x84af042d, 0x1ddccbca, 0xd0eeb6eb, 0x0e7969ef, 0x3a5badde, 0x239a7013, 0x686f59df, 0xc024aa3b, 0xdf5283f2 }, // Message 3 + { 0x6bfdf3b6, 0xaaca115d, 0x13f71e94, 0xc1d58117, 0x7e20268a, 0xba1164ce, 0xa62d7111, 0x71bf438a, 0xb1ef1bf3, 0x568cf2cf, 0xf77cc908, 0x93abeb1a, 0x8b48bccb, 0xaf61594e, 0x7b12b87f, 0x7046e65c, 0x32c9f344, 0x36228da8, 0xa53e4064, 0x771240c7, 0x03d2bf66, 0xaa3889d6, 0xe3f62cef, 0x24654692, 0xba9e2567, 0xd35808c9, 0xe8b13f1e, 0xc96f9461, 0x6f9edb8d, 0xb4fa6907, 0xd14ae63c, 0x86bf6697 }, // Message 4 + { 0x34cd0e29, 0x91e27cb1, 0xe1d8f7db, 0x0c2dc716, 0x97120bbe, 0x25cf2024, 0xc15722b3, 0xcaab648a, 0x6a758a09, 0x3eac1b8d, 0x7b91c3c5, 0x2c3aadc7, 0xc9196b23, 0x3f6c39e0, 0xdd17e486, 0x7c434e32, 0xaaf69d85, 0xcee2ef13, 0x22dacc4b, 0x677ab494, 0x87a62367, 0xf86291e5, 0xb338ad6c, 0x8258efb1, 0x23e9774d, 0x60a6d823, 0x34695070, 0xf565c64e, 0x584506f0, 0x9ded2478, 0xf1e9c7f4, 0x183c968c }, // Message 5 + { 0x03ed1bc3, 0x66f78658, 0x56f5de66, 0xb1d3381d, 0x6bac53f4, 0xd1685ca9, 0xcf373482, 0xd960b73d, 0x742a9dc7, 0xe019a31c, 0x3986d712, 0xab3c3a15, 0x42ce85d2, 0xe583acaa, 0xec70af74, 0xb2da696b, 0xaa5a9dc8, 0x2ee1cc2e, 0x600e4fd7, 0xd2840802, 0xc32ffbc0, 0xd55791a6, 0xf3424580, 0xcdd76019, 0x1f361747, 0x14db8c4e, 0xecb886c0, 0x9946a2b2, 0xc82bb408, 0x56ed0518, 0x0f2ba4b8, 0x6c79af92 }, // Message 6 + { 0xf32f948b, 0xaaa0ba88, 0x6efc8dc3, 0xf4c72cf4, 0x56190319, 0x25ce0426, 0x8b4032a8, 0xf1f1bab2, 0x0af6897c, 0x8369048c, 0x0888f4a1, 0x383b42c8, 0x9b2e2506, 0x7e853647, 0xe96127b9, 0x306427a5, 0x92f81696, 0xfa01c29c, 0x89542d32, 0xe2375122, 0x852cd30a, 0x255f71cb, 0x69cf28d3, 0x42b2610b, 0xb69da15d, 0xe4d9ab19, 0x60969f81, 0xcca52357, 0x0dabf3fa, 0x5932bb4b, 0xd13fbb9b, 0x30d45c15 }, // Message 7 + { 0x2eda5bf8, 0x76a3e7b8, 0x16751170, 0xc8ffc24a, 0x95728188, 0x93022f0b, 0xfb1b62c7, 0xe6d717dd, 0x0706b505, 0xd4d087a2, 0xe191e84b, 0x65e33816, 0x2b8817d5, 0x784dff54, 0xa61dd1d6, 0xa584a5e7, 0xd428dc14, 0xd110c506, 0xb620c8ab, 0x8f94a2dd, 0x46c9c3c2, 0x2f64ac02, 0x9b2c5318, 0x76aaa4e9, 0x2f524ad6, 0x5d69276c, 0xe7dc1a82, 0x5e7fd117, 0xa99bb773, 0x84aa7db8, 0x0a9d029b, 0x88d825b6 }, // Message 8 + { 0x92e9d65d, 0x914bc653, 0x5640a70e, 0x7f83e6e7, 0xaefba43f, 0xf0b727a3, 0x8bb1980e, 0x9988f45b, 0xbfac224a, 0x05430955, 0x995463b5, 0xbc9c7e60, 0x0f5f1505, 0xc6e279d5, 0xd90c9ef7, 0x794af4d0, 0x280f1a4a, 0xac57f4ab, 0x4e7a3f80, 0x0e47c6ec, 0x5566b042, 0xc398f57a, 0x343d596b, 0x34ca3486, 0xe70b3159, 0x96c78d63, 0xa5a6e0d7, 0x27788786, 0xe10184d1, 0x15de4f99, 0x5dfbce0e, 0x16b500b1 }, // Message 9 + { 0x9ae2ade0, 0x795640d0, 0x2ec1ac95, 0xcf91ef35, 0x4e23ac9d, 0x6d928302, 0xabadc916, 0x2bd2e305, 0x7d2bbc26, 0xf63d6b0f, 0xbd7a4c3d, 0xbc279680, 0x11534f96, 0x2089ecd8, 0x9797457a, 0xdb30b13a, 0x6ac85237, 0xda1c13cd, 0x3bdeaeae, 0x9dc739c4, 0xb67ac1e1, 0xf638c0d4, 0x299b38e4, 0xe6357ce6, 0xae6d26c6, 0x16d7bc3b, 0xf2f0e029, 0x92627fe4, 0xb6eda95d, 0x8673ef07, 0xc43ae485, 0x895242a4 }, }, + }, + { /* Case 4 */ + .iv = { 0x96, 0x5a, 0x0c, 0xec, 0x53, 0xbd, 0x5c, 0xa0, 0x8a, 0xfa, 0xf2, 0x69, 0x28, 0x0c, 0x61, 0x74 }, + .p_data = { + .Y = { 0x82c81f75, 0x3fbaf0da, 0xc6e34fc2, 0x45169f5c, 0xe255af46, 0xea6fd6cf, 0x7be8b38c, 0xed9558e9, 0xa5f75c80, 0x96fcbf38, 0x9e877b9d, 0x9cbbf4fb, 0xb648b92a, 0x7d6e6ee1, 0x9e8fb667, 0xea81da47, 0x25958789, 0x3ec847fc, 0x65405670, 0x4eb7bd46, 0xf95f2c0a, 0x66555cd0, 0x819e2ffa, 0xbd22aa0d, 0xb03bc289, 0xcf448568, 0xc0aa54ec, 0x46065689, 0x8de9c7da, 0x0f16611e, 0xa1d3b8c6, 0x9438c825, 0x8faeb380, 0xfea9e5e1, 0xa1eecba8, 0x62462e46, 0xc09cfd74, 0xecda374c, 0xa6196ca3, 0x54efd66b, 0xea743ca1, 0x19789a65, 0x022ea12a, 0xe3ac2eab, 0xf479a469, 0x7b34acdb, 0xea219e1a, 0xf0237054, 0x9b262528, 0x762f3888, 0xf8267219, 0xec738096, 0xf6ccc182, 0x845b14bb, 0x59ab0f6d, 0x31e81d6b, 0x2236f9e0, 0xcc4af38f, 0x51498ea3, 0xf7f8d034, 0xf3123155, 0x71ba9378, 0x4f124842, 0x9a26f7ba, 0xb1901805, 0x336d432a, 0x612fec1c, 0x5ece3c11, 0x24c19a32, 0x28832604, 0xa2bb7f02, 0xbbfab0a8, 0x88dbb8cb, 0x136a7a7f, 0x262076d0, 0xeec1decb, 0xa6a2539b, 0x725f43bc, 0x6e2f8603, 0x6949f63f, 0xafc6c351, 0xa5f1ab05, 0x03a7beed, 0x5681066e, 0x1c9f8aef, 0x87dbd104, 0xa152c018, 0x28ce0851, 0xb2278a60, 0x3a29546a, 0xb9345089, 0x56c3e310, 0x4670cb8c, 0x1c50a849, 0x27d4a1eb, 0xb47c873d }, + .M = { 0xf47a9529, 0x7cdc5d2f, 0x8ddfa293, 0xedbb7e3c, 0x1adf4f8a, 0xecc813f4, 0x39f65592, 0xdd2ef7a6, 0xe65b167a, 0x7931218d, 0xe43da582, 0x68628cfd, 0x4d91dd6b, 0x7a5a57f1, 0xa50be84e, 0x27a6bcde, 0x5529180d, 0x33111902, 0xd0ab2634, 0x9e7461f3, 0xc1f763e9, 0x8363920b, 0xb7eb12f7, 0x60fdc99f, 0x6f7d173c, 0xef401975, 0xb2c5bdf1, 0x42e3b994, 0x239fc07e, 0xb6ed5b40, 0x6ace33a2, 0xc5e1e70e, 0x695fa37e, 0xdf5aaed5, 0x97287af7, 0x28f3dd1f, 0x36cbd0ff, 0x01857cc8, 0xb40bdc9e, 0x5b082b1e, 0x3fb250b0, 0x81a975ae, 0xd2f6c63b, 0x6b1cab14, 0x793b0616, 0x885dcfc1, 0x61554c88, 0xdf6858a4, 0xc5235b3e, 0xf3d2c933, 0xcdfd1682, 0x017a7632, 0x8eb8188f, 0x999c46aa, 0xc34511af, 0x18ad86ab, 0x1363da7b, 0x9d35489b, 0xd2ab7e17, 0x71d4817f, 0x4c8d996c, 0x90a7da31, 0x7b9a43e5, 0x6cd70b25, 0x0e13dff2, 0xc670ca90, 0x40a6eb52, 0x1f3dd155, 0x36b1024c, 0x976ba305, 0x017e4764, 0x0ab66429, 0x99fcbf60, 0xa88ecffc, 0xbb2de066, 0xf5a9a2db, 0x478a016e, 0xe18d6cd3, 0xe15505e1, 0x9e16794c, 0x2f15efd9, 0xe59c52e6, 0x6680ef0d, 0x21eea982, 0x75e19ec7, 0xbc3a7122, 0x9e994bbf, 0x7d455193, 0x716be910, 0xc39dcd8d, 0x8ebfa241, 0x9125ba77, 0xf42bc4b6, 0x3c9b2f05, 0x1439c4fd, 0xb9e90637 }, + .Rb = { 0x8f3b4d09, 0xbba2c348, 0xb867352d, 0x4ebd8e36, 0x05f0da1f, 0x3780796f, 0x8d21087b, 0x2400a294, 0xde074bc4, 0xa19c5093, 0x60f00569, 0x334a2e47, 0x63d8921d, 0x62170e03, 0x05d0fac1, 0x0e08a1ba, 0xbd48f047, 0xd714f484, 0xb961404d, 0x12eac1cc, 0xf3070419, 0xec9459d7, 0x16afe9df, 0xd8b2e349, 0x96ddbf5f, 0x64b4382d, 0xf0c1185e, 0xe76b1a0d, 0x521fc1a8, 0xb1691e50, 0xa31db4d0, 0x6bc32d6f, 0xaac31f31, 0x7a3cb989, 0x8eb9eacb, 0xa1529164, 0x803c1324, 0x06b6b739, 0xdd8b1fde, 0xb1c93b86, 0xec9461c8, 0xc1cb3858, 0x74c56d2f, 0x6ded889b, 0x6db1e4f5, 0xb447af73, 0xce2f2af8, 0x3c203809, 0x040d4d56, 0x1fe5010a, 0xa1d951e4, 0x6fcba419, 0xda33954e, 0x60d7b946, 0xaa853c70, 0x0b36aa27, 0xa4872e7d, 0xe762216d, 0x77084cbd, 0x46a986b8, 0x16654e20, 0xf3a55b75, 0xb1d3fa6b, 0x4c4fff97, 0xed2956c1, 0x91049070, 0x7efb88d7, 0xe75a5b81, 0x7af24ea2, 0x636ea094, 0x36d3172d, 0x990bd5c0, 0x43a6a5be, 0xde623246, 0xa3f60aa7, 0x20f65947, 0x9c661629, 0x262b0813, 0x767c3349, 0xafb28169, 0xb5675479, 0x13fde10c, 0x55f7b74f, 0xb893644b, 0x1dfb720c, 0xbc251e1a, 0x9da4b2ed, 0x05ee29bb, 0xa8fcc918, 0x4f1d3c4c, 0xc8380b75, 0x3d953f6b, 0x3f69eb6b, 0xc2134abb, 0x546ade53, 0x8c35df85 }, + .M_prime = 0xb30d28e7, + .length = 95, // 3072 bit + }, + .expected_c = { 0xe8, 0x71, 0xf4, 0x55, 0xae, 0x2c, 0x4a, 0x70, 0x1f, 0x19, 0x1c, 0x3d, 0x43, 0x50, 0x89, 0x1f, 0x3f, 0xd5, 0x88, 0x5c, 0xc5, 0x10, 0x17, 0x04, 0x30, 0xfd, 0x3a, 0x24, 0xb9, 0x17, 0x53, 0x7d, 0x0e, 0x67, 0xb4, 0xe0, 0x44, 0x9d, 0xc1, 0xd7, 0xe3, 0x40, 0x2c, 0xda, 0x5d, 0x85, 0x32, 0x46, 0xdc, 0x05, 0xa3, 0xe3, 0x8e, 0xb3, 0x92, 0xcc, 0xb3, 0x15, 0x0d, 0x13, 0x47, 0xcd, 0x7d, 0x0b, 0xee, 0x9c, 0xe0, 0xaa, 0x8d, 0xbe, 0x55, 0x51, 0x40, 0x6f, 0x52, 0xda, 0x1f, 0xa0, 0xb1, 0x0c, 0xb1, 0x8a, 0xce, 0x93, 0x8f, 0xd6, 0xd7, 0xa9, 0x00, 0x42, 0x55, 0x0b, 0x5d, 0x37, 0xc3, 0xa0, 0xd2, 0x99, 0x36, 0x2b, 0x3f, 0xbe, 0x20, 0xa6, 0x0f, 0x81, 0x1e, 0x1c, 0x15, 0x91, 0x01, 0x65, 0x00, 0xbf, 0xba, 0xad, 0x2f, 0x29, 0x5b, 0x4f, 0x96, 0x77, 0xea, 0xec, 0xaa, 0xb8, 0xf3, 0xd3, 0x47, 0x70, 0x25, 0xbb, 0xcb, 0xd4, 0xe2, 0x04, 0x71, 0xec, 0x10, 0x23, 0x3a, 0xf4, 0xbb, 0x1d, 0x43, 0x36, 0x06, 0x4c, 0xf5, 0xb4, 0x55, 0x3c, 0x1d, 0xee, 0x9c, 0xd7, 0x69, 0x5f, 0xef, 0x09, 0x80, 0x4b, 0x84, 0xec, 0x0f, 0x48, 0xef, 0xc2, 0x44, 0x4e, 0xd8, 0x41, 0x70, 0x07, 0x35, 0xb9, 0x0b, 0x1d, 0x42, 0x16, 0x2b, 0x8e, 0x10, 0x1a, 0xbb, 0xc5, 0x86, 0xc3, 0xbf, 0xa4, 0x8a, 0x90, 0xa8, 0x1c, 0xfe, 0x8c, 0x6f, 0x25, 0x42, 0x42, 0x37, 0x96, 0x3a, 0xe7, 0xe7, 0xdd, 0xd4, 0x12, 0x45, 0xf5, 0xd2, 0xc5, 0x8b, 0x1c, 0x35, 0xc2, 0x02, 0xaa, 0xa2, 0x6f, 0x31, 0x80, 0x15, 0xf3, 0x76, 0x7d, 0xab, 0x94, 0x64, 0x55, 0x2a, 0x92, 0xab, 0xfc, 0x34, 0x2b, 0x1e, 0x99, 0x93, 0x0b, 0xe7, 0x7f, 0x81, 0xb5, 0x67, 0x2c, 0xf0, 0xc4, 0xdb, 0xa5, 0xbb, 0x14, 0x51, 0xb4, 0x3a, 0x60, 0x72, 0xc6, 0xe1, 0x00, 0x4d, 0x7c, 0x5c, 0x5c, 0xf8, 0xca, 0xfd, 0xc9, 0xc8, 0x35, 0x82, 0x78, 0x49, 0xe4, 0x5f, 0x10, 0xa0, 0xa8, 0x1f, 0x27, 0x1a, 0x7b, 0xe7, 0x3f, 0x4c, 0xb8, 0x93, 0x5d, 0x67, 0x0b, 0x3d, 0xa1, 0x71, 0x2a, 0xaa, 0x49, 0x4d, 0x26, 0x4f, 0x68, 0x38, 0xe1, 0xc0, 0x8c, 0x1a, 0x45, 0x63, 0xea, 0x30, 0x69, 0x34, 0xf0, 0xb4, 0x36, 0xdd, 0x42, 0xbc, 0xe7, 0x9d, 0x24, 0xa2, 0x98, 0xbc, 0x22, 0xb9, 0x89, 0x92, 0xa3, 0xf9, 0x37, 0xe5, 0xf1, 0xc5, 0x2c, 0xe0, 0x53, 0xc7, 0xdf, 0x46, 0xcd, 0xde, 0x3b, 0x3f, 0x5c, 0xaf, 0xbd, 0x1a, 0x32, 0x29, 0x82, 0x30, 0xe4, 0xff, 0xa3, 0xff, 0x36, 0x75, 0x13, 0xee, 0x47, 0xa5, 0x15, 0x58, 0x4e, 0xf9, 0xac, 0x6a, 0xa6, 0x11, 0x48, 0x93, 0xe6, 0xce, 0x7a, 0xae, 0x28, 0xc5, 0x0b, 0x8d, 0x57, 0xca, 0xe9, 0x83, 0xd4, 0x68, 0x12, 0x74, 0xde, 0x65, 0xc1, 0x19, 0xed, 0xa2, 0x83, 0x2c, 0x32, 0xc3, 0x51, 0xdd, 0x7f, 0x05, 0x51, 0xd9, 0x46, 0xef, 0x05, 0xd5, 0xc6, 0x9b, 0x8a, 0xd0, 0x15, 0x5c, 0xfe, 0x4a, 0x21, 0x15, 0x3a, 0x9a, 0x37, 0xc3, 0x70, 0x13, 0x63, 0x24, 0x4a, 0xd3, 0x96, 0x3a, 0xa9, 0x22, 0x17, 0x78, 0xf5, 0x64, 0xd8, 0xa0, 0x4a, 0x0a, 0x0c, 0x99, 0xa9, 0x1c, 0xba, 0x6b, 0x6b, 0xf0, 0x29, 0xb7, 0x8c, 0xd8, 0x6d, 0x15, 0x4d, 0x8d, 0x56, 0xb2, 0x53, 0x62, 0xbd, 0xfc, 0xbe, 0x2b, 0xfa, 0x11, 0x96, 0x10, 0x48, 0xf3, 0x90, 0x8b, 0xb0, 0x72, 0x7f, 0x6e, 0xc1, 0x8a, 0xd0, 0xef, 0x81, 0xba, 0x12, 0x5e, 0x6d, 0x0d, 0xcf, 0xbc, 0x72, 0x53, 0x21, 0xbd, 0x97, 0xf0, 0x91, 0x41, 0xef, 0x4c, 0xe9, 0x25, 0x6d, 0xb8, 0xf5, 0x17, 0x33, 0xff, 0x5f, 0xfd, 0x34, 0x54, 0xba, 0xe4, 0x04, 0x33, 0x11, 0x94, 0x39, 0x67, 0x5a, 0x54, 0x30, 0x95, 0x7d, 0x68, 0x09, 0x6d, 0x80, 0xb2, 0xa1, 0xe0, 0x54, 0x3a, 0x71, 0x27, 0x43, 0x0f, 0xd7, 0xac, 0xa9, 0x51, 0xa4, 0xca, 0xb7, 0x22, 0x6b, 0xb4, 0x94, 0x39, 0x52, 0x15, 0x32, 0xc9, 0x8c, 0xe0, 0x53, 0xe1, 0x73, 0xc2, 0x17, 0xf6, 0xe0, 0x82, 0xd4, 0xa3, 0x6c, 0x81, 0xe3, 0x90, 0xc0, 0xc1, 0x1a, 0xe9, 0xd4, 0xa4, 0x9c, 0x00, 0x68, 0xc9, 0x65, 0x45, 0x74, 0xf6, 0xd0, 0x58, 0xb7, 0x8f, 0xc5, 0x38, 0x11, 0x68, 0x75, 0x44, 0x3b, 0x77, 0x75, 0x68, 0x02, 0x3c, 0xc9, 0x41, 0x05, 0x0f, 0x82, 0xc3, 0x63, 0xd7, 0x96, 0xb6, 0x73, 0xbb, 0xe4, 0x51, 0x1a, 0xe7, 0x6a, 0x03, 0xd8, 0x42, 0xb6, 0xb5, 0xdd, 0xa5, 0xc5, 0x90, 0xf4, 0xe8, 0x87, 0x94, 0x25, 0xd6, 0x8d, 0xdd, 0x9c, 0x53, 0x5d, 0x2f, 0xd2, 0xc5, 0xe9, 0xab, 0x38, 0xe6, 0x7b, 0x65, 0x6f, 0xe4, 0x77, 0x15, 0xc8, 0x8f, 0xb4, 0x7d, 0xde, 0xd6, 0xe2, 0xd7, 0x4c, 0xdd, 0xa8, 0x55, 0x33, 0x07, 0x9a, 0xad, 0x88, 0xdb, 0x03, 0x1b, 0x13, 0x1f, 0x16, 0x44, 0xc8, 0xcb, 0xed, 0x75, 0x54, 0x90, 0x44, 0x8f, 0x4e, 0xc3, 0x0d, 0xc9, 0xfc, 0x90, 0xed, 0x89, 0x73, 0x2f, 0xf2, 0x8a, 0x08, 0xce, 0x15, 0x2b, 0x8f, 0xb3, 0x6e, 0x20, 0x38, 0x08, 0x95, 0x2d, 0x9b, 0xd1, 0x62, 0x81, 0x09, 0xf8, 0xb0, 0xc4, 0xbb, 0xe4, 0xee, 0x67, 0x1c, 0x98, 0x93, 0xba, 0x17, 0x79, 0x90, 0x47, 0xac, 0x0e, 0xf9, 0x22, 0xbd, 0x5f, 0xbc, 0x77, 0x5c, 0x21, 0xb0, 0xbc, 0xd4, 0xeb, 0x8b, 0x1c, 0xd4, 0x42, 0x34, 0x19, 0xab, 0x9f, 0x67, 0x2a, 0x84, 0x20, 0xd9, 0x79, 0x39, 0x25, 0x2b, 0x9a, 0x31, 0xc1, 0xb2, 0x29, 0x8a, 0x8f, 0xe7, 0xb3, 0x09, 0x8a, 0xe5, 0x20, 0xcb, 0xb0, 0xfa, 0x42, 0xbc, 0xed, 0x68, 0x71, 0x66, 0x3d, 0x4b, 0x95, 0xe1, 0x5d, 0x56, 0x88, 0x32, 0x0d, 0x83, 0x84, 0x25, 0xe6, 0x8f, 0x6a, 0xeb, 0x99, 0x84, 0xda, 0x03, 0x32, 0x79, 0xea, 0x2f, 0xc6, 0x0f, 0x37, 0x80, 0x46, 0x69, 0xe1, 0xf3, 0xbc, 0x7f, 0x00, 0x29, 0x6d, 0x48, 0x00, 0xe5, 0x6f, 0x74, 0x18, 0x0f, 0xc2, 0xc9, 0x7c, 0x5d, 0x65, 0xf0, 0x00, 0x78, 0x44, 0xc6, 0x21, 0xf8, 0xfd, 0x6b, 0xc6, 0xb2, 0x97, 0x66, 0xd1, 0x4d, 0x2a, 0xb3, 0x47, 0xd6, 0x64, 0x63, 0xaa, 0xb4, 0xfd, 0xe3, 0x30, 0xb2, 0xd3, 0xd3, 0x67, 0x3c, 0x39, 0x07, 0xdb, 0x87, 0xe9, 0x78, 0x0f, 0x11, 0xf7, 0x19, 0xac, 0xc3, 0x50, 0xb2, 0x9d, 0xba, 0xec, 0x48, 0x6a, 0x74, 0xbe, 0x16, 0x8d, 0x03, 0x2e, 0xb2, 0x16, 0x20, 0x49, 0x5a, 0x27, 0xbc, 0x1f, 0xa7, 0x95, 0x03, 0xb2, 0xe3, 0x89, 0x3a, 0x68, 0x48, 0x47, 0x80, 0xe4, 0x04, 0xc1, 0xc6, 0x9d, 0x3c, 0x7b, 0xd2, 0x76, 0x52, 0x67, 0xf6, 0xfe, 0xf1, 0x21, 0x16, 0x5e, 0x0e, 0xab, 0x3f, 0xfd, 0x11, 0x6e, 0xd8, 0x63, 0xf2, 0x90, 0xfa, 0xf3, 0xfd, 0x17, 0xb3, 0xd3, 0x67, 0x72, 0x14, 0x01, 0x2a, 0xf0, 0xbe, 0x28, 0x3d, 0xfb, 0x78, 0x69, 0x6f, 0x30, 0x3a, 0xd0, 0x0c, 0x57, 0xe6, 0x37, 0xdf, 0x40, 0xce, 0xba, 0xc0, 0x7d, 0x17, 0x9c, 0x92, 0x57, 0x96, 0x4b, 0xe7, 0xe3, 0xa9, 0xf7, 0x0d, 0x12, 0x9c, 0xfb, 0x55, 0x37, 0x70, 0xd3, 0x8d, 0xa6, 0xfd, 0xc7, 0xab, 0x34, 0xf4, 0xbf, 0x60, 0xe1, 0xad, 0x7f, 0x42, 0x47, 0x29, 0xc6, 0x7e, 0xdb, 0xe2, 0x94, 0xaf, 0xd2, 0x72, 0x56, 0x52, 0x38, 0x56, 0x3f, 0xe2, 0x9b, 0xa3, 0x1e, 0x47, 0xda, 0xe7, 0x70, 0x3b, 0x8d, 0xc5, 0x7e, 0x7a, 0xfb, 0x89, 0x99, 0xb7, 0x11, 0xf0, 0x76, 0x26, 0xce, 0x9a, 0xc8, 0xd2, 0x77, 0x1c, 0x53, 0x3a, 0xbc, 0xd6, 0x3c, 0xf0, 0x0f, 0xf9, 0x62, 0x0e, 0x52, 0xe2, 0xdc, 0x75, 0x0e, 0x20, 0x23, 0x9e, 0x2c, 0xe4, 0x74, 0xbf, 0x7c, 0x35, 0x9b, 0xed, 0x7a, 0x3a, 0x01, 0xff, 0xc2, 0x7b, 0x58, 0x5d, 0xe0, 0x2e, 0x59, 0x6c, 0x1c, 0x0b, 0x67, 0x14, 0x8d, 0xde, 0x57, 0x59, 0x0c, 0xd4, 0x58, 0x7c, 0x15, 0x88, 0x90, 0xdf, 0xda, 0x0a, 0x47, 0x62, 0xc1, 0x49, 0xfb, 0xaa, 0x38, 0xbb, 0x93, 0x8e, 0xea, 0x43, 0x42, 0xf9, 0x49, 0x70, 0x97, 0xe7, 0x5c, 0xbc, 0x9d, 0x98, 0x40, 0x4c, 0x88, 0x0f, 0x8f, 0xff, 0xd5, 0x00, 0x1d, 0xe5, 0x3e, 0x63, 0x39, 0x5e, 0x79, 0x3a, 0x35, 0xc2, 0x58, 0x9e, 0x11, 0x8a, 0xd3, 0xb4, 0xe1, 0x62, 0x3d, 0x69, 0xb0, 0xb2, 0xc6, 0x89, 0x28, 0x6d, 0xfb, 0x25, 0x7d, 0xb3, 0x2e, 0x5b, 0x24, 0x59, 0xe1, 0x89, 0xca, 0x74, 0xa5, 0x32, 0x71, 0x5c, 0x00, 0x69, 0xe2, 0x03, 0x52, 0x28, 0xc0, 0x0b, 0x41, 0x3d, 0x59, 0x51, 0x3e, 0x9e, 0xe2, 0x6f, 0x6a, 0x66, 0xcd, 0x0d, 0xd4, 0x40, 0x87, 0xbd, 0x3e, 0x6d, 0x0c, 0x9f, 0x9b, 0x23, 0xf8, 0x6c, 0xb7, 0x90, 0xe5, 0x0b, 0x2c, 0xe7, 0x82, 0x9e }, + .hmac_key_idx = 1, + // results of message array encrypted with these keys + .expected_results = { + // Message 0 + { 0x98ae55fa, 0x8e3a5c6c, 0x70e6b8c3, 0x78c4ad7f, 0xc0585683, 0x154354e8, 0x14f7cd56, 0x716ee192, 0x8f248707, 0x412f07a0, 0x4cf38afb, 0xa6581443, 0x07d52cfa, 0x11829a8f, 0xc4eccd55, 0xc4784ad9, 0x7acb21a3, 0x1c5daf68, 0x44b01bf2, 0xaa7b4c35, 0x43d38c77, 0xe02200fb, 0x0c5dc289, 0xb266a4b0, 0xa632caa2, 0x0c4d9653, 0x1c840ad6, 0xc83a2533, 0x3593b4cc, 0xf927cf74, 0xfeb1a7c0, 0x0899b8aa, 0x624b9b41, 0xff0ba52e, 0x7a772e76, 0xe7e9104d, 0x7d56c83c, 0x58053fbf, 0x177fea07, 0xf5696d14, 0x09df3fdb, 0xb119c754, 0x47894350, 0xfc4c1071, 0xf2048c06, 0xea302c8f, 0xa70088d2, 0x1feebad9, 0x6eb748a7, 0x479b2f11, 0x71831c58, 0x90d71a8b, 0xd1ac563d, 0x14b15cb9, 0xdb89941e, 0xfc7fdfb5, 0x9c03e460, 0xd748f437, 0x43fd3af1, 0x6fc6afac, 0x7aa8e99c, 0xe4d9741d, 0xc939f2e9, 0x2a78ab68, 0xc782229e, 0x96949655, 0x56d7a65a, 0x80d8a5c5, 0x88341b02, 0x08b9eafa, 0x94a11163, 0xad184989, 0xd62e204a, 0x6a7a0dc2, 0x933692ed, 0xd61eb0e7, 0x483a5020, 0xb0cb79e1, 0xb58c0bbf, 0xdc0b1685, 0xf04dc7f9, 0xf0b7b944, 0x115741de, 0x04a8fbef, 0xc14b8ac8, 0xa0c842ff, 0x8d8be311, 0xc24fca56, 0xbeb2172d, 0xf458888a, 0x5cbd72b2, 0xf74dab5a, 0x19d4158d, 0x70b82f76, 0x578fe7ee, 0x041f3441 }, // Message 1 + { 0x269ecdc9, 0xec75529a, 0xe4dd9832, 0x9a7d9cf5, 0xbfc87ce8, 0x8f70440a, 0xc3b9c975, 0xce68167b, 0xdb39077a, 0xbfb2cfd0, 0x47f244fe, 0x2c569e22, 0x9dcb7c5f, 0x41f7e74a, 0xecb069e0, 0xcbd3441c, 0xe0afe198, 0xb0cc9efb, 0x8ed19f18, 0xeae16e4c, 0xd9a6f034, 0x30d135a9, 0x8ec193fe, 0x7da5123d, 0x2fdb72ab, 0x9377d3a9, 0xaf79140e, 0x06fa21f1, 0x1bf824d5, 0x4f4a3b7b, 0xbb0c9c22, 0xa9e61217, 0x2d4f1dbf, 0x43d39e8d, 0x427b3e3c, 0xc9d017a2, 0x80b9e970, 0x9465f675, 0x5fb718e8, 0x205885b9, 0x1d486275, 0xedf46bf1, 0x6e305e72, 0xeb929cab, 0x15935477, 0x89312f29, 0x95422f9a, 0xa3cf4f36, 0xd24898fe, 0x4230ba1c, 0x4bb221eb, 0xf24ac29d, 0xd0007433, 0x78d7800e, 0x93b99888, 0x65c62bea, 0xf50c78e9, 0xb25c1003, 0x366355fb, 0xe536c649, 0x1c18154e, 0xabdf177b, 0xcc62816a, 0x0281f158, 0x07c8f8eb, 0x3abc64d1, 0x84bcd4a5, 0x29f31b43, 0x53d922bf, 0x09363496, 0x643d9249, 0xf012c0ee, 0x00ca51ad, 0xdbdb113a, 0x388dffd8, 0xe04f75a7, 0x973614f0, 0x01f1c096, 0x2a9c1ae4, 0xf375cb42, 0xce289b7d, 0xe42faa32, 0x04dd740d, 0xfd5ffb21, 0x25a7648d, 0x73d1c77d, 0x04026145, 0x9cafe7fc, 0x3dcc66d6, 0x0797be68, 0x550c04e7, 0x9653c9ca, 0x3097b81d, 0x17d4672e, 0xbc072dc6, 0x14f66333 }, // Message 2 + { 0xf8262d26, 0xef952d84, 0xaeee6fbc, 0x0bfeee47, 0x214df086, 0xd27a921c, 0x23411c20, 0x4e6c94ec, 0xd06e91d8, 0x6402771f, 0x716ec0da, 0x708ba823, 0xeaca50b3, 0x675b5015, 0x0f924488, 0x453aaff3, 0x1f2236b4, 0x7415f7bc, 0x2e9b6a50, 0x4ec84f58, 0x95c70e14, 0x699a9833, 0x5a550933, 0xb7c2105f, 0xb3e5da91, 0xa8ee3cf7, 0x39ed39a7, 0x56968853, 0x4e134ad1, 0x6e9fe895, 0x295454f2, 0x096c319a, 0xbb94a7e7, 0x634a627f, 0x22106315, 0x4e8ce14c, 0xcb27f796, 0x32f54538, 0x77b88021, 0x7f352d1a, 0x7c72c2f3, 0x1336496a, 0x108bf300, 0xdfb97dba, 0x5027a576, 0xdb926660, 0x56666863, 0xc1879c2c, 0x876599d6, 0x9237412a, 0xb1fd9982, 0x04c47adf, 0xe3b33510, 0xac3ff9aa, 0xcce46ff1, 0x554eb4db, 0xd6e3b996, 0x5106ba01, 0x2a7dc00e, 0xfa58c795, 0x308cbdfa, 0x43253e75, 0x97e6a7c7, 0xf83e886a, 0xc8ed9a72, 0xffe67a8f, 0xbb088044, 0x9e45d2d3, 0x3b5bc70d, 0x4a84c1b2, 0x0908fb40, 0xf6cf9316, 0x089986d2, 0xb358e021, 0xd77ff93b, 0xd03062e0, 0x5c044518, 0x9c557dea, 0x90a4a40b, 0x8e6650b3, 0x549e79ac, 0xf7fa54f3, 0x6c0c6b1e, 0xbbe34ce7, 0x8a7ecc8a, 0x7ee66b62, 0xf983b274, 0xa2d5c6bb, 0x0365eab6, 0xea711268, 0x882172c9, 0x8be37923, 0xb217245a, 0x04643723, 0x55b4f658, 0x441bbe38 }, // Message 3 + { 0xfa45199e, 0x21b8e813, 0x6ca29c4c, 0xb7165335, 0x538f25e1, 0x5340bc94, 0xfee1d8f5, 0x33a4dd48, 0x8c91688f, 0x1424928e, 0xa42dd26a, 0x584a91d5, 0xde3a8a9a, 0xcd5940cc, 0xd22ae956, 0x5ad1a145, 0xabccf3e0, 0x0a43a19c, 0x01dc77a3, 0x746a47f8, 0x16c28528, 0xe8641692, 0xdae45f39, 0xddec1a36, 0x7e18a1cb, 0xa28ab236, 0x0302e70c, 0xed1fbda8, 0xdf23e52a, 0x945c375e, 0x7c35d8da, 0xec080cb3, 0x8d55eb5b, 0x222f6ab4, 0xf742aa49, 0xa89b3a75, 0x581b728e, 0xf0c02e05, 0x4be1f1ed, 0xe3000e8c, 0x7a6d642d, 0x454e0a78, 0x72718870, 0x1daabb07, 0x2f2916c1, 0x99d854a1, 0xb680961a, 0x0555f41f, 0xc117c2d6, 0x7cf1156a, 0x82f8c610, 0x0b2129a3, 0xa250eb75, 0x89bb4040, 0xf0fab8ab, 0xab4a00e4, 0x5642d1a3, 0x3a8c0552, 0xf1251a2a, 0x93f04b23, 0x62a6a308, 0x4258d041, 0xca347fef, 0xaf81466a, 0x1d26e962, 0x5ef34e17, 0xdeca4e68, 0x1e60cc38, 0x828fac7e, 0xfd5b5d4d, 0x3082d692, 0x914d8070, 0x8a376cbd, 0x6a875af9, 0x27825817, 0xce73030b, 0x1939c849, 0x95e9c475, 0xe469e8f8, 0xf4c39bb5, 0xa40677b6, 0x58ee1cdb, 0x7fd86c94, 0x4267db7a, 0xde52a266, 0xc73a200b, 0x04dde6d6, 0x031f5b47, 0x7ed8ffbe, 0xc8f1b319, 0x41066d4f, 0x60e2bb07, 0x068536b1, 0x9a2fed58, 0x85739a46, 0x3b0f16de }, // Message 4 + { 0x0ad48b36, 0x949c5fbe, 0x47df6bb2, 0x8dd75dc5, 0xe288cd71, 0xad15495a, 0x57428037, 0x7048c393, 0x4586e0a6, 0xf55df51d, 0x96650b5a, 0x552e0874, 0xfde91454, 0x7af4e7d7, 0xece36383, 0x29593e75, 0x7016c4ab, 0xdc5b5006, 0xaefe77ef, 0xcdfc7321, 0x6bccc4fb, 0x19605e14, 0x92d55392, 0x176f4a24, 0xf9619ff1, 0x6b119a11, 0x56530cbc, 0xbf046d9c, 0xf8468d64, 0xde8bf5d1, 0x2648704c, 0x19bc4fe8, 0x6b9d4501, 0x5c708ad7, 0x454b90d1, 0xeccebcba, 0x2c81861a, 0xdf330398, 0xb8a6a35f, 0xefc4c75e, 0x1c605049, 0x4d8155a9, 0x021dff92, 0x01f6e274, 0x43472025, 0xae429f76, 0xfd193375, 0x280c23c2, 0x200f0bde, 0x9f04c066, 0x657c2919, 0x5fd53a29, 0xcf0cc9fa, 0x40f79de0, 0x325e5f34, 0x600a6c77, 0x24aac398, 0xaef5d0a7, 0xf5cf51d0, 0x9f3ca128, 0xf134c6a3, 0x51d63e37, 0x9717f4c7, 0x4b0d2834, 0x2899d9f5, 0x45587051, 0x67b226c0, 0x5d6c38e9, 0x1465e434, 0xe6c984f0, 0xdbe15b76, 0xa9482eec, 0xe47df7d4, 0x805904bc, 0x945e4ef0, 0xace8eece, 0x25c944bd, 0x479bcb0d, 0x11d233b4, 0x57b379ad, 0x274f883d, 0xc4d92b5d, 0x13442f19, 0x38172f9e, 0xc442b5a3, 0x1a2ca4e2, 0x37c1acc6, 0x32c06c07, 0x0a48701c, 0xa35b7fc9, 0xf389ee99, 0x09baa0db, 0xe4e96f60, 0xd7e36530, 0x61144c55, 0x7362bca6 }, // Message 5 + { 0x8629bd73, 0x1b1475ba, 0x583f425e, 0x21a2189c, 0x4ffb0910, 0x1f1d93cd, 0x03dccd81, 0xc9c70b96, 0x2109c5c0, 0x9cdb087f, 0xdc2ec042, 0x6403868f, 0x9e5b994e, 0x42f54238, 0x87d73cca, 0x83fde6a0, 0x16f6740b, 0xa2955350, 0xc0da3132, 0xf4d7501e, 0x50cfff8b, 0x76f0f0f1, 0xe4e55ede, 0xb10f85b8, 0x9240924e, 0xb78b6f4a, 0x9ea9d535, 0x7f826364, 0x12627a1f, 0x7f9fd80d, 0x2ce28318, 0x2482b7f1, 0xf38b2df2, 0x831c93c9, 0xc58bf08d, 0x34b4e81d, 0xb6bcafbc, 0x15c44dde, 0xa76803e2, 0x32aed046, 0xb7c53573, 0x7b7a42ca, 0xbea2e6f5, 0x3dba3501, 0x25c940e2, 0xa8ba546a, 0x05740fa1, 0xf75952d6, 0xfdbe9c0d, 0x153a3659, 0xc4fd9a18, 0x309f889e, 0xbf4b301e, 0xaae9f765, 0x5bd0ce66, 0x57974080, 0x1a002b18, 0x53b86bce, 0x707d0da8, 0x5071dd78, 0xbd9fa428, 0xd09110e4, 0x2ccfe58f, 0x845226aa, 0xa857a860, 0x3ccccec7, 0x19a79959, 0x9910eaff, 0xd20c6529, 0x5fb0aa3e, 0x79594eee, 0x6a602474, 0x19e4934e, 0x05315ea9, 0x445be87a, 0xec78a296, 0x389556ba, 0xfb93aa16, 0x428b8ff6, 0xbbce5db6, 0x31b0d70e, 0x2e571c80, 0xea1352a5, 0x5a21aecd, 0x3ca2276e, 0x90a83c61, 0x2206b059, 0x5880df28, 0x604bff17, 0xac83bc48, 0x79ae9f2f, 0x2dd123c0, 0x370b4cb7, 0x87ff329d, 0xd337ff0c, 0x5d18e3f8 }, // Message 6 + { 0xa2e254b0, 0x6884b005, 0x24418c11, 0x9908ca41, 0x4bb60047, 0x8706344b, 0xcf1811aa, 0xc08b6acf, 0x9b1e9906, 0xc581c966, 0x4c8f5089, 0x2d12433e, 0x8a4fee82, 0xa4cd4bef, 0x191110bf, 0x16c6e0c2, 0x4bb8f64f, 0x66cd0f33, 0x7149b273, 0x84607692, 0x4065a925, 0xe4645988, 0x5a167e25, 0x68b53a54, 0xb0d800cb, 0xf7c3b213, 0xb47e214e, 0x8f3af683, 0xd8859f9f, 0x89a1fe53, 0xa39a3e89, 0x0b1ae43c, 0xa370d23d, 0x14601402, 0x83609e47, 0x240257e6, 0x0cf0be1b, 0xe7702330, 0x35ed27f4, 0xacf0000f, 0xf4c7083e, 0x6c7900de, 0x0bc038ef, 0xc587eb2d, 0xe1b056da, 0x2b6402a3, 0xa40c06bd, 0xf1fb6ef1, 0x1c51b0e2, 0xaf3a1c3c, 0xa4d59878, 0x778655d5, 0x2ff3ad3f, 0x7abeece6, 0xafef0177, 0x268e66f2, 0xeed5a22d, 0x05b074c5, 0xdbc62381, 0x81a76413, 0x8ed26f2f, 0xf68087d6, 0x77fbfe7e, 0x573b27b7, 0xb1e682b2, 0x91967fdd, 0x9d79fd4f, 0x2a7056e2, 0x24ddb17e, 0x5da9e4ea, 0xbff64981, 0x6eddbefd, 0xbc7ef3c3, 0x2094f3bd, 0xf4459273, 0x7e3ddda2, 0x8db553a8, 0x368d6f02, 0x0f365f00, 0x57fa4e43, 0xbe9dc56a, 0x563e0321, 0x7f02c833, 0x0883c3c4, 0x8d4ac3f7, 0xf360c8e5, 0xd0ad805c, 0x4d88cfa2, 0xd72e7019, 0x6a1694f0, 0xd764a4d5, 0xa5a1d620, 0x35192fdb, 0xbd445089, 0xa3f2555a, 0x33cca47e }, // Message 7 + { 0x7f4aa4b6, 0x3f60bc1f, 0x8f5c47d3, 0x3ab0a3d5, 0x7ac05847, 0x8455c8f9, 0x3fbe44da, 0x1aa38001, 0x7ecf7e66, 0xe10a8dc0, 0x4d8e0363, 0x292e6ef5, 0x318ff967, 0x6768981e, 0xd274c24a, 0xba72e572, 0xe5126a44, 0xb6e1aff1, 0xb5ee83d9, 0x806d15fb, 0x351a6a0d, 0xf385c53a, 0xbbdfafbd, 0x068040fa, 0x55bd7aa1, 0x09706c8a, 0xeed7f001, 0x0576a269, 0x4991bba8, 0xf5d63ca7, 0xb9090809, 0xefdb9d01, 0x0e569a5d, 0x88198cdf, 0x23f27b60, 0x2989e3aa, 0x63ac43eb, 0xfa787992, 0x7adeda6d, 0x45e2bb92, 0xcfbff8c3, 0xe530dcfb, 0x7814b3d4, 0x9c1dae62, 0x9a54e8fe, 0x7236dad2, 0x6f15b2dd, 0x16c31a83, 0x68195746, 0x5e09a6cc, 0x32296c82, 0x0430e96b, 0xa263ea48, 0x88fcb01b, 0x0043a382, 0xb943a56e, 0x6f2ebeea, 0xe02e2b97, 0x27aa6253, 0xc9fab5ee, 0x4417fa4f, 0x23b9d4b6, 0x2188b5cc, 0x62be7204, 0xa4e92917, 0x3e41e576, 0x3ded898b, 0xe5d2c291, 0xadc005fa, 0x77cf5a42, 0x602ee82e, 0x56380874, 0x3ef35e6f, 0x13974b7b, 0x12c8348e, 0xd9b0e727, 0xe12ac166, 0x959fe991, 0xa3e25dab, 0xf48ea55e, 0x03238261, 0x95753eec, 0x99f5e91d, 0x6e96df33, 0x8e7513a6, 0x35f05687, 0x795213e2, 0xe05e92a7, 0x4a379aa3, 0x3e367ba3, 0x090b5687, 0xe54fd5c1, 0x517245e4, 0x3b2fc347, 0xaec350e3, 0x53fa4f7d }, // Message 8 + { 0xba79ce1e, 0xdf957fb6, 0x0e69371c, 0x21cd0be9, 0x91d15f10, 0x1e284ef7, 0x13f695f0, 0x048174ce, 0x82653c98, 0x480739a3, 0x6b6309e8, 0xf259653b, 0x903d4788, 0xe5ff123d, 0xefb928c6, 0x3f8ab213, 0x0f004d7d, 0x1ef43198, 0x6fb3f8a0, 0x71a4e231, 0x5e017ce7, 0x0fc76394, 0xf9fda347, 0xb9d4dd95, 0xcb772d7a, 0x2f4a8728, 0xcc1fd8c5, 0xe623da36, 0xf02e2420, 0x3d81f71e, 0x2636fa6c, 0xceb47b75, 0xc16ee05c, 0xe453e3ce, 0xb5c328ea, 0xb7346190, 0xa5b78c76, 0xae1435b7, 0x3fe109e7, 0xc68a3991, 0x99dd7710, 0xa4cc1cf3, 0x7096fc5e, 0x9be4d5e7, 0xd1cc0c6e, 0x67a58657, 0xdd3fe831, 0x572a115a, 0x8e5ccdf2, 0x61b1f852, 0x9b7ef162, 0x11e052bb, 0x714bdc57, 0x3f4465cc, 0x59a1f45c, 0x8a7f8ca7, 0x8a5ea958, 0x66497d54, 0x45be0a42, 0xe08d427d, 0x1a043c7e, 0x00c36d56, 0x12e397fb, 0xdbb3066a, 0xe9784feb, 0x7ccb7d64, 0x5649d225, 0x04dae5a6, 0x7d1506ca, 0xf375bd50, 0x1610b9ab, 0x146aa493, 0xedb2cc41, 0x49992205, 0x89815982, 0x0affa370, 0x3022da89, 0x55f169e1, 0x136b1c2e, 0x19ae17cb, 0x02522159, 0xb08c3c33, 0x067e7f17, 0x0df72542, 0xc536df95, 0x0cf4d791, 0xc47d7f7f, 0x0f4fd915, 0x65341546, 0x65256b8f, 0x8fd2f1ad, 0x40f7b93d, 0x4d7e2e52, 0x625f7ff1, 0xbc4ba910, 0x72dc12dd }, // Message 9 + { 0xd8d0816c, 0x0a23556a, 0xf4bed43e, 0xb6db0599, 0xff114899, 0x65c35c4f, 0x879a6f90, 0xa09c7ac9, 0x86ff9986, 0xcad84d99, 0xd6528759, 0xed5ba410, 0xe033ec61, 0x73e157ee, 0x88847f4a, 0x8f6dc0aa, 0x967e6f66, 0x5a06473c, 0x28f25f15, 0x2a2f1a72, 0x55bba8d3, 0x23132590, 0xb30a92e8, 0xf910db46, 0xf1abc0b4, 0x8453c659, 0x189edfc9, 0xee0afacf, 0x53112765, 0xb5a314ad, 0x1042581c, 0xce91ea41, 0x2dbc0b0f, 0xa6967c0d, 0x745b3433, 0x64f76890, 0xa208aec9, 0x8b5b0589, 0x9f03b037, 0x5732a80b, 0xab015e91, 0x86e40797, 0xbba1e8b1, 0xd6698112, 0x157f1d63, 0x66617f33, 0x60d7f860, 0xee40dcfd, 0x0b38a943, 0x8448532e, 0xf14fc44e, 0x6c32e29c, 0xd7fc3fd0, 0x8b2d4860, 0x1a8c16be, 0x7e7565ab, 0xe1cd1ed7, 0xde9b3963, 0xe28133a2, 0xb4ffd9e4, 0x18b61f1e, 0xcdce746d, 0x903e318d, 0x817fb9f1, 0x3d08714e, 0x374aa438, 0x253b72fc, 0x922cb88d, 0x33d13a88, 0x41aca7a3, 0x19c31f12, 0xe903c78d, 0x615ccd7b, 0x1af53245, 0x6baecb63, 0x4c825acf, 0x68b05156, 0xf365c4bc, 0xaccfddba, 0xb9cf7626, 0x84da2a56, 0x7e003cd4, 0x3616aaa0, 0xda4a5242, 0xd0b3b1ec, 0x2fb6a77d, 0x36cf0925, 0xd168c4b0, 0xc6855e2a, 0x622e6ddd, 0x2c87168e, 0x60647ac9, 0xf8d92b07, 0x7e2db3c8, 0x93050b32, 0x21417980 }, }, + }, + { /* Case 5 */ + .iv = { 0xd9, 0x12, 0xb3, 0xf5, 0xdf, 0x64, 0xfb, 0x7a, 0xc8, 0x87, 0xd9, 0xc1, 0xdd, 0x23, 0xf4, 0x7c }, + .p_data = { + .Y = { 0x1517abc5, 0xda0a07a7, 0x50a2630e, 0x580d6350, 0x24dca21d, 0xcc3acfe2, 0x7d44905c, 0x022aaf82, 0xb81555e9, 0xd3782c5f, 0x0496e1ca, 0x397a5a9c, 0xba536806, 0xf6099ee9, 0x6c738611, 0x6e141ced, 0x521bae67, 0x525cbad6, 0xf5f3ed2b, 0x0d566cb7, 0x188ff23f, 0xf97e5be8, 0x72531f32, 0x29f0bbb7, 0x935a7186, 0x6ee0abc9, 0x4a680783, 0xd3bc67aa, 0x0623a3cd, 0xb8e6a152, 0xfe9e13dd, 0x1cc8bec0, 0x800c3eda, 0xbb137d8f, 0xcac2fe1e, 0xf4a50bf5, 0xf28e0d3d, 0x40f8279e, 0x3f62bb10, 0x177d1550, 0x1df24c80, 0x7e5dd8f0, 0xe9d567fa, 0x81529deb, 0x3d0a7df5, 0x0d603614, 0xf4ae7363, 0x506a3966, 0xce69b06f, 0x57c1eba6, 0xcb2a4c49, 0x33ad633f, 0xb520c7a0, 0x44c615f3, 0xdd38bcec, 0x1694bff4, 0xec7f13fe, 0xd9750709, 0xd8845ff8, 0x766f2f4c, 0x4ca8e68b, 0xe9b2814d, 0x3be493ef, 0x46d960d6 }, + .M = { 0xaa8caac5, 0xd9f24cde, 0x0e4d95f0, 0xc8cbcac2, 0x9d4a096f, 0x18fde814, 0x706a6052, 0x1ddcc861, 0xe3c04364, 0x32f7b992, 0xb15e44aa, 0x050328bb, 0xf25b9408, 0x92e786ed, 0x01092f61, 0xa73c035b, 0xf122a068, 0x70a54bab, 0xcc76414e, 0xb5ee0849, 0x1cc247d3, 0x62d427aa, 0x8a078598, 0x14cb69d1, 0xa40f51ea, 0x42985516, 0xab575a8a, 0x59d170a5, 0xfa1e17e2, 0x05b9ff3a, 0xb0ab5ced, 0x07a74f23, 0xbe8f8b39, 0xd97d55ed, 0x69f71138, 0x49503e00, 0xbbce0e16, 0x1229c8fe, 0xc2e9b9da, 0xb80a1d50, 0x5017a493, 0x2e0a575f, 0x0671e0fe, 0x6ab56bbb, 0xc642df1d, 0x7f901396, 0x87e287e7, 0x917017b4, 0x4572fd68, 0x140ccde3, 0xc1b13adf, 0x46b315e1, 0xabe3cbc5, 0xb4a7543b, 0x736514dc, 0xf18117ae, 0xfab70fb2, 0x5fe7b7cb, 0x3f6bd75c, 0xec1da247, 0x48216c7c, 0x1ef1fcaf, 0x63c85a99, 0xa7dfdc9a }, + .Rb = { 0xfd6df2a9, 0x2f001a69, 0xb5ec8e9f, 0xab1dd561, 0x8582ce6f, 0x4cf430da, 0x08775576, 0x0d498fa1, 0x78b2729a, 0x15df619c, 0x72636ee8, 0xf4f3efee, 0x6b4b0c17, 0x04094180, 0x97cc5f2c, 0xe4aef62b, 0x2393f3a9, 0x9ae3fe26, 0xfff62fb0, 0x462569a8, 0xa2356966, 0x4d25a0db, 0xbc59613a, 0xc3ac647c, 0x2b2280a0, 0x8074898f, 0x3b5547d3, 0xdf141401, 0x359c89cf, 0xe3c361f6, 0xd52d786f, 0x15254b3a, 0x43b486f6, 0x934c815e, 0xf0203620, 0x8df19844, 0xb82debac, 0xd8a81748, 0xfbc7a424, 0xcbb7d6fc, 0x7cef838e, 0x3cd70cdd, 0xa1019630, 0xbe2421eb, 0xa9a951e2, 0x0284e983, 0xf84d5c59, 0x02c038dc, 0x9d5bee73, 0x5011288a, 0xc82401e1, 0xaf272849, 0xa5adb2b3, 0x33b9e9c7, 0x14bf3b82, 0x99b707b4, 0xe276bdbc, 0x2d0dc0d1, 0x66df46f5, 0x5a843c54, 0x11d6dfd8, 0x15e56656, 0xa8565021, 0x71cd14b4 }, + .M_prime = 0x988cbbf3, + .length = 63, // 2048 bit + }, + .expected_c = { 0x6d, 0x68, 0x5d, 0x15, 0xe7, 0x44, 0xcb, 0x67, 0x0c, 0x86, 0x0e, 0x53, 0x96, 0x50, 0x8f, 0x4e, 0x16, 0x48, 0x04, 0x61, 0xca, 0xdb, 0x70, 0xf8, 0x5b, 0xcc, 0xf9, 0xbc, 0xc4, 0x6c, 0xbb, 0x02, 0x0a, 0xa1, 0x65, 0xef, 0xb0, 0x8b, 0x15, 0xb1, 0x99, 0x16, 0xb5, 0xb8, 0xc5, 0xb1, 0x17, 0x83, 0xe7, 0x80, 0x39, 0xe3, 0x52, 0x1f, 0x85, 0x92, 0xbf, 0x61, 0x79, 0x27, 0xc5, 0x25, 0x01, 0x20, 0x06, 0x46, 0xab, 0x55, 0x19, 0xf7, 0xfa, 0x80, 0x29, 0xef, 0xa4, 0xa9, 0xe0, 0xca, 0x8b, 0x6f, 0xaf, 0xee, 0x49, 0x34, 0x74, 0xa0, 0x50, 0x4d, 0x01, 0xc1, 0xbf, 0x68, 0x82, 0xb2, 0x65, 0x50, 0x1d, 0x9a, 0x45, 0x6b, 0x73, 0x66, 0xa6, 0x97, 0xd5, 0x0d, 0x0c, 0x3e, 0x9f, 0x6d, 0xf6, 0x49, 0xff, 0x27, 0xb3, 0x22, 0xcd, 0xe9, 0xb8, 0x91, 0x88, 0xb2, 0x76, 0xb9, 0x5d, 0x2c, 0x78, 0xcf, 0x79, 0x9a, 0x5a, 0x0e, 0x37, 0x67, 0xc6, 0x89, 0x1c, 0x02, 0x8c, 0x16, 0xb6, 0xa4, 0x92, 0xf7, 0x35, 0xa3, 0x07, 0xcb, 0xc1, 0x75, 0x0a, 0x8b, 0xcb, 0xd4, 0x0d, 0x21, 0xda, 0x90, 0x0e, 0x08, 0xd0, 0x71, 0xda, 0x2f, 0xc9, 0xfa, 0x36, 0xb4, 0x9f, 0x5a, 0x2e, 0xbe, 0xcd, 0xd5, 0xf6, 0x5a, 0x67, 0xd5, 0x9e, 0x84, 0x78, 0xb6, 0x52, 0xec, 0xe8, 0x63, 0x47, 0x4b, 0x24, 0x2e, 0xb0, 0xee, 0x58, 0x1b, 0x3e, 0x4e, 0x2e, 0x1d, 0xef, 0x7e, 0xc0, 0x04, 0xe3, 0x53, 0xc6, 0x32, 0x6d, 0x8c, 0x71, 0x18, 0xcd, 0x4c, 0x15, 0xde, 0xee, 0x7d, 0x9b, 0x8f, 0x49, 0x30, 0x2c, 0xf3, 0x9c, 0xfc, 0xb1, 0x63, 0x70, 0x2b, 0x32, 0xd7, 0x5e, 0xe5, 0x77, 0xbd, 0x49, 0xe9, 0x59, 0x6a, 0xf7, 0xda, 0xeb, 0x92, 0x87, 0x05, 0x17, 0xad, 0x56, 0x55, 0x67, 0xe7, 0xe5, 0x57, 0x13, 0x29, 0x70, 0xab, 0x72, 0xd5, 0x83, 0x67, 0x07, 0x8a, 0x70, 0x8d, 0x7a, 0x20, 0x04, 0x90, 0xcd, 0xc4, 0xa6, 0x35, 0xa0, 0x2d, 0x9e, 0x02, 0x44, 0x34, 0x09, 0x5f, 0xc3, 0x56, 0x67, 0x74, 0xfa, 0x20, 0x87, 0x01, 0x2d, 0xc7, 0x5f, 0x57, 0x46, 0x45, 0x8a, 0x6a, 0x05, 0xf1, 0x47, 0xf8, 0x43, 0xbc, 0xc5, 0x9b, 0x5c, 0xea, 0x8f, 0xf7, 0xc9, 0xd2, 0xfe, 0x38, 0x04, 0x2a, 0x88, 0x3e, 0xbf, 0xca, 0xc3, 0xe7, 0x1f, 0x0d, 0x3a, 0x2c, 0x8e, 0xa3, 0x2a, 0x24, 0x24, 0x2d, 0xbc, 0xb4, 0x46, 0x2c, 0x14, 0x57, 0xc9, 0x2e, 0xcf, 0xc5, 0x2b, 0xc7, 0xe5, 0xb9, 0xdd, 0xd0, 0x80, 0x09, 0xa0, 0x1e, 0xa6, 0xcd, 0xa2, 0xc0, 0x2e, 0x4f, 0x70, 0x06, 0xe4, 0xeb, 0x8d, 0xc8, 0x4f, 0x17, 0xa0, 0xc2, 0xde, 0x2c, 0xf5, 0xde, 0x4f, 0x25, 0x3c, 0x16, 0xec, 0x54, 0x84, 0xed, 0xdd, 0x3b, 0x28, 0x43, 0x86, 0xf3, 0x30, 0x43, 0x2c, 0x7d, 0x4d, 0x7c, 0x76, 0xd8, 0x70, 0x11, 0x7b, 0x99, 0xab, 0xc0, 0xa6, 0xf4, 0x2c, 0xd1, 0x8a, 0xe5, 0xd5, 0xd7, 0xda, 0xd8, 0x39, 0x81, 0x07, 0xd4, 0x70, 0x52, 0x0d, 0xd8, 0x9a, 0x27, 0x26, 0x6d, 0xe4, 0x12, 0x32, 0x0b, 0x4b, 0x24, 0x43, 0xf4, 0x38, 0xfc, 0x9b, 0x01, 0x1a, 0xcf, 0x28, 0x03, 0xc3, 0x6a, 0x26, 0x9a, 0x3c, 0x1f, 0x0e, 0xd2, 0x9d, 0x6e, 0xb5, 0xba, 0x2f, 0xdb, 0x96, 0x82, 0x42, 0xe7, 0x56, 0x4d, 0xf7, 0xf3, 0x96, 0xed, 0x2e, 0x14, 0x25, 0x56, 0x4e, 0x53, 0x19, 0x83, 0xd9, 0x35, 0x28, 0x1a, 0x93, 0xe3, 0xdf, 0x82, 0x05, 0x74, 0x70, 0x73, 0x14, 0x08, 0x35, 0xf6, 0x89, 0x2f, 0xd2, 0xf0, 0x4f, 0x51, 0x8e, 0xda, 0x9c, 0xf3, 0x6d, 0xe7, 0x16, 0xf0, 0xc9, 0x3e, 0x9a, 0x9c, 0x2c, 0x24, 0xd5, 0x26, 0x0a, 0xdb, 0x68, 0xe8, 0xc6, 0x8a, 0x43, 0x37, 0x97, 0xe9, 0x25, 0x83, 0xa1, 0x30, 0x2a, 0x08, 0x64, 0x24, 0xda, 0xa9, 0xa9, 0x93, 0x8b, 0xdd, 0x1e, 0x5b, 0xb6, 0x9e, 0x83, 0xe7, 0xe5, 0x72, 0xb9, 0xa6, 0xb1, 0x53, 0x8a, 0x99, 0x0b, 0x8b, 0x25, 0x2d, 0x73, 0x83, 0x77, 0x82, 0xcc, 0xfe, 0xff, 0x2b, 0x57, 0xd2, 0x13, 0xf1, 0xb6, 0x9b, 0xe8, 0x2e, 0x96, 0xb9, 0x37, 0x43, 0x64, 0x8a, 0xc5, 0x0f, 0xaf, 0x47, 0xe4, 0x07, 0x34, 0xfb, 0x47, 0xb9, 0xa4, 0x16, 0xbb, 0xbb, 0x13, 0x53, 0x87, 0xcb, 0x84, 0xed, 0x3f, 0xbe, 0x32, 0xe2, 0x47, 0x74, 0x72, 0xc4, 0x2e, 0xbe, 0x8e, 0xd4, 0x8d, 0xe8, 0x03, 0x7b, 0x5b, 0xc5, 0xd8, 0xd3, 0xe1, 0x57, 0x81, 0x94, 0x2b, 0x4e, 0x0c, 0x68, 0xbb, 0x92, 0x34, 0xce, 0x68, 0x52, 0xbc, 0xb1, 0xdf, 0x39, 0x43, 0x00, 0x48, 0x2a, 0x84, 0x2c, 0x32, 0x3a, 0xe2, 0x14, 0xad, 0x33, 0x62, 0xb7, 0xd8, 0x7b, 0xe6, 0x14, 0xe2, 0x41, 0x5b, 0x55, 0x58, 0x67, 0xbd, 0xc9, 0x52, 0x20, 0xa3, 0x5c, 0x57, 0xe0, 0xa2, 0xf8, 0x56, 0xae, 0x01, 0x59, 0xe9, 0xd8, 0x16, 0x25, 0xfc, 0xd8, 0x3d, 0xed, 0xd5, 0x4d, 0x6f, 0x17, 0xee, 0x4d, 0x25, 0xd5, 0xa9, 0x97, 0x42, 0xa6, 0xa7, 0x37, 0xd3, 0xac, 0x30, 0xed, 0x12, 0x81, 0x16, 0xa7, 0x9e, 0xed, 0x6d, 0x14, 0x3a, 0xde, 0x37, 0x09, 0x8c, 0x39, 0xee, 0x2b, 0x3a, 0x2b, 0xdb, 0xe3, 0xd1, 0x84, 0x52, 0x0f, 0x1c, 0x3c, 0xf3, 0x5b, 0x82, 0x6b, 0xea, 0xdb, 0xa7, 0x51, 0x5e, 0xc3, 0xf7, 0x20, 0x1d, 0x7b, 0x52, 0x38, 0x3a, 0x6f, 0xde, 0xe6, 0x2e, 0x33, 0xec, 0xb7, 0x37, 0x61, 0x0e, 0xb6, 0xf2, 0x37, 0x7d, 0x87, 0x55, 0x33, 0x9e, 0x1d, 0x0d, 0xc9, 0x5a, 0x58, 0xfc, 0x87, 0x64, 0xc3, 0x06, 0xdb, 0xec, 0x33, 0x2d, 0x82, 0x6c, 0x9f, 0xe5, 0x4c, 0xff, 0xb3, 0x3e, 0x33, 0xe1, 0xcd, 0xc5, 0x9b, 0x65, 0x90, 0xe8, 0xd4, 0xf4, 0xc2, 0xfd, 0x72, 0x5e, 0x18, 0x6a, 0x08, 0x3c, 0x99, 0xc9, 0x22, 0x31, 0x4b, 0xa4, 0x6a, 0xd7, 0x77, 0xe6, 0xb2, 0x7e, 0x2c, 0x1d, 0x5c, 0xb5, 0x9c, 0x26, 0xe5, 0xb8, 0xcc, 0x45, 0x36, 0xb9, 0x7c, 0xd8, 0x60, 0x07, 0xc1, 0x9f, 0xfc, 0xbb, 0xe5, 0xeb, 0xfc, 0x8c, 0xc5, 0x1a, 0xcc, 0x10, 0x53, 0xbe, 0x32, 0x5a, 0x63, 0x91, 0x0d, 0x88, 0x67, 0x76, 0xfa, 0xaa, 0x36, 0xa3, 0x08, 0xad, 0x3e, 0x42, 0xfd, 0xca, 0xad, 0xf4, 0xf5, 0xc9, 0x36, 0xb9, 0x87, 0xbb, 0x42, 0x2c, 0x4b, 0x05, 0xbe, 0x7d, 0xf7, 0x28, 0x8b, 0x90, 0x9d, 0x3b, 0xe4, 0x1a, 0xd8, 0xbe, 0x6d, 0x28, 0xe3, 0x41, 0xa9, 0xc0, 0x6f, 0x85, 0x4e, 0xfb, 0xf6, 0x9c, 0x21, 0xaa, 0x7f, 0x20, 0x98, 0x35, 0x76, 0xb4, 0x83, 0xc6, 0xe2, 0xeb, 0xe2, 0x8d, 0xe5, 0x35, 0xcf, 0xe7, 0x73, 0x4b, 0x44, 0xed, 0x79, 0x44, 0x5d, 0x37, 0x09, 0x59, 0x52, 0x41, 0xab, 0x05, 0x79, 0xc0, 0xf7, 0x86, 0xac, 0x6e, 0x01, 0xf4, 0x34, 0xe7, 0xd4, 0x76, 0x38, 0x73, 0x72, 0xc5, 0xf7, 0x51, 0xfb, 0x99, 0x71, 0x38, 0x63, 0xba, 0xe4, 0x35, 0x38, 0xa2, 0xf1, 0xe5, 0x19, 0xfe, 0xba, 0xca, 0xe8, 0x8e, 0x66, 0xd2, 0xfe, 0x07, 0x40, 0x54, 0x31, 0x83, 0x9d, 0xa2, 0xf5, 0x89, 0x26, 0x4a, 0xca, 0xbb, 0xc1, 0x52, 0xc7, 0x1d, 0xe8, 0xa6, 0x0e, 0x0f, 0x78, 0x64, 0x08, 0xed, 0x2d, 0xfa, 0x0c, 0xc4, 0x84, 0x9a, 0xa9, 0x0d, 0xe1, 0x69, 0x57, 0xde, 0x4f, 0xbf, 0xb6, 0x8f, 0x49, 0x0a, 0x06, 0xc7, 0x14, 0xb0, 0x29, 0xd1, 0xdb, 0x5c, 0x02, 0xcb, 0xea, 0xc1, 0xef, 0x8f, 0xf0, 0x8e, 0xde, 0x11, 0x0b, 0xd6, 0xc1, 0x28, 0x13, 0xd3, 0x7e, 0x55, 0x64, 0xfc, 0xe7, 0x38, 0xce, 0x6e, 0xd4, 0x35, 0x74, 0xb9, 0x2c, 0xe7, 0x3c, 0x67, 0xcc, 0xf3, 0xdb, 0xa1, 0x9b, 0x9f, 0xc2, 0xd5, 0xce, 0x85, 0xfc, 0x72, 0x52, 0x81, 0x94, 0x2c, 0x18, 0xd3, 0x06, 0x0d, 0x39, 0x5a, 0x05, 0x9d, 0xef, 0xaf, 0xea, 0x30, 0xf2, 0x07, 0xb6, 0x44, 0x44, 0x59, 0xe2, 0x20, 0xea, 0xde, 0x69, 0x4e, 0x88, 0x7f, 0x52, 0x0a, 0x02, 0x82, 0x6a, 0xf8, 0x96, 0x7f, 0x0b, 0xb2, 0x6e, 0x19, 0x88, 0x2d, 0xd1, 0x05, 0x08, 0x78, 0x08, 0xa0, 0x45, 0xf8, 0xa0, 0x3c, 0x62, 0xa0, 0xbf, 0x5e, 0x60, 0xa5, 0xae, 0x80, 0x69, 0x85, 0x01, 0x93, 0x37, 0x41, 0xc5, 0xf4, 0x53, 0x96, 0x38, 0xb9, 0xd9, 0xad, 0xf7, 0xc9, 0xf6, 0x86, 0x06, 0x52, 0x6d, 0x10, 0xc8, 0x35, 0x52, 0xff, 0x0b, 0xae, 0x50, 0xd1, 0x22, 0xb1, 0x12, 0x9e, 0x4e, 0xda, 0xb0, 0xfb, 0x36, 0x47, 0x9b, 0x28, 0xb3, 0xa3, 0x51, 0x32, 0x8d, 0x20, 0x55, 0x47, 0xf0, 0xa8, 0xeb, 0xac, 0x77, 0x52, 0x28, 0xf8, 0x88, 0xcc, 0xff, 0x71, 0xc1, 0xbe, 0xc2, 0x19, 0x44, 0xac, 0x86, 0xe0, 0x4c, 0xfb, 0xcf, 0x8b, 0x5a, 0xff, 0x17, 0x3a, 0xb6, 0xd4, 0x53, 0xae, 0x95 }, + .hmac_key_idx = 2, + // results of message array encrypted with these keys + .expected_results = { + // Message 0 + { 0x7b22c206, 0x46ae989a, 0x6456c231, 0x2183bc5c, 0x92bdea51, 0x13417e21, 0xde38f455, 0xcc113b62, 0xa787a973, 0x8672490a, 0x5adf07e5, 0x3585f4ce, 0x9861c55d, 0xcfd465d0, 0xd38daf34, 0x49c1e9e4, 0x8f6e74c6, 0x61d6e2c8, 0xef486e63, 0x87da49e5, 0xfba091e3, 0x9775901b, 0xd0bafdd4, 0x8ceab0e0, 0x7214d792, 0x8e96474d, 0x6a30e56d, 0x27aeb6dd, 0x1e0a13c5, 0xc70bf66a, 0xabdb794b, 0x79615211, 0xec31b142, 0xc7e78250, 0x7b3436f1, 0x836e97a3, 0x18f69feb, 0x5f7ae9da, 0xa3c8aaea, 0x6e4a0942, 0xf046b062, 0xe173890e, 0x73011a58, 0x7a2e2e75, 0xcafe8105, 0xa7ef42da, 0xd8bf1dd3, 0xca3ef9c1, 0xa385d157, 0x1bc73056, 0x08f45713, 0x8f03b489, 0x2e3278c5, 0x0e085028, 0xab6d3a8b, 0xf875ebe7, 0xabafe41c, 0x0e6588a6, 0xaeb530ac, 0xae2deb58, 0x37a7d1e8, 0x4ac42801, 0x84838ea8, 0x9807a9c7 }, // Message 1 + { 0x189ece24, 0x588c859b, 0x4d3c4fe2, 0xaba143e4, 0xa3e69b16, 0xe892939c, 0x30b96777, 0x275fa922, 0xa090a7a4, 0x5ea8df3a, 0x4e63ace7, 0xb64336a0, 0xef87769e, 0x734e623a, 0xefec6481, 0x404f1ffa, 0x0eb53616, 0x5f641f9b, 0xc8ca81e5, 0x6562bd99, 0x90092de8, 0x756cd3da, 0x6d0e99a3, 0xc0887d8f, 0x35d380b2, 0x9f145969, 0x4e0d55b0, 0xa116d5a1, 0x3c60be2b, 0xcd970c74, 0x10086e47, 0x59fe8ec7, 0x642c179b, 0x5ba3646a, 0x849ad310, 0xf3fa09ce, 0x8b691d8d, 0xf27f1c3f, 0xbe74426f, 0x3e18f1a9, 0xe4eee4a8, 0xa1c1a4b8, 0xff82d121, 0xb442aa78, 0x12fa04ac, 0x34bec6bb, 0xb0988597, 0x48e2d92b, 0x2ceb5756, 0x7ed5290a, 0x7d240f20, 0xc970a910, 0x8962e1c6, 0x76c99d2d, 0xd431a0b5, 0xaa1f84a6, 0x83f97dc8, 0x0ca52886, 0x7c9f003a, 0xd1c0547c, 0xaaef6bd0, 0x3c25ee0d, 0x8fbb2719, 0xa2d8e535 }, // Message 2 + { 0x842f8773, 0x98344f46, 0x56583e5d, 0xf87e2ad3, 0x0dacf1b1, 0x1ad44410, 0x57d1cc41, 0xab528173, 0xa0b497bb, 0xcc9ffdfe, 0xbba26264, 0xfe1f176d, 0x814f7757, 0x8a13bc51, 0x412036d0, 0xa6bdb540, 0x565e9a13, 0x556d394e, 0x5aafa0cc, 0xf39796eb, 0xa8a3ac8f, 0xb9dd179f, 0x1a6b04a8, 0x61f36111, 0xaf9c5b78, 0xd7b32762, 0x1c751ff9, 0x31a7c78f, 0xd2ed9fb5, 0x81c19261, 0x973af61d, 0x1767c39f, 0x1a974921, 0xcc5b404d, 0x4e83c304, 0xf60c3d9b, 0xba033aab, 0xeac94156, 0x1addc5d0, 0xb706577b, 0x77e4cfff, 0x2009a3bf, 0xd68739f1, 0xa67fc485, 0x3e87d453, 0x5f9360f3, 0x78736697, 0xb0bda2a0, 0x9f9ec632, 0x4bbf4c8e, 0x4cb613c0, 0x2985c43b, 0xbcc89045, 0xb44d377a, 0x9f3efdab, 0x03708d30, 0x8fcbe8fb, 0x25a68e46, 0xc7df4e31, 0xf5f2aaeb, 0x82693a70, 0xbe82063b, 0x16d49fc1, 0x14d4cc5c }, // Message 3 + { 0x2e2e90d9, 0x2de4fc9e, 0x3bbf80ec, 0x8b1b08d7, 0xbb0ca909, 0x2768e2fd, 0x6b120d64, 0x6d5acc4d, 0x10ac6fcd, 0xe5e4a5cc, 0xba41bfd7, 0xac7c4660, 0x07606976, 0xab87cf16, 0x7feeb177, 0x2acd9b2b, 0xa62382e1, 0xd402b527, 0x72dd3033, 0x38a93ab0, 0xd83b1608, 0xcc945333, 0x982cea7d, 0x9319041f, 0xc94d029c, 0xa6e87c8a, 0x173d3a35, 0xf4e70cc3, 0x8c2d4ad7, 0xfd802823, 0x545d5aef, 0x5234deaa, 0x926ac06b, 0xcd39f99d, 0x1cdd2e32, 0x0532f48c, 0x2e2cb6f7, 0x61d2358f, 0xb46f8636, 0xb7a25c52, 0x1ef22814, 0xcef40419, 0x07424471, 0x349b854f, 0xc936a63a, 0xe6a5d41e, 0x56690c91, 0xbf84aad4, 0x0151e023, 0xa4949a71, 0x38bbf6f0, 0xf1abdfb8, 0x1e8b818b, 0x10d67b20, 0xb150f729, 0x553ca2df, 0x9f7d178b, 0x3a863661, 0x76a4c9aa, 0x89cc0fe6, 0x62fea752, 0x42339488, 0xcf99ff81, 0x4e1aecfe }, // Message 4 + { 0x841f4980, 0x2cf046b2, 0x82e95cc2, 0xa47ebc7c, 0xea548361, 0x564ccec3, 0x2faf266c, 0x659471dd, 0x4bbeaa68, 0xb4c256a1, 0xb7171691, 0x38e03b80, 0x4278d5f9, 0x46b2501c, 0x17fd4074, 0x74de63cd, 0x597e3de8, 0xf49ab732, 0x3590c171, 0x412474f5, 0xcab54898, 0xd8b1b004, 0x44443aaa, 0x76d906d3, 0x9dec151c, 0xf58d2673, 0x9bf53ae2, 0x1da366d9, 0x309135cb, 0x0fa7c2d3, 0x64c6fa06, 0x2fd482d8, 0x42ecbf3c, 0x0b2059a9, 0xeaeeb86a, 0xad7ca190, 0xedfd71ea, 0x86899035, 0x9ec7ee43, 0xd6ed40c0, 0xa5f99f9c, 0x34f924b1, 0x70b03003, 0x698d7c34, 0xc1f0d5fc, 0x4fa2274a, 0x4db6e8ac, 0x6540723c, 0xa25dc0a1, 0xfea69928, 0x43b40634, 0x569e0518, 0x4e390450, 0xc44901b4, 0x90967b05, 0xd4916f29, 0xb04e38c6, 0x4bb3f4cd, 0x55a0e3cf, 0x4058a3ee, 0x07d9ce28, 0x46e2defd, 0x8039fee1, 0x03e662ad }, // Message 5 + { 0x89019435, 0x24c401fa, 0x4d7c4b63, 0x17bff47b, 0x95a39c40, 0xb7346f21, 0x2e0464b4, 0xc885b549, 0xa1951ca1, 0x8bee01ee, 0x6d077d2a, 0x538f67db, 0xf1eb9773, 0x57e86797, 0x189b0494, 0xf1011d51, 0x0e2592f2, 0xeabbc83c, 0xf0badf63, 0xd61f066d, 0x0b88110e, 0xc00883ec, 0xd4d157ac, 0xfccad14f, 0xfc326202, 0xdba0ccbe, 0xc8aa8a62, 0x17ccf405, 0xd62cd80c, 0x1ea7730e, 0xec66f387, 0xfbf6b135, 0x0f019e3e, 0x487948aa, 0xb6117873, 0x032aa30e, 0x095d8c24, 0x40839164, 0x68ba9af0, 0x87639199, 0xae153b7f, 0x2dcfcc37, 0xec71e709, 0xbd84076a, 0x2a96711c, 0x99e37df3, 0x0b22ddd6, 0xfadba214, 0x77d71182, 0xa68cfd81, 0x2aab3ec2, 0xce30169e, 0xc46d9aee, 0x5f1206b9, 0x4622ef37, 0x9d13fa6b, 0x480f58ff, 0xf965ee1f, 0x360d1e3b, 0x0613ee41, 0xcb720f23, 0xa1465579, 0x05c19d02, 0x38669af2 }, // Message 6 + { 0x432cf8ba, 0xaf3b700b, 0xb4b5ae74, 0xd1561ebd, 0x369b3869, 0xb76b7cb6, 0x0d7d1ef1, 0x3011b466, 0x1207ded1, 0x4885f193, 0xdae5f9b1, 0xfb450105, 0x052e9eba, 0xc7ec34a1, 0xdcc48d31, 0x24c859f1, 0x8329c06f, 0x21e7b2f8, 0x74afea39, 0xcd9ee06b, 0x51ba6020, 0x8e0be42d, 0x283c6b39, 0xcd3fc394, 0x4e8497e0, 0x5cee0cbe, 0x437a14fc, 0x30df6d23, 0x1272bdd5, 0xe26a86e3, 0xab0f6163, 0x36a692b3, 0x7c49e052, 0xd4e65c50, 0x15c2a394, 0xeb357b9f, 0xbb795751, 0xb72df6ee, 0xf238e9f7, 0xa1ff9dfb, 0xa753208a, 0x7f78fd97, 0x0ff1c41d, 0xb3c4c174, 0xcf395664, 0x6676ba72, 0x849f7e7a, 0xac0473d7, 0x9b72d66e, 0x8fb69c14, 0x9e8878b2, 0x2dedf30d, 0xc8af55f5, 0x3f3d2083, 0x7fe947fe, 0x0a210322, 0xb92ab78d, 0xeb34a0ca, 0x39334df1, 0x773e3c8e, 0xa90774e1, 0xca705a5a, 0x218f28b7, 0x475ebdb0 }, // Message 7 + { 0x8c5c7218, 0x958a48f2, 0x1c20099a, 0xa9b5c3e9, 0xfca5473d, 0x746376da, 0xf575f9f4, 0x6b2282a0, 0xa31a843d, 0x66355730, 0x8988ca45, 0x2fb33584, 0x4670b87f, 0xe581a153, 0x7e710075, 0x995cebc1, 0x2f19171e, 0x8de26c2f, 0x09a125b4, 0x690d908a, 0xe44c5c98, 0xe9c76193, 0xb789803c, 0xcc76e6ff, 0x6a39b96f, 0x831c32de, 0x48c47e27, 0x28368d9b, 0x586f2c41, 0xaa95608a, 0x83689888, 0x406dae8c, 0x8b25ef7d, 0x0b4e553e, 0x64db76c6, 0x58a4f783, 0x63220f5c, 0x2ddff5db, 0x18e2dfea, 0x125b86c3, 0x90414551, 0x265b269b, 0x321ef362, 0x922f8e4a, 0xe43611cb, 0xd47a5216, 0xe6004e4f, 0xa6811400, 0x431e3e45, 0x8a8b1184, 0x64c52dd2, 0x12fdc22b, 0x0bd34023, 0x9a7fa998, 0x7495bc65, 0x0644fb9c, 0x2dddf147, 0xa3b17ca5, 0x828bc41b, 0xab194108, 0x464bbf74, 0xaa2b4852, 0x93c6adf8, 0x254ba88d }, // Message 8 + { 0xaf33125e, 0xcd61f762, 0xd52dcbea, 0x3b99e7a6, 0x431be6ef, 0xddec4ed5, 0x7cb4f2c6, 0x92ffb45e, 0x973c46af, 0xc5581b3b, 0x5bbab1db, 0xa6680da8, 0x30f38ce4, 0x1d93e00e, 0x0ceef86a, 0x07534741, 0xa9f570c9, 0xd8cf633e, 0x5c4ba0c3, 0x0968158a, 0xba0a4e25, 0x4a44017e, 0xdc1c6132, 0xae608ca8, 0x32c543ea, 0x2950f268, 0x7c6eda54, 0xbab7a023, 0xf36585ee, 0xdf0c66f3, 0x4a1ba502, 0xcac38574, 0x36e869fc, 0xb5509b0d, 0x1c088009, 0x178f1c26, 0x3c1cc513, 0x66a3141e, 0x6ddffe33, 0xe4417aee, 0xbdb6d8d3, 0xd9fe0bd2, 0x1262d566, 0xeda0ae23, 0x48f00099, 0xb0c61240, 0x46cc7c83, 0xa6d3d845, 0x9feb70de, 0xefa2f7ed, 0x5857fd55, 0x9bd3508f, 0x1c1bb350, 0xb31849c8, 0x51dfa657, 0xdd9029bc, 0xd1869778, 0xaf978c3f, 0x8c33cec1, 0x0c739f65, 0x36c69fc2, 0xe2874fe5, 0x8e41bf9e, 0x2e4bfd1e }, // Message 9 + { 0xf5d26d39, 0xe7673325, 0xf8051f90, 0xef04d0df, 0xa14bc15d, 0x830af6a3, 0x3e22caed, 0x4ae14f16, 0x9bf6bc8a, 0xe8bdf224, 0x10fafc74, 0x2dd86523, 0xa5361fc8, 0x67f39978, 0xbea39d9a, 0x93a68e79, 0x7306e87a, 0x6b702aeb, 0x6b11c96e, 0x2ea1315a, 0x6d9e46e8, 0x499c0493, 0xb2c670de, 0x684c0b90, 0xcfe86873, 0x750c4b73, 0x6d0d35e5, 0x5eb2a6b3, 0x7d2a2cfb, 0x2c5db123, 0x170d1d83, 0x6b4abe2a, 0x0351e500, 0xe2377316, 0x809b6ed5, 0xabb0c00d, 0x0d0e4060, 0x8910784a, 0x4f46fa98, 0x089aba27, 0x05b71b1a, 0xd77b3b8e, 0xc50c7f92, 0xeedb077a, 0x2adaf56e, 0xd3a00ea4, 0x452f597f, 0xe29b5e3a, 0xeb50742c, 0x502948d0, 0x7c0c6f6d, 0x847fa4ce, 0x8fa07655, 0x06ba7b82, 0x511e8807, 0x24e059f0, 0x85a49a42, 0x56e9bcf4, 0xb38ab575, 0x18be81df, 0x4175bad7, 0xf2cfb405, 0x99caaec9, 0x4f81f12f }, }, + }, +}; diff --git a/components/esp32h2/test/test_ds.c b/components/esp32h2/test/test_ds.c new file mode 100644 index 0000000000..aaffce8439 --- /dev/null +++ b/components/esp32h2/test/test_ds.c @@ -0,0 +1,382 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "unity.h" +#include "esp32c3/rom/efuse.h" +#include "esp32c3/rom/digital_signature.h" +#include "esp32c3/rom/hmac.h" +#include + +#include "esp_ds.h" + +#define NUM_RESULTS 10 +#define DS_MAX_BITS (ETS_DS_MAX_BITS) + +typedef struct { + uint8_t iv[ETS_DS_IV_LEN]; + ets_ds_p_data_t p_data; + uint8_t expected_c[ETS_DS_C_LEN]; + uint8_t hmac_key_idx; + uint32_t expected_results[NUM_RESULTS][DS_MAX_BITS/32]; +} encrypt_testcase_t; + +// Generated header (components/esp32s2/test/gen_digital_signature_tests.py) defines +// NUM_HMAC_KEYS, test_hmac_keys, NUM_MESSAGES, NUM_CASES, test_messages[], test_cases[] +#include "digital_signature_test_cases.h" + +_Static_assert(NUM_RESULTS == NUM_MESSAGES, "expected_results size should be the same as NUM_MESSAGES in generated header"); + +TEST_CASE("Digital Signature Parameter Encryption data NULL", "[hw_crypto] [ds]") +{ + const char iv [32]; + esp_ds_p_data_t p_data; + const char key [32]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(NULL, iv, &p_data, key)); +} + +TEST_CASE("Digital Signature Parameter Encryption iv NULL", "[hw_crypto] [ds]") +{ + esp_ds_data_t data; + esp_ds_p_data_t p_data; + const char key [32]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, NULL, &p_data, key)); +} + +TEST_CASE("Digital Signature Parameter Encryption p_data NULL", "[hw_crypto] [ds]") +{ + esp_ds_data_t data; + const char iv [32]; + const char key [32]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, iv, NULL, key)); +} + +TEST_CASE("Digital Signature Parameter Encryption key NULL", "[hw_crypto] [ds]") +{ + esp_ds_data_t data; + const char iv [32]; + esp_ds_p_data_t p_data; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, iv, &p_data, NULL)); +} + +TEST_CASE("Digital Signature Parameter Encryption", "[hw_crypto] [ds]") +{ + for (int i = 0; i < NUM_CASES; i++) { + printf("Encrypting test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[i]; + esp_ds_data_t result = { }; + esp_ds_p_data_t p_data; + + memcpy(p_data.Y, t->p_data.Y, ESP_DS_SIGNATURE_MAX_BIT_LEN/8); + memcpy(p_data.M, t->p_data.M, ESP_DS_SIGNATURE_MAX_BIT_LEN/8); + memcpy(p_data.Rb, t->p_data.Rb, ESP_DS_SIGNATURE_MAX_BIT_LEN/8); + p_data.M_prime = t->p_data.M_prime; + p_data.length = t->p_data.length; + + esp_err_t r = esp_ds_encrypt_params(&result, t->iv, &p_data, + test_hmac_keys[t->hmac_key_idx]); + printf("Encrypting test case %d done\n", i); + + TEST_ASSERT_EQUAL(ESP_OK, r); + TEST_ASSERT_EQUAL(t->p_data.length, result.rsa_length); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->iv, result.iv, ETS_DS_IV_LEN); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_c, result.c, ETS_DS_C_LEN); + } +} + +TEST_CASE("Digital Signature start Invalid message", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = { }; + ds_data.rsa_length = ESP_DS_RSA_3072; + esp_ds_context_t *ctx; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(NULL, &ds_data, HMAC_KEY1, &ctx)); +} + +TEST_CASE("Digital Signature start Invalid data", "[hw_crypto] [ds]") +{ + const char *message = "test"; + esp_ds_context_t *ctx; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, NULL, HMAC_KEY1, &ctx)); +} + +TEST_CASE("Digital Signature start Invalid context", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = ESP_DS_RSA_3072; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature RSA length 0", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 0; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature RSA length too long", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 128; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature start HMAC key out of range", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = ESP_DS_RSA_3072; + esp_ds_context_t *ctx; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY5 + 1, &ctx)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY0 - 1, &ctx)); +} + +TEST_CASE("Digital Signature finish Invalid signature ptr", "[hw_crypto] [ds]") +{ + esp_ds_context_t *ctx = NULL; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_finish_sign(NULL, ctx)); +} + +TEST_CASE("Digital Signature finish Invalid context", "[hw_crypto] [ds]") +{ + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_finish_sign(signature_data, NULL)); +} + +TEST_CASE("Digital Signature Blocking Invalid message", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = { }; + ds_data.rsa_length = ESP_DS_RSA_3072; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(NULL, &ds_data, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking Invalid data", "[hw_crypto] [ds]") +{ + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, NULL, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking Invalid signature ptr", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = ESP_DS_RSA_3072; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature Blocking RSA length 0", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 0; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking RSA length too long", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 128; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking HMAC key out of range", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 127; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY5 + 1, signature_data)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY0 - 1, signature_data)); +} + +#if CONFIG_IDF_ENV_FPGA + +// Burn eFuse blocks 1, 2 and 3. Block 0 is used for HMAC tests already. +static void burn_hmac_keys(void) +{ + printf("Burning %d HMAC keys to efuse...\n", NUM_HMAC_KEYS); + for (int i = 0; i < NUM_HMAC_KEYS; i++) { + // TODO: vary the purpose across the keys + ets_efuse_purpose_t purpose = ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE; + ets_efuse_write_key(ETS_EFUSE_BLOCK_KEY1 + i, + purpose, + test_hmac_keys[i], 32); + } + /* verify the keys are what we expect (possibly they're already burned, doesn't matter but they have to match) */ + uint8_t block_compare[32]; + for (int i = 0; i < NUM_HMAC_KEYS; i++) { + printf("Checking key %d...\n", i); + memcpy(block_compare, (void *)ets_efuse_get_read_register_address(ETS_EFUSE_BLOCK_KEY1 + i), 32); + TEST_ASSERT_EQUAL_HEX8_ARRAY(test_hmac_keys[i], block_compare, 32); + } +} + +// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). +// HMAC_KEY0 is usually used for HMAC upstream (user access) tests. +TEST_CASE("Digital Signature wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = ESP_DS_RSA_3072; + esp_ds_context_t *ctx; + const char *message = "test"; + + // HMAC fails in that case because it checks for the correct purpose + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx)); +} + +// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). +// HMAC_KEY0 is usually used for HMAC upstream (user access) tests. +TEST_CASE("Digital Signature Blocking wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = ESP_DS_RSA_3072; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + // HMAC fails in that case because it checks for the correct purpose + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data)); +} + +TEST_CASE("Digital Signature Operation (FPGA only)", "[hw_crypto] [ds]") +{ + burn_hmac_keys(); + + for (int i = 0; i < NUM_CASES; i++) { + printf("Running test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[i]; + + // copy encrypt parameter test case into ds_data structure + esp_ds_data_t ds_data = { }; + memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + for (int j = 0; j < NUM_MESSAGES; j++) { + uint8_t signature[DS_MAX_BITS/8] = { 0 }; + printf(" ... message %d\n", j); + + esp_ds_context_t *esp_ds_ctx; + esp_err_t ds_r = esp_ds_start_sign(test_messages[j], + &ds_data, + t->hmac_key_idx + 1, + &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[j], signature, sizeof(signature)); + } + + ets_hmac_invalidate_downstream(ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); + } +} + +TEST_CASE("Digital Signature Blocking Operation (FPGA only)", "[hw_crypto] [ds]") +{ + burn_hmac_keys(); + + for (int i = 0; i < NUM_CASES; i++) { + printf("Running test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[i]; + + // copy encrypt parameter test case into ds_data structure + esp_ds_data_t ds_data = { }; + memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + uint8_t signature[DS_MAX_BITS/8] = { 0 }; + + esp_err_t ds_r = esp_ds_sign(test_messages[0], + &ds_data, + t->hmac_key_idx + 1, + signature); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[0], signature, sizeof(signature)); + } +} + +TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]") +{ + burn_hmac_keys(); + + // Set up a valid test case + const encrypt_testcase_t *t = &test_cases[0]; + esp_ds_data_t ds_data = { }; + memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + uint8_t signature[DS_MAX_BITS/8] = { 0 }; + const uint8_t zero[DS_MAX_BITS/8] = { 0 }; + + // Corrupt the IV one bit at a time, rerun and expect failure + for (int bit = 0; bit < 128; bit++) { + printf("Corrupting IV bit %d...\n", bit); + ds_data.iv[bit / 8] ^= 1 << (bit % 8); + esp_ds_context_t *esp_ds_ctx; + + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); + TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS/8); + + ds_data.iv[bit / 8] ^= 1 << (bit % 8); + } + + // Corrupt encrypted key data one bit at a time, rerun and expect failure + printf("Corrupting C...\n"); + for (int bit = 0; bit < ETS_DS_C_LEN * 8; bit++) { + printf("Corrupting C bit %d...\n", bit); + ds_data.c[bit / 8] ^= 1 << (bit % 8); + esp_ds_context_t *esp_ds_ctx; + + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); + TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS/8); + + ds_data.c[bit / 8] ^= 1 << (bit % 8); + } +} + +#endif // CONFIG_IDF_ENV_FPGA diff --git a/components/esp32h2/test/test_sha.c b/components/esp32h2/test/test_sha.c new file mode 100644 index 0000000000..052433d6ac --- /dev/null +++ b/components/esp32h2/test/test_sha.c @@ -0,0 +1,80 @@ +#include +#include +#include +#include "esp_types.h" +#include "esp32c3/clk.h" +#include "esp_log.h" +#include "esp_timer.h" +#include "esp_heap_caps.h" +#include "idf_performance.h" + +#include "unity.h" +#include "test_utils.h" +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "sha/sha_dma.h" + +/* Note: Most of the SHA functions are called as part of mbedTLS, so +are tested as part of mbedTLS tests. Only esp_sha() is different. +*/ + +#define TAG "sha_test" + +TEST_CASE("Test esp_sha()", "[hw_crypto]") +{ + const size_t BUFFER_SZ = 32 * 1024 + 6; // NB: not an exact multiple of SHA block size + + int64_t begin, end; + uint32_t us_sha1; + uint8_t sha1_result[20] = { 0 }; + void *buffer = heap_caps_malloc(BUFFER_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + TEST_ASSERT_NOT_NULL(buffer); + memset(buffer, 0xEE, BUFFER_SZ); + + const uint8_t sha1_expected[20] = { 0xc7, 0xbb, 0xd3, 0x74, 0xf2, 0xf6, 0x20, 0x86, + 0x61, 0xf4, 0x50, 0xd5, 0xf5, 0x18, 0x44, 0xcc, + 0x7a, 0xb7, 0xa5, 0x4a }; + + begin = esp_timer_get_time(); + esp_sha(SHA1, buffer, BUFFER_SZ, sha1_result); + end = esp_timer_get_time(); + TEST_ASSERT_EQUAL_HEX8_ARRAY(sha1_expected, sha1_result, sizeof(sha1_expected)); + us_sha1 = end - begin; + ESP_LOGI(TAG, "esp_sha() 32KB SHA1 in %u us", us_sha1); + + free(buffer); + + TEST_PERFORMANCE_CCOMP_LESS_THAN(TIME_SHA1_32KB, "%dus", us_sha1); +} + +TEST_CASE("Test esp_sha() function with long input", "[hw_crypto]") +{ + const void* ptr; + spi_flash_mmap_handle_t handle; + uint8_t sha1_espsha[20] = { 0 }; + uint8_t sha1_mbedtls[20] = { 0 }; + uint8_t sha256_espsha[32] = { 0 }; + uint8_t sha256_mbedtls[32] = { 0 }; + + const size_t LEN = 1024 * 1024; + + /* mmap() 1MB of flash, we don't care what it is really */ + esp_err_t err = spi_flash_mmap(0x0, LEN, SPI_FLASH_MMAP_DATA, &ptr, &handle); + + TEST_ASSERT_EQUAL_HEX32(ESP_OK, err); + TEST_ASSERT_NOT_NULL(ptr); + + /* Compare esp_sha() result to the mbedTLS result, should always be the same */ + + esp_sha(SHA1, ptr, LEN, sha1_espsha); + int r = mbedtls_sha1_ret(ptr, LEN, sha1_mbedtls); + TEST_ASSERT_EQUAL(0, r); + + esp_sha(SHA2_256, ptr, LEN, sha256_espsha); + r = mbedtls_sha256_ret(ptr, LEN, sha256_mbedtls, 0); + TEST_ASSERT_EQUAL(0, r); + + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha1_espsha, sha1_mbedtls, sizeof(sha1_espsha), "SHA1 results should match"); + + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha256_espsha, sha256_mbedtls, sizeof(sha256_espsha), "SHA256 results should match"); +} diff --git a/components/hal/esp32h2/adc_hal.c b/components/hal/esp32h2/adc_hal.c new file mode 100644 index 0000000000..e4b893bdb6 --- /dev/null +++ b/components/hal/esp32h2/adc_hal.c @@ -0,0 +1,165 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The HAL layer for ADC (ESP32-C3 specific part) + +#include +#include "soc/soc_caps.h" +#include "hal/adc_hal.h" +#include "hal/adc_types.h" +#include "soc/soc.h" + +//Currently we don't have context for the ADC HAL. So HAL variables are temporarily put here. But +//please don't follow this code. Create a context for your own HAL! + +static bool s_filter_enabled[SOC_ADC_DIGI_FILTER_NUM] = {}; +static adc_digi_filter_t s_filter[SOC_ADC_DIGI_FILTER_NUM] = {}; + +static bool s_monitor_enabled[SOC_ADC_DIGI_MONITOR_NUM] = {}; +static adc_digi_monitor_t s_monitor_config[SOC_ADC_DIGI_MONITOR_NUM] = {}; + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ +void adc_hal_digi_deinit(void) +{ + adc_ll_digi_trigger_disable(); // boss + adc_ll_digi_dma_disable(); + adc_ll_digi_clear_pattern_table(ADC_NUM_1); + adc_ll_digi_clear_pattern_table(ADC_NUM_2); + adc_ll_digi_filter_reset(ADC_NUM_1); + adc_ll_digi_filter_reset(ADC_NUM_2); + adc_ll_digi_reset(); + adc_ll_digi_controller_clk_disable(); +} + +/** + * - Set ADC digital controller clock division factor. The clock is divided from `APLL` or `APB` clock. + * Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1). + * - Enable clock and select clock source for ADC digital controller. + */ +static void adc_hal_digi_clk_config(void) +{ + //Here we set the clock divider factor to make the digital clock to 5M Hz + adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT); + adc_ll_digi_controller_clk_enable(0); +} + +void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) +{ + //only one pattern table is supported on C3, but LL still needs one argument. + const int pattern_both = 0; + + if (cfg->adc_pattern_len) { + adc_ll_digi_clear_pattern_table(pattern_both); + adc_ll_digi_set_pattern_table_len(pattern_both, cfg->adc_pattern_len); + for (uint32_t i = 0; i < cfg->adc_pattern_len; i++) { + adc_ll_digi_set_pattern_table(pattern_both, i, cfg->adc_pattern[i]); + } + } + + if (cfg->conv_limit_en) { + adc_ll_digi_set_convert_limit_num(cfg->conv_limit_num); + adc_ll_digi_convert_limit_enable(); + } else { + adc_ll_digi_convert_limit_disable(); + } + + //clock + uint32_t interval = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / cfg->sample_freq_hz; + adc_ll_digi_set_trigger_interval(interval); + adc_hal_digi_clk_config(); +} + +static void filter_update(adc_digi_filter_idx_t idx) +{ + //ESP32-C3 has no enable bit, the filter will be enabled when the filter channel is configured + if (s_filter_enabled[idx]) { + adc_ll_digi_filter_set_factor(idx, &s_filter[idx]); + } else { + adc_ll_digi_filter_disable(idx); + } +} + +/** + * Set adc digital controller filter factor. + * + * @param idx ADC filter unit. + * @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +void adc_hal_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) +{ + s_filter[idx] = *filter; + filter_update(idx); +} + +/** + * Get adc digital controller filter factor. + * + * @param adc_n ADC unit. + * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +void adc_hal_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) +{ + *filter = s_filter[idx]; +} + +void adc_hal_digi_filter_enable(adc_digi_filter_idx_t filter_idx, bool enable) +{ + s_filter_enabled[filter_idx] = enable; + filter_update(filter_idx); +} + +static void update_monitor(adc_digi_monitor_idx_t idx) +{ + //ESP32-C3 has no enable bit, the monitor will be enabled when the monitor channel is configured + if (s_monitor_enabled[idx]) { + adc_ll_digi_monitor_set_mode(idx, &s_monitor_config[idx]); + } else { + adc_ll_digi_monitor_disable(idx); + } +} + +void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config) +{ + s_monitor_config[idx] = *config; + update_monitor(idx); +} + +void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable) +{ + s_monitor_enabled[mon_idx] = enable; + update_monitor(mon_idx); +} + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ + +/** + * Config ADC2 module arbiter. + * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, + * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data. + * + * @note Only ADC2 support arbiter. + * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. + * @note Default priority: Wi-Fi > RTC > Digital; + * + * @param config Refer to `adc_arbiter_t`. + */ +void adc_hal_arbiter_config(adc_arbiter_t *config) +{ + adc_ll_set_arbiter_work_mode(config->mode); + adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri); +} diff --git a/components/hal/esp32h2/brownout_hal.c b/components/hal/esp32h2/brownout_hal.c new file mode 100644 index 0000000000..5dac36f067 --- /dev/null +++ b/components/hal/esp32h2/brownout_hal.c @@ -0,0 +1,45 @@ + +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "hal/brownout_hal.h" +#include "soc/rtc_cntl_struct.h" +#include "soc/rtc_cntl_reg.h" +#include "regi2c_ctrl.h" +#include "regi2c_brownout.h" + + +void brownout_hal_config(const brownout_hal_config_t *cfg) +{ + REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, cfg->threshold); + typeof(RTCCNTL.brown_out) brown_out_reg = { + .close_flash_ena = cfg->flash_power_down, + .pd_rf_ena = cfg->rf_power_down, + .rst_wait = 0x3ff, + .rst_ena = cfg->reset_enabled, + .ena = cfg->enabled, + .rst_sel = 1, + }; + RTCCNTL.brown_out = brown_out_reg; +} + +void brownout_hal_intr_enable(bool enable) +{ + RTCCNTL.int_ena.rtc_brown_out = enable; +} + +void brownout_hal_intr_clear(void) +{ + RTCCNTL.int_clr.rtc_brown_out = 1; +} diff --git a/components/hal/esp32h2/hmac_hal.c b/components/hal/esp32h2/hmac_hal.c new file mode 100644 index 0000000000..795c3e4247 --- /dev/null +++ b/components/hal/esp32h2/hmac_hal.c @@ -0,0 +1,83 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "stdio.h" +#include "hal/hmac_hal.h" +#include "hal/hmac_ll.h" + +void hmac_hal_start(void) +{ + hmac_ll_wait_idle(); + hmac_ll_start(); +} + +uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id) +{ + hmac_ll_wait_idle(); + hmac_ll_config_output(config); + hmac_ll_config_hw_key_id(key_id); + hmac_ll_config_finish(); + hmac_ll_wait_idle(); + + uint32_t conf_error = hmac_ll_config_error(); + if (conf_error) { + hmac_ll_calc_finish(); + return 1; + } else if (config != HMAC_OUTPUT_USER) { + // In "downstream" mode, this will be the last hmac operation. Make sure HMAC is ready for + // the other peripheral. + hmac_ll_wait_idle(); + } + + return 0; +} + +void hmac_hal_write_one_block_512(const void *block) +{ + hmac_ll_wait_idle(); + hmac_ll_write_block_512(block); + hmac_ll_wait_idle(); + hmac_ll_msg_one_block(); +} + +void hmac_hal_write_block_512(const void *block) +{ + hmac_ll_wait_idle(); + hmac_ll_write_block_512(block); +} + +void hmac_hal_next_block_padding(void) +{ + hmac_ll_wait_idle(); + hmac_ll_msg_padding(); +} + +void hmac_hal_next_block_normal(void) +{ + hmac_ll_wait_idle(); + hmac_ll_msg_continue(); +} + +void hmac_hal_read_result_256(void *result) +{ + hmac_ll_wait_idle(); + hmac_ll_read_result_256(result); + hmac_ll_calc_finish(); +} + +void hmac_hal_clean(void) +{ + hmac_ll_wait_idle(); + hmac_ll_clean(); +} diff --git a/components/hal/esp32h2/include/hal/adc_hal.h b/components/hal/esp32h2/include/hal/adc_hal.h new file mode 100644 index 0000000000..9993f9e8d9 --- /dev/null +++ b/components/hal/esp32h2/include/hal/adc_hal.h @@ -0,0 +1,119 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The HAL layer for ADC (esp32s2 specific part) + +#pragma once + +#include "hal/adc_ll.h" +#include "hal/adc_types.h" + +#include_next "hal/adc_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ +/** + * Digital controller deinitialization. + */ +void adc_hal_digi_deinit(void); + +/** + * Setting the digital controller. + * + * @param cfg Pointer to digital controller paramter. + */ +void adc_hal_digi_controller_config(const adc_digi_config_t *cfg); + +/** + * Reset adc digital controller filter. + * + * @param filter_idx ADC filter unit. + */ +#define adc_hal_digi_filter_reset(filter_idx) adc_ll_digi_filter_reset(filter_idx) + +/** + * Set adc digital controller filter factor. + * + * @param filter_idx ADC filter unit. + * @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +void adc_hal_digi_filter_set_factor(adc_digi_filter_idx_t filter_idx, adc_digi_filter_t *filter); + +/** + * Get adc digital controller filter factor. + * + * @param filter_idx ADC filter unit. + * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +void adc_hal_digi_filter_get_factor(adc_digi_filter_idx_t filter_idx, adc_digi_filter_t *filter); + +/** + * Enable/disable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @note The filter will filter all the enabled channel data of the each ADC unit at the same time. + * @param filter_idx ADC filter unit. + * @param enable True to enable the filter, otherwise disable. + */ +void adc_hal_digi_filter_enable(adc_digi_filter_idx_t filter_idx, bool enable); + +/** + * Config monitor of adc digital controller. + * + * @note If the channel info is not supported, the monitor function will not be enabled. + * @param mon_idx ADC monitor index. + * @param config Refer to `adc_digi_monitor_t`. + */ +void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t mon_idx, adc_digi_monitor_t *config); + +/** + * Enable/disable monitor of adc digital controller. + * + * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. + * @param mon_idx ADC monitor index. + * @param enable True to enable the monitor, otherwise disable. + */ +void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable); + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ + +/** + * Config ADC2 module arbiter. + * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, + * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data. + * + * @note Only ADC2 support arbiter. + * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. + * @note Default priority: Wi-Fi > RTC > Digital; + * + * @param config Refer to `adc_arbiter_t`. + */ +void adc_hal_arbiter_config(adc_arbiter_t *config); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/adc_hal_conf.h b/components/hal/esp32h2/include/hal/adc_hal_conf.h new file mode 100644 index 0000000000..02e43632d2 --- /dev/null +++ b/components/hal/esp32h2/include/hal/adc_hal_conf.h @@ -0,0 +1,31 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_ADC1_DATA_INVERT_DEFAULT (0) +#define SOC_ADC2_DATA_INVERT_DEFAULT (0) + +#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) + +#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) +#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) +#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) +#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) + +#define SOC_ADC_PWDET_CCT_DEFAULT (4) + +#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1) + +#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1) diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h new file mode 100644 index 0000000000..a2fd21f2b5 --- /dev/null +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -0,0 +1,801 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include "regi2c_ctrl.h" +#include "esp_attr.h" + +#include "soc/adc_periph.h" +#include "hal/adc_types.h" +#include "soc/apb_saradc_struct.h" +#include "soc/apb_saradc_reg.h" +#include "soc/rtc_cntl_struct.h" +#include "soc/rtc_cntl_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 +#define ADC_LL_CLKM_DIV_B_DEFAULT 1 +#define ADC_LL_CLKM_DIV_A_DEFAULT 0 + +typedef enum { + ADC_NUM_1 = 0, /*!< SAR ADC 1 */ + ADC_NUM_2 = 1, /*!< SAR ADC 2 */ + ADC_NUM_MAX, +} adc_ll_num_t; + +typedef enum { + ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */ + ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */ + ADC_POWER_SW_OFF, /*!< ADC XPD controled by SW. power off. */ + ADC_POWER_MAX, /*!< For parameter check. */ +} adc_ll_power_t; + +typedef enum { + ADC_RTC_DATA_OK = 0, + ADC_RTC_CTRL_UNSELECTED = 1, + ADC_RTC_CTRL_BREAK = 2, + ADC_RTC_DATA_FAIL = -1, +} adc_ll_rtc_raw_data_t; + +//These values should be set according to the HW +typedef enum { + ADC_LL_INTR_THRES1_LOW = BIT(26), + ADC_LL_INTR_THRES0_LOW = BIT(27), + ADC_LL_INTR_THRES1_HIGH = BIT(28), + ADC_LL_INTR_THRES0_HIGH = BIT(29), + ADC_LL_INTR_ADC2_DONE = BIT(30), + ADC_LL_INTR_ADC1_DONE = BIT(31), +} adc_ll_intr_t; +FLAG_ATTR(adc_ll_intr_t) + +/** + * @brief ADC controller type selection. + * + * @note For ADC2, use the force option with care. The system power consumption detection will use ADC2. + * If it is forced to switch to another controller, it may cause the system to obtain incorrect values. + * @note Normally, there is no need to switch the controller manually. + */ +typedef enum { + ADC_CTRL_RTC = 0, /*!> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back +} + +/** + * Reset the pattern table pointer, then take the measurement rule from table header in next measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) +{ + APB_SARADC.ctrl.sar_patt_p_clear = 1; + APB_SARADC.ctrl.sar_patt_p_clear = 0; +} + +/** + * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. + * + * @note Only ADC2 have arbiter function. + * @param cycle range: 0 ~ 4. + */ +static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) +{ + APB_SARADC.ctrl.wait_arb_cycle = cycle; +} + +/** + * ADC Digital controller output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) +{ + if (adc_n == ADC_NUM_1) { + APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert + } else { // adc_n == ADC_NUM_2 + APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert + } +} + +/** + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. + * + * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. + */ +static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) +{ + APB_SARADC.ctrl2.timer_target = cycle; +} + +/** + * Enable digital controller timer to trigger the measurement. + */ +static inline void adc_ll_digi_trigger_enable(void) +{ + APB_SARADC.ctrl2.timer_en = 1; +} + +/** + * Disable digital controller timer to trigger the measurement. + */ +static inline void adc_ll_digi_trigger_disable(void) +{ + APB_SARADC.ctrl2.timer_en = 0; +} + +/** + * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. + * Expression: controller_clk = APLL/APB * (div_num + div_b / div_a). + * + * @param div_num Division factor. Range: 1 ~ 255. + * @param div_b Division factor. Range: 1 ~ 63. + * @param div_a Division factor. Range: 0 ~ 63. + */ +static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) +{ + APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num; + APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b; + APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a; +} + +/** + * Enable clock and select clock source for ADC digital controller. + * + * @param use_apll true: use APLL clock; false: use APB clock. + */ +static inline void adc_ll_digi_controller_clk_enable(bool use_apll) +{ + if (use_apll) { + APB_SARADC.apb_adc_clkm_conf.clk_sel = 1; // APLL clock + } else { + APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; // APB clock + } + APB_SARADC.ctrl.sar_clk_gated = 1; +} + +/** + * Disable clock for ADC digital controller. + */ +static inline void adc_ll_digi_controller_clk_disable(void) +{ + APB_SARADC.ctrl.sar_clk_gated = 0; +} + +/** + * Reset adc digital controller filter. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) +{ + APB_SARADC.filter_ctrl0.filter_reset = 1; +} + +/** + * Set adc digital controller filter factor. + * + * @note If the channel info is not supported, the filter function will not be enabled. + * @param idx ADC filter unit. + * @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) +{ + if (idx == ADC_DIGI_FILTER_IDX0) { + APB_SARADC.filter_ctrl0.filter_channel0 = (filter->adc_unit << 3) | (filter->channel & 0x7); + APB_SARADC.filter_ctrl1.filter_factor0 = filter->mode; + } else if (idx == ADC_DIGI_FILTER_IDX1) { + APB_SARADC.filter_ctrl0.filter_channel1 = (filter->adc_unit << 3) | (filter->channel & 0x7); + APB_SARADC.filter_ctrl1.filter_factor1 = filter->mode; + } +} + +/** + * Get adc digital controller filter factor. + * + * @param adc_n ADC unit. + * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) +{ + if (idx == ADC_DIGI_FILTER_IDX0) { + filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel0 >> 3) & 0x1; + filter->channel = APB_SARADC.filter_ctrl0.filter_channel0 & 0x7; + filter->mode = APB_SARADC.filter_ctrl1.filter_factor0; + } else if (idx == ADC_DIGI_FILTER_IDX1) { + filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel1 >> 3) & 0x1; + filter->channel = APB_SARADC.filter_ctrl0.filter_channel1 & 0x7; + filter->mode = APB_SARADC.filter_ctrl1.filter_factor1; + } +} + +/** + * Disable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @note If the channel info is not supported, the filter function will not be enabled. + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx) +{ + if (idx == ADC_DIGI_FILTER_IDX0) { + APB_SARADC.filter_ctrl0.filter_channel0 = 0xF; + APB_SARADC.filter_ctrl1.filter_factor0 = 0; + } else if (idx == ADC_DIGI_FILTER_IDX1) { + APB_SARADC.filter_ctrl0.filter_channel1 = 0xF; + APB_SARADC.filter_ctrl1.filter_factor1 = 0; + } +} + +/** + * Set monitor mode of adc digital controller. + * + * @note If the channel info is not supported, the monitor function will not be enabled. + * @param adc_n ADC unit. + * @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt. + * false: If ADC_OUT < threshold, Generates monitor interrupt. + */ +static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg) +{ + if (idx == ADC_DIGI_MONITOR_IDX0) { + APB_SARADC.thres0_ctrl.thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + APB_SARADC.thres0_ctrl.thres0_high = cfg->h_threshold; + APB_SARADC.thres0_ctrl.thres0_low = cfg->l_threshold; + } else { // ADC_DIGI_MONITOR_IDX1 + APB_SARADC.thres1_ctrl.thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + APB_SARADC.thres1_ctrl.thres1_high = cfg->h_threshold; + APB_SARADC.thres1_ctrl.thres1_low = cfg->l_threshold; + } +} + +/** + * Enable/disable monitor of adc digital controller. + * + * @note If the channel info is not supported, the monitor function will not be enabled. + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) +{ + if (idx == ADC_DIGI_MONITOR_IDX0) { + APB_SARADC.thres0_ctrl.thres0_channel = 0xF; + } else { // ADC_DIGI_MONITOR_IDX1 + APB_SARADC.thres1_ctrl.thres1_channel = 0xF; + } +} + +/** + * Set DMA eof num of adc digital controller. + * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated. + * + * @param num eof num of DMA. + */ +static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) +{ + APB_SARADC.dma_conf.apb_adc_eof_num = num; +} + +/** + * Enable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_enable(void) +{ + APB_SARADC.dma_conf.apb_adc_trans = 1; +} + +/** + * Disable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_disable(void) +{ + APB_SARADC.dma_conf.apb_adc_trans = 0; +} + +/** + * Reset adc digital controller. + */ +static inline void adc_ll_digi_reset(void) +{ + APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; + APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; +} + +/*--------------------------------------------------------------- + PWDET(Power detect) controller setting +---------------------------------------------------------------*/ +/** + * Set adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @param cct Range: 0 ~ 7. + */ +static inline void adc_ll_pwdet_set_cct(uint32_t cct) +{ + /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ + RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; +} + +/** + * Get adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @return cct Range: 0 ~ 7. + */ +static inline uint32_t adc_ll_pwdet_get_cct(void) +{ + /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ + return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; +} + +/** + * Analyze whether the obtained raw data is correct. + * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. + * + * @param adc_n ADC unit. + * @param raw_data ADC raw data input (convert value). + * @return + * - 0: The data is correct to use. + * - -1: The data is invalid. + */ +static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data) +{ + if (adc_n == ADC_NUM_1) { + return ADC_RTC_DATA_OK; + } + + //The raw data API returns value without channel information. Read value directly from the register + if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) { + return ADC_RTC_DATA_FAIL; + } + + return ADC_RTC_DATA_OK; +} + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ +/** + * Set ADC module power management. + * + * @param manage Set ADC power status. + */ +static inline void adc_ll_set_power_manage(adc_ll_power_t manage) +{ + // /* Bit1 0:Fsm 1: SW mode + // Bit0 0:SW mode power down 1: SW mode power on */ + if (manage == ADC_POWER_SW_ON) { + APB_SARADC.ctrl.sar_clk_gated = 1; + APB_SARADC.ctrl.xpd_sar_force = 3; + } else if (manage == ADC_POWER_BY_FSM) { + APB_SARADC.ctrl.sar_clk_gated = 1; + APB_SARADC.ctrl.xpd_sar_force = 0; + } else if (manage == ADC_POWER_SW_OFF) { + APB_SARADC.ctrl.xpd_sar_force = 2; + APB_SARADC.ctrl.sar_clk_gated = 0; + } +} + +/** + * Get ADC module power management. + * + * @return + * - ADC power status. + */ +static inline adc_ll_power_t adc_ll_get_power_manage(void) +{ + /* Bit1 0:Fsm 1: SW mode + Bit0 0:SW mode power down 1: SW mode power on */ + adc_ll_power_t manage; + if (APB_SARADC.ctrl.xpd_sar_force == 3) { + manage = ADC_POWER_SW_ON; + } else if (APB_SARADC.ctrl.xpd_sar_force == 2) { + manage = ADC_POWER_SW_OFF; + } else { + manage = ADC_POWER_BY_FSM; + } + return manage; +} + +/** + * Set ADC2 module arbiter work mode. + * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, + * the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data. + * + * @note Only ADC2 support arbiter. + * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. + * + * @param mode Refer to `adc_arbiter_mode_t`. + */ +static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode) +{ + if (mode == ADC_ARB_MODE_FIX) { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1; + } else if (mode == ADC_ARB_MODE_LOOP) { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0; + } else { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter. + } +} + +/** + * Set ADC2 module controller priority in arbiter. + * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, + * the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data. + * + * @note Only ADC2 support arbiter. + * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. + * @note Default priority: Wi-Fi(2) > RTC(1) > Digital(0); + * + * @param pri_rtc RTC controller priority. Range: 0 ~ 2. + * @param pri_dig Digital controller priority. Range: 0 ~ 2. + * @param pri_pwdet Wi-Fi controller priority. Range: 0 ~ 2. + */ +static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, uint8_t pri_pwdet) +{ + if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet; + } + /* Should select highest priority controller. */ + if (pri_rtc > pri_dig) { + if (pri_rtc > pri_pwdet) { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 1; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; + } else { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; + } + } else { + if (pri_dig > pri_pwdet) { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 1; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; + } else { + APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; + APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; + } + } +} + +/* ADC calibration code. */ +/** + * @brief Set common calibration configuration. Should be shared with other parts (PWDET). + */ +static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) +{ + if (adc_n == ADC_NUM_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); + } +} + +/** + * Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + * @param channel adc channel number. + * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. + * false: Use IO external voltage as calibration voltage. + */ +static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) +{ + /* Enable/disable internal connect GND (for calibration). */ + if (adc_n == ADC_NUM_1) { + if (internal_gnd) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + } + } else { + if (internal_gnd) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); + } + } +} + +/** + * Resume register status after calibration. + * + * @param adc_n ADC index number. + */ +static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) +{ + if (adc_n == ADC_NUM_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); + } +} + +/** + * Set the calibration result to ADC. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + */ +static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) +{ + uint8_t msb = param >> 8; + uint8_t lsb = param & 0xFF; + if (adc_n == ADC_NUM_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); + } +} +/* Temp code end. */ + +/** + * Output ADCn inter reference voltage to ADC2 channels. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC1's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @param[in] adc ADC unit select + * @param[in] channel ADC1 channel number + * @param[in] en Enable/disable the reference voltage output + */ +static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) +{ + if (en) { + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); + SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); + + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF; + APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF; + APB_SARADC.onetime_sample.adc1_onetime_sample = 1; + APB_SARADC.onetime_sample.onetime_channel = channel; + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); + if (adc == ADC_NUM_1) { + /* Config test mux to route v_ref to ADC1 Channels */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); + } else { + /* Config test mux to route v_ref to ADC2 Channels */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + } + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + APB_SARADC.onetime_sample.adc1_onetime_sample = 0; + APB_SARADC.onetime_sample.onetime_channel = 0xf; + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + } +} + +/*--------------------------------------------------------------- + Single Read +---------------------------------------------------------------*/ +/** + * Trigger single read + * + * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle, + * otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow. + * This hardware limitation will be removed in future versions. + */ +static inline void adc_ll_onetime_start(bool val) +{ + APB_SARADC.onetime_sample.onetime_start = val; +} + +static inline void adc_ll_onetime_set_channel(adc_ll_num_t unit, adc_channel_t channel) +{ + APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel); +} + +static inline void adc_ll_onetime_set_atten(adc_atten_t atten) +{ + APB_SARADC.onetime_sample.onetime_atten = atten; +} + +static inline void adc_ll_intr_enable(adc_ll_intr_t mask) +{ + APB_SARADC.int_ena.val |= mask; +} + +static inline void adc_ll_intr_disable(adc_ll_intr_t mask) +{ + APB_SARADC.int_ena.val &= ~mask; +} + +static inline void adc_ll_intr_clear(adc_ll_intr_t mask) +{ + APB_SARADC.int_clr.val |= mask; +} + +static inline bool adc_ll_intr_get_raw(adc_ll_intr_t mask) +{ + return (APB_SARADC.int_raw.val & mask); +} + +static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask) +{ + return (APB_SARADC.int_st.val & mask); +} + +static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable) +{ + if (adc_n == ADC_NUM_1) { + APB_SARADC.onetime_sample.adc1_onetime_sample = enable; + } else { + APB_SARADC.onetime_sample.adc2_onetime_sample = enable; + } +} + +static inline uint32_t adc_ll_adc1_read(void) +{ + //On ESP32C3, valid data width is 12-bit + return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff); +} + +static inline uint32_t adc_ll_adc2_read(void) +{ + //On ESP32C3, valid data width is 12-bit + return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/aes_ll.h b/components/hal/esp32h2/include/hal/aes_ll.h new file mode 100644 index 0000000000..0eb7fabc64 --- /dev/null +++ b/components/hal/esp32h2/include/hal/aes_ll.h @@ -0,0 +1,235 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "soc/hwcrypto_reg.h" +#include "hal/aes_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief State of AES accelerator, busy, idle or done + * + */ +typedef enum { + ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */ + ESP_AES_STATE_BUSY, /* Transform in progress */ + ESP_AES_STATE_DONE, /* Transform completed */ +} esp_aes_state_t; + + +/** + * @brief Write the encryption/decryption key to hardware + * + * @param key Key to be written to the AES hardware + * @param key_word_len Number of words in the key + * + * @return volatile number of bytes written to hardware, used for fault injection check + */ +static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len) +{ + /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ + volatile uint8_t key_in_hardware = 0; + uint32_t *key_words = (uint32_t *)key; + + for (int i = 0; i < key_word_len; i++) { + REG_WRITE(AES_KEY_BASE + i * 4, *(key_words + i)); + key_in_hardware += 4; + } + return key_in_hardware; +} + +/** + * @brief Sets the mode + * + * @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0 + * @param key_bytes Number of bytes in the key + */ +static inline void aes_ll_set_mode(int mode, uint8_t key_bytes) +{ + const uint32_t MODE_DECRYPT_BIT = 4; + unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; + + /* See TRM for the mapping between keylength and mode bit */ + REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); +} + +/** + * @brief Writes message block to AES hardware + * + * @param input Block to be written + */ +static inline void aes_ll_write_block(const void *input) +{ + const uint32_t *input_words = (const uint32_t *)input; + uint32_t i0, i1, i2, i3; + + /* Storing i0,i1,i2,i3 in registers, not in an array + helps a lot with optimisations at -Os level */ + i0 = input_words[0]; + REG_WRITE(AES_TEXT_IN_BASE, i0); + + i1 = input_words[1]; + REG_WRITE(AES_TEXT_IN_BASE + 4, i1); + + i2 = input_words[2]; + REG_WRITE(AES_TEXT_IN_BASE + 8, i2); + + i3 = input_words[3]; + REG_WRITE(AES_TEXT_IN_BASE + 12, i3); +} + +/** + * @brief Read the AES block + * + * @param output the output of the transform, length = AES_BLOCK_BYTES + */ +static inline void aes_ll_read_block(void *output) +{ + uint32_t *output_words = (uint32_t *)output; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < AES_BLOCK_WORDS; i++) { + output_words[i] = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); + } +} + +/** + * @brief Starts block transform + * + */ +static inline void aes_ll_start_transform(void) +{ + REG_WRITE(AES_TRIGGER_REG, 1); +} + + +/** + * @brief Read state of AES accelerator + * + * @return esp_aes_state_t + */ +static inline esp_aes_state_t aes_ll_get_state(void) +{ + return REG_READ(AES_STATE_REG); +} + + +/** + * @brief Set mode of operation + * + * @note Only used for DMA transforms + * + * @param mode + */ +static inline void aes_ll_set_block_mode(esp_aes_mode_t mode) +{ + REG_WRITE(AES_BLOCK_MODE_REG, mode); +} + +/** + * @brief Set AES-CTR counter to INC32 + * + * @note Only affects AES-CTR mode + * + */ +static inline void aes_ll_set_inc(void) +{ + REG_WRITE(AES_INC_SEL_REG, 0); +} + +/** + * @brief Release the DMA + * + */ +static inline void aes_ll_dma_exit(void) +{ + REG_WRITE(AES_DMA_EXIT_REG, 0); +} + +/** + * @brief Sets the number of blocks to be transformed + * + * @note Only used for DMA transforms + * + * @param num_blocks Number of blocks to transform + */ +static inline void aes_ll_set_num_blocks(size_t num_blocks) +{ + REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); +} + +/* + * Write IV to hardware iv registers + */ +static inline void aes_ll_set_iv(const uint8_t *iv) +{ + uint32_t *iv_words = (uint32_t *)iv; + uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE); + + for (int i = 0; i < IV_WORDS; i++ ) { + REG_WRITE(®_addr_buf[i], iv_words[i]); + } +} + +/* + * Read IV from hardware iv registers + */ +static inline void aes_ll_read_iv(uint8_t *iv) +{ + uint32_t *iv_words = (uint32_t *)iv; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < IV_WORDS; i++) { + iv_words[i] = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); + } +} + +/** + * @brief Enable or disable DMA mode + * + * @param enable true to enable, false to disable. + */ +static inline void aes_ll_dma_enable(bool enable) +{ + REG_WRITE(AES_DMA_ENABLE_REG, enable); +} + +/** + * @brief Enable or disable transform completed interrupt + * + * @param enable true to enable, false to disable. + */ +static inline void aes_ll_interrupt_enable(bool enable) +{ + REG_WRITE(AES_INT_ENA_REG, enable); +} + +/** + * @brief Clears the interrupt + * + */ +static inline void aes_ll_interrupt_clear(void) +{ + REG_WRITE(AES_INT_CLR_REG, 1); +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h new file mode 100644 index 0000000000..f7382650d5 --- /dev/null +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -0,0 +1,252 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/periph_defs.h" +#include "soc/system_reg.h" +#include "soc/syscon_reg.h" +#include "soc/dport_access.h" + +static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) +{ + switch (periph) { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_CLK_EN; + case PERIPH_RMT_MODULE: + return SYSTEM_RMT_CLK_EN; + case PERIPH_LEDC_MODULE: + return SYSTEM_LEDC_CLK_EN; + case PERIPH_UART0_MODULE: + return SYSTEM_UART_CLK_EN; + case PERIPH_UART1_MODULE: + return SYSTEM_UART1_CLK_EN; + case PERIPH_I2C0_MODULE: + return SYSTEM_I2C_EXT0_CLK_EN; + case PERIPH_I2S1_MODULE: + return SYSTEM_I2S1_CLK_EN; + case PERIPH_TIMG0_MODULE: + return SYSTEM_TIMERGROUP_CLK_EN; + case PERIPH_TIMG1_MODULE: + return SYSTEM_TIMERGROUP1_CLK_EN; + case PERIPH_UHCI0_MODULE: + return SYSTEM_UHCI0_CLK_EN; + case PERIPH_SYSTIMER_MODULE: + return SYSTEM_SYSTIMER_CLK_EN; + case PERIPH_SPI_MODULE: + return SYSTEM_SPI01_CLK_EN; + case PERIPH_SPI2_MODULE: + return SYSTEM_SPI2_CLK_EN; + case PERIPH_TWAI_MODULE: + return SYSTEM_TWAI_CLK_EN; + case PERIPH_GDMA_MODULE: + return SYSTEM_DMA_CLK_EN; + case PERIPH_AES_MODULE: + return SYSTEM_CRYPTO_AES_CLK_EN; + case PERIPH_SHA_MODULE: + return SYSTEM_CRYPTO_SHA_CLK_EN; + case PERIPH_RSA_MODULE: + return SYSTEM_CRYPTO_RSA_CLK_EN; + case PERIPH_HMAC_MODULE: + return SYSTEM_CRYPTO_HMAC_CLK_EN; + case PERIPH_DS_MODULE: + return SYSTEM_CRYPTO_DS_CLK_EN; + case PERIPH_RNG_MODULE: + return SYSTEM_WIFI_CLK_RNG_EN; + case PERIPH_WIFI_MODULE: + return SYSTEM_WIFI_CLK_WIFI_EN_M; + case PERIPH_BT_MODULE: + return SYSTEM_WIFI_CLK_BT_EN_M; + case PERIPH_WIFI_BT_COMMON_MODULE: + return SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M; + case PERIPH_BT_BASEBAND_MODULE: + return SYSTEM_BT_BASEBAND_EN; + case PERIPH_BT_LC_MODULE: + return SYSTEM_BT_LC_EN; + default: + return 0; + } +} + +static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable) +{ + + (void)enable; // unused + + switch (periph) { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_RST; + case PERIPH_RMT_MODULE: + return SYSTEM_RMT_RST; + case PERIPH_LEDC_MODULE: + return SYSTEM_LEDC_RST; + case PERIPH_UART0_MODULE: + return SYSTEM_UART_RST; + case PERIPH_UART1_MODULE: + return SYSTEM_UART1_RST; + case PERIPH_I2C0_MODULE: + return SYSTEM_I2C_EXT0_RST; + case PERIPH_I2S1_MODULE: + return SYSTEM_I2S1_RST; + case PERIPH_TIMG0_MODULE: + return SYSTEM_TIMERGROUP_RST; + case PERIPH_TIMG1_MODULE: + return SYSTEM_TIMERGROUP1_RST; + case PERIPH_UHCI0_MODULE: + return SYSTEM_UHCI0_RST; + case PERIPH_SYSTIMER_MODULE: + return SYSTEM_SYSTIMER_RST; + case PERIPH_GDMA_MODULE: + return SYSTEM_DMA_RST; + case PERIPH_SPI_MODULE: + return SYSTEM_SPI01_RST; + case PERIPH_SPI2_MODULE: + return SYSTEM_SPI2_RST; + case PERIPH_TWAI_MODULE: + return SYSTEM_TWAI_RST; + case PERIPH_HMAC_MODULE: + return SYSTEM_CRYPTO_HMAC_RST; + case PERIPH_AES_MODULE: + if (enable == true) { + // Clear reset on digital signature, otherwise AES unit is held in reset also. + return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST); + } else { + //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. + return SYSTEM_CRYPTO_AES_RST; + } + case PERIPH_SHA_MODULE: + if (enable == true) { + // Clear reset on digital signature and HMAC, otherwise SHA is held in reset + return (SYSTEM_CRYPTO_SHA_RST | SYSTEM_CRYPTO_DS_RST | SYSTEM_CRYPTO_HMAC_RST); + } else { + // Don't assert reset on secure boot, otherwise AES is held in reset + return SYSTEM_CRYPTO_SHA_RST; + } + case PERIPH_RSA_MODULE: + if (enable == true) { + /* also clear reset on digital signature, otherwise RSA is held in reset */ + return (SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_DS_RST); + } else { + /* don't reset digital signature unit, as this resets AES also */ + return SYSTEM_CRYPTO_RSA_RST; + } + case PERIPH_DS_MODULE: + return SYSTEM_CRYPTO_DS_RST; + default: + return 0; + } +} + +static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) +{ + switch (periph) { + case PERIPH_RNG_MODULE: + case PERIPH_WIFI_MODULE: + case PERIPH_BT_MODULE: + case PERIPH_WIFI_BT_COMMON_MODULE: + case PERIPH_BT_BASEBAND_MODULE: + case PERIPH_BT_LC_MODULE: + return SYSTEM_WIFI_CLK_EN_REG; + + case PERIPH_HMAC_MODULE: + case PERIPH_DS_MODULE: + case PERIPH_AES_MODULE: + case PERIPH_RSA_MODULE: + case PERIPH_SHA_MODULE: + case PERIPH_GDMA_MODULE: + return SYSTEM_PERIP_CLK_EN1_REG; + default: + return SYSTEM_PERIP_CLK_EN0_REG; + } +} + +static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) +{ + switch (periph) { + case PERIPH_RNG_MODULE: + case PERIPH_WIFI_MODULE: + case PERIPH_BT_MODULE: + case PERIPH_WIFI_BT_COMMON_MODULE: + case PERIPH_BT_BASEBAND_MODULE: + case PERIPH_BT_LC_MODULE: + return SYSTEM_WIFI_RST_EN_REG; + + case PERIPH_HMAC_MODULE: + case PERIPH_DS_MODULE: + case PERIPH_AES_MODULE: + case PERIPH_RSA_MODULE: + case PERIPH_SHA_MODULE: + case PERIPH_GDMA_MODULE: + return SYSTEM_PERIP_RST_EN1_REG; + default: + return SYSTEM_PERIP_RST_EN0_REG; + } +} + +static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph) +{ + DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); +} + +static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) +{ + DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +{ + DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +{ + DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void periph_ll_reset(periph_module_t periph) +{ + DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); +} + +static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) +{ + return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && + DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; +} + +static inline void periph_ll_wifi_module_enable_clk_clear_rst(void) +{ + DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); + DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void periph_ll_wifi_module_disable_clk_set_rst(void) +{ + DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); + DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/cpu_ll.h b/components/hal/esp32h2/include/hal/cpu_ll.h new file mode 100644 index 0000000000..4e9d449409 --- /dev/null +++ b/components/hal/esp32h2/include/hal/cpu_ll.h @@ -0,0 +1,161 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include + +#include "soc/soc_caps.h" +#include "esp_bit_defs.h" +#include "soc/assist_debug_reg.h" +#include "esp_attr.h" +#include "riscv/csr.h" + +/*performance counter*/ +#define CSR_PCER_MACHINE 0x7e0 +#define CSR_PCMR_MACHINE 0x7e1 +#define CSR_PCCR_MACHINE 0x7e2 + +#ifdef __cplusplus +extern "C" { +#endif + +static inline int IRAM_ATTR cpu_ll_get_core_id(void) +{ +#if SOC_CPU_CORES_NUM == 1 + return 0; // No need to check core ID on single core hardware +#else + int cpuid; + cpuid = RV_READ_CSR(mhartid); + return cpuid; +#endif +} + +static inline void cpu_ll_enable_cycle_count(void) +{ + RV_WRITE_CSR(CSR_PCER_MACHINE,1); + RV_WRITE_CSR(CSR_PCMR_MACHINE,1); + return; +} + +static inline uint32_t IRAM_ATTR cpu_ll_get_cycle_count(void) +{ + uint32_t result; + result = RV_READ_CSR(CSR_PCCR_MACHINE); + return result; +} + +static inline void IRAM_ATTR cpu_ll_set_cycle_count(uint32_t val) +{ + RV_WRITE_CSR(CSR_PCCR_MACHINE, val); +} + +static inline void* cpu_ll_get_sp(void) +{ + void *sp; + asm volatile ("mv %0, sp;" : "=r" (sp)); + return sp; +} + +static inline void cpu_ll_init_hwloop(void) +{ + // Nothing needed here for ESP32-C3 +} + +static inline void cpu_ll_set_breakpoint(int id, uint32_t pc) +{ + RV_WRITE_CSR(tselect,id); + RV_SET_CSR(CSR_TCONTROL,TCONTROL_MTE); + RV_SET_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE|TDATA1_EXECUTE); + RV_WRITE_CSR(tdata2,pc); + return; +} + +static inline void cpu_ll_clear_breakpoint(int id) +{ + RV_WRITE_CSR(tselect,id); + RV_CLEAR_CSR(CSR_TCONTROL,TCONTROL_MTE); + RV_CLEAR_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE|TDATA1_EXECUTE); + return; +} + +static inline uint32_t cpu_ll_ptr_to_pc(const void* addr) +{ + return ((uint32_t) addr); +} + +static inline void* cpu_ll_pc_to_ptr(uint32_t pc) +{ + return (void*) ((pc & 0x3fffffff) | 0x40000000); +} + +static inline void cpu_ll_set_watchpoint(int id, + const void* addr, + size_t size, + bool on_read, + bool on_write) +{ + uint32_t addr_napot; + RV_WRITE_CSR(tselect,id); + RV_SET_CSR(CSR_TCONTROL, TCONTROL_MPTE | TCONTROL_MTE); + RV_SET_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE); + RV_SET_CSR_FIELD(CSR_TDATA1, TDATA1_MATCH, 1); + // add 0 in napot encoding + addr_napot = ((uint32_t) addr) | ((size >> 1) - 1); + if (on_read) { + RV_SET_CSR(CSR_TDATA1, TDATA1_LOAD); + } + if (on_write) { + RV_SET_CSR(CSR_TDATA1, TDATA1_STORE); + } + RV_WRITE_CSR(tdata2,addr_napot); + return; +} + +static inline void cpu_ll_clear_watchpoint(int id) +{ + RV_WRITE_CSR(tselect,id); + RV_CLEAR_CSR(CSR_TCONTROL,TCONTROL_MTE); + RV_CLEAR_CSR(CSR_TDATA1, TDATA1_USER|TDATA1_MACHINE); + RV_CLEAR_CSR_FIELD(CSR_TDATA1,TDATA1_MATCH); + RV_CLEAR_CSR(CSR_TDATA1, TDATA1_MACHINE); + RV_CLEAR_CSR(CSR_TDATA1, TDATA1_LOAD|TDATA1_STORE|TDATA1_EXECUTE); + return; +} + +FORCE_INLINE_ATTR bool cpu_ll_is_debugger_attached(void) +{ + return REG_GET_BIT(ASSIST_DEBUG_C0RE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); +} + +static inline void cpu_ll_break(void) +{ + asm volatile("ebreak\n"); + return; +} + +static inline void cpu_ll_set_vecbase(const void* vecbase) +{ + uintptr_t vecbase_int = (uintptr_t)vecbase; + vecbase_int |= 1; // Set MODE field to treat MTVEC as a vector base address + RV_WRITE_CSR(mtvec, vecbase_int); +} + +static inline void cpu_ll_waiti(void) +{ + asm volatile ("wfi\n"); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/ds_ll.h b/components/hal/esp32h2/include/hal/ds_ll.h new file mode 100644 index 0000000000..fd98de367f --- /dev/null +++ b/components/hal/esp32h2/include/hal/ds_ll.h @@ -0,0 +1,175 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use it in application code. + ******************************************************************************/ + +#pragma once + +#include +#include +#include + +#include "soc/hwcrypto_reg.h" +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void ds_ll_start(void) +{ + REG_WRITE(DS_SET_START_REG, 1); +} + +/** + * @brief Wait until DS peripheral has finished any outstanding operation. + */ +static inline bool ds_ll_busy(void) +{ + return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; +} + +/** + * @brief Busy wait until the hardware is ready. + */ +static inline void ds_ll_wait_busy(void) +{ + while (ds_ll_busy()); +} + +/** + * @brief In case of a key error, check what caused it. + */ +static inline ds_key_check_t ds_ll_key_error_source(void) +{ + uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); + if (key_error == 0) { + return DS_NO_KEY_INPUT; + } else { + return DS_OTHER_WRONG; + } +} + +/** + * @brief Write the initialization vector to the corresponding register field. + */ +static inline void ds_ll_configure_iv(const uint32_t *iv) +{ + for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) { + REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]); + } +} + +/** + * @brief Write the message which should be signed. + * + * @param msg Pointer to the message. + * @param size Length of msg in bytes. It is the RSA signature length in bytes. + */ +static inline void ds_ll_write_message(const uint8_t *msg, size_t size) +{ + memcpy((uint8_t*) DS_X_BASE, msg, size); + asm volatile ("fence"); +} + +/** + * @brief Write the encrypted private key parameters. + */ +static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_params) +{ + /* Note: as the internal peripheral still has RSA 4096 structure, + but C is encrypted based on the actual max RSA length (ETS_DS_MAX_BITS), need to fragment it + when copying to hardware... + + (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment) + */ + typedef struct { uint32_t addr; size_t len; } frag_t; + const frag_t frags[] = { + {DS_C_Y_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, + {DS_C_M_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, + {DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, + {DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE}, + }; + const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t); + const uint8_t *from = encrypted_key_params; + + for (int i = 0; i < NUM_FRAGS; i++) { + memcpy((uint8_t *)frags[i].addr, from, frags[i].len); + asm volatile ("fence"); + from += frags[i].len; + } +} + +/** + * @brief Begin signing procedure. + */ +static inline void ds_ll_start_sign(void) +{ + REG_WRITE(DS_SET_ME_REG, 1); +} + +/** + * @brief check the calculated signature. + * + * @return + * - DS_SIGNATURE_OK if no issue is detected with the signature. + * - DS_SIGNATURE_PADDING_FAIL if the padding of the private key parameters is wrong. + * - DS_SIGNATURE_MD_FAIL if the message digest check failed. This means that the message digest calculated using + * the private key parameters fails, i.e., the integrity of the private key parameters is not protected. + * - DS_SIGNATURE_PADDING_AND_MD_FAIL if both padding and message digest check fail. + */ +static inline ds_signature_check_t ds_ll_check_signature(void) +{ + uint32_t result = REG_READ(DS_QUERY_CHECK_REG); + switch(result) { + case 0: + return DS_SIGNATURE_OK; + case 1: + return DS_SIGNATURE_MD_FAIL; + case 2: + return DS_SIGNATURE_PADDING_FAIL; + default: + return DS_SIGNATURE_PADDING_AND_MD_FAIL; + } +} + +/** + * @brief Read the signature from the hardware. + * + * @param result The signature result. + * @param size Length of signature result in bytes. It is the RSA signature length in bytes. + */ +static inline void ds_ll_read_result(uint8_t *result, size_t size) +{ + memcpy(result, (uint8_t*) DS_Z_BASE, size); + asm volatile ("fence"); +} + +/** + * @brief Exit the signature operation. + * + * @note This does not deactivate the module. Corresponding clock/reset bits have to be triggered for deactivation. + */ +static inline void ds_ll_finish(void) +{ + REG_WRITE(DS_SET_FINISH_REG, 1); + ds_ll_wait_busy(); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/gdma_ll.h b/components/hal/esp32h2/include/hal/gdma_ll.h new file mode 100644 index 0000000000..6ce2f89f66 --- /dev/null +++ b/components/hal/esp32h2/include/hal/gdma_ll.h @@ -0,0 +1,456 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include "soc/gdma_struct.h" +#include "soc/gdma_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) + +#define GDMA_LL_RX_EVENT_MASK (0x06A7) +#define GDMA_LL_TX_EVENT_MASK (0x1958) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<10) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<9) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<8) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<7) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<6) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<5) +#define GDMA_LL_EVENT_TX_EOF (1<<4) +#define GDMA_LL_EVENT_TX_DONE (1<<3) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +///////////////////////////////////// Common ///////////////////////////////////////// +/** + * @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default + */ +static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.mem_trans_en = enable; + if (enable) { + // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value + dev->channel[channel].in.in_peri_sel.sel = 0; + dev->channel[channel].out.out_peri_sel.sel = 0; + } +} + +/** + * @brief Enable DMA clock gating + */ +static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable) +{ + dev->misc_conf.clk_en = enable; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +{ + return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); + } else { + dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf1.in_check_owner = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, disabled by default + */ +static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_data_burst_en = enable; +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.indscr_burst_en = enable; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_conf0.in_rst = 1; + dev->channel[channel].in.in_conf0.in_rst = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.infifo_cnt; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_pop.infifo_pop = 1; + return dev->channel[channel].in.in_pop.infifo_rdata; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].in.in_link.addr = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.start = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.stop = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.restart = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_link.auto_ret = enable; +} + +/** + * @brief Check if DMA RX FSM is in IDLE state + */ +static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_link.park; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_suc_eof_des_addr; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_err_eof_des_addr; +} + +/** + * @brief Get current RX descriptor's address + */ +static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_dscr; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].in.in_pri.rx_pri = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) +{ + dev->channel[channel].in.in_peri_sel.sel = periph_id; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +{ + return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK); + } else { + dev->intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK); + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK); +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf1.out_check_owner = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, disabled by default + */ +static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_data_burst_en = enable; +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.outdscr_burst_en = enable; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + dev->channel[channel].out.out_conf0.out_eof_mode = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_auto_wrback = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_conf0.out_rst = 1; + dev->channel[channel].out.out_conf0.out_rst = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.outfifo_cnt; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) +{ + dev->channel[channel].out.out_push.outfifo_wdata = data; + dev->channel[channel].out.out_push.outfifo_push = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].out.out_link.addr = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.start = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.stop = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.restart = 1; +} + +/** + * @brief Check if DMA TX FSM is in IDLE state + */ +static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_link.park; +} + +/** + * @brief Get TX EOF descriptor's address + */ +static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_eof_des_addr; +} + +/** + * @brief Get current TX descriptor's address + */ +static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_dscr; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].out.out_pri.tx_pri = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) +{ + dev->channel[channel].out.out_peri_sel.sel = periph_id; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h new file mode 100644 index 0000000000..6ba4d601b9 --- /dev/null +++ b/components/hal/esp32h2/include/hal/gpio_ll.h @@ -0,0 +1,586 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-C3 GPIO register operations + +#pragma once + +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "soc/rtc_cntl_reg.h" +#include "hal/gpio_types.h" +#include "stdlib.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The following defines are used to disable USB JTAG when pins 18 and pins 19 + * are set to be used as GPIO. + * See gpio_pad_select_gpio() below. + * + * TODO: Delete these definitions once the USB device registers definition is + * merged. + */ +#define USB_DEVICE_CONF0_REG (0x60043018) +#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) + +// Get GPIO hardware instance with giving gpio num +#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) + +#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) +/** + * @brief Enable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Disable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Enable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief Disable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief GPIO set interrupt trigger type + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; +} + +/** + * @brief Get GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status + */ +static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = hw->pcpu_int.intr; +} + +/** + * @brief Get GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status high + */ +static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = 0; // Less than 32 GPIOs in ESP32-C3 +} + +/** + * @brief Clear GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status clear mask + */ +static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) +{ + hw->status_w1tc.status_w1tc = mask; +} + +/** + * @brief Clear GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status high clear mask + */ +static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) +{ + // Not supported on C3 +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id Interrupt enabled CPU to corresponding ID + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num) +{ + if (core_id == 0) { + GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr + } else { + // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr + } +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].int_ena = 0; //disable GPIO intr +} + +/** + * @brief Disable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); + // Ensure no other output signal is routed via GPIO matrix to this pin + REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), + SIG_GPIO_OUT_IDX); +} + +/** + * @brief Enable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); +} + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 0; +} + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 1; +} + +/** + * @brief GPIO set output level + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level) +{ + if (level) { + hw->out_w1ts.out_w1ts = (1 << gpio_num); + } else { + hw->out_w1tc.out_w1tc = (1 << gpio_num); + } +} + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + return (hw->in.data >> gpio_num) & 0x1; +} + +/** + * @brief Enable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; + hw->pin[gpio_num].wakeup_enable = 0x1; +} + +/** + * @brief Disable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].wakeup_enable = 0; +} + +/** + * @brief Set GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength) +{ + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); +} + +/** + * @brief Get GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength) +{ + *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); +} + +/** + * @brief Enable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Disable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); +} + +/** + * @brief Enable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num <= GPIO_NUM_5) { + REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); + } else { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); + } +} + +/** + * @brief Disable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num <= GPIO_NUM_5) { + REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); + } +} + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) +{ + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); +} + +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { + CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(pin_name, func); +} + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) +{ + hw->func_out_sel_cfg[gpio_num].oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); +} + +static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); +} + +static inline void gpio_ll_force_unhold_all(void) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); +} + +/** + * @brief Enable GPIO pin used for wakeup from sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pin used for wakeup from sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO deep-sleep wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + if (gpio_num > GPIO_NUM_5) { + abort(); // gpio lager than 5 doesn't support. + } + REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); + REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); + SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); + uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG); + reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3))); + reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3)); + REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg); +} + +/** + * @brief Disable GPIO deep-sleep wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num > GPIO_NUM_5) { + abort(); // gpio lager than 5 doesn't support. + } + CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); + CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h new file mode 100644 index 0000000000..f80fc83b26 --- /dev/null +++ b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h @@ -0,0 +1,394 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include +#include "soc/spi_periph.h" +#include "hal/spi_types.h" +#include "hal/spi_flash_types.h" +#include // For MIN/MAX +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//NOTE: These macros are changed on c3 for build. MODIFY these when bringup flash. +#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) ) +#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 ) + +typedef typeof(GPSPI2.clock) gpspi_flash_ll_clock_reg_t; + +//Supported clock register values +#define GPSPI_FLASH_LL_CLKREG_VAL_5MHZ ((gpspi_flash_ll_clock_reg_t){.val=0x0000F1CF}) ///< Clock set to 5 MHz +#define GPSPI_FLASH_LL_CLKREG_VAL_10MHZ ((gpspi_flash_ll_clock_reg_t){.val=0x000070C7}) ///< Clock set to 10 MHz +#define GPSPI_FLASH_LL_CLKREG_VAL_20MHZ ((gpspi_flash_ll_clock_reg_t){.val=0x00003043}) ///< Clock set to 20 MHz +#define GPSPI_FLASH_LL_CLKREG_VAL_26MHZ ((gpspi_flash_ll_clock_reg_t){.val=0x00002002}) ///< Clock set to 26 MHz +#define GPSPI_FLASH_LL_CLKREG_VAL_40MHZ ((gpspi_flash_ll_clock_reg_t){.val=0x00001001}) ///< Clock set to 40 MHz +#define GPSPI_FLASH_LL_CLKREG_VAL_80MHZ ((gpspi_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Reset peripheral registers before configuration and starting control + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_reset(spi_dev_t *dev) +{ + dev->user.val = 0; + dev->ctrl.val = 0; + + dev->clk_gate.clk_en = 1; + dev->clk_gate.mst_clk_active = 1; + dev->clk_gate.mst_clk_sel = 1; + + dev->dma_conf.val = 0; + dev->dma_conf.tx_seg_trans_clr_en = 1; + dev->dma_conf.rx_seg_trans_clr_en = 1; + dev->dma_conf.dma_seg_trans_en = 0; +} + +/** + * Check whether the previous operation is done. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if last command is done, otherwise false. + */ +static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev) +{ + return (dev->cmd.usr == 0); +} + +/** + * Get the read data from the buffer after ``gpspi_flash_ll_read`` is done. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer to hold the output data + * @param read_len Length to get out of the buffer + */ +static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len) +{ + if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { + // If everything is word-aligned, do a faster memcpy + memcpy(buffer, (void *)dev->data_buf, read_len); + } else { + // Otherwise, slow(er) path copies word by word + int copy_len = read_len; + for (int i = 0; i < (read_len + 3) / 4; i++) { + int word_len = MIN(sizeof(uint32_t), copy_len); + uint32_t word = dev->data_buf[i]; + memcpy(buffer, &word, word_len); + buffer = (void *)((intptr_t)buffer + word_len); + copy_len -= word_len; + } + } +} + +/** + * Write a word to the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param word Data to write at address 0. + */ +static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word) +{ + dev->data_buf[0] = word; +} + +/** + * Set the data to be written in the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data + * @param length Length of data in bytes. + */ +static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) +{ + // Load data registers, word at a time + int num_words = (length + 3) / 4; + for (int i = 0; i < num_words; i++) { + uint32_t word = 0; + uint32_t word_len = MIN(length, sizeof(word)); + memcpy(&word, buffer, word_len); + dev->data_buf[i] = word; + length -= word_len; + buffer = (void *)((intptr_t)buffer + word_len); + } +} + +/** + * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, + * should be configured before this is called. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_user_start(spi_dev_t *dev) +{ + dev->ctrl.hold_pol = 1; + dev->cmd.update = 1; + while (dev->cmd.update); + dev->cmd.usr = 1; +} + +/** + * Check whether the host is idle to perform new commands. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if the host is idle, otherwise false + */ +static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) +{ + return dev->cmd.usr == 0; +} + +/** + * Set phases for user-defined transaction to read + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) +{ + typeof (dev->user) user = { + .usr_command = 1, + .usr_mosi = 0, + .usr_miso = 1, + .usr_addr = 1, + }; + dev->user = user; +} +/*------------------------------------------------------------------------------ + * Configs + *----------------------------------------------------------------------------*/ +/** + * Select which pin to use for the flash + * + * @param dev Beginning address of the peripheral registers. + * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + */ +static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) +{ + dev->misc.cs0_dis = (pin == 0) ? 0 : 1; + dev->misc.cs1_dis = (pin == 1) ? 0 : 1; +} + +/** + * Set the read io mode. + * + * @param dev Beginning address of the peripheral registers. + * @param read_mode I/O mode to use in the following transactions. + */ +static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) +{ + typeof (dev->ctrl) ctrl = dev->ctrl; + typeof (dev->user) user = dev->user; + + ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); + user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); + + switch (read_mode) { + case SPI_FLASH_FASTRD: + //the default option + case SPI_FLASH_SLOWRD: + break; + case SPI_FLASH_QIO: + ctrl.fread_quad = 1; + ctrl.faddr_quad = 1; + user.fwrite_quad = 1; + break; + case SPI_FLASH_QOUT: + ctrl.fread_quad = 1; + user.fwrite_quad = 1; + break; + case SPI_FLASH_DIO: + ctrl.fread_dual = 1; + ctrl.faddr_dual = 1; + user.fwrite_dual = 1; + break; + case SPI_FLASH_DOUT: + ctrl.fread_dual = 1; + user.fwrite_dual = 1; + break; + default: + abort(); + } + + dev->ctrl = ctrl; + dev->user = user; +} + +/** + * Set clock frequency to work at. + * + * @param dev Beginning address of the peripheral registers. + * @param clock_val pointer to the clock value to set + */ +static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val) +{ + dev->clock = *clock_val; +} + +/** + * Set the input length, in bits. + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of input, in bits. + */ +static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_miso = bitlen > 0; + if (bitlen) { + dev->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the output length, in bits (not including command, address and dummy + * phases) + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of output, in bits. + */ +static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_mosi = bitlen > 0; + if (bitlen) { + dev->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the command. + * + * @param dev Beginning address of the peripheral registers. + * @param command Command to send + * @param bitlen Length of the command + */ +static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen) +{ + dev->user.usr_command = 1; + typeof(dev->user2) user2 = { + .usr_command_value = command, + .usr_command_bitlen = (bitlen - 1), + }; + dev->user2 = user2; +} + +/** + * Get the address length that is set in register, in bits. + * + * @param dev Beginning address of the peripheral registers. + * + */ +static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev) +{ + return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; +} + +/** + * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of the address, in bits + */ +static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + dev->user1.usr_addr_bitlen = (bitlen - 1); + dev->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + // The blank region should be all ones + uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + dev->addr = (addr << (32 - bitlen)) | padding_ones; +} + +/** + * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) +{ + dev->addr = addr; +} + +/** + * Set the length of dummy cycles. + * + * @param dev Beginning address of the peripheral registers. + * @param dummy_n Cycles of dummy phases + */ +static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) +{ + dev->user.usr_dummy = dummy_n ? 1 : 0; + dev->user1.usr_dummy_cyclelen = dummy_n - 1; +} + +/** + * Set D/Q output level during dummy phase + * + * @param dev Beginning address of the peripheral registers. + * @param out_en whether to enable IO output for dummy phase + * @param out_level dummy output level + */ +static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev) +{ + dev->ctrl.dummy_out = out_en; + dev->ctrl.q_pol = out_lev; + dev->ctrl.d_pol = out_lev; +} + +/** + * Set extra hold time of CS after the clocks. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n Cycles of clocks before CS is inactive + */ +static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) +{ + dev->user1.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + +static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) +{ + dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + dev->user1.cs_setup_time = cs_setup_time - 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/hmac_hal.h b/components/hal/esp32h2/include/hal/hmac_hal.h new file mode 100644 index 0000000000..e8e29d07fd --- /dev/null +++ b/components/hal/esp32h2/include/hal/hmac_hal.h @@ -0,0 +1,109 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use it in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The HMAC peripheral can be configured to deliver its output to the user directly, or to deliver + * the output directly to another peripheral instead, e.g. the Digital Signature peripheral. + */ +typedef enum { + HMAC_OUTPUT_USER = 0, /**< Let user provide a message and read the HMAC result */ + HMAC_OUTPUT_DS = 1, /**< HMAC is provided to the DS peripheral to decrypt DS private key parameters */ + HMAC_OUTPUT_JTAG_ENABLE = 2, /**< HMAC is used to enable JTAG after soft-disabling it */ + HMAC_OUTPUT_ALL = 3 /**< HMAC is used for both as DS input for or enabling JTAG */ +} hmac_hal_output_t; + +/** + * @brief Make the peripheral ready for use. + * + * This triggers any further steps necessary after enabling the device + */ +void hmac_hal_start(void); + +/** + * @brief Configure which hardware key slot should be used and configure the target of the HMAC output. + * + * @note Writing out-of-range values is undefined behavior. The user has to ensure that the parameters are in range. + * + * @param config The target of the HMAC. Possible targets are described in \c hmac_hal_output_t. + * See the ESP32C3 TRM for more details. + * @param key_id The ID of the hardware key slot to be used. + * + * @return 0 if the configuration was successful, non-zero if not. + * An unsuccessful configuration means that the purpose value in the eFuse of the corresponding key slot + * doesn't match to supplied value of \c config. + */ +uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id); + +/** + * @brief Write a padded single-block message of 512 bits to the HMAC peripheral. + * + * The message must not be longer than one block (512 bits) and the padding has to be applied by software before + * writing. The padding has to be able to fit into the block after the message. + * For more information on HMAC padding, see the ESP32C3 TRM. + */ +void hmac_hal_write_one_block_512(const void *block); + +/** + * @brief Write a message block of 512 bits to the HMAC peripheral. + * + * This function must be used incombination with \c hmac_hal_next_block_normal() or \c hmac_hal_next_block_padding(). + * The first message block is written without any prerequisite. + * All message blocks which are not the last one, need a call to \c hmac_hal_next_block_normal() before, indicating + * to the hardware that a "normal", i.e. non-padded block will follow. This is even the case for a block which begins + * padding already but where the padding doesn't fit in (remaining message size > (block size - padding size)). + * Before writing the last block which contains the padding, a call to \c hmac_hal_next_block_padding() is necessary + * to indicate to the hardware that a block with padding will be written. + * + * For more information on HMAC padding, see the ESP32C3 TRM. + */ +void hmac_hal_write_block_512(const void *block); + +/** + * @brief Indicate to the hardware that a normal block will be written. + */ +void hmac_hal_next_block_normal(void); + +/** + * @brief Indicate to the hardware that a block with padding will be written. + */ +void hmac_hal_next_block_padding(void); + +/** + * @brief Read the 256 bit HMAC result from the hardware. + */ +void hmac_hal_read_result_256(void *result); + +/** + * @brief Clear (invalidate) the HMAC result provided to other hardware. + */ +void hmac_hal_clean(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/hmac_ll.h b/components/hal/esp32h2/include/hal/hmac_ll.h new file mode 100644 index 0000000000..8e257a7d32 --- /dev/null +++ b/components/hal/esp32h2/include/hal/hmac_ll.h @@ -0,0 +1,199 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use it in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include + +#include "soc/system_reg.h" +#include "soc/hwcrypto_reg.h" +#include "hal/hmac_hal.h" + +#define SHA256_BLOCK_SZ 64 +#define SHA256_DIGEST_SZ 32 + +#define EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG 6 +#define EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE 7 +#define EFUSE_KEY_PURPOSE_HMAC_UP 8 +#define EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL 5 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Makes the peripheral ready for use, after enabling it. + */ +static inline void hmac_ll_start(void) +{ + REG_WRITE(HMAC_SET_START_REG, 1); +} + +/** + * @brief Determine where the HMAC output should go. + * + * The HMAC peripheral can be configured to deliver its output to the user directly, or to deliver + * the output directly to another peripheral instead, e.g. the Digital Signature peripheral. + */ +static inline void hmac_ll_config_output(hmac_hal_output_t config) +{ + switch(config) { + case HMAC_OUTPUT_USER: + REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); + break; + case HMAC_OUTPUT_DS: + REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); + break; + case HMAC_OUTPUT_JTAG_ENABLE: + REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); + break; + case HMAC_OUTPUT_ALL: + REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); + break; + default: + ; // do nothing, error will be indicated by hmac_hal_config_error() + } +} + +/** + * @brief Selects which hardware key should be used. + */ +static inline void hmac_ll_config_hw_key_id(uint32_t key_id) +{ + REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); +} + +/** + * @brief Apply and check configuration. + * + * Afterwards, the configuration can be checked for errors with hmac_hal_config_error(). + */ +static inline void hmac_ll_config_finish(void) +{ + REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); +} + +/** + * + * @brief Query HMAC error state after configuration actions. + * + * @return + * - 1 or greater on error + * - 0 on success + */ +static inline uint32_t hmac_ll_config_error(void) +{ + return REG_READ(HMAC_QUERY_ERROR_REG); +} + +/** + * Wait until the HAL is ready for the next interaction. + */ +static inline void hmac_ll_wait_idle(void) +{ + uint32_t query; + do { + query = REG_READ(HMAC_QUERY_BUSY_REG); + } while(query != 0); +} + +/** + * @brief Write a message block of 512 bits to the HMAC peripheral. + */ +static inline void hmac_ll_write_block_512(const uint32_t *block) +{ + const size_t REG_WIDTH = sizeof(uint32_t); + for (size_t i = 0; i < SHA256_BLOCK_SZ / REG_WIDTH; i++) { + REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); + } + + REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); +} + +/** + * @brief Read the 256 bit HMAC. + */ +static inline void hmac_ll_read_result_256(uint32_t *result) +{ + const size_t REG_WIDTH = sizeof(uint32_t); + for (size_t i = 0; i < SHA256_DIGEST_SZ / REG_WIDTH; i++) { + result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); + } +} + +/** + * @brief Clean the HMAC result provided to other hardware. + */ +static inline void hmac_ll_clean(void) +{ + REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); + REG_WRITE(HMAC_SET_INVALIDATE_JTAG_REG, 1); +} + +/** + * @brief Signals that the following block will be the padded last block. + */ +static inline void hmac_ll_msg_padding(void) +{ + REG_WRITE(HMAC_SET_MESSAGE_PAD_REG, 1); +} + +/** + * @brief Signals that all blocks have been written and a padding block will automatically be applied by hardware. + * + * Only applies if the message length is a multiple of 512 bits. + * See ESP32C3 TRM HMAC chapter for more details. + */ +static inline void hmac_ll_msg_end(void) +{ + REG_WRITE(HMAC_SET_MESSAGE_END_REG, 1); +} + +/** + * @brief The message including padding fits into one block, so no further action needs to be taken. + * + * This is called after the one-block-message has been written. + */ +static inline void hmac_ll_msg_one_block(void) +{ + REG_WRITE(HMAC_ONE_BLOCK_REG, 1); +} + +/** + * @brief Indicate that more blocks will be written after the last block. + */ +static inline void hmac_ll_msg_continue(void) +{ + REG_WRITE(HMAC_SET_MESSAGE_ING_REG, 1); +} + +/** + * @brief Clear the HMAC result. + * + * Use this after reading the HMAC result or if aborting after any of the other steps above. + */ +static inline void hmac_ll_calc_finish(void) +{ + REG_WRITE(HMAC_SET_RESULT_FINISH_REG, 2); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/i2c_ll.h b/components/hal/esp32h2/include/hal/i2c_ll.h new file mode 100644 index 0000000000..88d4493b0e --- /dev/null +++ b/components/hal/esp32h2/include/hal/i2c_ll.h @@ -0,0 +1,914 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for I2C register operations + +#pragma once +#include "soc/i2c_periph.h" +#include "soc/soc_caps.h" +#include "hal/i2c_types.h" +#include "soc/rtc_cntl_reg.h" +#include "esp_rom_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C hardware cmd register filed. + */ +typedef union { + struct { + uint32_t byte_num: 8, + ack_en: 1, + ack_exp: 1, + ack_val: 1, + op_code: 3, + reserved14: 17, + done: 1; + }; + uint32_t val; +} i2c_hw_cmd_t; + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + +/** + * @brief Data structure for calculating I2C bus timing. + */ +typedef struct { + uint16_t clkm_div; /*!< I2C core clock devider */ + uint16_t scl_low; /*!< I2C scl low period */ + uint16_t scl_high; /*!< I2C scl hight period */ + uint16_t scl_wait_high; /*!< I2C scl wait_high period */ + uint16_t sda_hold; /*!< I2C scl low period */ + uint16_t sda_sample; /*!< I2C sda sample time */ + uint16_t setup; /*!< I2C start and stop condition setup period */ + uint16_t hold; /*!< I2C start and stop condition hold period */ + uint16_t tout; /*!< I2C bus timeout period */ +} i2c_clk_cal_t; + +// I2C operation mode command +#define I2C_LL_CMD_RESTART 6 /*!clkm_div = clkm_div; + clk_cal->scl_low = half_cycle; + // default, scl_wait_high < scl_high + int scl_wait_high = (bus_freq <= 50000) ? 0 : (half_cycle / 8); // compensate the time when freq > 50K + clk_cal->scl_wait_high = scl_wait_high; + clk_cal->scl_high = half_cycle - scl_wait_high; + clk_cal->sda_hold = half_cycle / 4; + // scl_wait_high < sda_sample <= scl_high + clk_cal->sda_sample = half_cycle / 2; + clk_cal->setup = half_cycle; + clk_cal->hold = half_cycle; + //default we set the timeout value to about 10 bus cycles + // log(20*half_cycle)/log(2) = log(half_cycle)/log(2) + log(20)/log(2) + clk_cal->tout = (int)(sizeof(half_cycle) * 8 - __builtin_clz(5 * half_cycle)) + 2; +} + +/** + * @brief Update I2C configuration + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_update(i2c_dev_t *hw) +{ + hw->ctr.conf_upgate = 1; +} + +/** + * @brief Configure the I2C bus timing related register. + * + * @param hw Beginning address of the peripheral registers + * @param bus_cfg Pointer to the data structure holding the register configuration. + * + * @return None + */ +static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) +{ + hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1; + //scl period + hw->scl_low_period.period = bus_cfg->scl_low - 1; + hw->scl_high_period.period = bus_cfg->scl_high; + //sda sample + hw->sda_hold.time = bus_cfg->sda_hold; + hw->sda_sample.time = bus_cfg->sda_sample; + //setup + hw->scl_rstart_setup.time = bus_cfg->setup; + hw->scl_stop_setup.time = bus_cfg->setup; + //hold + hw->scl_start_hold.time = bus_cfg->hold - 1; + hw->scl_stop_hold.time = bus_cfg->hold; + hw->timeout.time_out_value = bus_cfg->tout; + hw->timeout.time_out_en = 1; +} + +/** + * @brief Reset I2C txFIFO + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_txfifo_rst(i2c_dev_t *hw) +{ + hw->fifo_conf.tx_fifo_rst = 1; + hw->fifo_conf.tx_fifo_rst = 0; +} + +/** + * @brief Reset I2C rxFIFO + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw) +{ + hw->fifo_conf.rx_fifo_rst = 1; + hw->fifo_conf.rx_fifo_rst = 0; +} + +/** + * @brief Configure I2C SCL timing + * + * @param hw Beginning address of the peripheral registers + * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) + * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) + * + * @return None. + */ +static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period) +{ + hw->scl_low_period.period = low_period - 1; + hw->scl_high_period.period = hight_period - 10; + hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.period; +} + +/** + * @brief Clear I2C interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param mask Interrupt mask needs to be cleared + * + * @return None + */ +static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +{ + hw->int_clr.val = mask; +} + +/** + * @brief Enable I2C interrupt + * + * @param hw Beginning address of the peripheral registers + * @param mask Interrupt mask needs to be enabled + * + * @return None + */ +static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val |= mask; +} + +/** + * @brief Disable I2C interrupt + * + * @param hw Beginning address of the peripheral registers + * @param mask Interrupt mask needs to be disabled + * + * @return None + */ +static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val &= (~mask); +} + +/** + * @brief Get I2C interrupt status + * + * @param hw Beginning address of the peripheral registers + * + * @return I2C interrupt status + */ +static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +{ + return hw->int_status.val; +} + +/** + * @brief Configure I2C memory access mode, FIFO mode or non-FIFO mode + * + * @param hw Beginning address of the peripheral registers + * @param fifo_mode_en Set true to enable FIFO access mode, else, set it false + * + * @return None + */ +static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en) +{ + hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1; +} + +/** + * @brief Configure I2C timeout + * + * @param hw Beginning address of the peripheral registers + * @param tout_num The I2C timeout value needs to be set (2^tout in core clock cycle) + * + * @return None + */ +static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout) +{ + hw->timeout.time_out_value = tout; +} + +/** + * @brief Configure I2C slave address + * + * @param hw Beginning address of the peripheral registers + * @param slave_addr I2C slave address needs to be set + * @param addr_10bit_en Set true to enable 10-bit slave address mode, set false to enable 7-bit address mode + * + * @return None + */ +static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, bool addr_10bit_en) +{ + hw->slave_addr.addr = slave_addr; + hw->slave_addr.en_10bit = addr_10bit_en; +} + +/** + * @brief Write I2C hardware command register + * + * @param hw Beginning address of the peripheral registers + * @param cmd I2C hardware command + * @param cmd_idx The index of the command register, should be less than 16 + * + * @return None + */ +static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_hw_cmd_t cmd, int cmd_idx) +{ + hw->command[cmd_idx].val = cmd.val; +} + +/** + * @brief Configure I2C start timing + * + * @param hw Beginning address of the peripheral registers + * @param start_setup The start condition setup period (in core clock cycle) + * @param start_hold The start condition hold period (in core clock cycle) + * + * @return None + */ +static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold) +{ + hw->scl_rstart_setup.time = start_setup; + hw->scl_start_hold.time = start_hold - 1; +} + +/** + * @brief Configure I2C stop timing + * + * @param hw Beginning address of the peripheral registers + * @param stop_setup The stop condition setup period (in core clock cycle) + * @param stop_hold The stop condition hold period (in core clock cycle) + * + * @return None + */ +static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold) +{ + hw->scl_stop_setup.time = stop_setup; + hw->scl_stop_hold.time = stop_hold; +} + +/** + * @brief Configure I2C stop timing + * + * @param hw Beginning address of the peripheral registers + * @param sda_sample The SDA sample time (in core clock cycle) + * @param sda_hold The SDA hold time (in core clock cycle) + * + * @return None + */ +static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_hold) +{ + hw->sda_hold.time = sda_hold; + hw->sda_sample.time = sda_sample; +} + +/** + * @brief Set I2C txFIFO empty threshold + * + * @param hw Beginning address of the peripheral registers + * @param empty_thr The txFIFO empty threshold + * + * @return None + */ +static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr) +{ + hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr; +} + +/** + * @brief Set I2C rxFIFO full threshold + * + * @param hw Beginning address of the peripheral registers + * @param full_thr The rxFIFO full threshold + * + * @return None + */ +static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr) +{ + hw->fifo_conf.rx_fifo_wm_thrhd = full_thr; +} + +/** + * @brief Set the I2C data mode, LSB or MSB + * + * @param hw Beginning address of the peripheral registers + * @param tx_mode Tx data bit mode + * @param rx_mode Rx data bit mode + * + * @return None + */ +static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode) +{ + hw->ctr.tx_lsb_first = tx_mode; + hw->ctr.rx_lsb_first = rx_mode; +} + +/** + * @brief Get the I2C data mode + * + * @param hw Beginning address of the peripheral registers + * @param tx_mode Pointer to accept the received bytes mode + * @param rx_mode Pointer to accept the sended bytes mode + * + * @return None + */ +static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode) +{ + *tx_mode = hw->ctr.tx_lsb_first; + *rx_mode = hw->ctr.rx_lsb_first; +} + +/** + * @brief Get I2C sda timing configuration + * + * @param hw Beginning address of the peripheral registers + * @param sda_sample Pointer to accept the SDA sample timing configuration + * @param sda_hold Pointer to accept the SDA hold timing configuration + * + * @return None + */ +static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold) +{ + *sda_hold = hw->sda_hold.time; + *sda_sample = hw->sda_sample.time; +} + +/** + * @brief Get the I2C hardware version + * + * @param hw Beginning address of the peripheral registers + * + * @return The I2C hardware version + */ +static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw) +{ + return hw->date; +} + +/** + * @brief Check if the I2C bus is busy + * + * @param hw Beginning address of the peripheral registers + * + * @return True if I2C state machine is busy, else false will be returned + */ +static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw) +{ + return hw->sr.bus_busy; +} + +/** + * @brief Check if I2C is master mode + * + * @param hw Beginning address of the peripheral registers + * + * @return True if I2C is master mode, else false will be returned + */ +static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) +{ + return hw->ctr.ms_mode; +} + +/** + * @brief Get the rxFIFO readable length + * + * @param hw Beginning address of the peripheral registers + * + * @return RxFIFO readable length + */ +static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +{ + return hw->sr.rx_fifo_cnt; +} + +/** + * @brief Get I2C txFIFO writable length + * + * @param hw Beginning address of the peripheral registers + * + * @return TxFIFO writable length + */ +static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +{ + return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; +} + +/** + * @brief Get I2C timeout configuration + * + * @param hw Beginning address of the peripheral registers + * + * @return The I2C timeout value + */ +static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +{ + return hw->timeout.time_out_value; +} + +/** + * @brief Start I2C transfer + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_trans_start(i2c_dev_t *hw) +{ + hw->ctr.trans_start = 1; +} + +/** + * @brief Get I2C start timing configuration + * + * @param hw Beginning address of the peripheral registers + * @param setup_time Pointer to accept the start condition setup period + * @param hold_time Pointer to accept the start condition hold period + * + * @return None + */ +static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time) +{ + *setup_time = hw->scl_rstart_setup.time; + *hold_time = hw->scl_start_hold.time + 1; +} + +/** + * @brief Get I2C stop timing configuration + * + * @param hw Beginning address of the peripheral registers + * @param setup_time Pointer to accept the stop condition setup period + * @param hold_time Pointer to accept the stop condition hold period + * + * @return None + */ +static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *hold_time) +{ + *setup_time = hw->scl_stop_setup.time; + *hold_time = hw->scl_stop_hold.time; +} + +/** + * @brief Get I2C SCL timing configuration + * + * @param hw Beginning address of the peripheral registers + * @param high_period Pointer to accept the SCL high period + * @param low_period Pointer to accept the SCL low period + * + * @return None + */ +static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period) +{ + *high_period = hw->scl_high_period.period + hw->scl_high_period.scl_wait_high_period; + *low_period = hw->scl_low_period.period + 1; +} + +/** + * @brief Write the I2C hardware txFIFO + * + * @param hw Beginning address of the peripheral registers + * @param ptr Pointer to data buffer + * @param len Amount of data needs to be writen + * + * @return None. + */ +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +{ + for (int i = 0; i< len; i++) { + hw->fifo_data.data = ptr[i]; + } +} + +/** + * @brief Read the I2C hardware rxFIFO + * + * @param hw Beginning address of the peripheral registers + * @param ptr Pointer to data buffer + * @param len Amount of data needs read + * + * @return None + */ +static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +{ + for(int i = 0; i < len; i++) { + ptr[i] = hw->fifo_data.data; + } +} + +/** + * @brief Configure I2C hardware filter + * + * @param hw Beginning address of the peripheral registers + * @param filter_num If the glitch period on the line is less than this value, it can be filtered out + * If `filter_num == 0`, the filter will be disabled + * + * @return None + */ +static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) +{ + if (filter_num > 0) { + hw->filter_cfg.scl_thres = filter_num; + hw->filter_cfg.sda_thres = filter_num; + hw->filter_cfg.scl_en = 1; + hw->filter_cfg.sda_en = 1; + } else { + hw->filter_cfg.scl_en = 0; + hw->filter_cfg.sda_en = 0; + } +} + +/** + * @brief Get I2C hardware filter configuration + * + * @param hw Beginning address of the peripheral registers + * + * @return The hardware filter configuration + */ +static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +{ + return hw->filter_cfg.scl_thres; +} + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = ~0; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = ~0; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + +/** + * @brief Clear I2C master TX interrupt status register + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Clear I2C master RX interrupt status register + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; +} + +/** + * @brief Enable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Disable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); +} + +/** + * @brief Disable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); +} + +/** + * @brief Clear I2C slave TX interrupt status register + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = I2C_LL_SLAVE_TX_INT; +} + +/** + * @brief Clear I2C slave RX interrupt status register. + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) +{ + hw->ctr.fsm_rst = 1; +} + +/** + * @brief Clear I2C bus, when the slave is stuck in a deadlock and keeps pulling the bus low, + * master can controls the SCL bus to generate 9 CLKs. + * + * Note: The master cannot detect if deadlock happens, but when the scl_st_to interrupt is generated, a deadlock may occur. + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw) +{ + hw->scl_sp_conf.scl_rst_slv_num = 9; + hw->scl_sp_conf.scl_rst_slv_en = 0; + hw->ctr.conf_upgate = 1; + hw->scl_sp_conf.scl_rst_slv_en = 1; +} + +/** + * @brief Set I2C source clock + * + * @param hw Beginning address of the peripheral registers + * @param src_clk Source clock of the I2C + * + * @return None + */ +static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_sclk_t src_clk) +{ + // rtc_clk needs to switch on. + if (src_clk == I2C_SCLK_RTC) { + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); + esp_rom_delay_us(DELAY_RTC_CLK_SWITCH); + } + // src_clk : (1) for RTC_CLK, (0) for XTAL + hw->clk_conf.sclk_sel = (src_clk == I2C_SCLK_RTC) ? 1 : 0; +} + +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.arbitration_lost) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.nack) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Get I2C slave interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.tx_fifo_wm) { + *event = I2C_INTR_EVENT_TXFIFO_EMPTY; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else if (int_sts.rx_fifo_wm) { + *event = I2C_INTR_EVENT_RXFIFO_FULL; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Init I2C master + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_init(i2c_dev_t *hw) +{ + typeof(hw->ctr) ctrl_reg; + ctrl_reg.val = 0; + ctrl_reg.ms_mode = 1; + ctrl_reg.clk_en = 1; + ctrl_reg.sda_force_out = 1; + ctrl_reg.scl_force_out = 1; + hw->ctr.val = ctrl_reg.val; +} + +/** + * @brief Init I2C slave + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_init(i2c_dev_t *hw) +{ + typeof(hw->ctr) ctrl_reg; + ctrl_reg.val = 0; + ctrl_reg.sda_force_out = 1; + ctrl_reg.scl_force_out = 1; + hw->ctr.val = ctrl_reg.val; + hw->ctr.slv_tx_auto_start_en = 1; + hw->fifo_conf.fifo_addr_cfg_en = 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h new file mode 100644 index 0000000000..4a6042cf12 --- /dev/null +++ b/components/hal/esp32h2/include/hal/i2s_ll.h @@ -0,0 +1,912 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-S3 I2S register operations + +#pragma once + +#include +#include +#include "soc/i2s_periph.h" +#include "hal/i2s_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get I2S hardware instance with giving i2s num +#define I2S_LL_GET_HW(num) (((num) == 0) ? (&I2S0) : NULL) + +#define I2S_INTR_IN_SUC_EOF BIT(9) +#define I2S_INTR_OUT_EOF BIT(12) +#define I2S_INTR_IN_DSCR_ERR BIT(13) +#define I2S_INTR_OUT_DSCR_ERR BIT(14) +#define I2S_INTR_MAX (0xFFFFFFFF) + +/** + * @brief Reset rx fifo + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Reset tx fifo + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Enable rx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Disable rx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Disable tx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Enable tx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Reset dma in + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Reset dma out + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Reset tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_tx(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Reset rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_rx(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + + +} + +/** + * @brief Start out link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_out_link(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Start tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_tx(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Start in link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_in_link(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Start rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_rx(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Stop out link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Stop tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_tx(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Stop in link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Stop rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_rx(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Enable dma + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_dma(i2s_dev_t *hw) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // //Enable and configure DMA + // typeof(hw->lc_conf) lc_conf; + // lc_conf.val = 0; + // lc_conf.out_eof_mode = 1; + +} + +/** + * @brief Get I2S interrupt status + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get interrupt status + */ +static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->int_st.val; +} + +/** + * @brief Clear I2S interrupt status + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to clear interrupt status + */ +static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Get I2S out eof des address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get out eof des address + */ +static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->out_eof_des_addr; +} + +/** + * @brief Get I2S in eof des address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get in eof des address + */ +static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->in_eof_des_addr; +} + +/** + * @brief Get I2S tx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx fifo mode + */ +static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->fifo_conf.tx_fifo_mod; +} + +/** + * @brief Set I2S tx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx fifo mode + */ +static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Get I2S rx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx fifo mode + */ +static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->fifo_conf.rx_fifo_mod; +} + +/** + * @brief Set I2S rx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx fifo mode + */ +static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx chan mode + */ +static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx chan mode + */ +static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S out link address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set out link address + */ +static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S in link address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set in link address + */ +static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx eof num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx eof num + */ +static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Get I2S tx pdm fp + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx pdm fp + */ +static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->pdm_freq_conf.tx_pdm_fp; +} + +/** + * @brief Get I2S tx pdm fs + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx pdm fs + */ +static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->pdm_freq_conf.tx_pdm_fs; +} + +/** + * @brief Set I2S tx pdm fp + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm fp + */ +static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx pdm fs + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm fs + */ +static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Get I2S rx sinc dsr 16 en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx sinc dsr 16 en + */ +static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->pdm_conf.rx_sinc_dsr_16_en; +} + +/** + * @brief Set I2S clkm div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div num + */ +static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S clkm div b + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div b + */ +static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S clkm div a + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div a + */ +static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bck div num + */ +static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bck div num + */ +static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S clk sel + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clk sel + */ +static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx bits mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bits mod + */ +static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx bits mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bits mod + */ +static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx sinc dsr 16 en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx sinc dsr 16 en + */ +static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S dscr en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set dscr en + */ +static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S lcd en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set lcd en + */ +static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S camera en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set camera en + */ +static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S pcm2pdm conv en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set pcm2pdm conv en + */ +static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S TX to MSB Alignment Standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw) +{ +} + + +static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to PCM long standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to PCM long standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to PCM short standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to philip standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to PCM short standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to philip standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S pdm2pcm conv en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set pdm2pcm conv en + */ +static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx pdm en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx pdm en + */ +static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx pdm en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm en + */ +static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx fifo mod force en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx fifo mod force en + */ +static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx fifo mod force en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx fifo mod force en + */ +static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx right first + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx right first + */ +static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx right first + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx right first + */ +static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx slave mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx slave mod + */ +static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx slave mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx slave mod + */ +static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Get I2S tx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx msb right + */ +static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->conf.tx_msb_right; +} + +/** + * @brief Get I2S rx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx msb right + */ +static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + // *val = hw->conf.rx_msb_right; +} + +/** + * @brief Set I2S tx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx msb right + */ +static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx msb right + */ +static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx mono + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx mono + */ +static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S rx mono + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx mono + */ +static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S tx sinc osr2 + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx sinc osr2 + */ +static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +/** + * @brief Set I2S sig loopback + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set sig loopback + */ +static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val) +{ + abort(); // TODO ESP32-C3 IDF-2098 + +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/interrupt_controller_ll.h b/components/hal/esp32h2/include/hal/interrupt_controller_ll.h new file mode 100644 index 0000000000..70afe314cf --- /dev/null +++ b/components/hal/esp32h2/include/hal/interrupt_controller_ll.h @@ -0,0 +1,132 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "soc/soc.h" +#include "soc/interrupt_core0_reg.h" +#include "riscv/interrupt.h" +#include "riscv/csr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be enabled + */ +static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask) +{ + unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); + esprv_intc_int_enable(mask); + RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); +} + +/** + * @brief disable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be disabled + */ +static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask) +{ + unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); + esprv_intc_int_disable(mask); + RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); +} + +/** + * @brief Read the current interrupt mask of the CPU running this code. + * + * @return The current interrupt bitmask. + */ +static inline uint32_t intr_cntrl_ll_read_interrupt_mask(void) +{ + return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG); +} + +/** + * @brief checks if given interrupt number has a valid handler + * + * @param intr interrupt number ranged from 0 to 31 + * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1 + * @return true for valid handler, false otherwise + */ +static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu) +{ + return intr_handler_get(intr); +} + +/** + * @brief sets interrupt handler and optional argument of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * @param handler handler invoked when an interrupt occurs + * @param arg optional argument to pass to the handler + */ +static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg) +{ + intr_handler_set(intr, (void *)handler, arg); +} + +/** + * @brief Gets argument passed to handler of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * + * @return argument used by handler of passed interrupt number + */ +static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr) +{ + return intr_handler_get_arg(intr); +} + +/** + * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag + * + * @param intr interrupt number ranged from 0 to 31 + */ +static inline void intr_cntrl_ll_edge_int_acknowledge(int intr) +{ + REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr); +} + +/** + * @brief Sets the interrupt level int the interrupt controller. + * + * @param interrupt_number Interrupt number 0 to 31 + * @param level priority between 1 (lowest) to 7 (highest) + */ +static inline void intr_cntrl_ll_set_int_level(int intr, int level) +{ + esprv_intc_int_set_priority(intr, level); +} + +/** + * @brief Set the type of an interrupt in the controller. + * + * @param interrupt_number Interrupt number 0 to 31 + * @param type interrupt type as edge or level triggered + */ +static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type) +{ + esprv_intc_int_set_type(BIT(intr), type); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/ledc_ll.h b/components/hal/esp32h2/include/hal/ledc_ll.h new file mode 100644 index 0000000000..eafae904ba --- /dev/null +++ b/components/hal/esp32h2/include/hal/ledc_ll.h @@ -0,0 +1,518 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for LEDC register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include "hal/ledc_types.h" +#include "soc/ledc_periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEDC_LL_GET_HW() &LEDC + +/** + * @brief Set LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel) +{ + uint32_t clk_sel_val = 0; + if (slow_clk_sel == LEDC_SLOW_CLK_APB) { + clk_sel_val = 1; + } else if (slow_clk_sel == LEDC_SLOW_CLK_RTC8M) { + clk_sel_val = 2; + } else if (slow_clk_sel == LEDC_SLOW_CLK_XTAL) { + clk_sel_val = 3; + } + hw->conf.apb_clk_sel = clk_sel_val; +} + +/** + * @brief Get LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel) +{ + uint32_t clk_sel_val = hw->conf.apb_clk_sel; + if (clk_sel_val == 1) { + *slow_clk_sel = LEDC_SLOW_CLK_APB; + } else if (clk_sel_val == 2) { + *slow_clk_sel = LEDC_SLOW_CLK_RTC8M; + } else if (clk_sel_val == 3) { + *slow_clk_sel = LEDC_SLOW_CLK_XTAL; + } +} + +/** + * @brief Update LEDC low speed timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.low_speed_update = 1; +} + +/** + * @brief Reset LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1; + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0; +} + +/** + * @brief Pause LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1; +} + +/** + * @brief Resume LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0; +} + +/** + * @brief Set LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider = clock_divider; +} + +/** + * @brief Get LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider) +{ + *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider; +} + +/** + * @brief Set LEDC timer clock source + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clk_src Timer clock source + * + * @return None + */ +static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src) +{ + if (clk_src == LEDC_REF_TICK) { + //REF_TICK can only be used when APB is selected. + hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1; + hw->conf.apb_clk_sel = 1; + } else { + hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 0; + } +} + +/** + * @brief Get LEDC timer clock source + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clk_src Pointer to accept the timer clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) +{ + if (hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 1) { + *clk_src = LEDC_REF_TICK; + } else { + *clk_src = LEDC_APB_CLK; + } +} + +/** + * @brief Set LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.duty_resolution = duty_resolution; +} + +/** + * @brief Get LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Pointer to accept the resolution of duty setting in number of bits. + * + * @return None + */ +static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution) +{ + *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_resolution; +} + +/** + * @brief Update channel configure when select low speed mode + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.low_speed_update = 1; +} + +/** + * @brief Get LEDC max duty + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param max_duty Pointer to accept the max duty + * + * @return None + */ +static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *max_duty) +{ + uint32_t timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel; + *max_duty = (1 << (LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_resolution)); +} + +/** + * @brief Set LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param hpoint_val LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val) +{ + hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; +} + +/** + * @brief Get LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val) +{ + *hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint; +} + +/** + * @brief Set LEDC the integer part of duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val) +{ + hw->channel_group[speed_mode].channel[channel_num].duty.duty = duty_val << 4; +} + +/** + * @brief Get LEDC duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_val Pointer to accept the LEDC duty value + * + * @return None + */ +static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) +{ + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_rd.duty_read >> 4); +} + +/** + * @brief Set LEDC duty change direction + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_direction LEDC duty change direction, increase or decrease + * + * @return None + */ +static inline void ledc_ll_set_duty_direction(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_duty_direction_t duty_direction) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; +} + +/** + * @brief Get LEDC duty change direction + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_direction Pointer to accept the LEDC duty change direction, increase or decrease + * + * @return None + */ +static inline void ledc_ll_get_duty_direction(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_duty_direction_t *duty_direction) +{ + *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; +} + +/** + * @brief Set the number of increased or decreased times + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_num The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_duty_num(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; +} + +/** + * @brief Set the duty cycles of increase or decrease + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_cycle The duty cycles + * + * @return None + */ +static inline void ledc_ll_set_duty_cycle(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_cycle) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; +} + +/** + * @brief Set the step scale of increase or decrease + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_scale The step scale + * + * @return None + */ +static inline void ledc_ll_set_duty_scale(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_scale) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; +} + +/** + * @brief Set the output enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param sig_out_en The output enable status + * + * @return None + */ +static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en; +} + +/** + * @brief Set the duty start + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_start The duty start + * + * @return None + */ +static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool duty_start) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; +} + +/** + * @brief Set output idle level + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param idle_level The output idle level + * + * @return None + */ +static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1; +} + +/** + * @brief Set fade end interrupt enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param fade_end_intr_en The fade end interrupt enable status + * + * @return None + */ +static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en) +{ + uint32_t value = hw->int_ena.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; + hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num)))); +} + +/** + * @brief Get fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param intr_status The fade end interrupt status + * + * @return None + */ +static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status) +{ + uint32_t value = hw->int_st.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; + *intr_status = (value >> int_en_base) & 0xff; +} + +/** + * @brief Clear fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; + hw->int_clr.val = BIT(int_en_base + channel_num); +} + +/** + * @brief Set timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel; +} + +/** + * @brief Get timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param timer_sel Pointer to accept the LEDC timer index + * + * @return None + */ +static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel) +{ + *timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/memprot_ll.h b/components/hal/esp32h2/include/hal/memprot_ll.h new file mode 100644 index 0000000000..5da2b452d3 --- /dev/null +++ b/components/hal/esp32h2/include/hal/memprot_ll.h @@ -0,0 +1,571 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/sensitive_reg.h" +#include "soc/cache_memory.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ****************************************************************************************************** + * *** GLOBALS *** + * NOTE: in this version, all the configurations apply only to WORLD_0 + */ + +#define IRAM_SRAM_START 0x4037C000 +#define DRAM_SRAM_START 0x3FC7C000 + +/* ICache size is fixed to 16KB on ESP32-C3 */ +#ifndef ICACHE_SIZE +#define ICACHE_SIZE 0x4000 +#endif + +#ifndef I_D_SRAM_SEGMENT_SIZE +#define I_D_SRAM_SEGMENT_SIZE 0x20000 +#endif + +#define I_D_SPLIT_LINE_SHIFT 0x9 +#define I_D_FAULT_ADDR_SHIFT 0x2 + +static inline void memprot_ll_set_iram0_dram0_split_line_lock(void) +{ + REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, 1); +} + +static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void) +{ + return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; +} + +static inline void* memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t base) +{ + return (void*) + (base + ((regval & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M) + >> (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S - I_D_SPLIT_LINE_SHIFT))); +} + +/* ****************************************************************************************************** + * *** IRAM0 *** + */ + +//16kB (CACHE) +#define IRAM0_SRAM_LEVEL_0_LOW IRAM_SRAM_START //0x40370000 +#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x4037FFFF + +//128kB (LEVEL 1) +#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 +#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF + +//128kB (LEVEL 2) +#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 +#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF + +//128kB (LEVEL 3) +#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 +#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF + +//permission bits +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F 0x4 + +static inline uint32_t memprot_ll_iram0_get_intr_source_num(void) +{ + return ETS_CORE0_IRAM0_PMS_INTR_SOURCE; +} + + +/////////////////////////////////// +// IRAM0 - SPLIT LINES +/////////////////////////////////// + +static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg) +{ + uint32_t addr = (uint32_t)line_addr; + assert( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH ); + + uint32_t category[3] = {0}; + if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) { + category[0] = 0x2; + category[1] = category[2] = 0x3; + } else if (addr >= IRAM0_SRAM_LEVEL_2_LOW && addr <= IRAM0_SRAM_LEVEL_2_HIGH) { + category[1] = 0x2; + category[2] = 0x3; + } else { + category[2] = 0x2; + } + + //NOTE: category & split line address bits are the same for all the areas + uint32_t category_bits = + (category[0] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) | + (category[1] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) | + (category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S); + + uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S; + + uint32_t reg_cfg = conf_addr | category_bits; + + REG_WRITE(sensitive_reg, reg_cfg); +} + +/* can be both IRAM0/DRAM0 address */ +static inline void memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr) +{ + memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG); +} + +static inline void memprot_ll_set_iram0_split_line_I_0(const void *line_addr) +{ + memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); +} + +static inline void memprot_ll_set_iram0_split_line_I_1(const void *line_addr) +{ + memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); +} + +static inline void* memprot_ll_get_iram0_split_line_main_I_D(void) +{ + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG), SOC_DIRAM_IRAM_LOW); +} + +static inline void* memprot_ll_get_iram0_split_line_I_0(void) +{ + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_IRAM_LOW); +} + +static inline void* memprot_ll_get_iram0_split_line_I_1(void) +{ + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_IRAM_LOW); +} + + +/////////////////////////////////// +// IRAM0 - PMS CONFIGURATION +/////////////////////////////////// + +// lock +static inline void memprot_ll_iram0_set_pms_lock(void) +{ + REG_WRITE(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG, 1); +} + +static inline bool memprot_ll_iram0_get_pms_lock(void) +{ + return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1; +} + +// permission settings +static inline uint32_t memprot_ll_iram0_set_permissions(bool r, bool w, bool x) +{ + uint32_t permissions = 0; + if ( r ) { + permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; + } + if ( w ) { + permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; + } + if ( x ) { + permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F; + } + + return permissions; +} + +static inline void memprot_ll_iram0_set_pms_area_0(bool r, bool w, bool x) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_iram0_set_permissions(r, w, x)); +} + +static inline void memprot_ll_iram0_set_pms_area_1(bool r, bool w, bool x) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_iram0_set_permissions(r, w, x)); +} + +static inline void memprot_ll_iram0_set_pms_area_2(bool r, bool w, bool x) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_iram0_set_permissions(r, w, x)); +} + +static inline void memprot_ll_iram0_set_pms_area_3(bool r, bool w, bool x) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_iram0_set_permissions(r, w, x)); +} + +static inline void memprot_ll_iram0_get_permissions(uint32_t perms, bool *r, bool *w, bool *x) +{ + *r = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; + *w = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; + *x = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F; +} + +static inline void memprot_ll_iram0_get_pms_area_0(bool *r, bool *w, bool *x) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0); + memprot_ll_iram0_get_permissions( permissions, r, w, x); +} + +static inline void memprot_ll_iram0_get_pms_area_1(bool *r, bool *w, bool *x) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1); + memprot_ll_iram0_get_permissions( permissions, r, w, x); +} + +static inline void memprot_ll_iram0_get_pms_area_2(bool *r, bool *w, bool *x) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2); + memprot_ll_iram0_get_permissions( permissions, r, w, x); +} + +static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3); + memprot_ll_iram0_get_permissions( permissions, r, w, x); +} + + +/////////////////////////////////// +// IRAM0 - MONITOR +/////////////////////////////////// + +// lock +static inline void memprot_ll_iram0_set_monitor_lock(void) +{ + REG_WRITE(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG, 1); +} + +static inline bool memprot_ll_iram0_get_monitor_lock(void) +{ + return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; +} + +// interrupt enable/clear +static inline void memprot_ll_iram0_set_monitor_en(bool enable) +{ + if ( enable ) { + REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ); + } else { + REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ); + } +} + +static inline bool memprot_ll_iram0_get_monitor_en(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ) == 1; +} + +static inline void memprot_ll_iram0_clear_monitor_intr(void) +{ + REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR ); +} + +static inline void memprot_ll_iram0_reset_clear_monitor_intr(void) +{ + REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR ); +} + +static inline uint32_t memprot_ll_iram0_get_monitor_enable_register(void) +{ + return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); +} + +// // permission violation status +static inline uint32_t memprot_ll_iram0_get_monitor_status_intr(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR ); +} + +static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_wr(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR ); +} + +static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_loadstore(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE ); +} + +static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_world(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD ); +} + +static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_addr(void) +{ + uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR ); + return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0; +} + +static inline uint32_t memprot_ll_iram0_get_monitor_status_register(void) +{ + return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); +} + + +/* ****************************************************************************************************** + * *** DRAM0 *** + */ + +//cache not available from DRAM (!) +#define DRAM0_SRAM_LEVEL_0_LOW DRAM_SRAM_START //0x3FC7C000 +#define DRAM0_SRAM_LEVEL_0_HIGH (DRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x3FC7FFFF + +//128kB +#define DRAM0_SRAM_LEVEL_1_LOW (DRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x3FC80000 +#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF + +//128kB +#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 +#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF + +//128kB +#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 +#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1 + + +static inline uint32_t memprot_ll_dram0_get_intr_source_num(void) +{ + return ETS_CORE0_DRAM0_PMS_INTR_SOURCE; +} + + +/////////////////////////////////// +// DRAM0 - SPLIT LINES +/////////////////////////////////// + +static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg) +{ + uint32_t addr = (uint32_t)line_addr; + assert( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH ); + + uint32_t category[3] = {0}; + if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) { + category[0] = 0x2; + category[1] = category[2] = 0x3; + } else if (addr >= DRAM0_SRAM_LEVEL_2_LOW && addr <= DRAM0_SRAM_LEVEL_2_HIGH) { + category[1] = 0x2; + category[2] = 0x3; + } else { + category[2] = 0x2; + } + + //NOTE: line address & category bits, shifts and masks are the same for all the areas + uint32_t category_bits = + (category[0] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) | + (category[1] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) | + (category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S); + + uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S; + + uint32_t reg_cfg = conf_addr | category_bits; + + REG_WRITE(sensitive_reg, reg_cfg); +} + +static inline void memprot_ll_set_dram0_split_line_D_0(const void *line_addr) +{ + memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); +} + +static inline void memprot_ll_set_dram0_split_line_D_1(const void *line_addr) +{ + memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); +} + +static inline void* memprot_ll_get_dram0_split_line_D_0(void) +{ + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_DRAM_LOW); +} + +static inline void* memprot_ll_get_dram0_split_line_D_1(void) +{ + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_DRAM_LOW); +} + + +/////////////////////////////////// +// DRAM0 - PMS CONFIGURATION +/////////////////////////////////// + +// lock +static inline void memprot_ll_dram0_set_pms_lock(void) +{ + REG_WRITE(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG, 1); +} + +static inline bool memprot_ll_dram0_get_pms_lock(void) +{ + return REG_READ(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG) == 1; +} + +// permission settings +static inline uint32_t memprot_ll_dram0_set_permissions(bool r, bool w) +{ + uint32_t permissions = 0; + if ( r ) { + permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; + } + if ( w ) { + permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; + } + + return permissions; +} + +static inline void memprot_ll_dram0_set_pms_area_0(bool r, bool w) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_dram0_set_permissions(r, w)); +} + +static inline void memprot_ll_dram0_set_pms_area_1(bool r, bool w) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_dram0_set_permissions(r, w)); +} + +static inline void memprot_ll_dram0_set_pms_area_2(bool r, bool w) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_dram0_set_permissions(r, w)); +} + +static inline void memprot_ll_dram0_set_pms_area_3(bool r, bool w) +{ + REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_dram0_set_permissions(r, w)); +} + +static inline void memprot_ll_dram0_get_permissions(uint32_t perms, bool *r, bool *w ) +{ + *r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; + *w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; +} + +static inline void memprot_ll_dram0_get_pms_area_0(bool *r, bool *w) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0); + memprot_ll_dram0_get_permissions( permissions, r, w); +} + +static inline void memprot_ll_dram0_get_pms_area_1(bool *r, bool *w) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1); + memprot_ll_dram0_get_permissions( permissions, r, w); +} + +static inline void memprot_ll_dram0_get_pms_area_2(bool *r, bool *w) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2); + memprot_ll_dram0_get_permissions( permissions, r, w); +} + +static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w) +{ + uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3); + memprot_ll_dram0_get_permissions( permissions, r, w); +} + +/////////////////////////////////// +// DRAM0 - MONITOR +/////////////////////////////////// + +// lock +static inline void memprot_ll_dram0_set_monitor_lock(void) +{ + REG_WRITE(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG, 1); +} + +static inline bool memprot_ll_dram0_get_monitor_lock(void) +{ + return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1; +} + +// interrupt enable/clear +static inline void memprot_ll_dram0_set_monitor_en(bool enable) +{ + if ( enable ) { + REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ); + } else { + REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ); + } +} + +static inline bool memprot_ll_dram0_get_monitor_en(void) +{ + return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ) == 1; +} + +static inline void memprot_ll_dram0_clear_monitor_intr(void) +{ + REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR ); +} + +static inline void memprot_ll_dram0_reset_clear_monitor_intr(void) +{ + REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR ); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_enable_register(void) +{ + return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG); +} + +// permission violation status +static inline uint32_t memprot_ll_dram0_get_monitor_status_intr(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR ); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_lock(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK ); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_world(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD ); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_addr(void) +{ + uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR ); + return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + DRAM0_ADDRESS_LOW : 0; +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_wr(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR ); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_byte_en(void) +{ + return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN ); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_register_1(void) +{ + return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG); +} + +static inline uint32_t memprot_ll_dram0_get_monitor_status_register_2(void) +{ + return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/mpu_ll.h b/components/hal/esp32h2/include/hal/mpu_ll.h new file mode 100644 index 0000000000..77fa580cdb --- /dev/null +++ b/components/hal/esp32h2/include/hal/mpu_ll.h @@ -0,0 +1,53 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* This LL is currently unused for ESP32-C3 - cleanup is TODO ESP32-C3 IDF-2375 */ + +static inline uint32_t mpu_ll_id_to_addr(unsigned id) +{ + abort(); +} + +static inline void mpu_ll_set_region_rw(uint32_t addr) +{ + abort(); +} + +static inline void mpu_ll_set_region_rwx(uint32_t addr) +{ + abort(); +} + +static inline void mpu_ll_set_region_x(uint32_t addr) +{ + abort(); +} + + +static inline void mpu_ll_set_region_illegal(uint32_t addr) +{ + abort(); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/mwdt_ll.h b/components/hal/esp32h2/include/hal/mwdt_ll.h new file mode 100644 index 0000000000..c1fd5be9d6 --- /dev/null +++ b/components/hal/esp32h2/include/hal/mwdt_ll.h @@ -0,0 +1,254 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/timer_periph.h" +#include "hal/wdt_types.h" +#include "esp_attr.h" + +//Type check wdt_stage_action_t +_Static_assert(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +_Static_assert(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the MWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) +{ + hw->wdt_config0.en = 1; +} + +/** + * @brief Disable the MWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) +{ + hw->wdt_config0.en = 0; +} + +/** + * Check if the MWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if the MWDT is enabled, false otherwise + */ +FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) +{ + return (hw->wdt_config0.en) ? true : false; +} + +/** + * @brief Configure a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout + * @param behavior What action to take when the stage times out + */ +FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) +{ + switch (stage) { + case WDT_STAGE0: + hw->wdt_config0.stg0 = behavior; + hw->wdt_config2 = timeout; + break; + case WDT_STAGE1: + hw->wdt_config0.stg1 = behavior; + hw->wdt_config3 = timeout; + break; + case WDT_STAGE2: + hw->wdt_config0.stg2 = behavior; + hw->wdt_config4 = timeout; + break; + case WDT_STAGE3: + hw->wdt_config0.stg3 = behavior; + hw->wdt_config5 = timeout; + break; + default: + break; + } + //Config registers are updated asynchronously + hw->wdt_config0.conf_update_en = 1; +} + +/** + * @brief Disable a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) +{ + switch (stage) { + case WDT_STAGE0: + hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE1: + hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE2: + hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE3: + hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF; + break; + default: + break; + } + //Config registers are updated asynchronously + hw->wdt_config0.conf_update_en = 1; +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->wdt_config0.cpu_reset_length = length; + //Config registers are updated asynchronously + hw->wdt_config0.conf_update_en = 1; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->wdt_config0.sys_reset_length = length; + //Config registers are updated asynchronously + hw->wdt_config0.conf_update_en = 1; +} + +/** + * @brief Enable/Disable the MWDT flashboot mode. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) +{ + hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0; + //Config registers are updated asynchronously + hw->wdt_config0.conf_update_en = 1; +} + +/** + * @brief Set the clock prescaler of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param prescaler Prescaler value between 1 to 65535 + */ +FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) +{ + hw->wdt_config1.clk_prescale = prescaler; + //Config registers are updated asynchronously + hw->wdt_config0.conf_update_en = 1; +} + +/** + * @brief Feed the MWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) +{ + hw->wdt_feed = 1; +} + +/** + * @brief Enable write protection of the MWDT registers + * + * Locking the MWDT will prevent any of the MWDT's registers from being modified + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) +{ + hw->wdt_wprotect = 0; +} + +/** + * @brief Disable write protection of the MWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) +{ + hw->wdt_wprotect = TIMG_WDT_WKEY_VALUE; +} + +/** + * @brief Clear the MWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) +{ + hw->int_clr.wdt = 1; +} + +/** + * @brief Set the interrupt enable bit for the MWDT interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Whether to enable the MWDT interrupt + */ +FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) +{ + hw->int_ena.wdt = (enable) ? 1 : 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h new file mode 100644 index 0000000000..a323adfbc1 --- /dev/null +++ b/components/hal/esp32h2/include/hal/rmt_ll.h @@ -0,0 +1,502 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include "soc/rmt_struct.h" +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RMT_LL_HW_BASE (&RMT) +#define RMT_LL_MEM_BASE (&RMTMEM) + +// Note: TX and RX channel number are all index from zero in the LL driver +// i.e. tx_channel belongs to [0,2], and rx_channel belongs to [0,2] + +static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) +{ + dev->sys_conf.clk_en = enable; // register clock gating + dev->sys_conf.mem_clk_force_on = enable; // memory clock gating +} + +static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) +{ + dev->sys_conf.mem_force_pu = !enable; + dev->sys_conf.mem_force_pd = enable; +} + +static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) +{ + // the RTC domain can also power down RMT memory + // so it's probably not enough to detect whether it's powered down or not + // mem_force_pd has higher priority than mem_force_pu + return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); +} + +static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) +{ + dev->sys_conf.fifo_mask = enable; +} + +static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) +{ + // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) + dev->sys_conf.sclk_active = 0; + dev->sys_conf.sclk_sel = src; + dev->sys_conf.sclk_div_num = div_num; + dev->sys_conf.sclk_div_a = div_a; + dev->sys_conf.sclk_div_b = div_b; + dev->sys_conf.sclk_active = 1; +} + +static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) +{ + return dev->sys_conf.sclk_sel; +} + +static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) +{ + dev->ref_cnt_rst.val |= (1 << channel); +} + +static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) +{ + dev->ref_cnt_rst.val |= channel_mask; +} + +static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) +{ + dev->ref_cnt_rst.val |= (1 << (channel + 2)); +} + +static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) +{ + dev->tx_conf[channel].mem_rd_rst = 1; + dev->tx_conf[channel].mem_rd_rst = 0; + dev->tx_conf[channel].mem_rst = 1; + dev->tx_conf[channel].mem_rst = 0; +} + +static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) +{ + dev->rx_conf[channel].conf1.mem_wr_rst = 1; + dev->rx_conf[channel].conf1.mem_wr_rst = 0; + dev->rx_conf[channel].conf1.mem_rst = 1; + dev->rx_conf[channel].conf1.mem_rst = 0; +} + +static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) +{ + dev->tx_conf[channel].conf_update = 1; + dev->tx_conf[channel].tx_start = 1; +} + +static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) +{ + dev->tx_conf[channel].tx_stop = 1; + dev->tx_conf[channel].conf_update = 1; +} + +static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->rx_conf[channel].conf1.rx_en = enable; + dev->rx_conf[channel].conf1.conf_update = 1; +} + +static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) +{ + dev->tx_conf[channel].mem_size = block_num; +} + +static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) +{ + dev->rx_conf[channel].conf0.mem_size = block_num; +} + +static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) +{ + return dev->tx_conf[channel].mem_size; +} + +static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) +{ + return dev->rx_conf[channel].conf0.mem_size; +} + +static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +{ + dev->tx_conf[channel].div_cnt = div; +} + +static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +{ + dev->rx_conf[channel].conf0.div_cnt = div; +} + +static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) +{ + return dev->tx_conf[channel].div_cnt; +} + +static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) +{ + return dev->rx_conf[channel].conf0.div_cnt; +} + +static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->tx_conf[channel].mem_tx_wrap_en = enable; +} + +static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) +{ + dev->rx_conf[channel].conf0.idle_thres = thres; +} + +static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) +{ + return dev->rx_conf[channel].conf0.idle_thres; +} + +static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) +{ + dev->rx_conf[channel].conf1.mem_owner = owner; +} + +static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) +{ + return dev->rx_conf[channel].conf1.mem_owner; +} + +static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->tx_conf[channel].tx_conti_mode = enable; +} + +static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) +{ + return dev->tx_conf[channel].tx_conti_mode; +} + +static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) +{ + dev->tx_lim[channel].tx_loop_num = count; +} + +static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) +{ + dev->tx_lim[channel].loop_count_reset = 1; + dev->tx_lim[channel].loop_count_reset = 0; +} + +static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->tx_lim[channel].tx_loop_cnt_en = enable; +} + +static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) +{ + dev->tx_sim.en = enable; +} + +static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) +{ + dev->tx_sim.val |= 1 << channel; +} + +static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) +{ + dev->tx_sim.val &= ~(1 << channel); +} + +static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->rx_conf[channel].conf1.rx_filter_en = enable; +} + +static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) +{ + dev->rx_conf[channel].conf1.rx_filter_thres = thres; +} + +static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->tx_conf[channel].idle_out_en = enable; +} + +static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) +{ + return dev->tx_conf[channel].idle_out_en; +} + +static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) +{ + dev->tx_conf[channel].idle_out_lv = level; +} + +static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) +{ + return dev->tx_conf[channel].idle_out_lv; +} + +static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) +{ + return dev->rx_status[channel].val; +} + +static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) +{ + return dev->tx_status[channel].val; +} + +static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) +{ + dev->tx_lim[channel].limit = limit; +} + +static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) +{ + dev->rx_lim[channel].rx_lim = limit; +} + +static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) +{ + return dev->rx_lim[channel].rx_lim; +} + +static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << channel); + } else { + dev->int_ena.val &= ~(1 << channel); + } +} + +static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << (channel + 4)); + } else { + dev->int_ena.val &= ~(1 << (channel + 4)); + } +} + +static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << (channel + 2)); + } else { + dev->int_ena.val &= ~(1 << (channel + 2)); + } +} + +static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << (channel + 6)); + } else { + dev->int_ena.val &= ~(1 << (channel + 6)); + } +} + +static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << (channel + 8)); + } else { + dev->int_ena.val &= ~(1 << (channel + 8)); + } +} + +static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << (channel + 12)); + } else { + dev->int_ena.val &= ~(1 << (channel + 12)); + } +} + +static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + if (enable) { + dev->int_ena.val |= (1 << (channel + 10)); + } else { + dev->int_ena.val &= ~(1 << (channel + 10)); + } +} + +static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel)); +} + +static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel + 2)); +} + +static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel + 4)); +} + +static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel + 6)); +} + +static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel + 8)); +} + +static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel + 12)); +} + +static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) +{ + dev->int_clr.val = (1 << (channel + 10)); +} + +static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) +{ + return dev->int_st.val & 0x03; +} + +static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 2) & 0x03; +} + +static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 4) & 0x03; +} + +static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 6) & 0x03; +} + +static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 8) & 0x03; +} + +static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 10) & 0x03; +} + +static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 12) & 0x03; +} + +static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) +{ + // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) + // We take care of the "read-modify-write" procedure by ourselves. + typeof(dev->tx_carrier[0]) reg; + reg.high = high_ticks; + reg.low = low_ticks; + dev->tx_carrier[channel].val = reg.val; +} + +static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) +{ + typeof(dev->rx_carrier[0]) reg; + reg.high_thres = high_ticks; + reg.low_thres = low_ticks; + dev->rx_carrier[channel].val = reg.val; +} + +static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) +{ + *high_ticks = dev->tx_carrier[channel].high; + *low_ticks = dev->tx_carrier[channel].low; +} + +static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) +{ + *high_ticks = dev->rx_carrier[channel].high_thres; + *low_ticks = dev->rx_carrier[channel].low_thres; +} + +static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->tx_conf[channel].carrier_en = enable; +} + +static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->rx_conf[channel].conf0.carrier_en = enable; +} + +static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) +{ + dev->tx_conf[channel].carrier_out_lv = level; +} + +static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) +{ + dev->rx_conf[channel].conf0.carrier_out_lv = level; +} + +// set true, enable carrier in all RMT state (idle, reading, sending) +// set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) +static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->tx_conf[channel].carrier_eff_en = !enable; +} + +//Writes items to the specified TX channel memory with the given offset and writen length. +//the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) +static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) +{ + for (uint32_t i = 0; i < length; i++) { + mem->chan[channel].data32[i + off].val = data[i].val; + } +} + +static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; +} + +/************************************************************************************************ + * Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0 + ***********************************************************************************************/ + +static inline void rmt_ll_set_intr_enable_mask(uint32_t mask) +{ + RMT.int_ena.val |= mask; +} + +static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask) +{ + RMT.int_ena.val &= (~mask); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h new file mode 100644 index 0000000000..72385568a4 --- /dev/null +++ b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h @@ -0,0 +1,67 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/apb_ctrl_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +{ + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); + + SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); + SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); +} + +static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void) +{ + return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); +} + +static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void) +{ + REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); +} + +static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void) +{ + REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); +} + +static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) +{ + /* write memory address to register */ + REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_LINK_ADDR, (uint32_t)addr); + /* Enable clock */ + REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); + /* Enable retention when cpu sleep enable */ + REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); +} + +static inline void rtc_cntl_ll_disable_cpu_retention(void) +{ + REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/rwdt_ll.h b/components/hal/esp32h2/include/hal/rwdt_ll.h new file mode 100644 index 0000000000..87ae4f7294 --- /dev/null +++ b/components/hal/esp32h2/include/hal/rwdt_ll.h @@ -0,0 +1,311 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/wdt_types.h" +#include "soc/rtc_cntl_periph.h" +#include "soc/efuse_reg.h" +#include "esp_attr.h" + +//Type check wdt_stage_action_t +_Static_assert(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +_Static_assert(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the RWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void rwdt_ll_enable(rtc_cntl_dev_t *hw) +{ + hw->wdt_config0.en = 1; +} + +/** + * @brief Disable the RWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void rwdt_ll_disable(rtc_cntl_dev_t *hw) +{ + hw->wdt_config0.en = 0; +} + +/** + * @brief Check if the RWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if RTC WDT is enabled + */ +FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rtc_cntl_dev_t *hw) +{ + return (hw->wdt_config0.en) ? true : false; +} + +/** + * @brief Configure a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout (see note). + * @param behavior What action to take when the stage times out + * + * @note The value of of RWDT stage 0 timeout register is special, in + * that an implicit multiplier is applied to that value to produce + * and effective timeout tick value. The multiplier is dependent + * on an EFuse value. Therefore, when configuring stage 0, the valid + * values for the timeout argument are: + * - If Efuse value is 0, any even number between [2,2*UINT32_MAX] + * - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX] + * - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX] + * - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX] + */ +FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) +{ + switch (stage) { + case WDT_STAGE0: + hw->wdt_config0.stg0 = behavior; + //Account of implicty multiplier applied to stage 0 timeout tick config value + hw->wdt_config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + break; + case WDT_STAGE1: + hw->wdt_config0.stg1 = behavior; + hw->wdt_config2 = timeout_ticks; + break; + case WDT_STAGE2: + hw->wdt_config0.stg2 = behavior; + hw->wdt_config3 = timeout_ticks; + break; + case WDT_STAGE3: + hw->wdt_config0.stg3 = behavior; + hw->wdt_config4 = timeout_ticks; + break; + default: + abort(); + } +} + +/** + * @brief Disable a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void rwdt_ll_disable_stage(rtc_cntl_dev_t *hw, wdt_stage_t stage) +{ + switch (stage) { + case WDT_STAGE0: + hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE1: + hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE2: + hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE3: + hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF; + break; + default: + abort(); + } +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void rwdt_ll_set_cpu_reset_length(rtc_cntl_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->wdt_config0.cpu_reset_length = length; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void rwdt_ll_set_sys_reset_length(rtc_cntl_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->wdt_config0.sys_reset_length = length; +} + +/** + * @brief Enable/Disable the RWDT flashboot mode. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void rwdt_ll_set_flashboot_en(rtc_cntl_dev_t *hw, bool enable) +{ + hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU0 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rtc_cntl_dev_t *hw, bool enable) +{ + hw->wdt_config0.procpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU1 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rtc_cntl_dev_t *hw, bool enable) +{ + hw->wdt_config0.appcpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the RWDT pause during sleep functionality + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void rwdt_ll_set_pause_in_sleep_en(rtc_cntl_dev_t *hw, bool enable) +{ + hw->wdt_config0.pause_in_slp = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable chip reset on RWDT timeout. + * + * A chip reset also resets the analog portion of the chip. It will appear as a + * POWERON reset rather than an RTC reset. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable) +{ + hw->wdt_config0.chip_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Set width of chip reset signal + * + * @param hw Start address of the peripheral registers. + * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles + */ +FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width) +{ + hw->wdt_config0.chip_reset_width = width; +} + +/** + * @brief Feed the RWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void rwdt_ll_feed(rtc_cntl_dev_t *hw) +{ + hw->wdt_feed.feed = 1; +} + +/** + * @brief Enable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void rwdt_ll_write_protect_enable(rtc_cntl_dev_t *hw) +{ + hw->wdt_wprotect = 0; +} + +/** + * @brief Disable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void rwdt_ll_write_protect_disable(rtc_cntl_dev_t *hw) +{ + hw->wdt_wprotect = RTC_CNTL_WDT_WKEY_VALUE; +} + +/** + * @brief Enable the RWDT interrupt. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT interrupt, false to disable. + */ +FORCE_INLINE_ATTR void rwdt_ll_set_intr_enable(rtc_cntl_dev_t *hw, bool enable) +{ + hw->int_ena.rtc_wdt = (enable) ? 1 : 0; +} + +/** + * @brief Check if the RWDT interrupt has been triggered + * + * @param hw Start address of the peripheral registers. + * @return True if the RWDT interrupt was triggered + */ +FORCE_INLINE_ATTR bool rwdt_ll_check_intr_status(rtc_cntl_dev_t *hw) +{ + return (hw->int_st.rtc_wdt) ? true : false; +} + +/** + * @brief Clear the RWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void rwdt_ll_clear_intr_status(rtc_cntl_dev_t *hw) +{ + hw->int_clr.rtc_wdt = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/sha_ll.h b/components/hal/esp32h2/include/hal/sha_ll.h new file mode 100644 index 0000000000..a7bc493252 --- /dev/null +++ b/components/hal/esp32h2/include/hal/sha_ll.h @@ -0,0 +1,157 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/hwcrypto_reg.h" +#include "hal/sha_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Start a new SHA block conversions (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_block(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_START_REG, 1); +} + +/** + * @brief Continue a SHA block conversion (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_block(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_CONTINUE_REG, 1); +} + +/** + * @brief Start a new SHA message conversion using DMA (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_dma(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_DMA_START_REG, 1); +} + +/** + * @brief Continue a SHA message conversion using DMA (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_dma(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); +} + +/** + * @brief Load the current hash digest to digest register + * + * @note Happens automatically on ESP32S3 + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_load(esp_sha_type sha_type) +{ +} + +/** + * @brief Sets the number of message blocks to be hashed + * + * @note DMA operation only + * + * @param num_blocks Number of message blocks to process + */ +static inline void sha_ll_set_block_num(size_t num_blocks) +{ + REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); +} + +/** + * @brief Checks if the SHA engine is currently busy hashing a block + * + * @return true SHA engine busy + * @return false SHA engine idle + */ +static inline bool sha_ll_busy(void) +{ + return REG_READ(SHA_BUSY_REG); +} + +/** + * @brief Write a text (message) block to the SHA engine + * + * @param input_text Input buffer to be written to the SHA engine + * @param block_word_len Number of words in block + */ +static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) +{ + uint32_t *data_words = (uint32_t *)input_text; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE); + + for (int i = 0; i < block_word_len; i++) { + REG_WRITE(®_addr_buf[i], data_words[i]); + } +} + +/** + * @brief Read the message digest from the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Buffer that message digest will be written to + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < digest_word_len; i++) { + digest_state_words[i] = REG_READ(SHA_H_BASE + (i * REG_WIDTH)); + } + +} + +/** + * @brief Write the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE); + + for (int i = 0; i < digest_word_len; i++) { + REG_WRITE(®_addr_buf[i], digest_state_words[i]); + } +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/sigmadelta_ll.h b/components/hal/esp32h2/include/hal/sigmadelta_ll.h new file mode 100644 index 0000000000..87f75dab9e --- /dev/null +++ b/components/hal/esp32h2/include/hal/sigmadelta_ll.h @@ -0,0 +1,73 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32 SIGMADELTA register operations + +#pragma once + +#include +#include "soc/sigmadelta_periph.h" +#include "hal/sigmadelta_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get SIGMADELTA hardware instance with giving sigmadelta num +#define SIGMADELTA_LL_GET_HW(num) (((num) == 0) ? (&SIGMADELTA) : NULL) + +/** + * @brief Set Sigma-delta enable + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param en Sigma-delta enable value + */ +static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en) +{ + hw->misc.function_clk_en = en; +} + +/** + * @brief Set Sigma-delta channel duty. + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param channel Sigma-delta channel number + * @param duty Sigma-delta duty of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90. + * The waveform is more like a random one in this range. + */ +static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty) +{ + hw->channel[channel].duty = duty; +} + +/** + * @brief Set Sigma-delta channel's clock pre-scale value. + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param channel Sigma-delta channel number + * @param val The divider of source clock, ranges from 0 to 255 + */ +static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale) +{ + hw->channel[channel].prescale = prescale; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/soc_ll.h b/components/hal/esp32h2/include/hal/soc_ll.h new file mode 100644 index 0000000000..36f2bd13b2 --- /dev/null +++ b/components/hal/esp32h2/include/hal/soc_ll.h @@ -0,0 +1,52 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void soc_ll_stall_core(int core) +{ + const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M}; + const int rtc_cntl_c1_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_S}; + const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M}; + const int rtc_cntl_c0_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_S}; + + CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1_m[core]); + SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21 << rtc_cntl_c1_s[core]); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_c0_m[core]); + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2 << rtc_cntl_c0_s[core]); +} + +static inline void soc_ll_unstall_core(int core) +{ + const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M}; + const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M}; + CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1_m[core]); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_c0_m[core]); +} + +static inline void soc_ll_reset_core(int core) +{ + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST_M); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h new file mode 100644 index 0000000000..cc1e627b96 --- /dev/null +++ b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h @@ -0,0 +1,157 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash Encryption. + +#include "soc/system_reg.h" +#include "soc/hwcrypto_reg.h" +#include "soc/soc.h" +#include "string.h" +#include "assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// Choose type of chip you want to encrypt manully +typedef enum +{ + FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip. + PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip. +} flash_encrypt_ll_type_t; + +/** + * Enable the flash encryption function under spi boot mode and download boot mode. + */ +static inline void spi_flash_encrypt_ll_enable(void) +{ + REG_SET_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, + SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | + SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); +} + +/* + * Disable the flash encryption mode. + */ +static inline void spi_flash_encrypt_ll_disable(void) +{ + REG_CLR_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, + SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); +} + +/** + * Choose type of chip you want to encrypt manully + * + * @param type The type of chip to be encrypted + * + * @note The hardware currently support flash encryption. + */ +static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) +{ + // Our hardware only support flash encryption + assert(type == FLASH_ENCRYPTION_MANU); + REG_WRITE(AES_XTS_DESTINATION_REG, type); +} + +/** + * Configure the data size of a single encryption. + * + * @param block_size Size of the desired block. + */ +static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size) +{ + // Desired block should not be larger than the block size. + REG_WRITE(AES_XTS_SIZE_REG, size >> 5); +} + +/** + * Save 32-bit piece of plaintext. + * + * @param address the address of written flash partition. + * @param buffer Buffer to store the input data. + * @param size Buffer size. + * + */ +static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size) +{ + uint32_t plaintext_offs = (address % 64); + memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size); +} + +/** + * Copy the flash address to XTS_AES physical address + * + * @param flash_addr flash address to write. + */ +static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) +{ + REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); +} + +/** + * Start flash encryption + */ +static inline void spi_flash_encrypt_ll_calculate_start(void) +{ + REG_WRITE(AES_XTS_TRIGGER_REG, 1); +} + +/** + * Wait for flash encryption termination + */ +static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) +{ + while(REG_READ(AES_XTS_STATE_REG) == 0x1) { + } +} + +/** + * Finish the flash encryption and make encrypted result accessible to SPI. + */ +static inline void spi_flash_encrypt_ll_done(void) +{ + REG_WRITE(AES_XTS_RELEASE_REG, 1); + while(REG_READ(AES_XTS_STATE_REG) != 0x3) { + } +} + +/** + * Set to destroy encrypted result + */ +static inline void spi_flash_encrypt_ll_destroy(void) +{ + REG_WRITE(AES_XTS_DESTROY_REG, 1); +} + +/** + * Check if is qualified to encrypt the buffer + * + * @param address the address of written flash partition. + * @param length Buffer size. + */ +static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) +{ + return ((address % length) == 0) ? true : false; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/spi_flash_ll.h b/components/hal/esp32h2/include/hal/spi_flash_ll.h new file mode 100644 index 0000000000..5508d161e0 --- /dev/null +++ b/components/hal/esp32h2/include/hal/spi_flash_ll.h @@ -0,0 +1,111 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include "gpspi_flash_ll.h" +#include "spimem_flash_ll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// For esp32s2, spimem is equivalent to traditional spi peripherals found +// in esp32. Let the spi flash clock reg definitions reflect this. +#define SPI_FLASH_LL_CLKREG_VAL_5MHZ {.spimem=SPIMEM_FLASH_LL_CLKREG_VAL_5MHZ} +#define SPI_FLASH_LL_CLKREG_VAL_10MHZ {.spimem=SPIMEM_FLASH_LL_CLKREG_VAL_10MHZ} +#define SPI_FLASH_LL_CLKREG_VAL_20MHZ {.spimem=SPIMEM_FLASH_LL_CLKREG_VAL_20MHZ} +#define SPI_FLASH_LL_CLKREG_VAL_26MHZ {.spimem=SPIMEM_FLASH_LL_CLKREG_VAL_26MHZ} +#define SPI_FLASH_LL_CLKREG_VAL_40MHZ {.spimem=SPIMEM_FLASH_LL_CLKREG_VAL_40MHZ} +#define SPI_FLASH_LL_CLKREG_VAL_80MHZ {.spimem=SPIMEM_FLASH_LL_CLKREG_VAL_80MHZ} + +#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \ + : gpspi_flash_ll_get_hw(host_id))) + +#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \ + if (dev_id < 0) {\ + dev_id = gpspi_flash_ll_hw_get_id(dev);\ + }\ + dev_id; \ + }) + + +typedef union { + gpspi_flash_ll_clock_reg_t gpspi; + spimem_flash_ll_clock_reg_t spimem; +} spi_flash_ll_clock_reg_t; + +#ifdef GPSPI_BUILD +#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev) +#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev) +#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len) +#define spi_flash_ll_set_buffer_data(dev, buffer, len) gpspi_flash_ll_set_buffer_data((spi_dev_t*)dev, buffer, len) +#define spi_flash_ll_user_start(dev) gpspi_flash_ll_user_start((spi_dev_t*)dev) +#define spi_flash_ll_host_idle(dev) gpspi_flash_ll_host_idle((spi_dev_t*)dev) +#define spi_flash_ll_read_phase(dev) gpspi_flash_ll_read_phase((spi_dev_t*)dev) +#define spi_flash_ll_set_cs_pin(dev, pin) gpspi_flash_ll_set_cs_pin((spi_dev_t*)dev, pin) +#define spi_flash_ll_set_read_mode(dev, read_mode) gpspi_flash_ll_set_read_mode((spi_dev_t*)dev, read_mode) +#define spi_flash_ll_set_clock(dev, clk) gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk) +#define spi_flash_ll_set_miso_bitlen(dev, bitlen) gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_set_command(dev, cmd, bitlen) gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen) +#define spi_flash_ll_set_addr_bitlen(dev, bitlen) gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_get_addr_bitlen(dev) gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev) +#define spi_flash_ll_set_address(dev, addr) gpspi_flash_ll_set_address((spi_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen) +#define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy) +#define spi_flash_ll_set_dummy_out(dev, en, lev) gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev) +#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n) +#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time) +#else +#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev) +#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_chip(dev) spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_sector(dev) spimem_flash_ll_erase_sector((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_block(dev) spimem_flash_ll_erase_block((spi_mem_dev_t*)dev) +#define spi_flash_ll_set_write_protect(dev, wp) spimem_flash_ll_set_write_protect((spi_mem_dev_t*)dev, wp) +#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) spimem_flash_ll_get_buffer_data((spi_mem_dev_t*)dev, buffer, read_len) +#define spi_flash_ll_set_buffer_data(dev, buffer, len) spimem_flash_ll_set_buffer_data((spi_mem_dev_t*)dev, buffer, len) +#define spi_flash_ll_program_page(dev, buffer, len) spimem_flash_ll_program_page((spi_mem_dev_t*)dev, buffer, len) +#define spi_flash_ll_user_start(dev) spimem_flash_ll_user_start((spi_mem_dev_t*)dev) +#define spi_flash_ll_host_idle(dev) spimem_flash_ll_host_idle((spi_mem_dev_t*)dev) +#define spi_flash_ll_read_phase(dev) spimem_flash_ll_read_phase((spi_mem_dev_t*)dev) +#define spi_flash_ll_set_cs_pin(dev, pin) spimem_flash_ll_set_cs_pin((spi_mem_dev_t*)dev, pin) +#define spi_flash_ll_set_read_mode(dev, read_mode) spimem_flash_ll_set_read_mode((spi_mem_dev_t*)dev, read_mode) +#define spi_flash_ll_set_clock(dev, clk) spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk) +#define spi_flash_ll_set_miso_bitlen(dev, bitlen) spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_set_command(dev, cmd, bitlen) spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen) +#define spi_flash_ll_set_addr_bitlen(dev, bitlen) spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_get_addr_bitlen(dev) spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev) +#define spi_flash_ll_set_address(dev, addr) spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen) +#define spi_flash_ll_set_dummy(dev, dummy) spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy) +#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) +#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) +#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h new file mode 100644 index 0000000000..6719905e09 --- /dev/null +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -0,0 +1,1090 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for SPI register operations + +#pragma once + +#include //for abs() +#include +#include "hal/hal_defs.h" +#include "esp_types.h" +#include "soc/spi_periph.h" +#include "esp32c3/rom/lldesc.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Interrupt not used. Don't use in app. +#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA) +/// Swap the bit order to its correct place to send +#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len)) +/// This is the expected clock frequency +#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000) +#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2) + +/** + * The data structure holding calculated clock configuration. Since the + * calculation needs long time, it should be calculated during initialization and + * stored somewhere to be quickly used. + */ +typedef uint32_t spi_ll_clock_val_t; +typedef spi_dev_t spi_dma_dev_t; + +/** IO modes supported by the master. */ +typedef enum { + SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases + SPI_LL_IO_MODE_DIO, ///< 2-bit mode for address and data phases, 1-bit mode for command phase + SPI_LL_IO_MODE_DUAL, ///< 2-bit mode for data phases only, 1-bit mode for command and address phases + SPI_LL_IO_MODE_QIO, ///< 4-bit mode for address and data phases, 1-bit mode for command phase + SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases +} spi_ll_io_mode_t; + +// Type definition of all supported interrupts +typedef enum { + SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done + SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD. + SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD. + SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD. + SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD. + SPI_LL_INTR_CMD7 = BIT(10), ///< Has received CMD7 command. Only available in slave HD. + SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD. + SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD. + SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD. + SPI_LL_INTR_SEG_DONE = BIT(14), +} spi_ll_intr_t; +FLAG_ATTR(spi_ll_intr_t) + +// Flags for conditions under which the transaction length should be recorded +typedef enum { + SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded + SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded + SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded + SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded +} spi_ll_trans_len_cond_t; +FLAG_ATTR(spi_ll_trans_len_cond_t) + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Initialize SPI peripheral (master). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_master_init(spi_dev_t *hw) +{ + //Reset timing + hw->user1.cs_setup_time = 0; + hw->user1.cs_hold_time = 0; + + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + //Disable unneeded ints + hw->slave.val = 0; + hw->user.val = 0; + + hw->clk_gate.clk_en = 1; + hw->clk_gate.mst_clk_active = 1; + hw->clk_gate.mst_clk_sel = 1; + + hw->dma_conf.val = 0; + hw->dma_conf.tx_seg_trans_clr_en = 1; + hw->dma_conf.rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_seg_trans_en = 0; +} + +/** + * Initialize SPI peripheral (slave). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_init(spi_dev_t *hw) +{ + //Configure slave + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 1; //we only support full duplex + hw->user.sio = 0; + hw->slave.slave_mode = 1; + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + hw->dma_conf.dma_seg_trans_en = 0; + + //Disable unneeded ints + hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; +} + +/** + * Initialize SPI peripheral (slave half duplex mode) + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_hd_init(spi_dev_t *hw) +{ + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 0; + hw->user.sio = 0; + + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + hw->slave.slave_mode = 1; +} + +/** + * Check whether user-defined transaction is done. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if transaction is done, otherwise false. + */ +static inline bool spi_ll_usr_is_done(spi_dev_t *hw) +{ + return hw->dma_int_raw.trans_done; +} + +/** + * Trigger start of user-defined transaction for master. + * The synchronization between two clock domains is required in ESP32-S3 + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_master_user_start(spi_dev_t *hw) +{ + hw->cmd.update = 1; + while (hw->cmd.update); + hw->cmd.usr = 1; +} + +/** + * Trigger start of user-defined transaction for slave. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_user_start(spi_dev_t *hw) +{ + hw->cmd.usr = 1; +} + +/** + * Get current running command bit-mask. (Preview) + * + * @param hw Beginning address of the peripheral registers. + * + * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. + */ +static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) +{ + return hw->cmd.val; +} + +/** + * Reset the slave peripheral before next transaction. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_reset(spi_dev_t *hw) +{ + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; +} + +/** + * Reset SPI CPU TX FIFO + * + * On ESP32C3, this function is not seperated + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.buf_afifo_rst = 1; + hw->dma_conf.buf_afifo_rst = 0; +} + +/** + * Reset SPI CPU RX FIFO + * + * On ESP32C3, this function is not seperated + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; +} + +/** + * Reset SPI DMA TX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.dma_afifo_rst = 1; + hw->dma_conf.dma_afifo_rst = 0; +} + +/** + * Reset SPI DMA RX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; +} + +/** + * Clear in fifo full error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) +{ + hw->dma_int_clr.infifo_full_err = 1; +} + +/** + * Clear out fifo empty error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) +{ + hw->dma_int_clr.outfifo_empty_err = 1; +} + +/*------------------------------------------------------------------------------ + * DMA + *----------------------------------------------------------------------------*/ +/** + * Enable/Disable RX DMA (Peripherals->DMA->RAM) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.dma_rx_ena = enable; +} + +/** + * Enable/Disable TX DMA (RAM->DMA->Peripherals) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.dma_tx_ena = enable; +} + +/** + * Configuration of RX DMA EOF interrupt generation way + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ +static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.rx_eof_en = enable; +} + +/*------------------------------------------------------------------------------ + * Buffer + *----------------------------------------------------------------------------*/ +/** + * Write to SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_send Address of the data to be written to the hardware data buffer. + * @param bitlen Length to write, in bits. + */ +static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Use memcpy to get around alignment issues for txdata + uint32_t word; + memcpy(&word, &buffer_to_send[x / 8], 4); + hw->data_buf[(x / 32)] = word; + } +} + +/** + * Write to SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be written + * @param data Address of the data to be written to the hardware data buffer. + * @param len Length to write, in bytes. + */ +static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) +{ + assert(byte_id+len <= 64); + assert(len > 0); + assert(byte_id >= 0); + + while (len > 0) { + uint32_t word; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) copy_len = len; + + //read-modify-write + if (copy_len != 4) word = hw->data_buf[byte_id / 4]; //read + memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify + hw->data_buf[byte_id / 4] = word; //write + + data += copy_len; + byte_id += copy_len; + len -= copy_len; + } +} + +/** + * Read from SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_rcv Address of a buffer to read data from hardware data buffer + * @param bitlen Length to read, in bits. + */ +static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Do a memcpy to get around possible alignment issues in rx_buffer + uint32_t word = hw->data_buf[x / 32]; + int len = bitlen - x; + if (len > 32) { + len = 32; + } + memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + } +} + +/** + * Read from SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be read + * @param data Address of a buffer to read data from hardware data buffer + * @param len Length to read, in bytes. + */ +static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) +{ + while (len > 0) { + uint32_t word = hw->data_buf[byte_id / 4]; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) copy_len = len; + + memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); + byte_id += copy_len; + out_data += copy_len; + len -= copy_len; + } +} + +/*------------------------------------------------------------------------------ + * Configs: mode + *----------------------------------------------------------------------------*/ +/** + * Enable/disable the postive-cs feature. + * + * @param hw Beginning address of the peripheral registers. + * @param cs One of the CS (0-2) to enable/disable the feature. + * @param pos_cs True to enable the feature, otherwise disable (default). + */ +static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) +{ + if (pos_cs) { + hw->misc.master_cs_pol |= (1 << cs); + } else { + hw->misc.master_cs_pol &= ~(1 << cs); + } +} + +/** + * Enable/disable the LSBFIRST feature for TX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if LSB of TX data to be sent first, otherwise MSB is sent first (default). + */ +static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + hw->ctrl.wr_bit_order = lsbfirst; +} + +/** + * Enable/disable the LSBFIRST feature for RX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if first bit received as LSB, otherwise as MSB (default). + */ +static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + hw->ctrl.rd_bit_order = lsbfirst; +} + +/** + * Set SPI mode for the peripheral as master. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) +{ + //Configure polarity + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 1; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 0; + } +} + +/** + * Set SPI mode for the peripheral as slave. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) +{ + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 0; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 1; + } + hw->slave.rsck_data_out = 0; +} + +/** + * Set SPI to work in full duplex or half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param half_duplex True to work in half duplex mode, otherwise in full duplex mode. + */ +static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) +{ + hw->user.doutdin = !half_duplex; +} + +/** + * Set SPI to work in SIO mode or not. + * + * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode. + * + * @param hw Beginning address of the peripheral registers. + * @param sio_mode True to work in SIO mode, otherwise false. + */ +static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) +{ + hw->user.sio = sio_mode; +} + +/** + * Configure the io mode for the master to work at. + * + * @param hw Beginning address of the peripheral registers. + * @param io_mode IO mode to work at, see ``spi_ll_io_mode_t``. + */ +static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode) +{ + if (io_mode == SPI_LL_IO_MODE_DIO || io_mode == SPI_LL_IO_MODE_DUAL) { + hw->ctrl.fcmd_dual = (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0; + hw->ctrl.faddr_dual = (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0; + hw->ctrl.fread_dual = 1; + hw->user.fwrite_dual = 1; + hw->ctrl.fcmd_quad = 0; + hw->ctrl.faddr_quad = 0; + hw->ctrl.fread_quad = 0; + hw->user.fwrite_quad = 0; + } else if (io_mode == SPI_LL_IO_MODE_QIO || io_mode == SPI_LL_IO_MODE_QUAD) { + hw->ctrl.fcmd_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0; + hw->ctrl.faddr_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0; + hw->ctrl.fread_quad = 1; + hw->user.fwrite_quad = 1; + hw->ctrl.fcmd_dual = 0; + hw->ctrl.faddr_dual = 0; + hw->ctrl.fread_dual = 0; + hw->user.fwrite_dual = 0; + } else { + hw->ctrl.fcmd_dual = 0; + hw->ctrl.faddr_dual = 0; + hw->ctrl.fread_dual = 0; + hw->user.fwrite_dual = 0; + hw->ctrl.fcmd_quad = 0; + hw->ctrl.faddr_quad = 0; + hw->ctrl.fread_quad = 0; + hw->user.fwrite_quad = 0; + } +} + +/** + * Set the SPI slave to work in segment transaction mode + * + * @param hw Beginning address of the peripheral registers. + * @param seg_trans True to work in seg mode, otherwise false. + */ +static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) +{ + hw->dma_conf.dma_seg_trans_en = seg_trans; + hw->dma_conf.rx_eof_en = seg_trans; +} + +/** + * Select one of the CS to use in current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param cs_id The cs to use, 0-2, otherwise none of them is used. + */ +static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) +{ + hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; + hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; + hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; +} + +/*------------------------------------------------------------------------------ + * Configs: parameters + *----------------------------------------------------------------------------*/ +/** + * Set the clock for master by stored value. + * + * @param hw Beginning address of the peripheral registers. + * @param val Stored clock configuration calculated before (by ``spi_ll_cal_clock``). + */ +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) +{ + hw->clock.val = *(uint32_t *)val; +} + +/** + * Get the frequency of given dividers. Don't use in app. + * + * @param fapb APB clock of the system. + * @param pre Pre devider. + * @param n Main divider. + * + * @return Frequency of given dividers. + */ +static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) +{ + return (fapb / (pre * n)); +} + +/** + * Calculate the nearest frequency avaliable for master. + * + * @param fapb APB clock of the system. + * @param hz Frequncy desired. + * @param duty_cycle Duty cycle desired. + * @param out_reg Output address to store the calculated clock configurations for the return frequency. + * + * @return Actual (nearest) frequency. + */ +static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) +{ + typeof(GPSPI2.clock) reg; + int eff_clk; + + //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. + if (hz > ((fapb / 4) * 3)) { + //Using Fapb directly will give us the best result here. + reg.clkcnt_l = 0; + reg.clkcnt_h = 0; + reg.clkcnt_n = 0; + reg.clkdiv_pre = 0; + reg.clk_equ_sysclk = 1; + eff_clk = fapb; + } else { + //For best duty cycle resolution, we want n to be as close to 32 as possible, but + //we also need a pre/n combo that gets us as close as possible to the intended freq. + //To do this, we bruteforce n and calculate the best pre to go along with that. + //If there's a choice between pre/n combos that give the same result, use the one + //with the higher n. + int pre, n, h, l; + int bestn = -1; + int bestpre = -1; + int besterr = 0; + int errval; + for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. + //Effectively, this does pre=round((fapb/n)/hz). + pre = ((fapb / n) + (hz / 2)) / hz; + if (pre <= 0) { + pre = 1; + } + if (pre > 16) { + pre = 16; + } + errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); + if (bestn == -1 || errval <= besterr) { + besterr = errval; + bestn = n; + bestpre = pre; + } + } + + n = bestn; + pre = bestpre; + l = n; + //This effectively does round((duty_cycle*n)/256) + h = (duty_cycle * n + 127) / 256; + if (h <= 0) { + h = 1; + } + + reg.clk_equ_sysclk = 0; + reg.clkcnt_n = n - 1; + reg.clkdiv_pre = pre - 1; + reg.clkcnt_h = h - 1; + reg.clkcnt_l = l - 1; + eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); + } + if (out_reg != NULL) { + *(uint32_t *)out_reg = reg.val; + } + return eff_clk; +} + +/** + * Calculate and set clock for SPI master according to desired parameters. + * + * This takes long, suggest to calculate the configuration during + * initialization by ``spi_ll_master_cal_clock`` and store the result, then + * configure the clock by stored value when used by + * ``spi_ll_msater_set_clock_by_reg``. + * + * @param hw Beginning address of the peripheral registers. + * @param fapb APB clock of the system. + * @param hz Frequncy desired. + * @param duty_cycle Duty cycle desired. + * + * @return Actual frequency that is used. + */ +static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) +{ + spi_ll_clock_val_t reg_val; + int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); + spi_ll_master_set_clock_by_reg(hw, ®_val); + return freq; +} + +/** + * Set the mosi delay after the output edge to the signal. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ +} + +/** + * Set the miso delay applied to the input signal before the internal peripheral. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ +} + +/** + * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock. + * + * @param hw Beginning address of the peripheral registers. + * @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase. + */ +static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) +{ + hw->user1.cs_hold_time = hold - 1; + hw->user.cs_hold = hold ? 1 : 0; +} + +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * Note ESP32 doesn't support to use this feature when command/address phases + * are used in full duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ +static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) +{ + hw->user1.cs_setup_time = setup - 1; + hw->user.cs_setup = setup ? 1 : 0; +} + +/*------------------------------------------------------------------------------ + * Configs: data + *----------------------------------------------------------------------------*/ +/** + * Set the output length (master). + * This should be called before master setting MISO(input) length + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen output length, in bits. + */ +static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) +{ + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the input length (master). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen input length, in bits. + */ +static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) +{ + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the maximum input length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Input length, in bits. + */ +static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + spi_ll_set_mosi_bitlen(hw, bitlen); +} + +/** + * Set the maximum output length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Output length, in bits. + */ +static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + spi_ll_set_mosi_bitlen(hw, bitlen); +} + +/** + * Set the length of command phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * command phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of command phase, in bits. 0 to disable the command phase. + */ +static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) +{ + hw->user2.usr_command_bitlen = bitlen - 1; + hw->user.usr_command = bitlen ? 1 : 0; +} + +/** + * Set the length of address phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * address phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of address phase, in bits. 0 to disable the address phase. + */ +static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) +{ + hw->user1.usr_addr_bitlen = bitlen - 1; + hw->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the address to the right place. + * + * @param hw Beginning address of the peripheral registers. + * @param address Address to set + * @param addrlen Length of the address phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) +{ + if (lsbfirst) { + /* The output address start from the LSB of the highest byte, i.e. + * addr[24] -> addr[31] + * ... + * addr[0] -> addr[7] + * So swap the byte order to let the LSB sent first. + */ + addr = HAL_SWAP32(addr); + //otherwise only addr register is sent + hw->addr = addr; + } else { + // shift the address to MSB of addr register. + // output address will be sent from MSB to LSB of addr register + hw->addr = addr << (32 - addrlen); + } +} + +/** + * Set the command value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the command to the right place. + * + * @param hw Beginning command of the peripheral registers. + * @param command Command to set + * @param addrlen Length of the command phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) +{ + if (lsbfirst) { + // The output command start from bit0 to bit 15, kept as is. + hw->user2.usr_command_value = cmd; + } else { + /* Output command will be sent from bit 7 to 0 of command_value, and + * then bit 15 to 8 of the same register field. Shift and swap to send + * more straightly. + */ + hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen); + } +} + +/** + * Set dummy clocks to output before RX phase (master), or clocks to skip + * before the data phase and after the address phase (slave). + * + * Note this phase is also used to compensate RX timing in half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. + */ +static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) +{ + hw->user.usr_dummy = dummy_n ? 1 : 0; + hw->user1.usr_dummy_cyclelen = dummy_n - 1; +} + +/** + * Enable/disable the RX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if RX phase exist, otherwise false. + */ +static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) +{ + hw->user.usr_miso = enable; +} + +/** + * Enable/disable the TX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if TX phase exist, otherwise false. + */ +static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) +{ + hw->user.usr_mosi = enable; +} + +/** + * Get the received bit length of the slave. + * + * @param hw Beginning address of the peripheral registers. + * + * @return Received bits of the slave. + */ +static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) +{ + return hw->slave1.data_bitlen; +} + +/*------------------------------------------------------------------------------ + * Interrupts + *----------------------------------------------------------------------------*/ +//helper macros to generate code for each interrupts +#define FOR_EACH_ITEM(op, list) do { list(op) } while(0) +#define INTR_LIST(item) \ + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done=1) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done=1) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done=1) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done=1) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done=1) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done=1) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1) + + +static inline void spi_ll_enable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + FOR_EACH_ITEM(ENA_INTR, INTR_LIST); +#undef ENA_INTR +} + +static inline void spi_ll_disable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + FOR_EACH_ITEM(DIS_INTR, INTR_LIST); +#undef DIS_INTR +} + +static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define SET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit)) hw->st_reg = 1; + FOR_EACH_ITEM(SET_INTR, INTR_LIST); +#undef SET_INTR +} + +static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define CLR_INTR(intr_bit, _, __, clr_reg) if (intr_mask & (intr_bit)) hw->clr_reg; + FOR_EACH_ITEM(CLR_INTR, INTR_LIST); +#undef CLR_INTR +} + +static inline bool spi_ll_get_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; + FOR_EACH_ITEM(GET_INTR, INTR_LIST); + return false; +#undef GET_INTR +} + +#undef FOR_EACH_ITEM +#undef INTR_LIST + +/** + * Disable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_disable_int(spi_dev_t *hw) +{ + hw->dma_int_ena.trans_done = 0; +} + +/** + * Clear the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +{ + hw->dma_int_raw.trans_done = 0; +} + +/** + * Set the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_int_stat(spi_dev_t *hw) +{ + hw->dma_int_raw.trans_done = 1; +} + +/** + * Enable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_enable_int(spi_dev_t *hw) +{ + hw->dma_int_ena.trans_done = 1; +} + +/*------------------------------------------------------------------------------ + * Slave HD + *----------------------------------------------------------------------------*/ +static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t* hw, spi_ll_trans_len_cond_t cond_mask) +{ + hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; +} + +static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t* hw) +{ + return hw->slave1.data_bitlen / 8; +} + +static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw) +{ + return hw->slave1.last_addr; +} + +#undef SPI_LL_RST_MASK +#undef SPI_LL_UNUSED_INT_MASK + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h new file mode 100644 index 0000000000..7641c3d723 --- /dev/null +++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h @@ -0,0 +1,560 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include +#include // For MIN/MAX +#include +#include + +#include "soc/spi_periph.h" +#include "hal/spi_types.h" +#include "hal/spi_flash_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL )) +#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1) + +typedef typeof(SPIMEM1.clock) spimem_flash_ll_clock_reg_t; + +//Supported clock register values +#define SPIMEM_FLASH_LL_CLKREG_VAL_5MHZ ((spimem_flash_ll_clock_reg_t){.val=0x000F070F}) ///< Clock set to 5 MHz +#define SPIMEM_FLASH_LL_CLKREG_VAL_10MHZ ((spimem_flash_ll_clock_reg_t){.val=0x00070307}) ///< Clock set to 10 MHz +#define SPIMEM_FLASH_LL_CLKREG_VAL_20MHZ ((spimem_flash_ll_clock_reg_t){.val=0x00030103}) ///< Clock set to 20 MHz +#define SPIMEM_FLASH_LL_CLKREG_VAL_26MHZ ((spimem_flash_ll_clock_reg_t){.val=0x00020002}) ///< Clock set to 26 MHz +#define SPIMEM_FLASH_LL_CLKREG_VAL_40MHZ ((spimem_flash_ll_clock_reg_t){.val=0x00010001}) ///< Clock set to 40 MHz +#define SPIMEM_FLASH_LL_CLKREG_VAL_80MHZ ((spimem_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Reset peripheral registers before configuration and starting control + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev) +{ + dev->user.val = 0; + dev->ctrl.val = 0; +} + +/** + * Check whether the previous operation is done. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if last command is done, otherwise false. + */ +static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev) +{ + return (dev->cmd.val == 0); +} + +/** + * Erase the flash chip. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_chip(spi_mem_dev_t *dev) +{ + dev->cmd.flash_ce = 1; +} + +/** + * Erase the sector, the address should be set by spimem_flash_ll_set_address. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev) +{ + dev->ctrl.val = 0; + dev->cmd.flash_se = 1; +} + +/** + * Erase the block, the address should be set by spimem_flash_ll_set_address. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev) +{ + dev->cmd.flash_be = 1; +} + +/** + * Suspend erase/program operation. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev) +{ + dev->flash_sus_ctrl.flash_pes = 1; +} + +/** + * Resume suspended erase/program operation. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev) +{ + dev->flash_sus_ctrl.flash_per = 1; +} + +/** + * Initialize auto suspend mode, and esp32c3 doesn't support disable auto-suspend. + * + * @param dev Beginning address of the peripheral registers. + * @param auto_sus Enable/disable Flash Auto-Suspend. + */ +static inline void spimem_flash_ll_auto_suspend_init(spi_mem_dev_t *dev, bool auto_sus) +{ + dev->flash_sus_ctrl.flash_pes_en = auto_sus; +} + +/** + * Initialize auto resume mode + * + * @param dev Beginning address of the peripheral registers. + * @param auto_res Enable/Disable Flash Auto-Resume. + * + */ +static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool auto_res) +{ + dev->flash_sus_ctrl.pes_per_en = auto_res; +} + +/** + * Setup the flash suspend command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_cmd Flash suspend command. + * + */ +static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd) +{ + dev->flash_sus_cmd.flash_pes_command = sus_cmd; +} + +/** + * Setup the flash resume command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param res_cmd Flash resume command. + * + */ +static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd) +{ + dev->flash_sus_cmd.flash_per_command = res_cmd; +} + +/** + * Setup the flash read suspend status command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param pesr_cmd Flash read suspend status command. + * + */ +static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd) +{ + dev->flash_sus_cmd.wait_pesr_command = pesr_cmd; +} + +/** + * Setup to check SUS/SUS1/SUS2 to ensure the suspend status of flashs. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_check_sus_en 1: enable, 0: disable. + * + */ +static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en) +{ + dev->flash_sus_ctrl.sus_timeout_cnt = 5; + dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en; +} + +/** + * Setup to check SUS/SUS1/SUS2 to ensure the resume status of flashs. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_check_sus_en 1: enable, 0: disable. + * + */ +static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en) +{ + dev->flash_sus_ctrl.sus_timeout_cnt = 5; + dev->flash_sus_ctrl.per_end_en = res_check_sus_en; +} + +/** + * Set 8 bit command to read suspend status + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf) +{ + dev->flash_sus_ctrl.frd_sus_2b = 0; + dev->flash_sus_ctrl.pesr_end_msk = sus_conf; +} + +/** + * Initialize auto wait idle mode + * + * @param dev Beginning address of the peripheral registers. + * @param auto_waiti Enable/disable auto wait-idle function + */ +static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) +{ + dev->flash_waiti_ctrl.waiti_cmd = 0x05; + dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti; + dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; +} + +/** + * Return the suspend status of erase or program operations. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if suspended, otherwise false. + */ +static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev) +{ + return dev->sus_status.flash_sus; +} + +/** + * Enable/disable write protection for the flash chip. + * + * @param dev Beginning address of the peripheral registers. + * @param wp true to enable the protection, false to disable (write enable). + */ +static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp) +{ + if (wp) { + dev->cmd.flash_wrdi = 1; + } else { + dev->cmd.flash_wren = 1; + } +} + +/** + * Get the read data from the buffer after ``spimem_flash_ll_read`` is done. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer to hold the output data + * @param read_len Length to get out of the buffer + */ +static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len) +{ + if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { + // If everything is word-aligned, do a faster memcpy + memcpy(buffer, (void *)dev->data_buf, read_len); + } else { + // Otherwise, slow(er) path copies word by word + int copy_len = read_len; + for (int i = 0; i < (read_len + 3) / 4; i++) { + int word_len = MIN(sizeof(uint32_t), copy_len); + uint32_t word = dev->data_buf[i]; + memcpy(buffer, &word, word_len); + buffer = (void *)((intptr_t)buffer + word_len); + copy_len -= word_len; + } + } +} + +/** + * Set the data to be written in the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data + * @param length Length of data in bytes. + */ +static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length) +{ + // Load data registers, word at a time + int num_words = (length + 3) / 4; + for (int i = 0; i < num_words; i++) { + uint32_t word = 0; + uint32_t word_len = MIN(length, sizeof(word)); + memcpy(&word, buffer, word_len); + dev->data_buf[i] = word; + length -= word_len; + buffer = (void *)((intptr_t)buffer + word_len); + } +} + + +/** + * Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before + * this to set the address to program. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data to program + * @param length Length to program. + */ +static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *buffer, uint32_t length) +{ + dev->user.usr_dummy = 0; + spimem_flash_ll_set_buffer_data(dev, buffer, length); + dev->cmd.flash_pp = 1; +} + +/** + * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, + * should be configured before this is called. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev) +{ + dev->cmd.usr = 1; +} + +/** + * Check whether the host is idle to perform new commands. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if the host is idle, otherwise false + */ +static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) +{ + return dev->fsm.spi0_mst_st == 0; +} + +/** + * Set phases for user-defined transaction to read + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) +{ + typeof (dev->user) user = { + .usr_command = 1, + .usr_mosi = 0, + .usr_miso = 1, + .usr_addr = 1, + }; + dev->user = user; +} +/*------------------------------------------------------------------------------ + * Configs + *----------------------------------------------------------------------------*/ +/** + * Select which pin to use for the flash + * + * @param dev Beginning address of the peripheral registers. + * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + */ +static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) +{ + dev->misc.cs0_dis = (pin == 0) ? 0 : 1; + dev->misc.cs1_dis = (pin == 1) ? 0 : 1; +} + +/** + * Set the read io mode. + * + * @param dev Beginning address of the peripheral registers. + * @param read_mode I/O mode to use in the following transactions. + */ +static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) +{ + typeof (dev->ctrl) ctrl = dev->ctrl; + ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); + ctrl.val |= SPI_MEM_FASTRD_MODE_M; + switch (read_mode) { + case SPI_FLASH_FASTRD: + //the default option + break; + case SPI_FLASH_QIO: + ctrl.fread_qio = 1; + break; + case SPI_FLASH_QOUT: + ctrl.fread_quad = 1; + break; + case SPI_FLASH_DIO: + ctrl.fread_dio = 1; + break; + case SPI_FLASH_DOUT: + ctrl.fread_dual = 1; + break; + case SPI_FLASH_SLOWRD: + ctrl.fastrd_mode = 0; + break; + default: + abort(); + } + dev->ctrl = ctrl; +} + +/** + * Set clock frequency to work at. + * + * @param dev Beginning address of the peripheral registers. + * @param clock_val pointer to the clock value to set + */ +static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll_clock_reg_t *clock_val) +{ + dev->clock = *clock_val; +} + +/** + * Set the input length, in bits. + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of input, in bits. + */ +static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_miso = bitlen > 0; + dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0; +} + +/** + * Set the output length, in bits (not including command, address and dummy + * phases) + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of output, in bits. + */ +static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_mosi = bitlen > 0; + dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0; +} + +/** + * Set the command. + * + * @param dev Beginning address of the peripheral registers. + * @param command Command to send + * @param bitlen Length of the command + */ +static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen) +{ + dev->user.usr_command = 1; + typeof(dev->user2) user2 = { + .usr_command_value = command, + .usr_command_bitlen = (bitlen - 1), + }; + dev->user2 = user2; +} + +/** + * Get the address length that is set in register, in bits. + * + * @param dev Beginning address of the peripheral registers. + * + */ +static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev) +{ + return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; +} + +/** + * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of the address, in bits + */ +static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user1.usr_addr_bitlen = (bitlen - 1); + dev->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr) +{ + dev->addr = addr; +} + +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + (void)bitlen; + spimem_flash_ll_set_address(dev, addr); +} + +/** + * Set the length of dummy cycles. + * + * @param dev Beginning address of the peripheral registers. + * @param dummy_n Cycles of dummy phases + */ +static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) +{ + dev->user.usr_dummy = dummy_n ? 1 : 0; + dev->user1.usr_dummy_cyclelen = dummy_n - 1; +} + +/** + * Set D/Q output level during dummy phase + * + * @param dev Beginning address of the peripheral registers. + * @param out_en whether to enable IO output for dummy phase + * @param out_level dummy output level + */ +static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t out_en, uint32_t out_lev) +{ + dev->ctrl.fdummy_out = out_en; + dev->ctrl.q_pol = out_lev; + dev->ctrl.d_pol = out_lev; +} + +/** + * Set CS hold time. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n CS hold time config used by the host. + */ +static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) +{ + dev->ctrl2.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + +static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) +{ + dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + dev->ctrl2.cs_setup_time = cs_setup_time - 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/systimer_ll.h b/components/hal/esp32h2/include/hal/systimer_ll.h new file mode 100644 index 0000000000..9aa0c32da5 --- /dev/null +++ b/components/hal/esp32h2/include/hal/systimer_ll.h @@ -0,0 +1,164 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include +#include "soc/systimer_struct.h" + +#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time +#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick +#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0 +#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time + +#define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us + +#ifdef __cplusplus +extern "C" { +#endif + +// All these functions get invoked either from ISR or HAL that linked to IRAM. +// Always inline these functions even no gcc optimization is applied. + +/******************* Clock *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) +{ + dev->conf.clk_en = en; +} + +/******************* Counter *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) +{ + if (en) { + dev->conf.val |= 1 << (30 - counter_id); + } else { + dev->conf.val &= ~(1 << (30 - counter_id)); + } +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) +{ + if (can) { + dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id); + } else { + dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id)); + } +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) +{ + dev->unit_op[counter_id].timer_unit_update = 1; +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_op[counter_id].timer_unit_value_valid; +} + +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) +{ + dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32; + dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_val[counter_id].lo.timer_unit_value_lo; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_val[counter_id].hi.timer_unit_value_hi; +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) +{ + dev->unit_load[counter_id].val = 0x01; +} + +/******************* Alarm *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) +{ + dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; + dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF; +} + +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) +{ + return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; +} + +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) +{ + dev->target_conf[alarm_id].target_timer_unit_sel = counter_id; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->target_conf[alarm_id].target_period_mode = 0; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->target_conf[alarm_id].target_period_mode = 1; +} + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) +{ + assert(period < (1 << 26)); + dev->target_conf[alarm_id].target_period = period; +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->comp_load[alarm_id].val = 0x01; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) +{ + if (en) { + dev->conf.val |= 1 << (24 - alarm_id); + } else { + dev->conf.val &= ~(1 << (24 - alarm_id)); + } +} + +/******************* Interrupt *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) +{ + if (en) { + dev->int_ena.val |= 1 << alarm_id; + } else { + dev->int_ena.val &= ~(1 << alarm_id); + } +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) +{ + return dev->int_st.val & (1 << alarm_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->int_clr.val |= 1 << alarm_id; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h new file mode 100644 index 0000000000..f3880b9a59 --- /dev/null +++ b/components/hal/esp32h2/include/hal/timer_ll.h @@ -0,0 +1,430 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "hal/timer_types.h" +#include "soc/timer_periph.h" + +_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); +_Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); + +typedef struct { + timg_dev_t *dev; + timer_idx_t idx; +} timer_ll_context_t; + +// Get timer group instance with giving group number +#define TIMER_LL_GET_HW(num) ((num == 0) ? (&TIMERG0) : (&TIMERG1)) + +/** + * @brief Set timer clock prescale value + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param divider Prescale value + * + * @return None + */ +static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) +{ + assert(divider >= 2 && divider <= 65536); + if (divider >= 65536) { + divider = 0; + } + int timer_en = hw->hw_timer[timer_num].config.enable; + hw->hw_timer[timer_num].config.enable = 0; + hw->hw_timer[timer_num].config.divcnt_rst = 1; + hw->hw_timer[timer_num].config.divider = divider; + hw->hw_timer[timer_num].config.enable = timer_en; +} + +/** + * @brief Get timer clock prescale value + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param divider Pointer to accept the prescale value + * + * @return None + */ +static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider) +{ + uint32_t d = hw->hw_timer[timer_num].config.divider; + if (d == 0) { + d = 65536; + } else if (d == 1) { + d = 2; + } + *divider = d; +} + +/** + * @brief Load counter value into time-base counter + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param load_val Counter value + * + * @return None + */ +static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val) +{ + hw->hw_timer[timer_num].load_high.load_hi = (uint32_t) (load_val >> 32); + hw->hw_timer[timer_num].load_low = (uint32_t) load_val; + hw->hw_timer[timer_num].reload = 1; +} + +/** + * @brief Get counter value from time-base counter + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param timer_val Pointer to accept the counter value + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val) +{ + hw->hw_timer[timer_num].update.update = 1; + while (hw->hw_timer[timer_num].update.update) {} + *timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high.hi << 32) | (hw->hw_timer[timer_num].cnt_low); +} + +/** + * @brief Set counter mode, include increment mode and decrement mode. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param increase_en True to increment mode, fasle to decrement mode + * + * @return None + */ +static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en) +{ + hw->hw_timer[timer_num].config.increase = increase_en; +} + +/** + * @brief Get counter mode, include increment mode and decrement mode. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return + * - true Increment mode + * - false Decrement mode + */ +static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num) +{ + return hw->hw_timer[timer_num].config.increase; +} + +/** + * @brief Set counter status, enable or disable counter. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param counter_en True to enable counter, false to disable counter + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en) +{ + hw->hw_timer[timer_num].config.enable = counter_en; +} + +/** + * @brief Get counter status. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return + * - true Enable counter + * - false Disable conuter + */ +static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num) +{ + return hw->hw_timer[timer_num].config.enable; +} + +/** + * @brief Set auto reload mode. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param auto_reload_en True to enable auto reload mode, flase to disable auto reload mode + * + * @return None + */ +static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en) +{ + hw->hw_timer[timer_num].config.autoreload = auto_reload_en; +} + +/** + * @brief Get auto reload mode. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return + * - true Enable auto reload mode + * - false Disable auto reload mode + */ +FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num) +{ + return hw->hw_timer[timer_num].config.autoreload; +} + +/** + * @brief Set the counter value to trigger the alarm. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param alarm_value Counter value to trigger the alarm + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value) +{ + hw->hw_timer[timer_num].alarm_high.alarm_hi = (uint32_t) (alarm_value >> 32); + hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value; +} + +/** + * @brief Get the counter value to trigger the alarm. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param alarm_value Pointer to accept the counter value to trigger the alarm + * + * @return None + */ +static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value) +{ + *alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high.alarm_hi << 32) | (hw->hw_timer[timer_num].alarm_low); +} + +/** + * @brief Set the alarm status, enable or disable the alarm. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param alarm_en True to enable alarm, false to disable alarm + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en) +{ + hw->hw_timer[timer_num].config.alarm_en = alarm_en; +} + +/** + * @brief Get the alarm status. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return + * - true Enable alarm + * - false Disable alarm + */ +static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num) +{ + return hw->hw_timer[timer_num].config.alarm_en; +} + +/** + * @brief Enable timer interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num) +{ + hw->int_ena.val |= BIT(timer_num); +} + +/** + * @brief Disable timer interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num) +{ + hw->int_ena.val &= (~BIT(timer_num)); +} + +/** + * @brief Disable timer interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num) +{ + hw->int_clr.val |= BIT(timer_num); +} + +/** + * @brief Get interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * @param intr_status Interrupt status + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status) +{ + *intr_status = hw->int_st.val & 0x01; +} + +/** + * @brief Get interrupt raw status. + * + * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1 + * @param intr_raw_status Interrupt raw status + * + * @return None + */ +FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status) +{ + timg_dev_t *hw = TIMER_LL_GET_HW(group_num); + *intr_raw_status = hw->int_raw.val & 0x01; +} + +/** + * @brief Set the level interrupt status, enable or disable the level interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param level_int_en True to enable level interrupt, false to disable level interrupt + * + * @return None + */ +static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool level_int_en) +{ + // Only "level" interrupts are supported on this target +} + +/** + * @brief Get the level interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return + * - true Enable level interrupt + * - false Disable level interrupt + */ +static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num) +{ + // Only "level" interrupts are supported on this target + return true; +} + +/** + * @brief Set the edge interrupt status, enable or disable the edge interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * @param edge_int_en True to enable edge interrupt, false to disable edge interrupt + * + * @return None + */ +static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en) +{ + // edge interrupt is not supported on C3 +} + +/** + * @brief Get the edge interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * @param timer_num The timer number + * + * @return + * - true Enable edge interrupt + * - false Disable edge interrupt + */ +static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num) +{ + // edge interrupt is not supported on C3 + return false; +} + +/** + * @brief Get interrupt status register address. + * + * @param hw Beginning address of the peripheral registers. + * + * @return uint32_t Interrupt status register address + */ +static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw) +{ + return (uint32_t) & (hw->int_st.val); +} + +static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num) +{ + return (1U << timer_num); +} + +/** + * @brief Set clock source. + * + * @param hal Context of the HAL layer + * @param use_xtal_en True to use XTAL clock, flase to use APB clock + * + * @return None + */ +static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num, bool use_xtal_en) +{ + hw->hw_timer[timer_num].config.use_xtal = use_xtal_en; +} + +/** + * @brief Get clock source. + * + * @param hal Context of the HAL layer + * + * @return + * - true Use XTAL clock + * - false Use APB clock + */ +static inline bool timer_ll_get_use_xtal(timg_dev_t *hw, timer_idx_t timer_num) +{ + return hw->hw_timer[timer_num].config.use_xtal; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/twai_ll.h b/components/hal/esp32h2/include/hal/twai_ll.h new file mode 100644 index 0000000000..6c9ae1b9fd --- /dev/null +++ b/components/hal/esp32h2/include/hal/twai_ll.h @@ -0,0 +1,667 @@ +// Copyright 2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for TWAI + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/twai_types.h" +#include "soc/twai_periph.h" + +/* ------------------------- Defines and Typedefs --------------------------- */ + +#define TWAI_LL_STATUS_RBS (0x1 << 0) //Receive Buffer Status +#define TWAI_LL_STATUS_DOS (0x1 << 1) //Data Overrun Status +#define TWAI_LL_STATUS_TBS (0x1 << 2) //Transmit Buffer Status +#define TWAI_LL_STATUS_TCS (0x1 << 3) //Transmission Complete Status +#define TWAI_LL_STATUS_RS (0x1 << 4) //Receive Status +#define TWAI_LL_STATUS_TS (0x1 << 5) //Transmit Status +#define TWAI_LL_STATUS_ES (0x1 << 6) //Error Status +#define TWAI_LL_STATUS_BS (0x1 << 7) //Bus Status +#define TWAI_LL_STATUS_MS (0x1 << 8) //Miss Status + +#define TWAI_LL_INTR_RI (0x1 << 0) //Receive Interrupt +#define TWAI_LL_INTR_TI (0x1 << 1) //Transmit Interrupt +#define TWAI_LL_INTR_EI (0x1 << 2) //Error Interrupt +//Data overrun interrupt not supported in SW due to HW peculiarities +#define TWAI_LL_INTR_EPI (0x1 << 5) //Error Passive Interrupt +#define TWAI_LL_INTR_ALI (0x1 << 6) //Arbitration Lost Interrupt +#define TWAI_LL_INTR_BEI (0x1 << 7) //Bus Error Interrupt + +/* + * The following frame structure has an NEARLY identical bit field layout to + * each byte of the TX buffer. This allows for formatting and parsing frames to + * be done outside of time critical regions (i.e., ISRs). All the ISR needs to + * do is to copy byte by byte to/from the TX/RX buffer. The two reserved bits in + * TX buffer are used in the frame structure to store the self_reception and + * single_shot flags which in turn indicate the type of transmission to execute. + */ +typedef union { + struct { + struct { + uint8_t dlc: 4; //Data length code (0 to 8) of the frame + uint8_t self_reception: 1; //This frame should be transmitted using self reception command + uint8_t single_shot: 1; //This frame should be transmitted using single shot command + uint8_t rtr: 1; //This frame is a remote transmission request + uint8_t frame_format: 1; //Format of the frame (1 = extended, 0 = standard) + }; + union { + struct { + uint8_t id[2]; //11 bit standard frame identifier + uint8_t data[8]; //Data bytes (0 to 8) + uint8_t reserved8[2]; + } standard; + struct { + uint8_t id[4]; //29 bit extended frame identifier + uint8_t data[8]; //Data bytes (0 to 8) + } extended; + }; + }; + uint8_t bytes[13]; +} __attribute__((packed)) twai_ll_frame_buffer_t; + +_Static_assert(sizeof(twai_ll_frame_buffer_t) == 13, "TX/RX buffer type should be 13 bytes"); + +/* ---------------------------- Mode Register ------------------------------- */ + +/** + * @brief Enter reset mode + * + * When in reset mode, the TWAI controller is effectively disconnected from the + * TWAI bus and will not participate in any bus activates. Reset mode is required + * in order to write the majority of configuration registers. + * + * @param hw Start address of the TWAI registers + * + * @note Reset mode is automatically entered on BUS OFF condition + */ +static inline void twai_ll_enter_reset_mode(twai_dev_t *hw) +{ + hw->mode_reg.rm = 1; +} + +/** + * @brief Exit reset mode + * + * When not in reset mode, the TWAI controller will take part in bus activities + * (e.g., send/receive/acknowledge messages and error frames) depending on the + * operating mode. + * + * @param hw Start address of the TWAI registers + * + * @note Reset mode must be exit to initiate BUS OFF recovery + */ +static inline void twai_ll_exit_reset_mode(twai_dev_t *hw) +{ + hw->mode_reg.rm = 0; +} + +/** + * @brief Check if in reset mode + * @param hw Start address of the TWAI registers + * @return true if in reset mode + */ +static inline bool twai_ll_is_in_reset_mode(twai_dev_t *hw) +{ + return hw->mode_reg.rm; +} + +/** + * @brief Set operating mode of TWAI controller + * + * @param hw Start address of the TWAI registers + * @param mode Operating mode + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_mode(twai_dev_t *hw, twai_mode_t mode) +{ + if (mode == TWAI_MODE_NORMAL) { //Normal Operating mode + hw->mode_reg.lom = 0; + hw->mode_reg.stm = 0; + } else if (mode == TWAI_MODE_NO_ACK) { //Self Test Mode (No Ack) + hw->mode_reg.lom = 0; + hw->mode_reg.stm = 1; + } else if (mode == TWAI_MODE_LISTEN_ONLY) { //Listen Only Mode + hw->mode_reg.lom = 1; + hw->mode_reg.stm = 0; + } +} + +/* --------------------------- Command Register ----------------------------- */ + +/** + * @brief Set TX command + * + * Setting the TX command will cause the TWAI controller to attempt to transmit + * the frame stored in the TX buffer. The TX buffer will be occupied (i.e., + * locked) until TX completes. + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_tx(twai_dev_t *hw) +{ + hw->command_reg.tr = 1; +} + +/** + * @brief Set single shot TX command + * + * Similar to setting TX command, but the TWAI controller will not automatically + * retry transmission upon an error (e.g., due to an acknowledgement error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_tx_single_shot(twai_dev_t *hw) +{ + hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmittion request +} + +/** + * @brief Aborts TX + * + * Frames awaiting TX will be aborted. Frames already being TX are not aborted. + * Transmission Complete Status bit is automatically set to 1. + * Similar to setting TX command, but the TWAI controller will not automatically + * retry transmission upon an error (e.g., due to acknowledge error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_abort_tx(twai_dev_t *hw) +{ + hw->command_reg.at = 1; +} + +/** + * @brief Release RX buffer + * + * Rotates RX buffer to the next frame in the RX FIFO. + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_set_cmd_release_rx_buffer(twai_dev_t *hw) +{ + hw->command_reg.rrb = 1; +} + +/** + * @brief Clear data overrun + * + * Clears the data overrun status bit + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_set_cmd_clear_data_overrun(twai_dev_t *hw) +{ + hw->command_reg.cdo = 1; +} + +/** + * @brief Set self reception single shot command + * + * Similar to setting TX command, but the TWAI controller also simultaneously + * receive the transmitted frame and is generally used for self testing + * purposes. The TWAI controller will not ACK the received message, so consider + * using the NO_ACK operating mode. + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_self_rx_request(twai_dev_t *hw) +{ + hw->command_reg.srr = 1; +} + +/** + * @brief Set self reception request command + * + * Similar to setting the self reception request, but the TWAI controller will + * not automatically retry transmission upon an error (e.g., due to and + * acknowledgement error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_self_rx_single_shot(twai_dev_t *hw) +{ + hw->command_reg.val = 0x12; //Set command_reg.srr and command_reg.at simultaneously for single shot self reception request +} + +/* --------------------------- Status Register ------------------------------ */ + +/** + * @brief Get all status bits + * + * @param hw Start address of the TWAI registers + * @return Status bits + */ +static inline uint32_t twai_ll_get_status(twai_dev_t *hw) +{ + return hw->status_reg.val; +} + +/** + * @brief Check if RX FIFO overrun status bit is set + * + * @param hw Start address of the TWAI registers + * @return Overrun status bit + */ +static inline bool twai_ll_is_fifo_overrun(twai_dev_t *hw) +{ + return hw->status_reg.dos; +} + +/** + * @brief Check if previously TX was successful + * + * @param hw Start address of the TWAI registers + * @return Whether previous TX was successful + */ +static inline bool twai_ll_is_last_tx_successful(twai_dev_t *hw) +{ + return hw->status_reg.tcs; +} + +/* -------------------------- Interrupt Register ---------------------------- */ + +/** + * @brief Get currently set interrupts + * + * Reading the interrupt registers will automatically clear all interrupts + * except for the Receive Interrupt. + * + * @param hw Start address of the TWAI registers + * @return Bit mask of set interrupts + */ +static inline uint32_t twai_ll_get_and_clear_intrs(twai_dev_t *hw) +{ + return hw->interrupt_reg.val; +} + +/* ----------------------- Interrupt Enable Register ------------------------ */ + +/** + * @brief Set which interrupts are enabled + * + * @param hw Start address of the TWAI registers + * @param Bit mask of interrupts to enable + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask) +{ + hw->interrupt_enable_reg.val = intr_mask; +} + +/* ------------------------ Bus Timing Registers --------------------------- */ + +/** + * @brief Set bus timing + * + * @param hw Start address of the TWAI registers + * @param brp Baud Rate Prescaler + * @param sjw Synchronization Jump Width + * @param tseg1 Timing Segment 1 + * @param tseg2 Timing Segment 2 + * @param triple_sampling Triple Sampling enable/disable + * + * @note Must be called in reset mode + * @note ESP32C3 brp can be any even number between 2 to 32768 + */ +static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling) +{ + hw->bus_timing_0_reg.brp = (brp / 2) - 1; + hw->bus_timing_0_reg.sjw = sjw - 1; + hw->bus_timing_1_reg.tseg1 = tseg1 - 1; + hw->bus_timing_1_reg.tseg2 = tseg2 - 1; + hw->bus_timing_1_reg.sam = triple_sampling; +} + +/* ----------------------------- ALC Register ------------------------------- */ + +/** + * @brief Clear Arbitration Lost Capture Register + * + * Reading the ALC register rearms the Arbitration Lost Interrupt + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_clear_arb_lost_cap(twai_dev_t *hw) +{ + (void)hw->arbitration_lost_captue_reg.val; +} + +/* ----------------------------- ECC Register ------------------------------- */ + +/** + * @brief Clear Error Code Capture register + * + * Reading the ECC register rearms the Bus Error Interrupt + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw) +{ + (void)hw->error_code_capture_reg.val; +} + +/* ----------------------------- EWL Register ------------------------------- */ + +/** + * @brief Set Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @param ewl Error Warning Limit + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl) +{ + hw->error_warning_limit_reg.ewl = ewl; +} + +/** + * @brief Get Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @return Error Warning Limit + */ +static inline uint32_t twai_ll_get_err_warn_lim(twai_dev_t *hw) +{ + return hw->error_warning_limit_reg.val; +} + +/* ------------------------ RX Error Count Register ------------------------- */ + +/** + * @brief Get RX Error Counter + * + * @param hw Start address of the TWAI registers + * @return REC value + * + * @note REC is not frozen in reset mode. Listen only mode will freeze it. A BUS + * OFF condition automatically sets the REC to 0. + */ +static inline uint32_t twai_ll_get_rec(twai_dev_t *hw) +{ + return hw->rx_error_counter_reg.val; +} + +/** + * @brief Set RX Error Counter + * + * @param hw Start address of the TWAI registers + * @param rec REC value + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec) +{ + hw->rx_error_counter_reg.rxerr = rec; +} + +/* ------------------------ TX Error Count Register ------------------------- */ + +/** + * @brief Get TX Error Counter + * + * @param hw Start address of the TWAI registers + * @return TEC value + * + * @note A BUS OFF condition will automatically set this to 128 + */ +static inline uint32_t twai_ll_get_tec(twai_dev_t *hw) +{ + return hw->tx_error_counter_reg.val; +} + +/** + * @brief Set TX Error Counter + * + * @param hw Start address of the TWAI registers + * @param tec TEC value + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec) +{ + hw->tx_error_counter_reg.txerr = tec; +} + +/* ---------------------- Acceptance Filter Registers ----------------------- */ + +/** + * @brief Set Acceptance Filter + * @param hw Start address of the TWAI registers + * @param code Acceptance Code + * @param mask Acceptance Mask + * @param single_filter Whether to enable single filter mode + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter) +{ + uint32_t code_swapped = __builtin_bswap32(code); + uint32_t mask_swapped = __builtin_bswap32(mask); + for (int i = 0; i < 4; i++) { + hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF); + hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF); + } + hw->mode_reg.afm = single_filter; +} + +/* ------------------------- TX/RX Buffer Registers ------------------------- */ + +/** + * @brief Copy a formatted TWAI frame into TX buffer for transmission + * + * @param hw Start address of the TWAI registers + * @param tx_frame Pointer to formatted frame + * + * @note Call twai_ll_format_frame_buffer() to format a frame + */ +static inline void twai_ll_set_tx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t *tx_frame) +{ + //Copy formatted frame into TX buffer + for (int i = 0; i < 13; i++) { + hw->tx_rx_buffer[i].val = tx_frame->bytes[i]; + } +} + +/** + * @brief Copy a received frame from the RX buffer for parsing + * + * @param hw Start address of the TWAI registers + * @param rx_frame Pointer to store formatted frame + * + * @note Call twai_ll_prase_frame_buffer() to parse the formatted frame + */ +static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t *rx_frame) +{ + //Copy RX buffer registers into frame + for (int i = 0; i < 13; i++) { + rx_frame->bytes[i] = hw->tx_rx_buffer[i].byte; + } +} + +/** + * @brief Format contents of a TWAI frame into layout of TX Buffer + * + * This function encodes a message into a frame structure. The frame structure + * has an identical layout to the TX buffer, allowing the frame structure to be + * directly copied into TX buffer. + * + * @param[in] 11bit or 29bit ID + * @param[in] dlc Data length code + * @param[in] data Pointer to an 8 byte array containing data. NULL if no data + * @param[in] format Type of TWAI frame + * @param[in] single_shot Frame will not be retransmitted on failure + * @param[in] self_rx Frame will also be simultaneously received + * @param[out] tx_frame Pointer to store formatted frame + */ +static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const uint8_t *data, + uint32_t flags, twai_ll_frame_buffer_t *tx_frame) +{ + bool is_extd = flags & TWAI_MSG_FLAG_EXTD; + bool is_rtr = flags & TWAI_MSG_FLAG_RTR; + + //Set frame information + tx_frame->dlc = dlc; + tx_frame->frame_format = is_extd; + tx_frame->rtr = is_rtr; + tx_frame->self_reception = (flags & TWAI_MSG_FLAG_SELF) ? 1 : 0; + tx_frame->single_shot = (flags & TWAI_MSG_FLAG_SS) ? 1 : 0; + + //Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required + if (is_extd) { + uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i)) + for (int i = 0; i < 4; i++) { + tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF; + } + } else { + uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i)) + for (int i = 0; i < 2; i++) { + tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF; + } + } + + uint8_t *data_buffer = (is_extd) ? tx_frame->extended.data : tx_frame->standard.data; + if (!is_rtr) { //Only copy data if the frame is a data frame (i.e not a remote frame) + for (int i = 0; (i < dlc) && (i < TWAI_FRAME_MAX_DLC); i++) { + data_buffer[i] = data[i]; + } + } +} + +/** + * @brief Parse formatted TWAI frame (RX Buffer Layout) into its constituent contents + * + * @param[in] rx_frame Pointer to formatted frame + * @param[out] id 11 or 29bit ID + * @param[out] dlc Data length code + * @param[out] data Data. Left over bytes set to 0. + * @param[out] format Type of TWAI frame + */ +static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame, uint32_t *id, uint8_t *dlc, + uint8_t *data, uint32_t *flags) +{ + //Copy frame information + *dlc = rx_frame->dlc; + uint32_t flags_temp = 0; + flags_temp |= (rx_frame->frame_format) ? TWAI_MSG_FLAG_EXTD : 0; + flags_temp |= (rx_frame->rtr) ? TWAI_MSG_FLAG_RTR : 0; + flags_temp |= (rx_frame->dlc > TWAI_FRAME_MAX_DLC) ? TWAI_MSG_FLAG_DLC_NON_COMP : 0; + *flags = flags_temp; + + //Copy ID. The ID registers are big endian and left aligned, therefore a bswap will be required + if (rx_frame->frame_format) { + uint32_t id_temp = 0; + for (int i = 0; i < 4; i++) { + id_temp |= rx_frame->extended.id[i] << (8 * i); + } + id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3) + *id = id_temp & TWAI_EXTD_ID_MASK; + } else { + uint32_t id_temp = 0; + for (int i = 0; i < 2; i++) { + id_temp |= rx_frame->standard.id[i] << (8 * i); + } + id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5) + *id = id_temp & TWAI_STD_ID_MASK; + } + + uint8_t *data_buffer = (rx_frame->frame_format) ? rx_frame->extended.data : rx_frame->standard.data; + //Only copy data if the frame is a data frame (i.e. not a remote frame) + int data_length = (rx_frame->rtr) ? 0 : ((rx_frame->dlc > TWAI_FRAME_MAX_DLC) ? TWAI_FRAME_MAX_DLC : rx_frame->dlc); + for (int i = 0; i < data_length; i++) { + data[i] = data_buffer[i]; + } + //Set remaining bytes of data to 0 + for (int i = data_length; i < TWAI_FRAME_MAX_DLC; i++) { + data[i] = 0; + } +} + +/* ----------------------- RX Message Count Register ------------------------ */ + +/** + * @brief Get RX Message Counter + * + * @param hw Start address of the TWAI registers + * @return RX Message Counter + */ +static inline uint32_t twai_ll_get_rx_msg_count(twai_dev_t *hw) +{ + return hw->rx_message_counter_reg.val; +} + +/* ------------------------- Clock Divider Register ------------------------- */ + +/** + * @brief Set CLKOUT Divider and enable/disable + * + * Configure CLKOUT. CLKOUT is a pre-scaled version of APB CLK. Divider can be + * 1, or any even number from 2 to 490. Set the divider to 0 to disable CLKOUT. + * + * @param hw Start address of the TWAI registers + * @param divider Divider for CLKOUT (any even number from 2 to 490). Set to 0 to disable CLKOUT + */ +static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) +{ + if (divider >= 2 && divider <= 490) { + hw->clock_divider_reg.co = 0; + hw->clock_divider_reg.cd = (divider / 2) - 1; + } else if (divider == 1) { + //Setting the divider reg to max value (255) means a divider of 1 + hw->clock_divider_reg.co = 0; + hw->clock_divider_reg.cd = 255; + } else { + hw->clock_divider_reg.co = 1; + hw->clock_divider_reg.cd = 0; + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h new file mode 100644 index 0000000000..c166e472f5 --- /dev/null +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -0,0 +1,937 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for UART register operations. +// Note that most of the register operations in this layer are non-atomic operations. + + +#pragma once +#include "hal/uart_types.h" +#include "soc/uart_periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// The default fifo depth +#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) +// Get UART hardware instance with giving uart num +#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1)) + +#define UART_LL_MIN_WAKEUP_THRESH (2) +#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask + +#define UART_LL_FSM_IDLE (0x0) +#define UART_LL_FSM_TX_WAIT_SEND (0xf) + +// Define UART interrupts +typedef enum { + UART_INTR_RXFIFO_FULL = (0x1 << 0), + UART_INTR_TXFIFO_EMPTY = (0x1 << 1), + UART_INTR_PARITY_ERR = (0x1 << 2), + UART_INTR_FRAM_ERR = (0x1 << 3), + UART_INTR_RXFIFO_OVF = (0x1 << 4), + UART_INTR_DSR_CHG = (0x1 << 5), + UART_INTR_CTS_CHG = (0x1 << 6), + UART_INTR_BRK_DET = (0x1 << 7), + UART_INTR_RXFIFO_TOUT = (0x1 << 8), + UART_INTR_SW_XON = (0x1 << 9), + UART_INTR_SW_XOFF = (0x1 << 10), + UART_INTR_GLITCH_DET = (0x1 << 11), + UART_INTR_TX_BRK_DONE = (0x1 << 12), + UART_INTR_TX_BRK_IDLE = (0x1 << 13), + UART_INTR_TX_DONE = (0x1 << 14), + UART_INTR_RS485_PARITY_ERR = (0x1 << 15), + UART_INTR_RS485_FRM_ERR = (0x1 << 16), + UART_INTR_RS485_CLASH = (0x1 << 17), + UART_INTR_CMD_CHAR_DET = (0x1 << 18), +} uart_intr_t; + +static inline void uart_ll_reset_core(uart_dev_t *hw) { + hw->clk_conf.rst_core = 1; + hw->clk_conf.rst_core = 0; +} + +static inline void uart_ll_sclk_enable(uart_dev_t *hw) { + hw->clk_conf.sclk_en = 1; + hw->clk_conf.rx_sclk_en = 1; + hw->clk_conf.tx_sclk_en = 1; +} + +static inline void uart_ll_sclk_disable(uart_dev_t *hw) { + hw->clk_conf.sclk_en = 0; + hw->clk_conf.rx_sclk_en = 0; + hw->clk_conf.tx_sclk_en = 0; +} + +/** + * @brief Set the UART source clock. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock. + * If the source clock is RTC/XTAL, the UART can still work when the APB changes. + * + * @return None. + */ +static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) +{ + switch (source_clk) { + default: + case UART_SCLK_APB: + hw->clk_conf.sclk_sel = 1; + break; + case UART_SCLK_RTC: + hw->clk_conf.sclk_sel = 2; + break; + case UART_SCLK_XTAL: + hw->clk_conf.sclk_sel = 3; + break; + } +} + +/** + * @brief Get the UART source clock type. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The pointer to accept the UART source clock type. + * + * @return None. + */ +static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) +{ + switch (hw->clk_conf.sclk_sel) { + default: + case 1: + *source_clk = UART_SCLK_APB; + break; + case 2: + *source_clk = UART_SCLK_RTC; + break; + case 3: + *source_clk = UART_SCLK_XTAL; + break; + } +} + +/** + * @brief Get the UART source clock frequency. + * + * @param hw Beginning address of the peripheral registers. + * + * @return Current source clock frequency + */ +static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) +{ + switch (hw->clk_conf.sclk_sel) { + default: + case 1: + return APB_CLK_FREQ; + case 2: + return RTC_CLK_FREQ; + case 3: + return XTAL_CLK_FREQ; + } +} + +/** + * @brief Configure the baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param baud The baud rate to be set. + * + * @return None + */ +static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +{ +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); + const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + int sclk_div = DIV_UP(sclk_freq, max_div * baud); + + uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // The baud rate configuration register is divided into + // an integer part and a fractional part. + hw->clk_div.div_int = clk_div >> 4; + hw->clk_div.div_frag = clk_div & 0xf; + hw->clk_conf.sclk_div_num = sclk_div - 1; +#undef DIV_UP +} + +/** + * @brief Get the current baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The current baudrate + */ +static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +{ + uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); + typeof(hw->clk_div) div_reg = hw->clk_div; + return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1)); +} + +/** + * @brief Enable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val |= mask; +} + +/** + * @brief Disable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val &= (~mask); +} + +/** + * @brief Get the UART interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART interrupt status. + */ +static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +{ + return hw->int_st.val; +} + +/** + * @brief Clear the UART interrupt status based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @param hw Beginning address of the peripheral registers. + * + * @return interrupt enable value + */ +static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +{ + return hw->int_ena.val; +} + +/** + * @brief Read the UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. The buffer size should be large than 128 byts. + * @param rd_len The data length needs to be read. + * + * @return None. + */ +static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +{ + for (int i = 0; i < (int)rd_len; i++) { + buf[i] = hw->ahb_fifo.rw_byte; + } +} + +/** + * @brief Write byte to the UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. + * @param wr_len The data length needs to be writen. + * + * @return None + */ +static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +{ + for (int i = 0; i < (int)wr_len; i++) { + hw->ahb_fifo.rw_byte = buf[i]; + } +} + +/** + * @brief Reset the UART hw rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) +{ + hw->conf0.rxfifo_rst = 1; + hw->conf0.rxfifo_rst = 0; +} + +/** + * @brief Reset the UART hw txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +static inline void uart_ll_txfifo_rst(uart_dev_t *hw) +{ + hw->conf0.txfifo_rst = 1; + hw->conf0.txfifo_rst = 0; +} + +/** + * @brief Get the length of readable data in UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The readable data length in rxfifo. + */ +static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +{ + return hw->status.rxfifo_cnt; +} + +/** + * @brief Get the writable data length of UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The data length of txfifo can be written. + */ +static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +{ + return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; +} + +/** + * @brief Configure the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The stop bit number to be set. + * + * @return None. + */ +static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +{ + hw->conf0.stop_bit_num = stop_bit; +} + +/** + * @brief Get the configuration of the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The pointer to accept the stop bit configuration + * + * @return None. + */ +static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +{ + *stop_bit = hw->conf0.stop_bit_num; +} + +/** + * @brief Configure the UART parity check mode. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The parity check mode to be set. + * + * @return None. + */ +static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +{ + if (parity_mode != UART_PARITY_DISABLE) { + hw->conf0.parity = parity_mode & 0x1; + } + hw->conf0.parity_en = (parity_mode >> 1) & 0x1; +} + +/** + * @brief Get the UART parity check mode configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The pointer to accept the parity check mode configuration. + * + * @return None. + */ +static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +{ + if (hw->conf0.parity_en) { + *parity_mode = 0X2 | hw->conf0.parity; + } else { + *parity_mode = UART_PARITY_DISABLE; + } +} + +/** + * @brief Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, + * it will produce rxfifo_full_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `UART_LL_FIFO_DEF_LEN`. + * + * @return None. + */ +static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +{ + hw->conf1.rxfifo_full_thrhd = full_thrhd; +} + +/** + * @brief Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, + * it will produce txfifo_empty_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param empty_thrhd The empty threshold of txfifo. + * + * @return None. + */ +static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +{ + hw->conf1.txfifo_empty_thrhd = empty_thrhd; +} + +/** + * @brief Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, + * it will produce frame end signal for uhci to stop receiving data. + * + * @param hw Beginning address of the peripheral registers. + * @param rx_idle_thr The rx-idle threshold to be set. + * + * @return None. + */ +static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +{ + hw->idle_conf.rx_idle_thrhd = rx_idle_thr; +} + +/** + * @brief Configure the duration time between transfers. + * + * @param hw Beginning address of the peripheral registers. + * @param idle_num the duration time between transfers. + * + * @return None. + */ +static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +{ + hw->idle_conf.tx_idle_num = idle_num; +} + +/** + * @brief Configure the transmiter to send break chars. + * + * @param hw Beginning address of the peripheral registers. + * @param break_num The number of the break chars need to be send. + * + * @return None. + */ +static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +{ + if (break_num > 0) { + hw->txbrk_conf.tx_brk_num = break_num; + hw->conf0.txd_brk = 1; + } else { + hw->conf0.txd_brk = 0; + } +} + +/** + * @brief Configure the UART hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The hw flow control configuration. + * @param rx_thrs The rx flow control signal will be active if the data length in rxfifo is more than this value. + * + * @return None. + */ +static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +{ + //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. + if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { + hw->mem_conf.rx_flow_thrhd = rx_thrs; + hw->conf1.rx_flow_en = 1; + } else { + hw->conf1.rx_flow_en = 0; + } + if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { + hw->conf0.tx_flow_en = 1; + } else { + hw->conf0.tx_flow_en = 0; + } +} + +/** + * @brief Configure the hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl A pointer to accept the hw flow control configuration. + * + * @return None. + */ +static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +{ + *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + if (hw->conf1.rx_flow_en) { + *flow_ctrl |= UART_HW_FLOWCTRL_RTS; + } + if (hw->conf0.tx_flow_en) { + *flow_ctrl |= UART_HW_FLOWCTRL_CTS; + } +} + +/** + * @brief Configure the software flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The UART sofware flow control settings. + * @param sw_flow_ctrl_en Set true to enable software flow control, otherwise set it false. + * + * @return None. + */ +static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +{ + if (sw_flow_ctrl_en) { + hw->flow_conf.xonoff_del = 1; + hw->flow_conf.sw_flow_con_en = 1; + hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; + hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd; + hw->swfc_conf1.xon_char = flow_ctrl->xon_char; + hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char; + } else { + hw->flow_conf.sw_flow_con_en = 0; + hw->flow_conf.xonoff_del = 0; + } +} + +/** + * @brief Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The AT cmd char configuration.The configuration member is: + * - cmd_char The AT cmd character + * - char_num The number of received AT cmd char must be equal to or greater than this value + * - gap_tout The interval between each AT cmd char, when the duration is less than this value, it will not take this data as AT cmd char + * - pre_idle The idle time before the first AT cmd char, when the duration is less than this value, it will not take the previous data as the last AT cmd char + * - post_idle The idle time after the last AT cmd char, when the duration is less than this value, it will not take this data as the first AT cmd char + * + * @return None. + */ +static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +{ + hw->at_cmd_char.data = cmd_char->cmd_char; + hw->at_cmd_char.char_num = cmd_char->char_num; + hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle; + hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle; + hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout; +} + +/** + * @brief Set the UART data bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The data bit mode to be set. + * + * @return None. + */ +static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +{ + hw->conf0.bit_num = data_bit; +} + +/** + * @brief Set the rts active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The rts active level, 0 or 1. + * + * @return None. + */ +static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +{ + hw->conf0.sw_rts = level & 0x1; +} + +/** + * @brief Set the dtr active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The dtr active level, 0 or 1. + * + * @return None. + */ +static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +{ + hw->conf0.sw_dtr = level & 0x1; +} + +/** + * @brief Set the UART wakeup threshold. + * + * @param hw Beginning address of the peripheral registers. + * @param wakeup_thrd The wakeup threshold value to be set. When the input rx edge changes more than this value, + * the UART will active from light sleeping mode. + * + * @return None. + */ +static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +{ + hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; +} + +/** + * @brief Configure the UART work in normal mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_normal(uart_dev_t *hw) +{ + hw->rs485_conf.en = 0; + hw->rs485_conf.tx_rx_en = 0; + hw->rs485_conf.rx_busy_tx_en = 0; + hw->conf0.irda_en = 0; +} + +/** + * @brief Configure the UART work in rs485_app_ctrl mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +{ + // Application software control, remove echo + hw->rs485_conf.rx_busy_tx_en = 1; + hw->conf0.irda_en = 0; + hw->conf0.sw_rts = 0; + hw->conf0.irda_en = 0; + hw->rs485_conf.dl0_en = 1; + hw->rs485_conf.dl1_en = 1; + hw->rs485_conf.en = 1; +} + +/** + * @brief Configure the UART work in rs485_half_duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +{ + // Enable receiver, sw_rts = 1 generates low level on RTS pin + hw->conf0.sw_rts = 1; + // Half duplex mode + hw->rs485_conf.tx_rx_en = 0; + // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). + // But note that this full-duplex mode has no conflict detection function + hw->rs485_conf.rx_busy_tx_en = 0; + hw->conf0.irda_en = 0; + hw->rs485_conf.dl0_en = 1; + hw->rs485_conf.dl1_en = 1; + hw->rs485_conf.en = 1; +} + +/** + * @brief Configure the UART work in collision_detect mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +{ + hw->conf0.irda_en = 0; + // Enable full-duplex mode + hw->rs485_conf.tx_rx_en = 1; + // Transmitter should send data when the receiver is busy, + hw->rs485_conf.rx_busy_tx_en = 1; + hw->rs485_conf.dl0_en = 1; + hw->rs485_conf.dl1_en = 1; + hw->conf0.sw_rts = 0; + hw->rs485_conf.en = 1; +} + +/** + * @brief Configure the UART work in irda mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_irda(uart_dev_t *hw) +{ + hw->rs485_conf.en = 0; + hw->rs485_conf.tx_rx_en = 0; + hw->rs485_conf.rx_busy_tx_en = 0; + hw->conf0.sw_rts = 0; + hw->conf0.irda_en = 1; +} + +/** + * @brief Set uart mode. + * + * @param hw Beginning address of the peripheral registers. + * @param mode The UART mode to be set. + * + * @return None. + */ +static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +{ + switch (mode) { + default: + case UART_MODE_UART: + uart_ll_set_mode_normal(hw); + break; + case UART_MODE_RS485_COLLISION_DETECT: + uart_ll_set_mode_collision_detect(hw); + break; + case UART_MODE_RS485_APP_CTRL: + uart_ll_set_mode_rs485_app_ctrl(hw); + break; + case UART_MODE_RS485_HALF_DUPLEX: + uart_ll_set_mode_rs485_half_duplex(hw); + break; + case UART_MODE_IRDA: + uart_ll_set_mode_irda(hw); + break; + } +} + +/** + * @brief Get the UART AT cmd char configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The Pointer to accept value of UART AT cmd char. + * @param char_num Pointer to accept the repeat number of UART AT cmd char. + * + * @return None. + */ +static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +{ + *cmd_char = hw->at_cmd_char.data; + *char_num = hw->at_cmd_char.char_num; +} + +/** + * @brief Get the UART wakeup threshold value. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART wakeup threshold value. + */ +static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +{ + return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH; +} + +/** + * @brief Get the UART data bit configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The pointer to accept the UART data bit configuration. + * + * @return The bit mode. + */ +static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +{ + *data_bit = hw->conf0.bit_num; +} + +/** + * @brief Check if the UART sending state machine is in the IDLE state. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if the state machine is in the IDLE state, otherwise false is returned. + */ +static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) +{ + return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); +} + +/** + * @brief Check if the UART rts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw rts flow control is enabled, otherwise false is returned. + */ +static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +{ + return hw->conf1.rx_flow_en; +} + +/** + * @brief Check if the UART cts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw cts flow control is enabled, otherwise false is returned. + */ +static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +{ + return hw->conf0.tx_flow_en; +} + +/** + * @brief Configure TX signal loop back to RX module, just for the testing purposes + * + * @param hw Beginning address of the peripheral registers. + * @param loop_back_en Set ture to enable the loop back function, else set it false. + * + * @return None + */ +static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +{ + hw->conf0.loopback = loop_back_en; +} + +static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +{ + hw->flow_conf.force_xon = 1; + if(!always_on) { + hw->flow_conf.force_xon = 0; + } +} + +/** + * @brief Inverse the UART signal with the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param inv_mask The UART signal bitmap needs to be inversed. + * Use the ORred mask of `uart_signal_inv_t`; + * + * @return None. + */ +static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +{ + typeof(hw->conf0) conf0_reg = hw->conf0; + conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; + conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; + conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; + conf0_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; + conf0_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; + conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; + conf0_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; + conf0_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; + hw->conf0.val = conf0_reg.val; +} + +/** + * @brief Configure the timeout value for receiver receiving a byte, and enable rx timeout function. + * + * @param hw Beginning address of the peripheral registers. + * @param tout_thrd The timeout value as UART bit time. The rx timeout function will be disabled if `tout_thrd == 0`. + * + * @return None. + */ +static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +{ + uint16_t tout_val = tout_thrd; + if(tout_thrd > 0) { + hw->mem_conf.rx_tout_thrhd = tout_val; + hw->conf1.rx_tout_en = 1; + } else { + hw->conf1.rx_tout_en = 0; + } +} + +/** + * @brief Get the timeout value for receiver receiving a byte. + * + * @param hw Beginning address of the peripheral registers. + * + * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. + */ +static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +{ + uint16_t tout_thrd = 0; + if(hw->conf1.rx_tout_en > 0) { + tout_thrd = hw->mem_conf.rx_tout_thrhd; + } + return tout_thrd; +} + +/** + * @brief Get UART maximum timeout threshold. + * + * @param hw Beginning address of the peripheral registers. + * + * @return maximum timeout threshold. + */ +static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +{ + return UART_RX_TOUT_THRHD_V; +} + +/** + * @brief Force UART xoff. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +static inline void uart_ll_force_xoff(uart_port_t uart_num) +{ + REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); + REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); + REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); +} + +/** + * @brief Force UART xon. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +static inline void uart_ll_force_xon(uart_port_t uart_num) +{ + REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF); + REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); + REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON); + REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); +} + +/** + * @brief Get UART final state machine status. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return UART module FSM status. + */ +static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) +{ + return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/uhci_ll.h b/components/hal/esp32h2/include/hal/uhci_ll.h new file mode 100644 index 0000000000..235d28ab3a --- /dev/null +++ b/components/hal/esp32h2/include/hal/uhci_ll.h @@ -0,0 +1,130 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer for UHCI register operations. +// Note that most of the register operations in this layer are non-atomic operations. + + +#pragma once +#include +#include "uhci_types.h" +#include "soc/uhci_struct.h" + +#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL)) + +typedef enum { + UHCI_RX_BREAK_CHR_EOF = 0x1, + UHCI_RX_IDLE_EOF = 0x2, + UHCI_RX_LEN_EOF = 0x4, + UHCI_RX_EOF_MAX = 0x7, +} uhci_rxeof_cfg_t; + +static inline void uhci_ll_init(uhci_dev_t *hw) +{ + typeof(hw->conf0) conf0_reg; + hw->conf0.clk_en = 1; + conf0_reg.val = 0; + conf0_reg.clk_en = 1; + hw->conf0.val = conf0_reg.val; + hw->conf1.val = 0; +} + +static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num) +{ + hw->conf0.uart0_ce = (uart_num == 0)? 1: 0; + hw->conf0.uart1_ce = (uart_num == 1)? 1: 0; +} + +static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char) +{ + if (seper_char->sub_chr_en) { + typeof(hw->esc_conf0) esc_conf0_reg = hw->esc_conf0; + esc_conf0_reg.seper_char = seper_char->seper_chr; + esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1; + esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2; + hw->esc_conf0.val = esc_conf0_reg.val; + hw->escape_conf.tx_c0_esc_en = 1; + hw->escape_conf.rx_c0_esc_en = 1; + } else { + hw->escape_conf.tx_c0_esc_en = 0; + hw->escape_conf.rx_c0_esc_en = 0; + } +} + +static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_chr) +{ + (void)hw; + (void)seper_chr; +} + +static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr) +{ + typeof(hw->escape_conf) escape_conf_reg = hw->escape_conf; + if (sub_ctr->flow_en == 1) { + typeof(hw->esc_conf2) esc_conf2_reg = hw->esc_conf2; + typeof(hw->esc_conf3) esc_conf3_reg = hw->esc_conf3; + esc_conf2_reg.seq1 = sub_ctr->xon_chr; + esc_conf2_reg.seq1_char0 = sub_ctr->xon_sub1; + esc_conf2_reg.seq1_char1 = sub_ctr->xon_sub2; + esc_conf3_reg.seq2 = sub_ctr->xoff_chr; + esc_conf3_reg.seq2_char0 = sub_ctr->xoff_sub1; + esc_conf3_reg.seq2_char1 = sub_ctr->xoff_sub2; + escape_conf_reg.tx_11_esc_en = 1; + escape_conf_reg.tx_13_esc_en = 1; + escape_conf_reg.rx_11_esc_en = 1; + escape_conf_reg.rx_13_esc_en = 1; + hw->esc_conf2.val = esc_conf2_reg.val; + hw->esc_conf3.val = esc_conf3_reg.val; + } else { + escape_conf_reg.tx_11_esc_en = 0; + escape_conf_reg.tx_13_esc_en = 0; + escape_conf_reg.rx_11_esc_en = 0; + escape_conf_reg.rx_13_esc_en = 0; + } + hw->escape_conf.val = escape_conf_reg.val; +} + +static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask) +{ + hw->int_ena.val |= intr_mask; +} + +static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask) +{ + hw->int_ena.val &= (~intr_mask); +} + +static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask) +{ + hw->int_clr.val = intr_mask; +} + +static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) +{ + return hw->int_st.val; +} + + +static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +{ + if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = 1; + } + if (eof_mode & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = 1; + } + if (eof_mode & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = 1; + } +} diff --git a/components/hal/esp32h2/include/hal/uhci_types.h b/components/hal/esp32h2/include/hal/uhci_types.h new file mode 100644 index 0000000000..7b7f41d0f9 --- /dev/null +++ b/components/hal/esp32h2/include/hal/uhci_types.h @@ -0,0 +1,54 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + + +// Though the UHCI driver hasn't been published, some types are defined here +// for users to develop over the HAL. See example: controller_hci_uart_esp32c3 + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @brief UHCI escape sequence + */ +typedef struct { + uint8_t seper_chr; /*!< escape sequence character */ + uint8_t sub_chr1; /*!< escape sequence sub-character 1 */ + uint8_t sub_chr2; /*!< escape sequence sub-character 2 */ + bool sub_chr_en; /*!< enable use of sub-chaacter of escape sequence */ +} uhci_seper_chr_t; + +/** + * @brief UHCI software flow control + */ +typedef struct { + uint8_t xon_chr; /*!< character for XON */ + uint8_t xon_sub1; /*!< sub-character 1 for XON */ + uint8_t xon_sub2; /*!< sub-character 2 for XON */ + uint8_t xoff_chr; /*!< character 2 for XOFF */ + uint8_t xoff_sub1; /*!< sub-character 1 for XOFF */ + uint8_t xoff_sub2; /*!< sub-character 2 for XOFF */ + uint8_t flow_en; /*!< enable use of software flow control */ +} uhci_swflow_ctrl_sub_chr_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h new file mode 100644 index 0000000000..e75cf67b43 --- /dev/null +++ b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h @@ -0,0 +1,169 @@ +// Copyright 2021 Espressif Systems (Shanghai) +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The LL layer of the USB-serial-jtag controller + +#pragma once +#include "soc/usb_serial_jtag_reg.h" +#include "soc/usb_serial_jtag_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//The in and out endpoints are this long. +#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64 + +#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask + +// Define USB_SERIAL_JTAG interrupts +// Note the hardware has more interrupts, but they're only useful for debugging +// the hardware. +typedef enum { + USB_SERIAL_JTAG_INTR_SOF = (1 << 1), + USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2), + USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3), + USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8), + USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9), + USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10), +} usb_serial_jtag_intr_t; + +/** + * @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask. + * + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_ena.val |= mask; +} + +/** + * @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask. + * + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_ena.val &= (~mask); +} + +/** + * @brief Get the USB_SERIAL_JTAG interrupt status. + * + * @return The USB_SERIAL_JTAG interrupt status. + */ +static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void) +{ + return USB_SERIAL_JTAG.int_st.val; +} + +/** + * @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask. + * + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @return interrupt enable value + */ +static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void) +{ + return USB_SERIAL_JTAG.int_ena.val; +} + +/** + * @brief Read the bytes from the USB_SERIAL_JTAG rxfifo. + * + * @param buf The data buffer. + * @param rd_len The data length needs to be read. + * + * @return amount of bytes read + */ +static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) +{ + int i; + for (i = 0; i < (int)rd_len; i++) { + if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; + buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + } + return i; +} + +/** + * @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there + * is room in the buffer. + * + * @param buf The data buffer. + * @param wr_len The data length needs to be writen. + * + * @return Amount of bytes actually written. May be less than wr_len. + */ +static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len) +{ + int i; + for (i = 0; i < (int)wr_len; i++) { + if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; + USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + } + return i; +} + +/** + * @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available. + * + * @return 0 if no data available, 1 if data available + */ +static inline int usb_serial_jtag_ll_rxfifo_data_available(void) +{ + return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail; +} + +/** + * @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room. + * + * @return 0 if no data available, 1 if data available + */ +static inline int usb_serial_jtag_ll_txfifo_writable(void) +{ + return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free; +} + +/** + * @brief Flushes the TX buffer, that is, make it available for the + * host to pick up. + * + * @return na + */ +static inline void usb_serial_jtag_ll_txfifo_flush(void) +{ + USB_SERIAL_JTAG.ep1_conf.wr_done=1; +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/rtc_cntl_hal.c b/components/hal/esp32h2/rtc_cntl_hal.c new file mode 100644 index 0000000000..aae2bfaed8 --- /dev/null +++ b/components/hal/esp32h2/rtc_cntl_hal.c @@ -0,0 +1,61 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The HAL layer for RTC CNTL (common part) + +#include "hal/rtc_hal.h" +#include "soc/soc_caps.h" +#include "esp32c3/rom/lldesc.h" +#include "esp_attr.h" + +#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ + +typedef struct rtc_cntl_link_buf_conf { + uint32_t cfg[4]; /* 4 word for dma link buffer configuration */ +} rtc_cntl_link_buf_conf_t; + +void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next) +{ + assert(elem != NULL); + assert(buff != NULL); + assert(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN); + + lldesc_t *plink = (lldesc_t *)elem; + + plink->eof = next ? 0 : 1; + plink->owner = 1; + plink->size = size >> 4; /* in unit of 16 bytes */ + plink->length = size >> 4; + plink->buf = buff; + plink->offset = 0; + plink->sosf = 0; + STAILQ_NEXT(plink, qe) = next; + return (void *)plink; +} + +void rtc_cntl_hal_enable_cpu_retention(void *addr) +{ + if (addr) { + lldesc_t *plink = (lldesc_t *)addr; + + /* dma link buffer configure */ + rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf; + pbuf->cfg[0] = 0; + pbuf->cfg[1] = 0; + pbuf->cfg[2] = 0; + pbuf->cfg[3] = (uint32_t)-1; + + rtc_cntl_ll_enable_cpu_retention((uint32_t)addr); + } +} diff --git a/components/soc/esp32h2/CMakeLists.txt b/components/soc/esp32h2/CMakeLists.txt new file mode 100644 index 0000000000..ce1c7d526f --- /dev/null +++ b/components/soc/esp32h2/CMakeLists.txt @@ -0,0 +1,20 @@ +set(srcs + "adc_periph.c" + "gdma_periph.c" + "gpio_periph.c" + "interrupts.c" + "spi_periph.c" + "ledc_periph.c" + "rmt_periph.c" + "soc_memory_layout.c" + "sigmadelta_periph.c" + "soc_memory_layout.c" + "i2s_periph.c" + "i2c_periph.c" + "uart_periph.c" + "timer_periph.c") + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + +target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") +target_include_directories(${COMPONENT_LIB} PUBLIC . include) diff --git a/components/soc/esp32h2/adc_periph.c b/components/soc/esp32h2/adc_periph.c new file mode 100644 index 0000000000..06a835d233 --- /dev/null +++ b/components/soc/esp32h2/adc_periph.c @@ -0,0 +1,27 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { + /* ADC1 */ + { + ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM + }, + /* ADC2 */ + { + ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1 + } +}; diff --git a/components/soc/esp32h2/gdma_periph.c b/components/soc/esp32h2/gdma_periph.c new file mode 100644 index 0000000000..1475487eb5 --- /dev/null +++ b/components/soc/esp32h2/gdma_periph.c @@ -0,0 +1,37 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/gdma_periph.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_GDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_DMA_CH2_INTR_SOURCE, + .tx_irq_id = ETS_DMA_CH2_INTR_SOURCE, + } + } + } + } +}; diff --git a/components/soc/esp32h2/gpio_periph.c b/components/soc/esp32h2/gpio_periph.c new file mode 100644 index 0000000000..e72f7e20a7 --- /dev/null +++ b/components/soc/esp32h2/gpio_periph.c @@ -0,0 +1,65 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { + IO_MUX_GPIO0_REG, + IO_MUX_GPIO1_REG, + IO_MUX_GPIO2_REG, + IO_MUX_GPIO3_REG, + IO_MUX_GPIO4_REG, + IO_MUX_GPIO5_REG, + IO_MUX_GPIO6_REG, + IO_MUX_GPIO7_REG, + IO_MUX_GPIO8_REG, + IO_MUX_GPIO9_REG, + IO_MUX_GPIO10_REG, + IO_MUX_GPIO11_REG, + IO_MUX_GPIO12_REG, + IO_MUX_GPIO13_REG, + IO_MUX_GPIO14_REG, + IO_MUX_GPIO15_REG, + IO_MUX_GPIO16_REG, + IO_MUX_GPIO17_REG, + IO_MUX_GPIO18_REG, + IO_MUX_GPIO19_REG, + IO_MUX_GPIO20_REG, + IO_MUX_GPIO21_REG, +}; + +const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { + BIT(0), //GPIO0 + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(5), //GPIO6 + BIT(6), //GPIO7 + BIT(3), //GPIO8 + BIT(4), //GPIO9 + BIT(0), //GPIO10 + BIT(15), //GPIO11 + BIT(10), //GPIO12 + BIT(12), //GPIO13 + BIT(8), //GPIO14 + BIT(7), //GPIO15 + BIT(9), //GPIO16 + BIT(11), //GPIO17 + BIT(1), //GPIO18 + BIT(2), //GPIO19 + BIT(13), //GPIO20 + BIT(14), //GPIO21 +}; diff --git a/components/soc/esp32h2/i2c_bbpll.h b/components/soc/esp32h2/i2c_bbpll.h new file mode 100644 index 0000000000..c9d4753f49 --- /dev/null +++ b/components/soc/esp32h2/i2c_bbpll.h @@ -0,0 +1,183 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_apll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 1 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_BBADC_DELAY1 9 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 diff --git a/components/soc/esp32h2/i2c_periph.c b/components/soc/esp32h2/i2c_periph.c new file mode 100644 index 0000000000..67dfbc56e0 --- /dev/null +++ b/components/soc/esp32h2/i2c_periph.c @@ -0,0 +1,30 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/i2c_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { + { + .sda_out_sig = I2CEXT0_SDA_OUT_IDX, + .sda_in_sig = I2CEXT0_SDA_IN_IDX, + .scl_out_sig = I2CEXT0_SCL_OUT_IDX, + .scl_in_sig = I2CEXT0_SCL_IN_IDX, + .irq = ETS_I2C_EXT0_INTR_SOURCE, + .module = PERIPH_I2C0_MODULE, + }, +}; diff --git a/components/soc/esp32h2/i2s_periph.c b/components/soc/esp32h2/i2s_periph.c new file mode 100644 index 0000000000..b20ff7fbf8 --- /dev/null +++ b/components/soc/esp32h2/i2s_periph.c @@ -0,0 +1,38 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/i2s_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { + { + // TODO ESP32-C3 IDF-2098 + + // .o_bck_in_sig = I2S0O_BCK_IN_IDX, + // .o_ws_in_sig = I2S0O_WS_IN_IDX, + // .o_bck_out_sig = I2S0O_BCK_OUT_IDX, + // .o_ws_out_sig = I2S0O_WS_OUT_IDX, + // .o_data_out_sig = I2S0O_SD_OUT_IDX, + // .i_bck_in_sig = I2S0I_BCK_OUT_IDX, + // .i_ws_in_sig = I2S0I_WS_OUT_IDX, + // .i_bck_out_sig = I2S0I_BCK_IN_IDX, + // .i_ws_out_sig = I2S0I_WS_IN_IDX, + // .i_data_in_sig = I2S0I_SD_IN_IDX, + .irq = ETS_I2S1_INTR_SOURCE, + .module = PERIPH_I2S1_MODULE, + } +}; diff --git a/components/soc/esp32h2/include/soc/adc_channel.h b/components/soc/esp32h2/include/soc/adc_channel.h new file mode 100644 index 0000000000..9a645006c4 --- /dev/null +++ b/components/soc/esp32h2/include/soc/adc_channel.h @@ -0,0 +1,36 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_ADC_CHANNEL_H +#define _SOC_ADC_CHANNEL_H + +#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0 +#define ADC1_CHANNEL_0_GPIO_NUM 0 + +#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1 +#define ADC1_CHANNEL_1_GPIO_NUM 1 + +#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2 +#define ADC1_CHANNEL_2_GPIO_NUM 2 + +#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3 +#define ADC1_CHANNEL_3_GPIO_NUM 3 + +#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4 +#define ADC1_CHANNEL_4_GPIO_NUM 4 + +#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0 +#define ADC2_CHANNEL_0_GPIO_NUM 5 + +#endif diff --git a/components/soc/esp32h2/include/soc/apb_ctrl_reg.h b/components/soc/esp32h2/include/soc/apb_ctrl_reg.h new file mode 100644 index 0000000000..055b919b08 --- /dev/null +++ b/components/soc/esp32h2/include/soc/apb_ctrl_reg.h @@ -0,0 +1,576 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_REG_H_ +#define _SOC_APB_CTRL_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000) +/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 +/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 +/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004) +/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define APB_CTRL_TICK_ENABLE (BIT(16)) +#define APB_CTRL_TICK_ENABLE_M (BIT(16)) +#define APB_CTRL_TICK_ENABLE_V 0x1 +#define APB_CTRL_TICK_ENABLE_S 16 +/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ +/*description: */ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 8 +/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008) +/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_V 0x1 +#define APB_CTRL_CLK_XTAL_OEN_S 10 +/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_V 0x1 +#define APB_CTRL_CLK40X_BB_OEN_S 9 +/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 +#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 +/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 +#define APB_CTRL_CLK_ADC_INF_OEN_S 7 +/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_OEN (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_M (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_V 0x1 +#define APB_CTRL_CLK_320M_OEN_S 6 +/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK160_OEN (BIT(5)) +#define APB_CTRL_CLK160_OEN_M (BIT(5)) +#define APB_CTRL_CLK160_OEN_V 0x1 +#define APB_CTRL_CLK160_OEN_S 5 +/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK80_OEN (BIT(4)) +#define APB_CTRL_CLK80_OEN_M (BIT(4)) +#define APB_CTRL_CLK80_OEN_V 0x1 +#define APB_CTRL_CLK80_OEN_S 4 +/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_BB_OEN (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_M (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_V 0x1 +#define APB_CTRL_CLK_BB_OEN_S 3 +/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK44_OEN (BIT(2)) +#define APB_CTRL_CLK44_OEN_M (BIT(2)) +#define APB_CTRL_CLK44_OEN_V 0x1 +#define APB_CTRL_CLK44_OEN_S 2 +/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK22_OEN (BIT(1)) +#define APB_CTRL_CLK22_OEN_M (BIT(1)) +#define APB_CTRL_CLK22_OEN_V 0x1 +#define APB_CTRL_CLK22_OEN_S 1 +/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK20_OEN (BIT(0)) +#define APB_CTRL_CLK20_OEN_M (BIT(0)) +#define APB_CTRL_CLK20_OEN_V 0x1 +#define APB_CTRL_CLK20_OEN_S 0 + +#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C) +/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S)) +#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_S 0 + +#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010) +/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S)) +#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_2_S 0 + +#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014) +/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF +#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S)) +#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF +#define APB_CTRL_WIFI_CLK_EN_S 0 + +#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018) +/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_WIFI_RST 0xFFFFFFFF +#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S)) +#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF +#define APB_CTRL_WIFI_RST_S 0 + +#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C) +/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define APB_CTRL_PERI_IO_SWAP 0x000000FF +#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S)) +#define APB_CTRL_PERI_IO_SWAP_V 0xFF +#define APB_CTRL_PERI_IO_SWAP_S 0 + +#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020) +/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 +#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 + +#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028) +/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003 +#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S)) +#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3 +#define APB_CTRL_FLASH_ACE0_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C) +/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003 +#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S)) +#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3 +#define APB_CTRL_FLASH_ACE1_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030) +/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003 +#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S)) +#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3 +#define APB_CTRL_FLASH_ACE2_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034) +/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003 +#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S)) +#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3 +#define APB_CTRL_FLASH_ACE3_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038) +/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C) +/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040) +/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044) +/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048) +/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF +#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S)) +#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF +#define APB_CTRL_FLASH_ACE0_SIZE_S 0 + +#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C) +/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF +#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S)) +#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF +#define APB_CTRL_FLASH_ACE1_SIZE_S 0 + +#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050) +/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF +#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S)) +#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF +#define APB_CTRL_FLASH_ACE2_SIZE_S 0 + +#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054) +/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF +#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S)) +#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF +#define APB_CTRL_FLASH_ACE3_SIZE_S 0 + +#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088) +/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F +#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S)) +#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F +#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 +/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 +/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 + +#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C) +/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S)) +#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 + +#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090) +/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 +#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 + +#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094) +/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_ANDOR (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_M (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_V 0x1 +#define APB_CTRL_REDCY_ANDOR_S 31 +/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S)) +#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG0_S 0 + +#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098) +/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_NANDOR (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_M (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_V 0x1 +#define APB_CTRL_REDCY_NANDOR_S 31 +/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S)) +#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG1_S 0 + +#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C) +/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PD_S 5 +/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PU_S 4 +/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 +/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 +/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PD_S 1 +/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 + +#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0) +/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27)) +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27)) +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1 +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27 +/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: */ +#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF +#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S)) +#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF +#define APB_CTRL_RETENTION_LINK_ADDR_S 0 + +#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0x0A4) +/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ +/*description: */ +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S)) +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 2 +/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000003 +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S)) +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x3 +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0 + +#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0x0A8) +/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */ +/*description: */ +#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F +#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S)) +#define APB_CTRL_SRAM_POWER_DOWN_V 0xF +#define APB_CTRL_SRAM_POWER_DOWN_S 2 +/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define APB_CTRL_ROM_POWER_DOWN 0x00000003 +#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S)) +#define APB_CTRL_ROM_POWER_DOWN_V 0x3 +#define APB_CTRL_ROM_POWER_DOWN_S 0 + +#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0x0AC) +/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ +/*description: */ +#define APB_CTRL_SRAM_POWER_UP 0x0000000F +#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S)) +#define APB_CTRL_SRAM_POWER_UP_V 0xF +#define APB_CTRL_SRAM_POWER_UP_S 2 +/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define APB_CTRL_ROM_POWER_UP 0x00000003 +#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S)) +#define APB_CTRL_ROM_POWER_UP_V 0x3 +#define APB_CTRL_ROM_POWER_UP_S 0 + +#define APB_CTRL_RND_DATA_REG (DR_REG_APB_CTRL_BASE + 0x0B0) +/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define APB_CTRL_RND_DATA 0xFFFFFFFF +#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S)) +#define APB_CTRL_RND_DATA_V 0xFFFFFFFF +#define APB_CTRL_RND_DATA_S 0 + +#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_APB_CTRL_BASE + 0x0B4) +/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_ENA (BIT(31)) +#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31)) +#define APB_CTRL_PERI_BACKUP_ENA_V 0x1 +#define APB_CTRL_PERI_BACKUP_ENA_S 31 +/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30)) +#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30)) +#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1 +#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30 +/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_START (BIT(29)) +#define APB_CTRL_PERI_BACKUP_START_M (BIT(29)) +#define APB_CTRL_PERI_BACKUP_START_V 0x1 +#define APB_CTRL_PERI_BACKUP_START_S 29 +/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF +#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S)) +#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF +#define APB_CTRL_PERI_BACKUP_SIZE_S 19 +/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF +#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S)) +#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF +#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9 +/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F +#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S)) +#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F +#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4 +/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003 +#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S)) +#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3 +#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1 + +#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B8) +/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF +#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S)) +#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF +#define APB_CTRL_BACKUP_APB_START_ADDR_S 0 + +#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC) +/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF +#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S)) +#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF +#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0 + +#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0C0) +/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1 +#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1 +/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1 +#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0 + +#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0C4) +/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1 +#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1 +/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1 +#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0 + +#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0C8) +/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1 +#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1 +/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1 +#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0 + +#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0D0) +/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) +#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1 +#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1 +/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) +#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1 +#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */ +/*description: Version control*/ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_APB_CTRL_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/apb_ctrl_struct.h b/components/soc/esp32h2/include/soc/apb_ctrl_struct.h new file mode 100644 index 0000000000..9b832df8dd --- /dev/null +++ b/components/soc/esp32h2/include/soc/apb_ctrl_struct.h @@ -0,0 +1,482 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_STRUCT_H_ +#define _SOC_APB_CTRL_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t pre_div: 10; + uint32_t clk_320m_en: 1; + uint32_t clk_en: 1; + uint32_t rst_tick: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t xtal_tick: 8; + uint32_t ck8m_tick: 8; + uint32_t tick_enable: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } tick_conf; + union { + struct { + uint32_t clk20_oen: 1; + uint32_t clk22_oen: 1; + uint32_t clk44_oen: 1; + uint32_t clk_bb_oen: 1; + uint32_t clk80_oen: 1; + uint32_t clk160_oen: 1; + uint32_t clk_320m_oen: 1; + uint32_t clk_adc_inf_oen: 1; + uint32_t clk_dac_cpu_oen: 1; + uint32_t clk40x_bb_oen: 1; + uint32_t clk_xtal_oen: 1; + uint32_t reserved11: 21; + }; + uint32_t val; + } clk_out_en; + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ + union { + struct { + uint32_t peri_io_swap: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } host_inf_sel; + union { + struct { + uint32_t ext_mem_pms_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } ext_mem_pms_lock; + uint32_t reserved_24; + union { + struct { + uint32_t flash_ace0_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace0_attr; + union { + struct { + uint32_t flash_ace1_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace1_attr; + union { + struct { + uint32_t flash_ace2_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace2_attr; + union { + struct { + uint32_t flash_ace3_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace3_attr; + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ + union { + struct { + uint32_t flash_ace0_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace0_size; + union { + struct { + uint32_t flash_ace1_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace1_size; + union { + struct { + uint32_t flash_ace2_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace2_size; + union { + struct { + uint32_t flash_ace3_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace3_size; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + union { + struct { + uint32_t spi_mem_reject_int: 1; + uint32_t spi_mem_reject_clr: 1; + uint32_t spi_mem_reject_cde: 5; + uint32_t reserved7: 25; + }; + uint32_t val; + } spi_mem_pms_ctrl; + uint32_t spi_mem_reject_addr; /**/ + union { + struct { + uint32_t sdio_win_access_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } sdio_ctrl; + union { + struct { + uint32_t redcy_sig0: 31; + uint32_t redcy_andor: 1; + }; + uint32_t val; + } redcy_sig0; + union { + struct { + uint32_t redcy_sig1: 31; + uint32_t redcy_nandor: 1; + }; + uint32_t val; + } redcy_sig1; + union { + struct { + uint32_t agc_mem_force_pu: 1; + uint32_t agc_mem_force_pd: 1; + uint32_t pbus_mem_force_pu: 1; + uint32_t pbus_mem_force_pd: 1; + uint32_t dc_mem_force_pu: 1; + uint32_t dc_mem_force_pd: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } front_end_mem_pd; + union { + struct { + uint32_t retention_link_addr: 27; + uint32_t nobypass_cpu_iso_rst: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t rom_clkgate_force_on: 2; + uint32_t sram_clkgate_force_on: 4; + uint32_t reserved6: 26; + }; + uint32_t val; + } clkgate_force_on; + union { + struct { + uint32_t rom_power_down: 2; + uint32_t sram_power_down: 4; + uint32_t reserved6: 26; + }; + uint32_t val; + } mem_power_down; + union { + struct { + uint32_t rom_power_up: 2; + uint32_t sram_power_up: 4; + uint32_t reserved6: 26; + }; + uint32_t val; + } mem_power_up; + uint32_t rnd_data; /**/ + union { + struct { + uint32_t reserved0: 1; + uint32_t peri_backup_flow_err: 2; + uint32_t reserved3: 1; + uint32_t peri_backup_burst_limit: 5; + uint32_t peri_backup_tout_thres: 10; + uint32_t peri_backup_size: 10; + uint32_t peri_backup_start: 1; + uint32_t peri_backup_to_mem: 1; + uint32_t peri_backup_ena: 1; + }; + uint32_t val; + } peri_backup_config; + uint32_t peri_backup_addr; /**/ + uint32_t peri_backup_mem_addr; /**/ + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_raw; + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_st; + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_ena; + uint32_t reserved_cc; + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_clr; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t date; /*Version control*/ +} apb_ctrl_dev_t; +extern apb_ctrl_dev_t APB_CTRL; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_APB_CTRL_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/apb_saradc_reg.h b/components/soc/esp32h2/include/soc/apb_saradc_reg.h new file mode 100644 index 0000000000..69785ca84d --- /dev/null +++ b/components/soc/esp32h2/include/soc/apb_saradc_reg.h @@ -0,0 +1,631 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_SARADC_REG_H_ +#define _SOC_APB_SARADC_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) +/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ +/*description: wait arbit signal stable after sar_done*/ +#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 +#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) +#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 +#define APB_SARADC_WAIT_ARB_CYCLE_S 30 +/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: force option to xpd sar blocks*/ +#define APB_SARADC_XPD_SAR_FORCE 0x00000003 +#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) +#define APB_SARADC_XPD_SAR_FORCE_V 0x3 +#define APB_SARADC_XPD_SAR_FORCE_S 27 +/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23)) +#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR_PATT_P_CLEAR_S 23 +/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_SARADC_SAR_PATT_LEN 0x00000007 +#define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S)) +#define APB_SARADC_SAR_PATT_LEN_V 0x7 +#define APB_SARADC_SAR_PATT_LEN_S 15 +/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) +#define APB_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_SARADC_SAR_CLK_DIV_S 7 +/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_SARADC_SAR_CLK_GATED_S 6 +/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_START (BIT(1)) +#define APB_SARADC_START_M (BIT(1)) +#define APB_SARADC_START_V 0x1 +#define APB_SARADC_START_S 1 +/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_START_FORCE_M (BIT(0)) +#define APB_SARADC_START_FORCE_V 0x1 +#define APB_SARADC_START_FORCE_S 0 + +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) +/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: to enable saradc timer trigger*/ +#define APB_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_TIMER_EN_M (BIT(24)) +#define APB_SARADC_TIMER_EN_V 0x1 +#define APB_SARADC_TIMER_EN_S 24 +/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ +/*description: to set saradc timer target*/ +#define APB_SARADC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) +#define APB_SARADC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_TIMER_TARGET_S 12 +/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SAR2_INV_M (BIT(10)) +#define APB_SARADC_SAR2_INV_V 0x1 +#define APB_SARADC_SAR2_INV_S 10 +/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SAR1_INV_M (BIT(9)) +#define APB_SARADC_SAR1_INV_V 0x1 +#define APB_SARADC_SAR1_INV_S 9 +/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) +#define APB_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_SARADC_MAX_MEAS_NUM_S 1 +/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008) +/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define APB_SARADC_FILTER_FACTOR0 0x00000007 +#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S)) +#define APB_SARADC_FILTER_FACTOR0_V 0x7 +#define APB_SARADC_FILTER_FACTOR0_S 29 +/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: */ +#define APB_SARADC_FILTER_FACTOR1 0x00000007 +#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S)) +#define APB_SARADC_FILTER_FACTOR1_V 0x7 +#define APB_SARADC_FILTER_FACTOR1_S 26 + +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) +/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ +/*description: */ +#define APB_SARADC_STANDBY_WAIT 0x000000FF +#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) +#define APB_SARADC_STANDBY_WAIT_V 0xFF +#define APB_SARADC_STANDBY_WAIT_S 16 +/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ +/*description: */ +#define APB_SARADC_RSTB_WAIT 0x000000FF +#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) +#define APB_SARADC_RSTB_WAIT_V 0xFF +#define APB_SARADC_RSTB_WAIT_S 8 +/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_SARADC_XPD_WAIT 0x000000FF +#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) +#define APB_SARADC_XPD_WAIT_V 0xFF +#define APB_SARADC_XPD_WAIT_S 0 + +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) +/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) +#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_S 0 + +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) +/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) +#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_S 0 + +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) +/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF +#define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S)) +#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF +#define APB_SARADC_SAR_PATT_TAB1_S 0 + +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) +/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF +#define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S)) +#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF +#define APB_SARADC_SAR_PATT_TAB2_S 0 + +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x020) +/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31)) +#define APB_SARADC1_ONETIME_SAMPLE_V 0x1 +#define APB_SARADC1_ONETIME_SAMPLE_S 31 +/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30)) +#define APB_SARADC2_ONETIME_SAMPLE_V 0x1 +#define APB_SARADC2_ONETIME_SAMPLE_S 30 +/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_ONETIME_START_M (BIT(29)) +#define APB_SARADC_ONETIME_START_V 0x1 +#define APB_SARADC_ONETIME_START_S 29 +/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */ +/*description: */ +#define APB_SARADC_ONETIME_CHANNEL 0x0000000F +#define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S)) +#define APB_SARADC_ONETIME_CHANNEL_V 0xF +#define APB_SARADC_ONETIME_CHANNEL_S 25 +/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ +/*description: */ +#define APB_SARADC_ONETIME_ATTEN 0x00000003 +#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S)) +#define APB_SARADC_ONETIME_ATTEN_V 0x3 +#define APB_SARADC_ONETIME_ATTEN_S 23 + +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024) +/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: adc2 arbiter uses fixed priority*/ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 +/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ +/*description: Set adc2 arbiter wifi priority*/ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ +/*description: Set adc2 arbiter rtc priority*/ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Set adc2 arbiterapb priority*/ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: adc2 arbiter force grant*/ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enable wifi controller*/ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enable rtc controller*/ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enableapb controller*/ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 + +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x028) +/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable apb_adc1_filter*/ +#define APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_FILTER_RESET_M (BIT(31)) +#define APB_SARADC_FILTER_RESET_V 0x1 +#define APB_SARADC_FILTER_RESET_S 31 +/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */ +/*description: apb_adc1_filter_factor*/ +#define APB_SARADC_FILTER_CHANNEL0 0x0000000F +#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S)) +#define APB_SARADC_FILTER_CHANNEL0_V 0xF +#define APB_SARADC_FILTER_CHANNEL0_S 22 +/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */ +/*description: */ +#define APB_SARADC_FILTER_CHANNEL1 0x0000000F +#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S)) +#define APB_SARADC_FILTER_CHANNEL1_V 0xF +#define APB_SARADC_FILTER_CHANNEL1_S 18 + +#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x02C) +/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DATA 0x0001FFFF +#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S)) +#define APB_SARADC_ADC1_DATA_V 0x1FFFF +#define APB_SARADC_ADC1_DATA_S 0 + +#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x030) +/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DATA 0x0001FFFF +#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S)) +#define APB_SARADC_ADC2_DATA_V 0x1FFFF +#define APB_SARADC_ADC2_DATA_S 0 + +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x034) +/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES0_LOW 0x00001FFF +#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S)) +#define APB_SARADC_THRES0_LOW_V 0x1FFF +#define APB_SARADC_THRES0_LOW_S 18 +/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES0_HIGH 0x00001FFF +#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S)) +#define APB_SARADC_THRES0_HIGH_V 0x1FFF +#define APB_SARADC_THRES0_HIGH_S 5 +/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ +/*description: */ +#define APB_SARADC_THRES0_CHANNEL 0x0000000F +#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S)) +#define APB_SARADC_THRES0_CHANNEL_V 0xF +#define APB_SARADC_THRES0_CHANNEL_S 0 + +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) +/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES1_LOW 0x00001FFF +#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S)) +#define APB_SARADC_THRES1_LOW_V 0x1FFF +#define APB_SARADC_THRES1_LOW_S 18 +/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES1_HIGH 0x00001FFF +#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S)) +#define APB_SARADC_THRES1_HIGH_V 0x1FFF +#define APB_SARADC_THRES1_HIGH_S 5 +/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ +/*description: */ +#define APB_SARADC_THRES1_CHANNEL 0x0000000F +#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S)) +#define APB_SARADC_THRES1_CHANNEL_V 0xF +#define APB_SARADC_THRES1_CHANNEL_S 0 + +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C) +/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_THRES0_EN_M (BIT(31)) +#define APB_SARADC_THRES0_EN_V 0x1 +#define APB_SARADC_THRES0_EN_S 31 +/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_THRES1_EN_M (BIT(30)) +#define APB_SARADC_THRES1_EN_V 0x1 +#define APB_SARADC_THRES1_EN_S 30 +/*description: */ +#define APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_V 0x1 +#define APB_SARADC_THRES_ALL_EN_S 27 + +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x040) +/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 +/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 +/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ENA_S 26 + +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044) +/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 +/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 +/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_RAW_S 26 + +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x048) +/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ST_S 31 +/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ST_S 30 +/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ST_S 27 +/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ST_S 26 + +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x04C) +/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 +/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 +/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_CLR_S 26 + +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x050) +/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: enable apb_adc use spi_dma*/ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_V 0x1 +#define APB_SARADC_APB_ADC_TRANS_S 31 +/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: reset_apb_adc_state*/ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ +/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF +#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 + +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x054) +/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ +/*description: Set this bit to enable clk_apll*/ +#define APB_SARADC_CLK_SEL 0x00000003 +#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) +#define APB_SARADC_CLK_SEL_V 0x3 +#define APB_SARADC_CLK_SEL_S 21 +/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (BIT(20)) +#define APB_SARADC_CLK_EN_V 0x1 +#define APB_SARADC_CLK_EN_S 20 +/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ +/*description: Fractional clock divider denominator value*/ +#define APB_SARADC_CLKM_DIV_A 0x0000003F +#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) +#define APB_SARADC_CLKM_DIV_A_V 0x3F +#define APB_SARADC_CLKM_DIV_A_S 14 +/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ +/*description: Fractional clock divider numerator value*/ +#define APB_SARADC_CLKM_DIV_B 0x0000003F +#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) +#define APB_SARADC_CLKM_DIV_B_V 0x3F +#define APB_SARADC_CLKM_DIV_B_S 8 +/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ +/*description: Integral I2S clock divider value*/ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FF +#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) +#define APB_SARADC_CLKM_DIV_NUM_V 0xFF +#define APB_SARADC_CLKM_DIV_NUM_S 0 + +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058) +/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_TSENS_PU (BIT(22)) +#define APB_SARADC_TSENS_PU_M (BIT(22)) +#define APB_SARADC_TSENS_PU_V 0x1 +#define APB_SARADC_TSENS_PU_S 22 +/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ +/*description: */ +#define APB_SARADC_TSENS_CLK_DIV 0x000000FF +#define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S)) +#define APB_SARADC_TSENS_CLK_DIV_V 0xFF +#define APB_SARADC_TSENS_CLK_DIV_S 14 +/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_M (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_V 0x1 +#define APB_SARADC_TSENS_IN_INV_S 13 +/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define APB_SARADC_TSENS_OUT 0x000000FF +#define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S)) +#define APB_SARADC_TSENS_OUT_V 0xFF +#define APB_SARADC_TSENS_OUT_S 0 + +#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x05C) +/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_V 0x1 +#define APB_SARADC_TSENS_CLK_SEL_S 15 +/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define APB_SARADC_TSENS_CLK_INV (BIT(14)) +#define APB_SARADC_TSENS_CLK_INV_M (BIT(14)) +#define APB_SARADC_TSENS_CLK_INV_V 0x1 +#define APB_SARADC_TSENS_CLK_INV_S 14 +/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define APB_SARADC_TSENS_XPD_FORCE 0x00000003 +#define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S)) +#define APB_SARADC_TSENS_XPD_FORCE_V 0x3 +#define APB_SARADC_TSENS_XPD_FORCE_S 12 +/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ +/*description: */ +#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF +#define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S)) +#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF +#define APB_SARADC_TSENS_XPD_WAIT_S 0 + +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x060) +/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */ +/*description: */ +#define APB_SARADC_CALI_CFG 0x0001FFFF +#define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S)) +#define APB_SARADC_CALI_CFG_V 0x1FFFF +#define APB_SARADC_CALI_CFG_S 0 + +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) +/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */ +/*description: */ +#define APB_SARADC_DATE 0xFFFFFFFF +#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S)) +#define APB_SARADC_DATE_V 0xFFFFFFFF +#define APB_SARADC_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_APB_SARADC_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/apb_saradc_struct.h b/components/soc/esp32h2/include/soc/apb_saradc_struct.h new file mode 100644 index 0000000000..c3ea73f150 --- /dev/null +++ b/components/soc/esp32h2/include/soc/apb_saradc_struct.h @@ -0,0 +1,490 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_SARADC_STRUCT_H_ +#define _SOC_APB_SARADC_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t start_force: 1; + uint32_t start: 1; + uint32_t reserved2: 4; /*0: single mode 1: double mode 2: alternate mode*/ + uint32_t sar_clk_gated: 1; + uint32_t sar_clk_div: 8; /*SAR clock divider*/ + uint32_t sar_patt_len: 3; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t reserved18: 5; + uint32_t sar_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + uint32_t reserved24: 3; + uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ + uint32_t reserved29: 1; + uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t meas_num_limit: 1; + uint32_t max_meas_num: 8; /*max conversion number*/ + uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + uint32_t reserved11: 1; /*1: select saradc timer 0: i2s_ws trigger*/ + uint32_t timer_target: 12; /*to set saradc timer target*/ + uint32_t timer_en: 1; /*to enable saradc timer trigger*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t reserved0: 26; + uint32_t filter_factor1: 3; + uint32_t filter_factor0: 3; + }; + uint32_t val; + } filter_ctrl1; + union { + struct { + uint32_t xpd_wait: 8; + uint32_t rstb_wait: 8; + uint32_t standby_wait: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } fsm_wait; + uint32_t sar1_status; /**/ + uint32_t sar2_status; /**/ + union { + struct { + uint32_t sar_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar_patt_tab[2]; + union { + struct { + uint32_t reserved0: 23; + uint32_t onetime_atten: 2; + uint32_t onetime_channel: 4; + uint32_t onetime_start: 1; + uint32_t adc2_onetime_sample: 1; + uint32_t adc1_onetime_sample: 1; + }; + uint32_t val; + } onetime_sample; + union { + struct { + uint32_t reserved0: 2; + uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ + uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ + uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ + uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ + uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ + uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ + uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ + uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } apb_adc_arb_ctrl; + union { + struct { + uint32_t reserved0: 18; + uint32_t filter_channel1: 4; + uint32_t filter_channel0: 4; /*apb_adc1_filter_factor*/ + uint32_t reserved26: 5; + uint32_t filter_reset: 1; /*enable apb_adc1_filter*/ + }; + uint32_t val; + } filter_ctrl0; + union { + struct { + uint32_t adc1_data: 17; + uint32_t reserved17:15; + }; + uint32_t val; + } apb_saradc1_data_status; + union { + struct { + uint32_t adc2_data: 17; + uint32_t reserved17:15; + }; + uint32_t val; + } apb_saradc2_data_status; + union { + struct { + uint32_t thres0_channel: 4; + uint32_t reserved4: 1; + uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } thres0_ctrl; + union { + struct { + uint32_t thres1_channel: 4; + uint32_t reserved4: 1; + uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } thres1_ctrl; + union { + struct { + uint32_t reserved0: 27; + uint32_t thres_all_en: 1; + uint32_t reserved28: 2; + uint32_t thres1_en: 1; + uint32_t thres0_en: 1; + }; + uint32_t val; + } thres_ctrl; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ + uint32_t reserved16: 14; + uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ + uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ + uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ + uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ + uint32_t clk_en: 1; + uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } apb_adc_clkm_conf; + union { + struct { + uint32_t tsens_out: 8; + uint32_t reserved8: 5; + uint32_t tsens_in_inv: 1; + uint32_t tsens_clk_div: 8; + uint32_t tsens_pu: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } apb_tsens_ctrl; + union { + struct { + uint32_t tsens_xpd_wait: 12; + uint32_t tsens_xpd_force: 2; + uint32_t tsens_clk_inv: 1; + uint32_t tsens_clk_sel: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } apb_tsens_ctrl2; + union { + struct { + uint32_t cali_cfg: 17; + uint32_t reserved17:15; + }; + uint32_t val; + } cali; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t apb_ctrl_date; /**/ +} apb_saradc_dev_t; +extern apb_saradc_dev_t APB_SARADC; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_APB_SARADC_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/assist_debug_reg.h b/components/soc/esp32h2/include/soc/assist_debug_reg.h new file mode 100644 index 0000000000..a0c1e9c9d8 --- /dev/null +++ b/components/soc/esp32h2/include/soc/assist_debug_reg.h @@ -0,0 +1,691 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_ASSIST_DEBUG_REG_H_ +#define _SOC_ASSIST_DEBUG_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 + +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 + +#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 + +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x028) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x02C) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x030) +/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x034) +/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S)) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x038) +/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S)) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x03C) +/* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S)) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x040) +/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S)) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x044) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable CPU Pdebug function if enable CPU will update PdebugPC*/ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x1 +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 +/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable recording function if enable assist_debug will update + PdebugPC so you can read it*/ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x1 +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x048) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x04C) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x050) +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x054) +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x058) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000F +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x05C) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x060) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000F +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x064) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 + +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x068) +/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x06C) +/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x070) +/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7)) +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(7)) +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1 +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7 +/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MODE 0x0000000F +#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S)) +#define ASSIST_DEBUG_LOG_MODE_V 0xF +#define ASSIST_DEBUG_LOG_MODE_S 3 +/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_ENA 0x00000007 +#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S)) +#define ASSIST_DEBUG_LOG_ENA_V 0x7 +#define ASSIST_DEBUG_LOG_ENA_S 0 + +#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x074) +/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S)) +#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_0_S 0 + +#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x078) +/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF +#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S)) +#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF +#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0 + +#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x07C) +/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S)) +#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MIN_S 0 + +#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x080) +/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S)) +#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MAX_S 0 + +#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x084) +/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S)) +#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_START_S 0 + +#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x088) +/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S)) +#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_END_S 0 + +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x08C) +/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)) +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0 + +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x090) +/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (BIT(1)) +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x1 +#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1 +/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0)) +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0)) +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1 +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0 + +#define ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094) +/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +#define ASSIST_DEBUG_C0RE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098) +/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x1 +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 +/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x1 +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 + +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC) +/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */ +/*description: */ +#define ASSIST_DEBUG_DATE 0x0FFFFFFF +#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S)) +#define ASSIST_DEBUG_DATE_V 0xFFFFFFF +#define ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_ASSIST_DEBUG_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/bb_reg.h b/components/soc/esp32h2/include/soc/bb_reg.h new file mode 100644 index 0000000000..186b6f0d2e --- /dev/null +++ b/components/soc/esp32h2/include/soc/bb_reg.h @@ -0,0 +1,37 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_M (BIT(3)) +#define BB_FFT_FORCE_PU_V 1 +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_M (BIT(2)) +#define BB_FFT_FORCE_PD_V 1 +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_M (BIT(1)) +#define BB_DC_EST_FORCE_PU_V 1 +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_M (BIT(0)) +#define BB_DC_EST_FORCE_PD_V 1 +#define BB_DC_EST_FORCE_PD_S 0 diff --git a/components/soc/esp32h2/include/soc/boot_mode.h b/components/soc/esp32h2/include/soc/boot_mode.h new file mode 100644 index 0000000000..648d0a4386 --- /dev/null +++ b/components/soc/esp32h2/include/soc/boot_mode.h @@ -0,0 +1,101 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32h2/include/soc/cache_memory.h b/components/soc/esp32h2/include/soc/cache_memory.h new file mode 100644 index 0000000000..db558c4e50 --- /dev/null +++ b/components/soc/esp32h2/include/soc/cache_memory.h @@ -0,0 +1,100 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _CACHE_MEMORY_H_ +#define _CACHE_MEMORY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*IRAM0 is connected with Cache IBUS0*/ +#define IRAM0_ADDRESS_LOW 0x40000000 +#define IRAM0_ADDRESS_HIGH 0x44000000 +#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define IRAM0_CACHE_ADDRESS_HIGH 0x42800000 + +/*DRAM0 is connected with Cache DBUS0*/ +#define DRAM0_ADDRESS_LOW 0x3C000000 +#define DRAM0_ADDRESS_HIGH 0x40000000 +#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 +#define DRAM0_CACHE_ADDRESS_HIGH 0x3C800000 +#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH +#define ESP_CACHE_TEMP_ADDR 0x3C000000 + +#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) +#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) +#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) +#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) + +#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) +#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) + +#define CACHE_IBUS 0 +#define CACHE_IBUS_MMU_START 0 +#define CACHE_IBUS_MMU_END 0x200 + +#define CACHE_DBUS 1 +#define CACHE_DBUS_MMU_START 0 +#define CACHE_DBUS_MMU_END 0x200 + +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x200 + +#define ICACHE_MMU_SIZE 0x200 +#define DCACHE_MMU_SIZE 0x200 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x200 + +#define MMU_INVALID BIT(8) +#define MMU_TYPE 0 +#define MMU_ACCESS_FLASH 0 + +#define CACHE_MAX_SYNC_NUM 0x400000 +#define CACHE_MAX_LOCK_NUM 0x8000 + +#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) +#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) + +#define MMU_TABLE_INVALID_VAL 0x100 +#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL +#define MMU_ADDRESS_MASK 0xff +#define MMU_PAGE_SIZE 0x10000 +#define INVALID_PHY_PAGE 0xffff + +#define BUS_ADDR_SIZE 0x800000 +#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) + +#define CACHE_ICACHE_LOW_SHIFT 0 +#define CACHE_ICACHE_HIGH_SHIFT 2 +#define CACHE_DCACHE_LOW_SHIFT 4 +#define CACHE_DCACHE_HIGH_SHIFT 6 + +#define CACHE_MEMORY_IBANK0_ADDR 0x4037c000 + +#ifdef __cplusplus +} +#endif + +#endif /*_CACHE_MEMORY_H_ */ diff --git a/components/soc/esp32h2/include/soc/clkout_channel.h b/components/soc/esp32h2/include/soc/clkout_channel.h new file mode 100644 index 0000000000..c9e9a0c245 --- /dev/null +++ b/components/soc/esp32h2/include/soc/clkout_channel.h @@ -0,0 +1,26 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_CLKOUT_CHANNEL_H +#define _SOC_CLKOUT_CHANNEL_H + +//CLKOUT channels +#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 +#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 +#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 +#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 +#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 +#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 + +#endif diff --git a/components/soc/esp32h2/include/soc/dport_access.h b/components/soc/esp32h2/include/soc/dport_access.h new file mode 100644 index 0000000000..e6dfa2bec0 --- /dev/null +++ b/components/soc/esp32h2/include/soc/dport_access.h @@ -0,0 +1,111 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DPORT_ACCESS_H_ +#define _DPORT_ACCESS_H_ + +#include +#include "esp_attr.h" +#include "esp_attr.h" +#include "esp32c3/dport_access.h" +#include "soc.h" +#include "uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif + +#endif /* _DPORT_ACCESS_H_ */ diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/include/soc/efuse_reg.h new file mode 100644 index 0000000000..ddaff7285c --- /dev/null +++ b/components/soc/esp32h2/include/soc/efuse_reg.h @@ -0,0 +1,2061 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_EFUSE_REG_H_ +#define _SOC_EFUSE_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) +/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Disable programming of individual eFuses.*/ +#define EFUSE_WR_DIS 0xFFFFFFFF +#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) +#define EFUSE_WR_DIS_V 0xFFFFFFFF +#define EFUSE_WR_DIS_S 0 + +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) +/* EFUSE_POWER_GLITCH_DSENSE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: Sample delay configuration of power glitch.*/ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 +#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 +#define EFUSE_POWER_GLITCH_DSENSE_S 30 +/* EFUSE_POWERGLITCH_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable power glitch function.*/ +#define EFUSE_POWERGLITCH_EN (BIT(29)) +#define EFUSE_POWERGLITCH_EN_M (BIT(29)) +#define EFUSE_POWERGLITCH_EN_V 0x1 +#define EFUSE_POWERGLITCH_EN_S 29 +/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */ +/*description: Enable btlc gpio.*/ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 +#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) +#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 +#define EFUSE_BTLC_GPIO_ENABLE_S 27 +/* EFUSE_VDD_SPI_AS_GPIO : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to vdd spi pin function as gpio.*/ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to exchange USB D+ and D- pins.*/ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_V 0x1 +#define EFUSE_USB_EXCHG_PINS_S 25 +/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with + step of 80 mV stored in eFuse.*/ +#define EFUSE_USB_DREFL 0x00000003 +#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) +#define EFUSE_USB_DREFL_V 0x3 +#define EFUSE_USB_DREFL_S 23 +/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with + step of 80 mV stored in eFuse.*/ +#define EFUSE_USB_DREFH 0x00000003 +#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) +#define EFUSE_USB_DREFH_V 0x3 +#define EFUSE_USB_DREFH_S 21 +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to disable flash encryption when in download boot modes.*/ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/* EFUSE_DIS_PAD_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_V 0x1 +#define EFUSE_DIS_PAD_JTAG_S 19 +/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: Set these bits to disable JTAG in the soft way (odd number 1 + means disable ). JTAG can be enabled in HMAC module.*/ +#define EFUSE_SOFT_DIS_JTAG 0x00000007 +#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) +#define EFUSE_SOFT_DIS_JTAG_V 0x7 +#define EFUSE_SOFT_DIS_JTAG_S 16 +/* EFUSE_JTAG_SEL_ENABLE : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag + through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_V 0x1 +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/* EFUSE_DIS_TWAI : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to disable TWAI function.*/ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (BIT(14)) +#define EFUSE_DIS_TWAI_V 0x1 +#define EFUSE_DIS_TWAI_S 14 +/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Reserved..*/ +#define EFUSE_RPT4_RESERVED6 (BIT(13)) +#define EFUSE_RPT4_RESERVED6_M (BIT(13)) +#define EFUSE_RPT4_RESERVED6_V 0x1 +#define EFUSE_RPT4_RESERVED6_S 13 +/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to disable the function that forces chip into download mode.*/ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/* EFUSE_DIS_USB_DEVICE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to disable usb device.*/ +#define EFUSE_DIS_USB_DEVICE (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_V 0x1 +#define EFUSE_DIS_USB_DEVICE_S 11 +/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] + is 0 1 2 3 6 7).*/ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/* EFUSE_DIS_USB_JTAG : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to disable function of usb switch to jtag in module of usb device.*/ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (BIT(9)) +#define EFUSE_DIS_USB_JTAG_V 0x1 +#define EFUSE_DIS_USB_JTAG_S 9 +/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to disable Icache.*/ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (BIT(8)) +#define EFUSE_DIS_ICACHE_V 0x1 +#define EFUSE_DIS_ICACHE_S 8 +/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to disable boot from RTC RAM.*/ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: Set this bit to disable reading from BlOCK4-10.*/ +#define EFUSE_RD_DIS 0x0000007F +#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) +#define EFUSE_RD_DIS_V 0x7F +#define EFUSE_RD_DIS_S 0 + +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) +/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: Purpose of Key1.*/ +#define EFUSE_KEY_PURPOSE_1 0x0000000F +#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) +#define EFUSE_KEY_PURPOSE_1_V 0xF +#define EFUSE_KEY_PURPOSE_1_S 28 +/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: Purpose of Key0.*/ +#define EFUSE_KEY_PURPOSE_0 0x0000000F +#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) +#define EFUSE_KEY_PURPOSE_0_V 0xF +#define EFUSE_KEY_PURPOSE_0_S 24 +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable revoking third secure boot key.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable revoking second secure boot key.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to enable revoking first secure boot key.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of + 1: enable. even number of 1: disable.*/ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: Selects RTC watchdog timeout threshold in unit of slow clock + cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ +#define EFUSE_WAT_DELAY_SEL 0x00000003 +#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) +#define EFUSE_WAT_DELAY_SEL_V 0x3 +#define EFUSE_WAT_DELAY_SEL_S 16 +/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 2'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED2 0x0000FFFF +#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) +#define EFUSE_RPT4_RESERVED2_V 0xFFFF +#define EFUSE_RPT4_RESERVED2_S 0 + +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) +/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: Configures flash waiting time after power-up in unit of ms. + If the value is less than 15 the waiting time is the configurable value*/ +#define EFUSE_FLASH_TPUW 0x0000000F +#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) +#define EFUSE_FLASH_TPUW_V 0xF +#define EFUSE_FLASH_TPUW_S 28 +/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED0 0x0000003F +#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) +#define EFUSE_RPT4_RESERVED0_V 0x3F +#define EFUSE_RPT4_RESERVED0_S 22 +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to enable revoking aggressive secure boot.*/ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to enable secure boot.*/ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_V 0x1 +#define EFUSE_SECURE_BOOT_EN_S 20 +/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED3 0x0000000F +#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) +#define EFUSE_RPT4_RESERVED3_V 0xF +#define EFUSE_RPT4_RESERVED3_S 16 +/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: Purpose of Key5.*/ +#define EFUSE_KEY_PURPOSE_5 0x0000000F +#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) +#define EFUSE_KEY_PURPOSE_5_V 0xF +#define EFUSE_KEY_PURPOSE_5_S 12 +/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: Purpose of Key4.*/ +#define EFUSE_KEY_PURPOSE_4 0x0000000F +#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) +#define EFUSE_KEY_PURPOSE_4_V 0xF +#define EFUSE_KEY_PURPOSE_4_S 8 +/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: Purpose of Key3.*/ +#define EFUSE_KEY_PURPOSE_3 0x0000000F +#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) +#define EFUSE_KEY_PURPOSE_3_V 0xF +#define EFUSE_KEY_PURPOSE_3_S 4 +/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: Purpose of Key2.*/ +#define EFUSE_KEY_PURPOSE_2 0x0000000F +#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) +#define EFUSE_KEY_PURPOSE_2_V 0xF +#define EFUSE_KEY_PURPOSE_2_S 0 + +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) +/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED1 0x00000003 +#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) +#define EFUSE_RPT4_RESERVED1_V 0x3 +#define EFUSE_RPT4_RESERVED1_S 30 +/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */ +/*description: Secure version (used by ESP-IDF anti-rollback feature).*/ +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) +#define EFUSE_SECURE_VERSION_V 0xFFFF +#define EFUSE_SECURE_VERSION_S 14 +/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_V 0x1 +#define EFUSE_FORCE_SEND_RESUME_S 13 +/* EFUSE_FLASH_ECC_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set 1 to enable ECC for flash boot.*/ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (BIT(12)) +#define EFUSE_FLASH_ECC_EN_V 0x1 +#define EFUSE_FLASH_ECC_EN_S 12 +/* EFUSE_FLASH_PAGE_SIZE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: Set Flash page size.*/ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003 +#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) +#define EFUSE_FLASH_PAGE_SIZE_V 0x3 +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (BIT(9)) +#define EFUSE_FLASH_TYPE_V 0x1 +#define EFUSE_FLASH_TYPE_S 9 +/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_V 0x1 +#define EFUSE_PIN_POWER_SELECTION_S 8 +/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: Set the default UARTboot message output mode. 00: Enabled. 01: + Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ +#define EFUSE_UART_PRINT_CONTROL 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) +#define EFUSE_UART_PRINT_CONTROL_V 0x3 +#define EFUSE_UART_PRINT_CONTROL_S 6 +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable secure UART download mode.*/ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to disable UART download mode through USB.*/ +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 +/* EFUSE_FLASH_ECC_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set ECC mode in ROM 0: ROM would Enable Flash ECC 16to18 byte + mode. 1:ROM would use 16to17 byte mode.*/ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_M (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_V 0x1 +#define EFUSE_FLASH_ECC_MODE_S 3 +/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Selectes the default UART print channel. 0: UART0. 1: UART1.*/ +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_V 0x1 +#define EFUSE_UART_PRINT_CHANNEL_S 2 +/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 +/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 + +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) +/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) +#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 + +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) +/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the sixth 32-bit data to be programmed.*/ +#define EFUSE_PGM_DATA_6 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_S 0 + +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) +/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the seventh 32-bit data to be programmed.*/ +#define EFUSE_PGM_DATA_7 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_S 0 + +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) +/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 0th 32-bit RS code to be programmed.*/ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_S 0 + +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) +/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the first 32-bit RS code to be programmed.*/ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_S 0 + +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) +/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the second 32-bit RS code to be programmed.*/ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_S 0 + +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02C) +/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The value of WR_DIS.*/ +#define EFUSE_WR_DIS 0xFFFFFFFF +#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) +#define EFUSE_WR_DIS_V 0xFFFFFFFF +#define EFUSE_WR_DIS_S 0 + +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) +/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: The value of POWER_GLITCH_DSENSE.*/ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 +#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 +#define EFUSE_POWER_GLITCH_DSENSE_S 30 +/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The value of POWERGLITCH_EN.*/ +#define EFUSE_POWERGLITCH_EN (BIT(29)) +#define EFUSE_POWERGLITCH_EN_M (BIT(29)) +#define EFUSE_POWERGLITCH_EN_V 0x1 +#define EFUSE_POWERGLITCH_EN_S 29 +/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ +/*description: The value of BTLC_GPIO_ENABLE.*/ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 +#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) +#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 +#define EFUSE_BTLC_GPIO_ENABLE_S 27 +/* EFUSE_VDD_SPI_AS_GPIO : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The value of VDD_SPI_AS_GPIO.*/ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The value of USB_EXCHG_PINS.*/ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_V 0x1 +#define EFUSE_USB_EXCHG_PINS_S 25 +/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: The value of USB_DREFL.*/ +#define EFUSE_USB_DREFL 0x00000003 +#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) +#define EFUSE_USB_DREFL_V 0x3 +#define EFUSE_USB_DREFL_S 23 +/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: The value of USB_DREFH.*/ +#define EFUSE_USB_DREFH 0x00000003 +#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) +#define EFUSE_USB_DREFH_V 0x3 +#define EFUSE_USB_DREFH_S 21 +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The value of DIS_PAD_JTAG.*/ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_V 0x1 +#define EFUSE_DIS_PAD_JTAG_S 19 +/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: The value of SOFT_DIS_JTAG.*/ +#define EFUSE_SOFT_DIS_JTAG 0x00000007 +#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) +#define EFUSE_SOFT_DIS_JTAG_V 0x7 +#define EFUSE_SOFT_DIS_JTAG_S 16 +/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The value of JTAG_SEL_ENABLE.*/ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_V 0x1 +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The value of DIS_TWAI.*/ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (BIT(14)) +#define EFUSE_DIS_TWAI_V 0x1 +#define EFUSE_DIS_TWAI_S 14 +/* EFUSE_RPT4_RESERVED6 : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Reserved (used for four backups method)..*/ +#define EFUSE_RPT4_RESERVED6 (BIT(13)) +#define EFUSE_RPT4_RESERVED6_M (BIT(13)) +#define EFUSE_RPT4_RESERVED6_V 0x1 +#define EFUSE_RPT4_RESERVED6_S 13 +/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The value of DIS_FORCE_DOWNLOAD.*/ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The value of DIS_USB_DEVICE.*/ +#define EFUSE_DIS_USB_DEVICE (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_V 0x1 +#define EFUSE_DIS_USB_DEVICE_S 11 +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The value of DIS_DOWNLOAD_ICACHE.*/ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The value of DIS_USB_JTAG.*/ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (BIT(9)) +#define EFUSE_DIS_USB_JTAG_V 0x1 +#define EFUSE_DIS_USB_JTAG_S 9 +/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The value of DIS_ICACHE.*/ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (BIT(8)) +#define EFUSE_DIS_ICACHE_V 0x1 +#define EFUSE_DIS_ICACHE_S 8 +/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The value of DIS_RTC_RAM_BOOT.*/ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: The value of RD_DIS.*/ +#define EFUSE_RD_DIS 0x0000007F +#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) +#define EFUSE_RD_DIS_V 0x7F +#define EFUSE_RD_DIS_S 0 + +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) +/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_1.*/ +#define EFUSE_KEY_PURPOSE_1 0x0000000F +#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) +#define EFUSE_KEY_PURPOSE_1_V 0xF +#define EFUSE_KEY_PURPOSE_1_S 28 +/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_0.*/ +#define EFUSE_KEY_PURPOSE_0 0x0000000F +#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) +#define EFUSE_KEY_PURPOSE_0_V 0xF +#define EFUSE_KEY_PURPOSE_0_S 24 +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: The value of SPI_BOOT_CRYPT_CNT.*/ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The value of WDT_DELAY_SEL.*/ +#define EFUSE_WDT_DELAY_SEL 0x00000003 +#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) +#define EFUSE_WDT_DELAY_SEL_V 0x3 +#define EFUSE_WDT_DELAY_SEL_S 16 +/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED2 0x0000FFFF +#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) +#define EFUSE_RPT4_RESERVED2_V 0xFFFF +#define EFUSE_RPT4_RESERVED2_S 0 + +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) +/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: The value of FLASH_TPUW.*/ +#define EFUSE_FLASH_TPUW 0x0000000F +#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) +#define EFUSE_FLASH_TPUW_V 0xF +#define EFUSE_FLASH_TPUW_S 28 +/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED0 0x0000003F +#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) +#define EFUSE_RPT4_RESERVED0_V 0x3F +#define EFUSE_RPT4_RESERVED0_S 22 +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The value of SECURE_BOOT_EN.*/ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_V 0x1 +#define EFUSE_SECURE_BOOT_EN_S 20 +/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED3 0x0000000F +#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) +#define EFUSE_RPT4_RESERVED3_V 0xF +#define EFUSE_RPT4_RESERVED3_S 16 +/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_5.*/ +#define EFUSE_KEY_PURPOSE_5 0x0000000F +#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) +#define EFUSE_KEY_PURPOSE_5_V 0xF +#define EFUSE_KEY_PURPOSE_5_S 12 +/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_4.*/ +#define EFUSE_KEY_PURPOSE_4 0x0000000F +#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) +#define EFUSE_KEY_PURPOSE_4_V 0xF +#define EFUSE_KEY_PURPOSE_4_S 8 +/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_3.*/ +#define EFUSE_KEY_PURPOSE_3 0x0000000F +#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) +#define EFUSE_KEY_PURPOSE_3_V 0xF +#define EFUSE_KEY_PURPOSE_3_S 4 +/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_2.*/ +#define EFUSE_KEY_PURPOSE_2 0x0000000F +#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) +#define EFUSE_KEY_PURPOSE_2_V 0xF +#define EFUSE_KEY_PURPOSE_2_S 0 + +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C) +/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED1 0x00000003 +#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) +#define EFUSE_RPT4_RESERVED1_V 0x3 +#define EFUSE_RPT4_RESERVED1_S 30 +/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ +/*description: The value of SECURE_VERSION.*/ +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) +#define EFUSE_SECURE_VERSION_V 0xFFFF +#define EFUSE_SECURE_VERSION_S 14 +/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The value of FORCE_SEND_RESUME.*/ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_V 0x1 +#define EFUSE_FORCE_SEND_RESUME_S 13 +/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The value of FLASH_ECC_EN.*/ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (BIT(12)) +#define EFUSE_FLASH_ECC_EN_V 0x1 +#define EFUSE_FLASH_ECC_EN_S 12 +/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: The value of FLASH_PAGE_SIZE.*/ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003 +#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) +#define EFUSE_FLASH_PAGE_SIZE_V 0x3 +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The value of FLASH_TYPE.*/ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (BIT(9)) +#define EFUSE_FLASH_TYPE_V 0x1 +#define EFUSE_FLASH_TYPE_S 9 +/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The value of PIN_POWER_SELECTION.*/ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_V 0x1 +#define EFUSE_PIN_POWER_SELECTION_S 8 +/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The value of UART_PRINT_CONTROL.*/ +#define EFUSE_UART_PRINT_CONTROL 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) +#define EFUSE_UART_PRINT_CONTROL_V 0x3 +#define EFUSE_UART_PRINT_CONTROL_S 6 +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The value of DIS_USB_DOWNLOAD_MODE.*/ +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 +/* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The value of FLASH_ECC_MODE.*/ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_M (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_V 0x1 +#define EFUSE_FLASH_ECC_MODE_S 3 +/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The value of UART_PRINT_CHANNEL.*/ +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_V 0x1 +#define EFUSE_UART_PRINT_CHANNEL_S 2 +/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The value of DIS_LEGACY_SPI_BOOT.*/ +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 +/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The value of DIS_DOWNLOAD_MODE.*/ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 + +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) +/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) +#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 + +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) +/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the low 32 bits of MAC address.*/ +#define EFUSE_MAC_0 0xFFFFFFFF +#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) +#define EFUSE_MAC_0_V 0xFFFFFFFF +#define EFUSE_MAC_0_S 0 + +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) +/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: Stores the zeroth part of SPI_PAD_CONF.*/ +#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) +#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF +#define EFUSE_SPI_PAD_CONF_0_S 16 +/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: Stores the high 16 bits of MAC address.*/ +#define EFUSE_MAC_1 0x0000FFFF +#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) +#define EFUSE_MAC_1_V 0xFFFF +#define EFUSE_MAC_1_S 0 + +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04C) +/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first part of SPI_PAD_CONF.*/ +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) +/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Stores the fist 8 bits of the zeroth part of system data.*/ +#define EFUSE_SYS_DATA_PART0_0 0x000000FF +#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) +#define EFUSE_SYS_DATA_PART0_0_V 0xFF +#define EFUSE_SYS_DATA_PART0_0_S 25 +/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: Package version 0:ESP32-C3 */ +#define EFUSE_PKG_VERSION 0x00000007 +#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) +#define EFUSE_PKG_VERSION_V 0x7 +#define EFUSE_PKG_VERSION_S 21 +/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: WAFER version 0:A */ +#define EFUSE_WAFER_VERSION 0x00000007 +#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) +#define EFUSE_WAFER_VERSION_V 0x7 +#define EFUSE_WAFER_VERSION_S 18 +/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ +/*description: Stores the second part of SPI_PAD_CONF.*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) +#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) +/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fist 32 bits of the zeroth part of system data.*/ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_S 0 + +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) +/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of the zeroth part of system data.*/ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_S 0 + +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05C) +/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_S 0 + +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) +/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_S 0 + +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) +/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_S 0 + +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) +/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_S 0 + +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06C) +/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_S 0 + +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) +/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_S 0 + +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) +/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_S 0 + +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) +/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_S 0 + +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07C) +/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA0 0xFFFFFFFF +#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) +#define EFUSE_USR_DATA0_V 0xFFFFFFFF +#define EFUSE_USR_DATA0_S 0 + +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) +/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA1 0xFFFFFFFF +#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) +#define EFUSE_USR_DATA1_V 0xFFFFFFFF +#define EFUSE_USR_DATA1_S 0 + +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) +/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA2 0xFFFFFFFF +#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) +#define EFUSE_USR_DATA2_V 0xFFFFFFFF +#define EFUSE_USR_DATA2_S 0 + +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) +/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA3 0xFFFFFFFF +#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) +#define EFUSE_USR_DATA3_V 0xFFFFFFFF +#define EFUSE_USR_DATA3_S 0 + +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08C) +/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA4 0xFFFFFFFF +#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) +#define EFUSE_USR_DATA4_V 0xFFFFFFFF +#define EFUSE_USR_DATA4_S 0 + +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) +/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA5 0xFFFFFFFF +#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) +#define EFUSE_USR_DATA5_V 0xFFFFFFFF +#define EFUSE_USR_DATA5_S 0 + +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) +/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA6 0xFFFFFFFF +#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) +#define EFUSE_USR_DATA6_V 0xFFFFFFFF +#define EFUSE_USR_DATA6_S 0 + +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) +/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ +#define EFUSE_USR_DATA7 0xFFFFFFFF +#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) +#define EFUSE_USR_DATA7_V 0xFFFFFFFF +#define EFUSE_USR_DATA7_S 0 + +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09C) +/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA0 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_S 0 + +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0A0) +/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA1 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_S 0 + +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0A4) +/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA2 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_S 0 + +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0A8) +/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA3 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_S 0 + +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0AC) +/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA4 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_S 0 + +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0B0) +/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA5 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_S 0 + +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0B4) +/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA6 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_S 0 + +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0B8) +/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of KEY0.*/ +#define EFUSE_KEY0_DATA7 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_S 0 + +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0BC) +/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA0 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_S 0 + +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0C0) +/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA1 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_S 0 + +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0C4) +/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA2 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_S 0 + +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0C8) +/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA3 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_S 0 + +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0CC) +/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA4 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_S 0 + +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0D0) +/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA5 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_S 0 + +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0D4) +/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA6 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_S 0 + +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0D8) +/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of KEY1.*/ +#define EFUSE_KEY1_DATA7 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_S 0 + +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0DC) +/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA0 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_S 0 + +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0E0) +/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA1 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_S 0 + +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0E4) +/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA2 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_S 0 + +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0E8) +/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA3 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_S 0 + +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0EC) +/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA4 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_S 0 + +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0F0) +/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA5 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_S 0 + +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0F4) +/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA6 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_S 0 + +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0F8) +/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of KEY2.*/ +#define EFUSE_KEY2_DATA7 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_S 0 + +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0FC) +/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA0 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_S 0 + +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA1 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_S 0 + +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA2 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_S 0 + +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA3 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_S 0 + +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) +/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA4 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_S 0 + +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA5 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_S 0 + +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA6 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_S 0 + +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of KEY3.*/ +#define EFUSE_KEY3_DATA7 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_S 0 + +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) +/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA0 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_S 0 + +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA1 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_S 0 + +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA2 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_S 0 + +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA3 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_S 0 + +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) +/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA4 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_S 0 + +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA5 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_S 0 + +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA6 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_S 0 + +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of KEY4.*/ +#define EFUSE_KEY4_DATA7 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_S 0 + +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) +/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA0 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_S 0 + +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA1 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_S 0 + +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA2 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_S 0 + +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA3 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_S 0 + +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) +/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA4 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_S 0 + +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA5 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_S 0 + +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA6 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_S 0 + +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of KEY5.*/ +#define EFUSE_KEY5_DATA7 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_S 0 + +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) +/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_S 0 + +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_S 0 + +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_S 0 + +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_S 0 + +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) +/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_S 0 + +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_S 0 + +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_S 0 + +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_S 0 + +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) +/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ +#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 +#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) +#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 +#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 +/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: If POWERGLITCH_EN is 1 then it indicates a programming error.*/ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) +#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(29)) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x1 +#define EFUSE_POWERGLITCH_EN_ERR_S 29 +/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ +/*description: If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ +#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 +#define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) +#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 +#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 +/* EFUSE_VDD_SPI_AS_GPIO_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x1 +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ +#define EFUSE_USB_DREFL_ERR 0x00000003 +#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) +#define EFUSE_USB_DREFL_ERR_V 0x3 +#define EFUSE_USB_DREFL_ERR_S 23 +/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ +#define EFUSE_USB_DREFH_ERR 0x00000003 +#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) +#define EFUSE_USB_DREFH_ERR_V 0x3 +#define EFUSE_USB_DREFH_ERR_S 21 +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 +#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x1 +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: If DIS_TWAI is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_V 0x1 +#define EFUSE_DIS_TWAI_ERR_S 14 +/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Reserved..*/ +#define EFUSE_RPT4_RESERVED6_ERR (BIT(13)) +#define EFUSE_RPT4_RESERVED6_ERR_M (BIT(13)) +#define EFUSE_RPT4_RESERVED6_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED6_ERR_S 13 +/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 +#define EFUSE_DIS_USB_DEVICE_ERR_S 11 +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: If DIS_USB_JTAG is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_V 0x1 +#define EFUSE_DIS_ICACHE_ERR_S 8 +/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ +#define EFUSE_RD_DIS_ERR 0x0000007F +#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) +#define EFUSE_RD_DIS_ERR_V 0x7F +#define EFUSE_RD_DIS_ERR_S 0 + +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 +/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFF +#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) +#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFF +#define EFUSE_RPT4_RESERVED2_ERR_S 0 + +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_TPUW_ERR 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) +#define EFUSE_FLASH_TPUW_ERR_V 0xF +#define EFUSE_FLASH_TPUW_ERR_S 28 +/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED0_ERR 0x0000003F +#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x3F +#define EFUSE_RPT4_RESERVED0_ERR_S 22 +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED3_ERR 0x0000000F +#define EFUSE_RPT4_RESERVED3_ERR_M ((EFUSE_RPT4_RESERVED3_ERR_V)<<(EFUSE_RPT4_RESERVED3_ERR_S)) +#define EFUSE_RPT4_RESERVED3_ERR_V 0xF +#define EFUSE_RPT4_RESERVED3_ERR_S 16 +/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 + +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED1_ERR 0x00000003 +#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S)) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x3 +#define EFUSE_RPT4_RESERVED1_ERR_S 30 +/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ +/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) +#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF +#define EFUSE_SECURE_VERSION_ERR_S 14 +/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: If FLASH_ECC_EN_ERR is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (BIT(12)) +#define EFUSE_FLASH_ECC_EN_V 0x1 +#define EFUSE_FLASH_ECC_EN_S 12 +/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: If any bits in FLASH_PAGE_SIZE is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003 +#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) +#define EFUSE_FLASH_PAGE_SIZE_V 0x3 +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: If FLASH_TYPE is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_V 0x1 +#define EFUSE_FLASH_TYPE_ERR_S 9 +/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: If FLASH_ECC_MODE is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_ERR_M (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_ERR_V 0x1 +#define EFUSE_FLASH_ECC_MODE_ERR_S 3 +/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x1 +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x1 +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 + +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) +#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_S 0 + +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) +/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (BIT(31)) +#define EFUSE_KEY4_FAIL_V 0x1 +#define EFUSE_KEY4_FAIL_S 31 +/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY4_ERR_NUM 0x00000007 +#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) +#define EFUSE_KEY4_ERR_NUM_V 0x7 +#define EFUSE_KEY4_ERR_NUM_S 28 +/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (BIT(27)) +#define EFUSE_KEY3_FAIL_V 0x1 +#define EFUSE_KEY3_FAIL_S 27 +/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY3_ERR_NUM 0x00000007 +#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) +#define EFUSE_KEY3_ERR_NUM_V 0x7 +#define EFUSE_KEY3_ERR_NUM_S 24 +/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (BIT(23)) +#define EFUSE_KEY2_FAIL_V 0x1 +#define EFUSE_KEY2_FAIL_S 23 +/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY2_ERR_NUM 0x00000007 +#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) +#define EFUSE_KEY2_ERR_NUM_V 0x7 +#define EFUSE_KEY2_ERR_NUM_S 20 +/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (BIT(19)) +#define EFUSE_KEY1_FAIL_V 0x1 +#define EFUSE_KEY1_FAIL_S 19 +/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY1_ERR_NUM 0x00000007 +#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) +#define EFUSE_KEY1_ERR_NUM_V 0x7 +#define EFUSE_KEY1_ERR_NUM_S 16 +/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (BIT(15)) +#define EFUSE_KEY0_FAIL_V 0x1 +#define EFUSE_KEY0_FAIL_S 15 +/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY0_ERR_NUM 0x00000007 +#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) +#define EFUSE_KEY0_ERR_NUM_V 0x7 +#define EFUSE_KEY0_ERR_NUM_S 12 +/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the user data is reliable 1: Means + that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (BIT(11)) +#define EFUSE_USR_DATA_FAIL_V 0x1 +#define EFUSE_USR_DATA_FAIL_S 11 +/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) +#define EFUSE_USR_DATA_ERR_NUM_V 0x7 +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of system part1 is reliable + 1: Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_V 0x1 +#define EFUSE_SYS_PART1_FAIL_S 7 +/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_SYS_PART1_NUM 0x00000007 +#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) +#define EFUSE_SYS_PART1_NUM_V 0x7 +#define EFUSE_SYS_PART1_NUM_S 4 +/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable + 1: Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 + +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) +/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of system part2 is reliable + 1: Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_V 0x1 +#define EFUSE_SYS_PART2_FAIL_S 7 +/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of KEY5 is reliable 1: + Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (BIT(3)) +#define EFUSE_KEY5_FAIL_V 0x1 +#define EFUSE_KEY5_FAIL_S 3 +/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY5_ERR_NUM 0x00000007 +#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) +#define EFUSE_KEY5_ERR_NUM_V 0x7 +#define EFUSE_KEY5_ERR_NUM_S 0 + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) +/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit and force to enable clock signal of eFuse memory.*/ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (BIT(16)) +#define EFUSE_CLK_EN_V 0x1 +#define EFUSE_CLK_EN_S 16 +/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to force eFuse SRAM into working mode.*/ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (BIT(2)) +#define EFUSE_MEM_FORCE_PU_V 0x1 +#define EFUSE_MEM_FORCE_PU_S 2 +/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (BIT(0)) +#define EFUSE_MEM_FORCE_PD_V 0x1 +#define EFUSE_MEM_FORCE_PD_S 0 + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) +/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) +#define EFUSE_OP_CODE_V 0xFFFF +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) +/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ +/*description: Indicates the number of error bits during programming BLOCK0.*/ +#define EFUSE_REPEAT_ERR_CNT 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) +#define EFUSE_REPEAT_ERR_CNT_V 0xFF +#define EFUSE_REPEAT_ERR_CNT_S 10 +/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The value of OTP_VDDQ_IS_SW.*/ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The value of OTP_PGENB_SW.*/ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (BIT(8)) +#define EFUSE_OTP_PGENB_SW_V 0x1 +#define EFUSE_OTP_PGENB_SW_S 8 +/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The value of OTP_CSB_SW.*/ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (BIT(7)) +#define EFUSE_OTP_CSB_SW_V 0x1 +#define EFUSE_OTP_CSB_SW_S 7 +/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The value of OTP_STROBE_SW.*/ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (BIT(6)) +#define EFUSE_OTP_STROBE_SW_V 0x1 +#define EFUSE_OTP_STROBE_SW_S 6 +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The value of OTP_VDDQ_C_SYNC2.*/ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The value of OTP_LOAD_SW.*/ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (BIT(4)) +#define EFUSE_OTP_LOAD_SW_V 0x1 +#define EFUSE_OTP_LOAD_SW_S 4 +/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: Indicates the state of the eFuse state machine.*/ +#define EFUSE_STATE 0x0000000F +#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) +#define EFUSE_STATE_V 0xF +#define EFUSE_STATE_S 0 + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) +/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ +/*description: The serial number of the block to be programmed. Value 0-10 corresponds + to block number 0-10 respectively.*/ +#define EFUSE_BLK_NUM 0x0000000F +#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) +#define EFUSE_BLK_NUM_V 0xF +#define EFUSE_BLK_NUM_S 2 +/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to send programming command.*/ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (BIT(1)) +#define EFUSE_PGM_CMD_V 0x1 +#define EFUSE_PGM_CMD_S 1 +/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to send read command.*/ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (BIT(0)) +#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_S 0 + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) +/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_V 0x1 +#define EFUSE_PGM_DONE_INT_RAW_S 1 +/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) +/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_V 0x1 +#define EFUSE_PGM_DONE_INT_ST_S 1 +/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_S 0 + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) +/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_V 0x1 +#define EFUSE_PGM_DONE_INT_ENA_S 1 +/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) +/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_V 0x1 +#define EFUSE_PGM_DONE_INT_CLR_S 1 +/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) +/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Reduces the power supply of the programming voltage.*/ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (BIT(17)) +#define EFUSE_OE_CLR_V 0x1 +#define EFUSE_OE_CLR_S 17 +/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ +/*description: Controls the rising period of the programming voltage.*/ +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) +#define EFUSE_DAC_NUM_V 0xFF +#define EFUSE_DAC_NUM_S 9 +/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Don't care.*/ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ +/*description: Controls the division factor of the rising clock of the programming voltage.*/ +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) +#define EFUSE_DAC_CLK_DIV_V 0xFF +#define EFUSE_DAC_CLK_DIV_S 0 + +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) +/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ +/*description: Configures the initial read time of eFuse.*/ +#define EFUSE_READ_INIT_NUM 0x000000FF +#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) +#define EFUSE_READ_INIT_NUM_V 0xFF +#define EFUSE_READ_INIT_NUM_S 24 + +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F0) +/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ +/*description: Configures the power up time for VDDQ.*/ +#define EFUSE_PWR_ON_NUM 0x0000FFFF +#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) +#define EFUSE_PWR_ON_NUM_V 0xFFFF +#define EFUSE_PWR_ON_NUM_S 8 + +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F4) +/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ +/*description: Configures the power outage time for VDDQ.*/ +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) +#define EFUSE_PWR_OFF_NUM_V 0xFFFF +#define EFUSE_PWR_OFF_NUM_S 0 + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) +/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007200 ; */ +/*description: Stores eFuse version.*/ +#define EFUSE_DATE 0x0FFFFFFF +#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) +#define EFUSE_DATE_V 0xFFFFFFF +#define EFUSE_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/include/soc/efuse_struct.h new file mode 100644 index 0000000000..1c51e71475 --- /dev/null +++ b/components/soc/esp32h2/include/soc/efuse_struct.h @@ -0,0 +1,514 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_EFUSE_STRUCT_H_ +#define _SOC_EFUSE_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/ + union { + struct { + uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/ + uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/ + uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/ + uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ + uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/ + uint32_t dis_usb_device: 1; /*Set this bit to disable usb device.*/ + uint32_t dis_force_download: 1; /*Set this bit to disable the function that forces chip into download mode.*/ + uint32_t dis_usb: 1; /*Set this bit to disable USB function.*/ + uint32_t dis_can: 1; /*Set this bit to disable CAN function.*/ + uint32_t jtag_sel_enable: 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ + uint32_t soft_dis_jtag: 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ + uint32_t dis_pad_jtag: 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ + uint32_t dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ + uint32_t usb_drefh: 2; /*Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.*/ + uint32_t usb_drefl: 2; /*Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.*/ + uint32_t usb_exchg_pins: 1; /*Set this bit to exchange USB D+ and D- pins.*/ + uint32_t vdd_spi_as_gpio: 1; /*Set this bit to vdd spi pin function as gpio.*/ + uint32_t btlc_gpio_enable: 2; /*Enable btlc gpio.*/ + uint32_t powerglitch_en: 1; /*Set this bit to enable power glitch function.*/ + uint32_t power_glitch_dsense: 2; /*Sample delay configuration of power glitch.*/ + }; + uint32_t val; + } pgm_data1; + union { + struct { + uint32_t rpt4_reserved2: 16; /*Reserved (used for four backups method).*/ + uint32_t wat_delay_sel: 2; /*Selects RTC watchdog timeout threshold in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ + uint32_t spi_boot_crypt_cnt: 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ + uint32_t secure_boot_key_revoke0: 1; /*Set this bit to enable revoking first secure boot key.*/ + uint32_t secure_boot_key_revoke1: 1; /*Set this bit to enable revoking second secure boot key.*/ + uint32_t secure_boot_key_revoke2: 1; /*Set this bit to enable revoking third secure boot key.*/ + uint32_t key_purpose_0: 4; /*Purpose of Key0.*/ + uint32_t key_purpose_1: 4; /*Purpose of Key1.*/ + }; + uint32_t val; + } pgm_data2; + union { + struct { + uint32_t key_purpose_2: 4; /*Purpose of Key2.*/ + uint32_t key_purpose_3: 4; /*Purpose of Key3.*/ + uint32_t key_purpose_4: 4; /*Purpose of Key4.*/ + uint32_t key_purpose_5: 4; /*Purpose of Key5.*/ + uint32_t rpt4_reserved3: 4; /*Reserved (used for four backups method).*/ + uint32_t secure_boot_en: 1; /*Set this bit to enable secure boot.*/ + uint32_t secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ + uint32_t rpt4_reserved0: 6; /*Reserved (used for four backups method).*/ + uint32_t flash_tpuw: 4; /*Configures flash waiting time after power-up in unit of ms. If the value is less than 15 the waiting time is the configurable value*/ + }; + uint32_t val; + } pgm_data3; + union { + struct { + uint32_t dis_download_mode: 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ + uint32_t dis_legacy_spi_boot: 1; /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ + uint32_t uart_print_channel: 1; /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/ + uint32_t flash_ecc_mode: 1; /*Set ECC mode in ROM 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/ + uint32_t dis_usb_download_mode: 1; /*Set this bit to disable UART download mode through USB.*/ + uint32_t enable_security_download: 1; /*Set this bit to enable secure UART download mode.*/ + uint32_t uart_print_control: 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ + uint32_t pin_power_selection: 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ + uint32_t flash_type: 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ + uint32_t flash_page_size: 2; /*Set Flash page size.*/ + uint32_t flash_ecc_en: 1; /*Set 1 to enable ECC for flash boot.*/ + uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ + uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ + uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/ + }; + uint32_t val; + } pgm_data4; + union { + struct { + uint32_t rpt4_reserved4:24; /*Reserved (used for four backups method).*/ + uint32_t reserved24: 8; /*Reserved.*/ + }; + uint32_t val; + } pgm_data5; + uint32_t pgm_data6; /*Register 6 that stores data to be programmed.*/ + uint32_t pgm_data7; /*Register 7 that stores data to be programmed.*/ + uint32_t pgm_check_value0; /*Register 0 that stores the RS code to be programmed.*/ + uint32_t pgm_check_value1; /*Register 1 that stores the RS code to be programmed.*/ + uint32_t pgm_check_value2; /*Register 2 that stores the RS code to be programmed.*/ + uint32_t rd_wr_dis; /*BLOCK0 data register $n.*/ + union { + struct { + uint32_t rd_dis: 7; /*The value of RD_DIS.*/ + uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/ + uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ + uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ + uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ + uint32_t dis_usb_device: 1; /*The value of DIS_USB_DEVICE.*/ + uint32_t dis_force_download: 1; /*The value of DIS_FORCE_DOWNLOAD.*/ + uint32_t dis_usb: 1; /*The value of DIS_USB.*/ + uint32_t dis_can: 1; /*The value of DIS_CAN.*/ + uint32_t jtag_sel_enable: 1; /*The value of JTAG_SEL_ENABLE.*/ + uint32_t soft_dis_jtag: 3; /*The value of SOFT_DIS_JTAG.*/ + uint32_t dis_pad_jtag: 1; /*The value of DIS_PAD_JTAG.*/ + uint32_t dis_download_manual_encrypt: 1; /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ + uint32_t usb_drefh: 2; /*The value of USB_DREFH.*/ + uint32_t usb_drefl: 2; /*The value of USB_DREFL.*/ + uint32_t usb_exchg_pins: 1; /*The value of USB_EXCHG_PINS.*/ + uint32_t vdd_spi_as_gpio: 1; /*The value of VDD_SPI_AS_GPIO.*/ + uint32_t btlc_gpio_enable: 2; /*The value of BTLC_GPIO_ENABLE.*/ + uint32_t powerglitch_en: 1; /*The value of POWERGLITCH_EN.*/ + uint32_t power_glitch_dsense: 2; /*The value of POWER_GLITCH_DSENSE.*/ + }; + uint32_t val; + } rd_repeat_data0; + union { + struct { + uint32_t rpt4_reserved2: 16; /*Reserved.*/ + uint32_t wdt_delay_sel: 2; /*The value of WDT_DELAY_SEL.*/ + uint32_t spi_boot_crypt_cnt: 3; /*The value of SPI_BOOT_CRYPT_CNT.*/ + uint32_t secure_boot_key_revoke0: 1; /*The value of SECURE_BOOT_KEY_REVOKE0.*/ + uint32_t secure_boot_key_revoke1: 1; /*The value of SECURE_BOOT_KEY_REVOKE1.*/ + uint32_t secure_boot_key_revoke2: 1; /*The value of SECURE_BOOT_KEY_REVOKE2.*/ + uint32_t key_purpose_0: 4; /*The value of KEY_PURPOSE_0.*/ + uint32_t key_purpose_1: 4; /*The value of KEY_PURPOSE_1.*/ + }; + uint32_t val; + } rd_repeat_data1; + union { + struct { + uint32_t key_purpose_2: 4; /*The value of KEY_PURPOSE_2.*/ + uint32_t key_purpose_3: 4; /*The value of KEY_PURPOSE_3.*/ + uint32_t key_purpose_4: 4; /*The value of KEY_PURPOSE_4.*/ + uint32_t key_purpose_5: 4; /*The value of KEY_PURPOSE_5.*/ + uint32_t rpt4_reserved3: 4; /*Reserved.*/ + uint32_t secure_boot_en: 1; /*The value of SECURE_BOOT_EN.*/ + uint32_t secure_boot_aggressive_revoke: 1; /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ + uint32_t rpt4_reserved0: 6; /*Reserved.*/ + uint32_t flash_tpuw: 4; /*The value of FLASH_TPUW.*/ + }; + uint32_t val; + } rd_repeat_data2; + union { + struct { + uint32_t dis_download_mode: 1; /*The value of DIS_DOWNLOAD_MODE.*/ + uint32_t dis_legacy_spi_boot: 1; /*The value of DIS_LEGACY_SPI_BOOT.*/ + uint32_t uart_print_channel: 1; /*The value of UART_PRINT_CHANNEL.*/ + uint32_t flash_ecc_mode: 1; /*The value of FLASH_ECC_MODE.*/ + uint32_t dis_usb_download_mode: 1; /*The value of DIS_USB_DOWNLOAD_MODE.*/ + uint32_t enable_security_download: 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/ + uint32_t uart_print_control: 2; /*The value of UART_PRINT_CONTROL.*/ + uint32_t pin_power_selection: 1; /*The value of PIN_POWER_SELECTION.*/ + uint32_t flash_type: 1; /*The value of FLASH_TYPE.*/ + uint32_t flash_page_size: 2; /*The value of FLASH_PAGE_SIZE.*/ + uint32_t flash_ecc_en: 1; /*The value of FLASH_ECC_EN.*/ + uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/ + uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/ + uint32_t rpt4_reserved1: 2; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_data3; + union { + struct { + uint32_t rpt4_reserved4:24; /*Reserved.*/ + uint32_t reserved24: 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_data4; + uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/ + union { + struct { + uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/ + uint32_t spi_pad_conf_0:16; /*Stores the zeroth part of SPI_PAD_CONF.*/ + }; + uint32_t val; + } rd_mac_spi_sys_1; + uint32_t rd_mac_spi_sys_2; /*BLOCK1 data register $n.*/ + union { + struct { + uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ + uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/ + }; + uint32_t val; + } rd_mac_spi_sys_3; + uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ + uint32_t rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/ + uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/ + uint32_t rd_usr_data0; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data1; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data2; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data3; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data4; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data5; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data6; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_usr_data7; /*Register $n of BLOCK3 (user).*/ + uint32_t rd_key0_data0; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data1; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data2; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data3; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data4; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data5; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data6; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key0_data7; /*Register $n of BLOCK4 (KEY0).*/ + uint32_t rd_key1_data0; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data1; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data2; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data3; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data4; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data5; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data6; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key1_data7; /*Register $n of BLOCK5 (KEY1).*/ + uint32_t rd_key2_data0; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data1; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data2; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data3; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data4; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data5; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data6; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key2_data7; /*Register $n of BLOCK6 (KEY2).*/ + uint32_t rd_key3_data0; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data1; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data2; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data3; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data4; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data5; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data6; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key3_data7; /*Register $n of BLOCK7 (KEY3).*/ + uint32_t rd_key4_data0; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data1; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data2; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data3; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data4; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data5; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data6; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key4_data7; /*Register $n of BLOCK8 (KEY4).*/ + uint32_t rd_key5_data0; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data1; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data2; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data3; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data4; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data5; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data6; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_key5_data7; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_sys_part2_data0; /*Register $n of BLOCK10 (system).*/ + uint32_t rd_sys_part2_data1; /*Register $n of BLOCK9 (KEY5).*/ + uint32_t rd_sys_part2_data2; /*Register $n of BLOCK10 (system).*/ + uint32_t rd_sys_part2_data3; /*Register $n of BLOCK10 (system).*/ + uint32_t rd_sys_part2_data4; /*Register $n of BLOCK10 (system).*/ + uint32_t rd_sys_part2_data5; /*Register $n of BLOCK10 (system).*/ + uint32_t rd_sys_part2_data6; /*Register $n of BLOCK10 (system).*/ + uint32_t rd_sys_part2_data7; /*Register $n of BLOCK10 (system).*/ + union { + struct { + uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ + uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ + uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ + uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ + uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ + uint32_t dis_usb_device_err: 1; /*If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ + uint32_t dis_force_download_err: 1; /*If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ + uint32_t dis_usb_err: 1; /*If DIS_USB is 1 then it indicates a programming error.*/ + uint32_t dis_can_err: 1; /*If DIS_CAN is 1 then it indicates a programming error.*/ + uint32_t jtag_sel_enable_err: 1; /*If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ + uint32_t soft_dis_jtag_err: 3; /*If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ + uint32_t dis_pad_jtag_err: 1; /*If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ + uint32_t dis_download_manual_encrypt_err: 1; /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ + uint32_t usb_drefh_err: 2; /*If any bit in USB_DREFH is 1 then it indicates a programming error.*/ + uint32_t usb_drefl_err: 2; /*If any bit in USB_DREFL is 1 then it indicates a programming error.*/ + uint32_t usb_exchg_pins_err: 1; /*If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ + uint32_t vdd_spi_as_gpio_err: 1; /*If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ + uint32_t btlc_gpio_enable_err: 2; /*If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ + uint32_t powerglitch_en_err: 1; /*If POWERGLITCH_EN is 1 then it indicates a programming error.*/ + uint32_t power_glitch_dsense_err: 2; /*If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err0; + union { + struct { + uint32_t rpt4_reserved2_err: 16; /*Reserved.*/ + uint32_t wdt_delay_sel_err: 2; /*If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ + uint32_t spi_boot_crypt_cnt_err: 3; /*If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ + uint32_t secure_boot_key_revoke0_err: 1; /*If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ + uint32_t secure_boot_key_revoke1_err: 1; /*If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ + uint32_t secure_boot_key_revoke2_err: 1; /*If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ + uint32_t key_purpose_0_err: 4; /*If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ + uint32_t key_purpose_1_err: 4; /*If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err1; + union { + struct { + uint32_t key_purpose_2_err: 4; /*If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ + uint32_t key_purpose_3_err: 4; /*If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ + uint32_t key_purpose_4_err: 4; /*If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ + uint32_t key_purpose_5_err: 4; /*If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ + uint32_t rpt4_reserved3_err: 4; /*Reserved.*/ + uint32_t secure_boot_en_err: 1; /*If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ + uint32_t secure_boot_aggressive_revoke_err: 1; /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ + uint32_t rpt4_reserved0_err: 6; /*Reserved.*/ + uint32_t flash_tpuw_err: 4; /*If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err2; + union { + struct { + uint32_t dis_download_mode_err: 1; /*If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ + uint32_t dis_legacy_spi_boot_err: 1; /*If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/ + uint32_t uart_print_channel_err: 1; /*If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/ + uint32_t flash_ecc_mode_err: 1; /*If FLASH_ECC_MODE is 1 then it indicates a programming error.*/ + uint32_t dis_usb_download_mode_err: 1; /*If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ + uint32_t enable_security_download_err: 1; /*If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ + uint32_t uart_print_control_err: 2; /*If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ + uint32_t pin_power_selection_err: 1; /*If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/ + uint32_t flash_type_err: 1; /*If FLASH_TYPE is 1 then it indicates a programming error.*/ + uint32_t flash_page_size: 2; /*If any bits in FLASH_PAGE_SIZE is 1 then it indicates a programming error.*/ + uint32_t flash_ecc_en: 1; /*If FLASH_ECC_EN_ERR is 1 then it indicates a programming error.*/ + uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ + uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ + uint32_t rpt4_reserved1_err: 2; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err3; + uint32_t reserved_18c; + union { + struct { + uint32_t rpt4_reserved4_err:24; /*Reserved.*/ + uint32_t reserved24: 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err4; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + union { + struct { + uint32_t mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + }; + uint32_t val; + } rd_rs_err0; + union { + struct { + uint32_t key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t sys_part2_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t reserved8: 24; /*Reserved.*/ + }; + uint32_t val; + } rd_rs_err1; + union { + struct { + uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ + uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ + uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ + uint32_t reserved3: 13; /*Reserved.*/ + uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ + uint32_t reserved17: 15; /*Reserved.*/ + }; + uint32_t val; + } clk; + union { + struct { + uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ + uint32_t reserved16:16; /*Reserved.*/ + }; + uint32_t val; + } conf; + union { + struct { + uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ + uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ + uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ + uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ + uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ + uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ + uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ + uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ + uint32_t reserved18: 14; /*Reserved.*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t read_cmd: 1; /*Set this bit to send read command.*/ + uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ + uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ + uint32_t reserved6: 26; /*Reserved.*/ + }; + uint32_t val; + } cmd; + union { + struct { + uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ + uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ + uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ + uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ + uint32_t reserved18: 14; /*Reserved.*/ + }; + uint32_t val; + } dac_conf; + union { + struct { + uint32_t reserved0: 24; /*Configures the setup time of read operation.*/ + uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/ + }; + uint32_t val; + } rd_tim_conf; + union { + struct { + uint32_t reserved0: 8; /*Configures the setup time of programming operation.*/ + uint32_t pwr_on_num:16; /*Configures the power up time for VDDQ.*/ + uint32_t reserved24: 8; /*Reserved.*/ + }; + uint32_t val; + } wr_tim_conf1; + union { + struct { + uint32_t pwr_off_num:16; /*Configures the power outage time for VDDQ.*/ + uint32_t reserved16: 16; /*Reserved.*/ + }; + uint32_t val; + } wr_tim_conf2; + uint32_t reserved_1f8; + union { + struct { + uint32_t date: 28; /*Stores eFuse version.*/ + uint32_t reserved28: 4; /*Reserved.*/ + }; + uint32_t val; + } date; +} efuse_dev_t; +extern efuse_dev_t EFUSE; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_EFUSE_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/extmem_reg.h b/components/soc/esp32h2/include/soc/extmem_reg.h new file mode 100644 index 0000000000..71ab60f640 --- /dev/null +++ b/components/soc/esp32h2/include/soc/extmem_reg.h @@ -0,0 +1,992 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_EXTMEM_REG_H_ +#define _SOC_EXTMEM_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) +/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ +#define EXTMEM_ICACHE_ENABLE (BIT(0)) +#define EXTMEM_ICACHE_ENABLE_M (BIT(0)) +#define EXTMEM_ICACHE_ENABLE_V 0x1 +#define EXTMEM_ICACHE_ENABLE_S 0 + +#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) +/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable core1 ibus 0: enable 1: disable*/ +#define EXTMEM_ICACHE_SHUT_DBUS (BIT(1)) +#define EXTMEM_ICACHE_SHUT_DBUS_M (BIT(1)) +#define EXTMEM_ICACHE_SHUT_DBUS_V 0x1 +#define EXTMEM_ICACHE_SHUT_DBUS_S 1 +/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable core0 ibus 0: enable 1: disable*/ +#define EXTMEM_ICACHE_SHUT_IBUS (BIT(0)) +#define EXTMEM_ICACHE_SHUT_IBUS_M (BIT(0)) +#define EXTMEM_ICACHE_SHUT_IBUS_V 0x1 +#define EXTMEM_ICACHE_SHUT_IBUS_S 0 + +#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) +/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 +/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp + 1: power down*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 +/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of icache tag memory. + 1: close gating 0: open clock gating.*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 + +#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C) +/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 +/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 + +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010) +/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to configure the first start virtual address + of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 + +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) +/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to configure the second start virtual address + of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 + +#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) +/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The bits are used to configure the first length of data locking + which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 +/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the second length of data locking + which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 + +#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C) +/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to indicate unlock/lock operation is finished.*/ +#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) +#define EXTMEM_ICACHE_LOCK_DONE_V 0x1 +#define EXTMEM_ICACHE_LOCK_DONE_S 2 +/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared + by hardware after unlock operation done.*/ +#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) +#define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_ICACHE_UNLOCK_ENA_S 1 +/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared + by hardware after lock operation done.*/ +#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) +#define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_LOCK_ENA_V 0x1 +#define EXTMEM_ICACHE_LOCK_ENA_S 0 + +#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020) +/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ +#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) +#define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_LOCK_ADDR_S 0 + +#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024) +/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for lock operations. + The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ +#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) +#define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_LOCK_SIZE_S 0 + +#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028) +/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate invalidate operation is finished.*/ +#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) +#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) +#define EXTMEM_ICACHE_SYNC_DONE_V 0x1 +#define EXTMEM_ICACHE_SYNC_DONE_S 1 +/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared + by hardware after invalidate operation done.*/ +#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) +#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 + +#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C) +/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ +#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) +#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_SYNC_ADDR_S 0 + +#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030) +/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ +/*description: The bits are used to configure the length for sync operations. + The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ +#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF +#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) +#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF +#define EXTMEM_ICACHE_SYNC_SIZE_S 0 + +#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034) +/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure the direction of preload operation. + 1: descending 0: ascending.*/ +#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 +/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to indicate preload operation is finished.*/ +#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_DONE_S 1 +/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable preload operation. It will be cleared + by hardware after preload operation done.*/ +#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_ENA_S 0 + +#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) +/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) +#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) +/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for preload operation. + The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ +#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) +#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) +/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ +/*description: The bits are used to configure trigger conditions for autoload. + 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ +#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) +#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 +#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 +/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of autoload. 1: + descending 0: ascending.*/ +#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) +#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) +#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 +/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: The bit is used to indicate autoload operation is finished.*/ +#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) +#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) +#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 +/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable and disable autoload operation. It + is combined with icache_autoload_done. 1: enable 0: disable.*/ +#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) +#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) +#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 +/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bits are used to enable the second section for autoload operation.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 +/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bits are used to enable the first section for autoload operation.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044) +/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048) +/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: The bits are used to configure the length of the first section + for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x04C) +/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x050) +/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: The bits are used to configure the length of the second section + for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x054) +/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */ +/*description: The bits are used to configure the start virtual address of ibus + to access flash. The register is used to give constraints to ibus access counter.*/ +#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 + +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x058) +/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */ +/*description: The bits are used to configure the end virtual address of ibus + to access flash. The register is used to give constraints to ibus access counter.*/ +#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 + +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x05C) +/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */ +/*description: The bits are used to configure the start virtual address of dbus + to access flash. The register is used to give constraints to dbus access counter.*/ +#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 + +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x060) +/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */ +/*description: The bits are used to configure the end virtual address of dbus + to access flash. The register is used to give constraints to dbus access counter.*/ +#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 + +#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x064) +/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear dbus counter.*/ +#define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1)) +#define EXTMEM_DBUS_ACS_CNT_CLR_M (BIT(1)) +#define EXTMEM_DBUS_ACS_CNT_CLR_V 0x1 +#define EXTMEM_DBUS_ACS_CNT_CLR_S 1 +/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear ibus counter.*/ +#define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0)) +#define EXTMEM_IBUS_ACS_CNT_CLR_M (BIT(0)) +#define EXTMEM_IBUS_ACS_CNT_CLR_V 0x1 +#define EXTMEM_IBUS_ACS_CNT_CLR_S 0 + +#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x068) +/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused + by ibus access flash.*/ +#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) +#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_MISS_CNT_S 0 + +#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x06C) +/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of ibus access flash through icache.*/ +#define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) +#define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_CNT_S 0 + +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x070) +/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused + by dbus access flash.*/ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 + +#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x074) +/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of dbus access flash through icache.*/ +#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) +#define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_CNT_S 0 + +#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x078) +/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dbus counter overflow.*/ +#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 +/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by ibus counter overflow.*/ +#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 +/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 +/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by preload configurations fault.*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 +/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by sync configurations fault.*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 + +#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x07C) +/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dbus counter overflow.*/ +#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 +/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by ibus counter overflow.*/ +#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 +/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 +/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by preload configurations fault.*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 +/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by sync configurations fault.*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 + +#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x080) +/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus access flash miss + counter overflow.*/ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 +/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus access flash/spiram + counter overflow.*/ +#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 +/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus access flash/spiram + miss counter overflow.*/ +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 +/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus access flash/spiram + counter overflow.*/ +#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 +/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 +/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by preload configurations fault.*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 +/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by sync configurations fault.*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 + +#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x084) +/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dbus trying to write icache*/ +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5 +/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 +/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access icache while + the corresponding dbus is disabled which include speculative access.*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3 +/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 +/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 +/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access icache while + the corresponding ibus is disabled which include speculative access.*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 + +#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x088) +/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dbus trying to write icache*/ +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5 +/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 +/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access icache while + the corresponding dbus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3 +/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 +/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 +/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access icache while + the corresponding ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 + +#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x08C) +/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus trying to write icache*/ +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (BIT(5)) +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5 +/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 +#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 +/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the core0_dbus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3 +/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 +/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 +/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the core0_ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 + +#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x090) +/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the world of CPU access dbus when + authentication fail. 0: WORLD0 1: WORLD1*/ +#define EXTMEM_CORE0_DBUS_WORLD (BIT(3)) +#define EXTMEM_CORE0_DBUS_WORLD_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_WORLD_V 0x1 +#define EXTMEM_CORE0_DBUS_WORLD_S 3 +/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access dbus + when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 +#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) +#define EXTMEM_CORE0_DBUS_ATTR_V 0x7 +#define EXTMEM_CORE0_DBUS_ATTR_S 0 + +#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x094) +/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: The bits are used to indicate the virtual address of CPU access + dbus when authentication fail.*/ +#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF +#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) +#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF +#define EXTMEM_CORE0_DBUS_VADDR_S 0 + +#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x098) +/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the world of CPU access ibus when + authentication fail. 0: WORLD0 1: WORLD1*/ +#define EXTMEM_CORE0_IBUS_WORLD (BIT(3)) +#define EXTMEM_CORE0_IBUS_WORLD_M (BIT(3)) +#define EXTMEM_CORE0_IBUS_WORLD_V 0x1 +#define EXTMEM_CORE0_IBUS_WORLD_S 3 +/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access ibus + when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ +#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 +#define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) +#define EXTMEM_CORE0_IBUS_ATTR_V 0x7 +#define EXTMEM_CORE0_IBUS_ATTR_S 0 + +#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x09C) +/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: The bits are used to indicate the virtual address of CPU access + ibus when authentication fail.*/ +#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF +#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) +#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF +#define EXTMEM_CORE0_IBUS_VADDR_S 0 + +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x0A0) +/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */ +/*description: The right-most 3 bits are used to indicate the operations which + cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ +#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F +#define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) +#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF +#define EXTMEM_CACHE_MMU_FAULT_CODE_S 10 +/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ +#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000003FF +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x3FF +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 + +#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4) +/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address which cause mmu fault..*/ +#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF +#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) +#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 + +#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A8) +/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable wrap around mode when read data from flash.*/ +#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 + +#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0AC) +/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 +/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 +/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable clock gating to save power when access + mmu memory 0: enable 1: disable*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 + +#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x0B0) +/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */ +/*description: The bit is used to indicate whether icache main fsm is in idle + state or not. 1: in idle state 0: not in idle state*/ +#define EXTMEM_ICACHE_STATE 0x00000FFF +#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) +#define EXTMEM_ICACHE_STATE_V 0xFFF +#define EXTMEM_ICACHE_STATE_S 0 + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x0B4) +/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 +/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x0B8) +/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of external memory encrypt + and decrypt clock. 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 +/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of automatic crypt clock. + 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 +/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of manual crypt clock. + 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 + +#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0BC) +/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by icache pre-load done.*/ +#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 +/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by icache pre-load done.*/ +#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 +/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by icache pre-load done.*/ +#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 + +#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0C0) +/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by icache sync done.*/ +#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) +#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) +#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 +/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by icache sync done.*/ +#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 +/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by icache sync done.*/ +#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) +#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_ST_S 0 + +#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x0C4) +/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus bit1/bit3: dbus*/ +#define EXTMEM_CACHE_MMU_OWNER 0x0000000F +#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) +#define EXTMEM_CACHE_MMU_OWNER_V 0xF +#define EXTMEM_CACHE_MMU_OWNER_S 0 + +#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x0C8) +/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to enable cache trace function.*/ +#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) +#define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) +#define EXTMEM_CACHE_TRACE_ENA_V 0x1 +#define EXTMEM_CACHE_TRACE_ENA_S 2 +/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable checking mmu entry fault by sync operation.*/ +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 +/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable checking mmu entry fault by preload operation.*/ +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 + +#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x0CC) +/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate icache freeze success*/ +#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) +#define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) +#define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 +#define EXTMEM_ICACHE_FREEZE_DONE_S 2 +/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to configure freeze mode 0: assert busy if + CPU miss 1: assert hit if CPU miss*/ +#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) +#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) +#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 +#define EXTMEM_ICACHE_FREEZE_MODE_S 1 +/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable icache freeze mode*/ +#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) +#define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 +#define EXTMEM_ICACHE_FREEZE_ENA_S 0 + +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x0D0) +/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to activate icache atomic operation protection. + In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 + +#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x0D4) +/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to disable request recording which could cause performance issue*/ +#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) +#define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) +#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 +#define EXTMEM_CACHE_REQUEST_BYPASS_S 0 + +#define EXTMEM_IBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0D8) +/* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to configure the ibus permission control section boundary0*/ +#define EXTMEM_IBUS_PMS_LOCK (BIT(0)) +#define EXTMEM_IBUS_PMS_LOCK_M (BIT(0)) +#define EXTMEM_IBUS_PMS_LOCK_V 0x1 +#define EXTMEM_IBUS_PMS_LOCK_S 0 + +#define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0DC) +/* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: The bit is used to configure the ibus permission control section boundary0*/ +#define EXTMEM_IBUS_PMS_BOUNDARY0 0x00000FFF +#define EXTMEM_IBUS_PMS_BOUNDARY0_M ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S)) +#define EXTMEM_IBUS_PMS_BOUNDARY0_V 0xFFF +#define EXTMEM_IBUS_PMS_BOUNDARY0_S 0 + +#define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0E0) +/* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: The bit is used to configure the ibus permission control section boundary1*/ +#define EXTMEM_IBUS_PMS_BOUNDARY1 0x00000FFF +#define EXTMEM_IBUS_PMS_BOUNDARY1_M ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S)) +#define EXTMEM_IBUS_PMS_BOUNDARY1_V 0xFFF +#define EXTMEM_IBUS_PMS_BOUNDARY1_S 0 + +#define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0E4) +/* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: The bit is used to configure the ibus permission control section boundary2*/ +#define EXTMEM_IBUS_PMS_BOUNDARY2 0x00000FFF +#define EXTMEM_IBUS_PMS_BOUNDARY2_M ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S)) +#define EXTMEM_IBUS_PMS_BOUNDARY2_V 0xFFF +#define EXTMEM_IBUS_PMS_BOUNDARY2_S 0 + +#define EXTMEM_IBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0E8) +/* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */ +/*description: The bit is used to configure attribute of the ibus permission + control section2 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/ +#define EXTMEM_IBUS_PMS_SCT2_ATTR 0x0000000F +#define EXTMEM_IBUS_PMS_SCT2_ATTR_M ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S)) +#define EXTMEM_IBUS_PMS_SCT2_ATTR_V 0xF +#define EXTMEM_IBUS_PMS_SCT2_ATTR_S 4 +/* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */ +/*description: The bit is used to configure attribute of the ibus permission + control section1 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/ +#define EXTMEM_IBUS_PMS_SCT1_ATTR 0x0000000F +#define EXTMEM_IBUS_PMS_SCT1_ATTR_M ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S)) +#define EXTMEM_IBUS_PMS_SCT1_ATTR_V 0xF +#define EXTMEM_IBUS_PMS_SCT1_ATTR_S 0 + +#define EXTMEM_DBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0EC) +/* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to configure the ibus permission control section boundary0*/ +#define EXTMEM_DBUS_PMS_LOCK (BIT(0)) +#define EXTMEM_DBUS_PMS_LOCK_M (BIT(0)) +#define EXTMEM_DBUS_PMS_LOCK_V 0x1 +#define EXTMEM_DBUS_PMS_LOCK_S 0 + +#define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0F0) +/* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: The bit is used to configure the dbus permission control section boundary0*/ +#define EXTMEM_DBUS_PMS_BOUNDARY0 0x00000FFF +#define EXTMEM_DBUS_PMS_BOUNDARY0_M ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S)) +#define EXTMEM_DBUS_PMS_BOUNDARY0_V 0xFFF +#define EXTMEM_DBUS_PMS_BOUNDARY0_S 0 + +#define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0F4) +/* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: The bit is used to configure the dbus permission control section boundary1*/ +#define EXTMEM_DBUS_PMS_BOUNDARY1 0x00000FFF +#define EXTMEM_DBUS_PMS_BOUNDARY1_M ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S)) +#define EXTMEM_DBUS_PMS_BOUNDARY1_V 0xFFF +#define EXTMEM_DBUS_PMS_BOUNDARY1_S 0 + +#define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0F8) +/* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: The bit is used to configure the dbus permission control section boundary2*/ +#define EXTMEM_DBUS_PMS_BOUNDARY2 0x00000FFF +#define EXTMEM_DBUS_PMS_BOUNDARY2_M ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S)) +#define EXTMEM_DBUS_PMS_BOUNDARY2_V 0xFFF +#define EXTMEM_DBUS_PMS_BOUNDARY2_S 0 + +#define EXTMEM_DBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0FC) +/* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: The bit is used to configure attribute of the dbus permission + control section2 bit0: load in world0 bit2: load in world1*/ +#define EXTMEM_DBUS_PMS_SCT2_ATTR 0x00000003 +#define EXTMEM_DBUS_PMS_SCT2_ATTR_M ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S)) +#define EXTMEM_DBUS_PMS_SCT2_ATTR_V 0x3 +#define EXTMEM_DBUS_PMS_SCT2_ATTR_S 2 +/* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */ +/*description: The bit is used to configure attribute of the dbus permission + control section1 bit0: load in world0 bit2: load in world1*/ +#define EXTMEM_DBUS_PMS_SCT1_ATTR 0x00000003 +#define EXTMEM_DBUS_PMS_SCT1_ATTR_M ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S)) +#define EXTMEM_DBUS_PMS_SCT1_ATTR_V 0x3 +#define EXTMEM_DBUS_PMS_SCT1_ATTR_S 0 + +#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100) +/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Reserved.*/ +#define EXTMEM_CLK_EN (BIT(0)) +#define EXTMEM_CLK_EN_M (BIT(0)) +#define EXTMEM_CLK_EN_V 0x1 +#define EXTMEM_CLK_EN_S 0 + +#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) +/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */ +/*description: Reserved.*/ +#define EXTMEM_DATE 0x0FFFFFFF +#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) +#define EXTMEM_DATE_V 0xFFFFFFF +#define EXTMEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_EXTMEM_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/fe_reg.h b/components/soc/esp32h2/include/soc/fe_reg.h new file mode 100644 index 0000000000..5d76651de5 --- /dev/null +++ b/components/soc/esp32h2/include/soc/fe_reg.h @@ -0,0 +1,41 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_M (BIT(5)) +#define FE_IQ_EST_FORCE_PU_V 1 +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_M (BIT(4)) +#define FE_IQ_EST_FORCE_PD_V 1 +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_M (BIT(10)) +#define FE2_TX_INF_FORCE_PU_V 1 +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_M (BIT(9)) +#define FE2_TX_INF_FORCE_PD_V 1 +#define FE2_TX_INF_FORCE_PD_S 9 diff --git a/components/soc/esp32h2/include/soc/gdma_channel.h b/components/soc/esp32h2/include/soc/gdma_channel.h new file mode 100644 index 0000000000..9108df78f2 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gdma_channel.h @@ -0,0 +1,24 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) +#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_AES0 (6) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) diff --git a/components/soc/esp32h2/include/soc/gdma_reg.h b/components/soc/esp32h2/include/soc/gdma_reg.h new file mode 100644 index 0000000000..4ade5dcee7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gdma_reg.h @@ -0,0 +1,2419 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_DMA_REG_H_ +#define _SOC_DMA_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x000) +/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is underflow.*/ +#define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S 12 +/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is overflow.*/ +#define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S 11 +/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is underflow.*/ +#define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_CH0_INT_RAW_S 10 +/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is overflow.*/ +#define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_CH0_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 +/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ +#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH0_INT_RAW_S 4 +/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ +#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH0_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ +#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 0.*/ +#define DMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH0_INT_RAW_S 0 + +#define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x004) +/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ST_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_CH0_INT_ST_S 12 +/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ST_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_CH0_INT_ST_S 11 +/* DMA_INFIFO_UDF_CH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH0_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ST_M (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_CH0_INT_ST_S 10 +/* DMA_INFIFO_OVF_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH0_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ST_M (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_CH0_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5 +/* DMA_OUT_EOF_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH0_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH0_INT_ST_S 4 +/* DMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH0_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH0_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/* DMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ST_V 0x1 +#define DMA_IN_DONE_CH0_INT_ST_S 0 + +#define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x008) +/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S 12 +/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S 11 +/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH0_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_CH0_INT_ENA_S 10 +/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH0_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_CH0_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 +/* DMA_OUT_EOF_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH0_INT_ENA_S 4 +/* DMA_OUT_DONE_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH0_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/* DMA_IN_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH0_INT_ENA_S 0 + +#define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x00C) +/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S 12 +/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S 11 +/* DMA_INFIFO_UDF_CH0_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH0_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_CH0_INT_CLR_S 10 +/* DMA_INFIFO_OVF_CH0_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH0_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_CH0_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 +/* DMA_OUT_EOF_CH0_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH0_INT_CLR_S 4 +/* DMA_OUT_DONE_CH0_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH0_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/* DMA_IN_DONE_CH0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH0_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH0_INT_CLR_S 0 + +#define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x010) +/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 1 is underflow.*/ +#define DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S 12 +/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 1 is overflow.*/ +#define DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S 11 +/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 1 is underflow.*/ +#define DMA_INFIFO_UDF_CH1_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_CH1_INT_RAW_S 10 +/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 1 is overflow.*/ +#define DMA_INFIFO_OVF_CH1_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_CH1_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 1.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 1.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 1.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 +/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 1.*/ +#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH1_INT_RAW_S 4 +/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.*/ +#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH1_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.*/ +#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 1.*/ +#define DMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH1_INT_RAW_S 0 + +#define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x014) +/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ST_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_CH1_INT_ST_S 12 +/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ST_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_CH1_INT_ST_S 11 +/* DMA_INFIFO_UDF_CH1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH1_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ST_M (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_CH1_INT_ST_S 10 +/* DMA_INFIFO_OVF_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH1_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ST_M (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_CH1_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5 +/* DMA_OUT_EOF_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH1_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH1_INT_ST_S 4 +/* DMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH1_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH1_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/* DMA_IN_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ST_V 0x1 +#define DMA_IN_DONE_CH1_INT_ST_S 0 + +#define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x018) +/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S 12 +/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S 11 +/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH1_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_CH1_INT_ENA_S 10 +/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH1_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_CH1_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 +/* DMA_OUT_EOF_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH1_INT_ENA_S 4 +/* DMA_OUT_DONE_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH1_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/* DMA_IN_DONE_CH1_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH1_INT_ENA_S 0 + +#define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x01C) +/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S 12 +/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S 11 +/* DMA_INFIFO_UDF_CH1_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH1_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_CH1_INT_CLR_S 10 +/* DMA_INFIFO_OVF_CH1_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH1_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_CH1_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 +/* DMA_OUT_EOF_CH1_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH1_INT_CLR_S 4 +/* DMA_OUT_DONE_CH1_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH1_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/* DMA_IN_DONE_CH1_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH1_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH1_INT_CLR_S 0 + +#define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x020) +/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 2 is underflow.*/ +#define DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S 12 +/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 2 is overflow.*/ +#define DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S 11 +/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 2 is underflow.*/ +#define DMA_INFIFO_UDF_CH2_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_CH2_INT_RAW_S 10 +/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 2 is overflow.*/ +#define DMA_INFIFO_OVF_CH2_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_CH2_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 2.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 2.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 2.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 +/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 2.*/ +#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH2_INT_RAW_S 4 +/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.*/ +#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH2_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.*/ +#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 2.*/ +#define DMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH2_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH2_INT_RAW_S 0 + +#define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x024) +/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ST_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_CH2_INT_ST_S 12 +/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ST_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_CH2_INT_ST_S 11 +/* DMA_INFIFO_UDF_CH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH2_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ST_M (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_CH2_INT_ST_S 10 +/* DMA_INFIFO_OVF_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH2_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ST_M (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_CH2_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5 +/* DMA_OUT_EOF_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH2_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH2_INT_ST_S 4 +/* DMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH2_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH2_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/* DMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ST_V 0x1 +#define DMA_IN_DONE_CH2_INT_ST_S 0 + +#define DMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x028) +/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S 12 +/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S 11 +/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH2_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_CH2_INT_ENA_S 10 +/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH2_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_CH2_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 +/* DMA_OUT_EOF_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH2_INT_ENA_S 4 +/* DMA_OUT_DONE_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH2_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/* DMA_IN_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH2_INT_ENA_S 0 + +#define DMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x02C) +/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S 12 +/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S 11 +/* DMA_INFIFO_UDF_CH2_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_CH2_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_CH2_INT_CLR_S 10 +/* DMA_INFIFO_OVF_CH2_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_CH2_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_CH2_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 +/* DMA_OUT_EOF_CH2_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH2_INT_CLR_S 4 +/* DMA_OUT_DONE_CH2_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH2_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/* DMA_IN_DONE_CH2_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH2_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH2_INT_CLR_S 0 + +#define DMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x040) +/* DMA_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_AHB_TESTADDR 0x00000003 +#define DMA_AHB_TESTADDR_M ((DMA_AHB_TESTADDR_V)<<(DMA_AHB_TESTADDR_S)) +#define DMA_AHB_TESTADDR_V 0x3 +#define DMA_AHB_TESTADDR_S 4 +/* DMA_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_AHB_TESTMODE 0x00000007 +#define DMA_AHB_TESTMODE_M ((DMA_AHB_TESTMODE_V)<<(DMA_AHB_TESTMODE_S)) +#define DMA_AHB_TESTMODE_V 0x7 +#define DMA_AHB_TESTMODE_S 0 + +#define DMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x044) +/* DMA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DMA_CLK_EN (BIT(3)) +#define DMA_CLK_EN_M (BIT(3)) +#define DMA_CLK_EN_V 0x1 +#define DMA_CLK_EN_S 3 +/* DMA_ARB_PRI_DIS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to disable priority arbitration function.*/ +#define DMA_ARB_PRI_DIS (BIT(2)) +#define DMA_ARB_PRI_DIS_M (BIT(2)) +#define DMA_ARB_PRI_DIS_V 0x1 +#define DMA_ARB_PRI_DIS_S 2 +/* DMA_AHBM_RST_INTER : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit then clear this bit to reset the internal ahb FSM.*/ +#define DMA_AHBM_RST_INTER (BIT(0)) +#define DMA_AHBM_RST_INTER_M (BIT(0)) +#define DMA_AHBM_RST_INTER_V 0x1 +#define DMA_AHBM_RST_INTER_S 0 + +#define DMA_DATE_REG (DR_REG_GDMA_BASE + 0x048) +/* DMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008250 ; */ +/*description: register version.*/ +#define DMA_DATE 0xFFFFFFFF +#define DMA_DATE_M ((DMA_DATE_V)<<(DMA_DATE_S)) +#define DMA_DATE_V 0xFFFFFFFF +#define DMA_DATE_S 0 + +#define DMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x070) +/* DMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH0_M (BIT(4)) +#define DMA_MEM_TRANS_EN_CH0_V 0x1 +#define DMA_MEM_TRANS_EN_CH0_S 4 +/* DMA_IN_DATA_BURST_EN_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 0 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH0_M (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH0_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH0_S 3 +/* DMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 0 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH0_M (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH0_V 0x1 +#define DMA_INDSCR_BURST_EN_CH0_S 2 +/* DMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH0_M (BIT(1)) +#define DMA_IN_LOOP_TEST_CH0_V 0x1 +#define DMA_IN_LOOP_TEST_CH0_S 1 +/* DMA_IN_RST_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH0 (BIT(0)) +#define DMA_IN_RST_CH0_M (BIT(0)) +#define DMA_IN_RST_CH0_V 0x1 +#define DMA_IN_RST_CH0_S 0 + +#define DMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x074) +/* DMA_IN_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH0_M (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH0_V 0x1 +#define DMA_IN_CHECK_OWNER_CH0_S 12 + +#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x078) +/* DMA_IN_BUF_HUNGRY_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH0_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH0_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH0_S 27 +/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH0_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH0_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH0_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH0_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/* DMA_INFIFO_CNT_CH0 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ +#define DMA_INFIFO_CNT_CH0 0x0000003F +#define DMA_INFIFO_CNT_CH0_M ((DMA_INFIFO_CNT_CH0_V)<<(DMA_INFIFO_CNT_CH0_S)) +#define DMA_INFIFO_CNT_CH0_V 0x3F +#define DMA_INFIFO_CNT_CH0_S 2 +/* DMA_INFIFO_EMPTY_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 0.*/ +#define DMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH0_M (BIT(1)) +#define DMA_INFIFO_EMPTY_CH0_V 0x1 +#define DMA_INFIFO_EMPTY_CH0_S 1 +/* DMA_INFIFO_FULL_CH0 : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 0.*/ +#define DMA_INFIFO_FULL_CH0 (BIT(0)) +#define DMA_INFIFO_FULL_CH0_M (BIT(0)) +#define DMA_INFIFO_FULL_CH0_V 0x1 +#define DMA_INFIFO_FULL_CH0_S 0 + +#define DMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x07C) +/* DMA_INFIFO_POP_CH0 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH0 (BIT(12)) +#define DMA_INFIFO_POP_CH0_M (BIT(12)) +#define DMA_INFIFO_POP_CH0_V 0x1 +#define DMA_INFIFO_POP_CH0_S 12 +/* DMA_INFIFO_RDATA_CH0 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH0 0x00000FFF +#define DMA_INFIFO_RDATA_CH0_M ((DMA_INFIFO_RDATA_CH0_V)<<(DMA_INFIFO_RDATA_CH0_S)) +#define DMA_INFIFO_RDATA_CH0_V 0xFFF +#define DMA_INFIFO_RDATA_CH0_S 0 + +#define DMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x080) +/* DMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH0 (BIT(24)) +#define DMA_INLINK_PARK_CH0_M (BIT(24)) +#define DMA_INLINK_PARK_CH0_V 0x1 +#define DMA_INLINK_PARK_CH0_S 24 +/* DMA_INLINK_RESTART_CH0 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH0 (BIT(23)) +#define DMA_INLINK_RESTART_CH0_M (BIT(23)) +#define DMA_INLINK_RESTART_CH0_V 0x1 +#define DMA_INLINK_RESTART_CH0_S 23 +/* DMA_INLINK_START_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH0 (BIT(22)) +#define DMA_INLINK_START_CH0_M (BIT(22)) +#define DMA_INLINK_START_CH0_V 0x1 +#define DMA_INLINK_START_CH0_S 22 +/* DMA_INLINK_STOP_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH0 (BIT(21)) +#define DMA_INLINK_STOP_CH0_M (BIT(21)) +#define DMA_INLINK_STOP_CH0_V 0x1 +#define DMA_INLINK_STOP_CH0_S 21 +/* DMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH0_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH0_V 0x1 +#define DMA_INLINK_AUTO_RET_CH0_S 20 +/* DMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH0 0x000FFFFF +#define DMA_INLINK_ADDR_CH0_M ((DMA_INLINK_ADDR_CH0_V)<<(DMA_INLINK_ADDR_CH0_S)) +#define DMA_INLINK_ADDR_CH0_V 0xFFFFF +#define DMA_INLINK_ADDR_CH0_S 0 + +#define DMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x084) +/* DMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH0 0x00000007 +#define DMA_IN_STATE_CH0_M ((DMA_IN_STATE_CH0_V)<<(DMA_IN_STATE_CH0_S)) +#define DMA_IN_STATE_CH0_V 0x7 +#define DMA_IN_STATE_CH0_S 20 +/* DMA_IN_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH0 0x00000003 +#define DMA_IN_DSCR_STATE_CH0_M ((DMA_IN_DSCR_STATE_CH0_V)<<(DMA_IN_DSCR_STATE_CH0_S)) +#define DMA_IN_DSCR_STATE_CH0_V 0x3 +#define DMA_IN_DSCR_STATE_CH0_S 18 +/* DMA_INLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_M ((DMA_INLINK_DSCR_ADDR_CH0_V)<<(DMA_INLINK_DSCR_ADDR_CH0_S)) +#define DMA_INLINK_DSCR_ADDR_CH0_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x088) +/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M ((DMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH0_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x08C) +/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M ((DMA_IN_ERR_EOF_DES_ADDR_CH0_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH0_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +#define DMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x090) +/* DMA_INLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_M ((DMA_INLINK_DSCR_CH0_V)<<(DMA_INLINK_DSCR_CH0_S)) +#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_S 0 + +#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x094) +/* DMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_M ((DMA_INLINK_DSCR_BF0_CH0_V)<<(DMA_INLINK_DSCR_BF0_CH0_S)) +#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_S 0 + +#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x098) +/* DMA_INLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_M ((DMA_INLINK_DSCR_BF1_CH0_V)<<(DMA_INLINK_DSCR_BF1_CH0_S)) +#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_S 0 + +#define DMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x09C) +/* DMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 0. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH0 0x0000000F +#define DMA_RX_PRI_CH0_M ((DMA_RX_PRI_CH0_V)<<(DMA_RX_PRI_CH0_S)) +#define DMA_RX_PRI_CH0_V 0xF +#define DMA_RX_PRI_CH0_S 0 + +#define DMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x0A0) +/* DMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 0. + 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ +#define DMA_PERI_IN_SEL_CH0 0x0000003F +#define DMA_PERI_IN_SEL_CH0_M ((DMA_PERI_IN_SEL_CH0_V)<<(DMA_PERI_IN_SEL_CH0_S)) +#define DMA_PERI_IN_SEL_CH0_V 0x3F +#define DMA_PERI_IN_SEL_CH0_S 0 + +#define DMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0D0) +/* DMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH0_M (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH0_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH0_S 5 +/* DMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH0_M (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH0_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH0_S 4 +/* DMA_OUT_EOF_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH0_M (BIT(3)) +#define DMA_OUT_EOF_MODE_CH0_V 0x1 +#define DMA_OUT_EOF_MODE_CH0_S 3 +/* DMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH0_M (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH0_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH0_S 2 +/* DMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH0_M (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH0_V 0x1 +#define DMA_OUT_LOOP_TEST_CH0_S 1 +/* DMA_OUT_RST_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH0 (BIT(0)) +#define DMA_OUT_RST_CH0_M (BIT(0)) +#define DMA_OUT_RST_CH0_V 0x1 +#define DMA_OUT_RST_CH0_S 0 + +#define DMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x0D4) +/* DMA_OUT_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH0_M (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH0_V 0x1 +#define DMA_OUT_CHECK_OWNER_CH0_S 12 + +#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x0D8) +/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH0_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH0_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH0_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH0_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/* DMA_OUTFIFO_CNT_CH0 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ +#define DMA_OUTFIFO_CNT_CH0 0x0000003F +#define DMA_OUTFIFO_CNT_CH0_M ((DMA_OUTFIFO_CNT_CH0_V)<<(DMA_OUTFIFO_CNT_CH0_S)) +#define DMA_OUTFIFO_CNT_CH0_V 0x3F +#define DMA_OUTFIFO_CNT_CH0_S 2 +/* DMA_OUTFIFO_EMPTY_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 0.*/ +#define DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH0_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH0_V 0x1 +#define DMA_OUTFIFO_EMPTY_CH0_S 1 +/* DMA_OUTFIFO_FULL_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 0.*/ +#define DMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH0_M (BIT(0)) +#define DMA_OUTFIFO_FULL_CH0_V 0x1 +#define DMA_OUTFIFO_FULL_CH0_S 0 + +#define DMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0x0DC) +/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH0_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH0_V 0x1 +#define DMA_OUTFIFO_PUSH_CH0_S 9 +/* DMA_OUTFIFO_WDATA_CH0 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH0 0x000001FF +#define DMA_OUTFIFO_WDATA_CH0_M ((DMA_OUTFIFO_WDATA_CH0_V)<<(DMA_OUTFIFO_WDATA_CH0_S)) +#define DMA_OUTFIFO_WDATA_CH0_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH0_S 0 + +#define DMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x0E0) +/* DMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH0 (BIT(23)) +#define DMA_OUTLINK_PARK_CH0_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH0_V 0x1 +#define DMA_OUTLINK_PARK_CH0_S 23 +/* DMA_OUTLINK_RESTART_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH0_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH0_V 0x1 +#define DMA_OUTLINK_RESTART_CH0_S 22 +/* DMA_OUTLINK_START_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH0 (BIT(21)) +#define DMA_OUTLINK_START_CH0_M (BIT(21)) +#define DMA_OUTLINK_START_CH0_V 0x1 +#define DMA_OUTLINK_START_CH0_S 21 +/* DMA_OUTLINK_STOP_CH0 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH0 (BIT(20)) +#define DMA_OUTLINK_STOP_CH0_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH0_V 0x1 +#define DMA_OUTLINK_STOP_CH0_S 20 +/* DMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH0_M ((DMA_OUTLINK_ADDR_CH0_V)<<(DMA_OUTLINK_ADDR_CH0_S)) +#define DMA_OUTLINK_ADDR_CH0_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH0_S 0 + +#define DMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x0E4) +/* DMA_OUT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH0 0x00000007 +#define DMA_OUT_STATE_CH0_M ((DMA_OUT_STATE_CH0_V)<<(DMA_OUT_STATE_CH0_S)) +#define DMA_OUT_STATE_CH0_V 0x7 +#define DMA_OUT_STATE_CH0_S 20 +/* DMA_OUT_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH0 0x00000003 +#define DMA_OUT_DSCR_STATE_CH0_M ((DMA_OUT_DSCR_STATE_CH0_V)<<(DMA_OUT_DSCR_STATE_CH0_S)) +#define DMA_OUT_DSCR_STATE_CH0_V 0x3 +#define DMA_OUT_DSCR_STATE_CH0_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_M ((DMA_OUTLINK_DSCR_ADDR_CH0_V)<<(DMA_OUTLINK_DSCR_ADDR_CH0_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x0E8) +/* DMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_M ((DMA_OUT_EOF_DES_ADDR_CH0_V)<<(DMA_OUT_EOF_DES_ADDR_CH0_S)) +#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x0EC) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +#define DMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x0F0) +/* DMA_OUTLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_M ((DMA_OUTLINK_DSCR_CH0_V)<<(DMA_OUTLINK_DSCR_CH0_S)) +#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_S 0 + +#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x0F4) +/* DMA_OUTLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_M ((DMA_OUTLINK_DSCR_BF0_CH0_V)<<(DMA_OUTLINK_DSCR_BF0_CH0_S)) +#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_S 0 + +#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x0F8) +/* DMA_OUTLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_M ((DMA_OUTLINK_DSCR_BF1_CH0_V)<<(DMA_OUTLINK_DSCR_BF1_CH0_S)) +#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_S 0 + +#define DMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x0FC) +/* DMA_TX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 0. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH0 0x0000000F +#define DMA_TX_PRI_CH0_M ((DMA_TX_PRI_CH0_V)<<(DMA_TX_PRI_CH0_S)) +#define DMA_TX_PRI_CH0_V 0xF +#define DMA_TX_PRI_CH0_S 0 + +#define DMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/* DMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 0. + 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ +#define DMA_PERI_OUT_SEL_CH0 0x0000003F +#define DMA_PERI_OUT_SEL_CH0_M ((DMA_PERI_OUT_SEL_CH0_V)<<(DMA_PERI_OUT_SEL_CH0_S)) +#define DMA_PERI_OUT_SEL_CH0_V 0x3F +#define DMA_PERI_OUT_SEL_CH0_S 0 + +#define DMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/* DMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH1_M (BIT(4)) +#define DMA_MEM_TRANS_EN_CH1_V 0x1 +#define DMA_MEM_TRANS_EN_CH1_S 4 +/* DMA_IN_DATA_BURST_EN_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 1 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH1_M (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH1_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH1_S 3 +/* DMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 1 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH1_M (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH1_V 0x1 +#define DMA_INDSCR_BURST_EN_CH1_S 2 +/* DMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH1_M (BIT(1)) +#define DMA_IN_LOOP_TEST_CH1_V 0x1 +#define DMA_IN_LOOP_TEST_CH1_S 1 +/* DMA_IN_RST_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH1 (BIT(0)) +#define DMA_IN_RST_CH1_M (BIT(0)) +#define DMA_IN_RST_CH1_V 0x1 +#define DMA_IN_RST_CH1_S 0 + +#define DMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/* DMA_IN_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH1_M (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH1_V 0x1 +#define DMA_IN_CHECK_OWNER_CH1_S 12 + +#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/* DMA_IN_BUF_HUNGRY_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH1_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH1_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH1_S 27 +/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH1_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH1_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH1_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH1_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/* DMA_INFIFO_CNT_CH1 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.*/ +#define DMA_INFIFO_CNT_CH1 0x0000003F +#define DMA_INFIFO_CNT_CH1_M ((DMA_INFIFO_CNT_CH1_V)<<(DMA_INFIFO_CNT_CH1_S)) +#define DMA_INFIFO_CNT_CH1_V 0x3F +#define DMA_INFIFO_CNT_CH1_S 2 +/* DMA_INFIFO_EMPTY_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 1.*/ +#define DMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH1_M (BIT(1)) +#define DMA_INFIFO_EMPTY_CH1_V 0x1 +#define DMA_INFIFO_EMPTY_CH1_S 1 +/* DMA_INFIFO_FULL_CH1 : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 1.*/ +#define DMA_INFIFO_FULL_CH1 (BIT(0)) +#define DMA_INFIFO_FULL_CH1_M (BIT(0)) +#define DMA_INFIFO_FULL_CH1_V 0x1 +#define DMA_INFIFO_FULL_CH1_S 0 + +#define DMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13C) +/* DMA_INFIFO_POP_CH1 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH1 (BIT(12)) +#define DMA_INFIFO_POP_CH1_M (BIT(12)) +#define DMA_INFIFO_POP_CH1_V 0x1 +#define DMA_INFIFO_POP_CH1_S 12 +/* DMA_INFIFO_RDATA_CH1 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH1 0x00000FFF +#define DMA_INFIFO_RDATA_CH1_M ((DMA_INFIFO_RDATA_CH1_V)<<(DMA_INFIFO_RDATA_CH1_S)) +#define DMA_INFIFO_RDATA_CH1_V 0xFFF +#define DMA_INFIFO_RDATA_CH1_S 0 + +#define DMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/* DMA_INLINK_PARK_CH1 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH1 (BIT(24)) +#define DMA_INLINK_PARK_CH1_M (BIT(24)) +#define DMA_INLINK_PARK_CH1_V 0x1 +#define DMA_INLINK_PARK_CH1_S 24 +/* DMA_INLINK_RESTART_CH1 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH1 (BIT(23)) +#define DMA_INLINK_RESTART_CH1_M (BIT(23)) +#define DMA_INLINK_RESTART_CH1_V 0x1 +#define DMA_INLINK_RESTART_CH1_S 23 +/* DMA_INLINK_START_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH1 (BIT(22)) +#define DMA_INLINK_START_CH1_M (BIT(22)) +#define DMA_INLINK_START_CH1_V 0x1 +#define DMA_INLINK_START_CH1_S 22 +/* DMA_INLINK_STOP_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH1 (BIT(21)) +#define DMA_INLINK_STOP_CH1_M (BIT(21)) +#define DMA_INLINK_STOP_CH1_V 0x1 +#define DMA_INLINK_STOP_CH1_S 21 +/* DMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH1_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH1_V 0x1 +#define DMA_INLINK_AUTO_RET_CH1_S 20 +/* DMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH1 0x000FFFFF +#define DMA_INLINK_ADDR_CH1_M ((DMA_INLINK_ADDR_CH1_V)<<(DMA_INLINK_ADDR_CH1_S)) +#define DMA_INLINK_ADDR_CH1_V 0xFFFFF +#define DMA_INLINK_ADDR_CH1_S 0 + +#define DMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/* DMA_IN_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH1 0x00000007 +#define DMA_IN_STATE_CH1_M ((DMA_IN_STATE_CH1_V)<<(DMA_IN_STATE_CH1_S)) +#define DMA_IN_STATE_CH1_V 0x7 +#define DMA_IN_STATE_CH1_S 20 +/* DMA_IN_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH1 0x00000003 +#define DMA_IN_DSCR_STATE_CH1_M ((DMA_IN_DSCR_STATE_CH1_V)<<(DMA_IN_DSCR_STATE_CH1_S)) +#define DMA_IN_DSCR_STATE_CH1_V 0x3 +#define DMA_IN_DSCR_STATE_CH1_S 18 +/* DMA_INLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_M ((DMA_INLINK_DSCR_ADDR_CH1_V)<<(DMA_INLINK_DSCR_ADDR_CH1_S)) +#define DMA_INLINK_DSCR_ADDR_CH1_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M ((DMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH1_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14C) +/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M ((DMA_IN_ERR_EOF_DES_ADDR_CH1_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH1_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +#define DMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/* DMA_INLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_M ((DMA_INLINK_DSCR_CH1_V)<<(DMA_INLINK_DSCR_CH1_S)) +#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_S 0 + +#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/* DMA_INLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_M ((DMA_INLINK_DSCR_BF0_CH1_V)<<(DMA_INLINK_DSCR_BF0_CH1_S)) +#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_S 0 + +#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/* DMA_INLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_M ((DMA_INLINK_DSCR_BF1_CH1_V)<<(DMA_INLINK_DSCR_BF1_CH1_S)) +#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_S 0 + +#define DMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15C) +/* DMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 1. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH1 0x0000000F +#define DMA_RX_PRI_CH1_M ((DMA_RX_PRI_CH1_V)<<(DMA_RX_PRI_CH1_S)) +#define DMA_RX_PRI_CH1_V 0xF +#define DMA_RX_PRI_CH1_S 0 + +#define DMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/* DMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 1. + 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ +#define DMA_PERI_IN_SEL_CH1 0x0000003F +#define DMA_PERI_IN_SEL_CH1_M ((DMA_PERI_IN_SEL_CH1_V)<<(DMA_PERI_IN_SEL_CH1_S)) +#define DMA_PERI_IN_SEL_CH1_V 0x3F +#define DMA_PERI_IN_SEL_CH1_S 0 + +#define DMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/* DMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 1 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH1_M (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH1_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH1_S 5 +/* DMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 1 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH1_M (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH1_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH1_S 4 +/* DMA_OUT_EOF_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH1_M (BIT(3)) +#define DMA_OUT_EOF_MODE_CH1_V 0x1 +#define DMA_OUT_EOF_MODE_CH1_S 3 +/* DMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH1_M (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH1_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH1_S 2 +/* DMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH1_M (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH1_V 0x1 +#define DMA_OUT_LOOP_TEST_CH1_S 1 +/* DMA_OUT_RST_CH1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH1 (BIT(0)) +#define DMA_OUT_RST_CH1_M (BIT(0)) +#define DMA_OUT_RST_CH1_V 0x1 +#define DMA_OUT_RST_CH1_S 0 + +#define DMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/* DMA_OUT_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH1_M (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH1_V 0x1 +#define DMA_OUT_CHECK_OWNER_CH1_S 12 + +#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH1_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH1_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH1_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH1_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/* DMA_OUTFIFO_CNT_CH1 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.*/ +#define DMA_OUTFIFO_CNT_CH1 0x0000003F +#define DMA_OUTFIFO_CNT_CH1_M ((DMA_OUTFIFO_CNT_CH1_V)<<(DMA_OUTFIFO_CNT_CH1_S)) +#define DMA_OUTFIFO_CNT_CH1_V 0x3F +#define DMA_OUTFIFO_CNT_CH1_S 2 +/* DMA_OUTFIFO_EMPTY_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 1.*/ +#define DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH1_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH1_V 0x1 +#define DMA_OUTFIFO_EMPTY_CH1_S 1 +/* DMA_OUTFIFO_FULL_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 1.*/ +#define DMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH1_M (BIT(0)) +#define DMA_OUTFIFO_FULL_CH1_V 0x1 +#define DMA_OUTFIFO_FULL_CH1_S 0 + +#define DMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19C) +/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH1_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH1_V 0x1 +#define DMA_OUTFIFO_PUSH_CH1_S 9 +/* DMA_OUTFIFO_WDATA_CH1 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH1 0x000001FF +#define DMA_OUTFIFO_WDATA_CH1_M ((DMA_OUTFIFO_WDATA_CH1_V)<<(DMA_OUTFIFO_WDATA_CH1_S)) +#define DMA_OUTFIFO_WDATA_CH1_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH1_S 0 + +#define DMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1A0) +/* DMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH1 (BIT(23)) +#define DMA_OUTLINK_PARK_CH1_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH1_V 0x1 +#define DMA_OUTLINK_PARK_CH1_S 23 +/* DMA_OUTLINK_RESTART_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH1_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH1_V 0x1 +#define DMA_OUTLINK_RESTART_CH1_S 22 +/* DMA_OUTLINK_START_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH1 (BIT(21)) +#define DMA_OUTLINK_START_CH1_M (BIT(21)) +#define DMA_OUTLINK_START_CH1_V 0x1 +#define DMA_OUTLINK_START_CH1_S 21 +/* DMA_OUTLINK_STOP_CH1 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH1 (BIT(20)) +#define DMA_OUTLINK_STOP_CH1_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH1_V 0x1 +#define DMA_OUTLINK_STOP_CH1_S 20 +/* DMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH1_M ((DMA_OUTLINK_ADDR_CH1_V)<<(DMA_OUTLINK_ADDR_CH1_S)) +#define DMA_OUTLINK_ADDR_CH1_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH1_S 0 + +#define DMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1A4) +/* DMA_OUT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH1 0x00000007 +#define DMA_OUT_STATE_CH1_M ((DMA_OUT_STATE_CH1_V)<<(DMA_OUT_STATE_CH1_S)) +#define DMA_OUT_STATE_CH1_V 0x7 +#define DMA_OUT_STATE_CH1_S 20 +/* DMA_OUT_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH1 0x00000003 +#define DMA_OUT_DSCR_STATE_CH1_M ((DMA_OUT_DSCR_STATE_CH1_V)<<(DMA_OUT_DSCR_STATE_CH1_S)) +#define DMA_OUT_DSCR_STATE_CH1_V 0x3 +#define DMA_OUT_DSCR_STATE_CH1_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_M ((DMA_OUTLINK_DSCR_ADDR_CH1_V)<<(DMA_OUTLINK_DSCR_ADDR_CH1_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1A8) +/* DMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_M ((DMA_OUT_EOF_DES_ADDR_CH1_V)<<(DMA_OUT_EOF_DES_ADDR_CH1_S)) +#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1AC) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +#define DMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1B0) +/* DMA_OUTLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_M ((DMA_OUTLINK_DSCR_CH1_V)<<(DMA_OUTLINK_DSCR_CH1_S)) +#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_S 0 + +#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1B4) +/* DMA_OUTLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_M ((DMA_OUTLINK_DSCR_BF0_CH1_V)<<(DMA_OUTLINK_DSCR_BF0_CH1_S)) +#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_S 0 + +#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1B8) +/* DMA_OUTLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_M ((DMA_OUTLINK_DSCR_BF1_CH1_V)<<(DMA_OUTLINK_DSCR_BF1_CH1_S)) +#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_S 0 + +#define DMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1BC) +/* DMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 1. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH1 0x0000000F +#define DMA_TX_PRI_CH1_M ((DMA_TX_PRI_CH1_V)<<(DMA_TX_PRI_CH1_S)) +#define DMA_TX_PRI_CH1_V 0xF +#define DMA_TX_PRI_CH1_S 0 + +#define DMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1C0) +/* DMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 1. + 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ +#define DMA_PERI_OUT_SEL_CH1 0x0000003F +#define DMA_PERI_OUT_SEL_CH1_M ((DMA_PERI_OUT_SEL_CH1_V)<<(DMA_PERI_OUT_SEL_CH1_S)) +#define DMA_PERI_OUT_SEL_CH1_V 0x3F +#define DMA_PERI_OUT_SEL_CH1_S 0 + +#define DMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1F0) +/* DMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH2_M (BIT(4)) +#define DMA_MEM_TRANS_EN_CH2_V 0x1 +#define DMA_MEM_TRANS_EN_CH2_S 4 +/* DMA_IN_DATA_BURST_EN_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 2 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH2_M (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH2_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH2_S 3 +/* DMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 2 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH2_M (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH2_V 0x1 +#define DMA_INDSCR_BURST_EN_CH2_S 2 +/* DMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH2_M (BIT(1)) +#define DMA_IN_LOOP_TEST_CH2_V 0x1 +#define DMA_IN_LOOP_TEST_CH2_S 1 +/* DMA_IN_RST_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH2 (BIT(0)) +#define DMA_IN_RST_CH2_M (BIT(0)) +#define DMA_IN_RST_CH2_V 0x1 +#define DMA_IN_RST_CH2_S 0 + +#define DMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1F4) +/* DMA_IN_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH2_M (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH2_V 0x1 +#define DMA_IN_CHECK_OWNER_CH2_S 12 + +#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1F8) +/* DMA_IN_BUF_HUNGRY_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH2_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH2_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH2_S 27 +/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH2_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH2_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH2_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH2_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/* DMA_INFIFO_CNT_CH2 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.*/ +#define DMA_INFIFO_CNT_CH2 0x0000003F +#define DMA_INFIFO_CNT_CH2_M ((DMA_INFIFO_CNT_CH2_V)<<(DMA_INFIFO_CNT_CH2_S)) +#define DMA_INFIFO_CNT_CH2_V 0x3F +#define DMA_INFIFO_CNT_CH2_S 2 +/* DMA_INFIFO_EMPTY_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 2.*/ +#define DMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH2_M (BIT(1)) +#define DMA_INFIFO_EMPTY_CH2_V 0x1 +#define DMA_INFIFO_EMPTY_CH2_S 1 +/* DMA_INFIFO_FULL_CH2 : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 2.*/ +#define DMA_INFIFO_FULL_CH2 (BIT(0)) +#define DMA_INFIFO_FULL_CH2_M (BIT(0)) +#define DMA_INFIFO_FULL_CH2_V 0x1 +#define DMA_INFIFO_FULL_CH2_S 0 + +#define DMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1FC) +/* DMA_INFIFO_POP_CH2 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH2 (BIT(12)) +#define DMA_INFIFO_POP_CH2_M (BIT(12)) +#define DMA_INFIFO_POP_CH2_V 0x1 +#define DMA_INFIFO_POP_CH2_S 12 +/* DMA_INFIFO_RDATA_CH2 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH2 0x00000FFF +#define DMA_INFIFO_RDATA_CH2_M ((DMA_INFIFO_RDATA_CH2_V)<<(DMA_INFIFO_RDATA_CH2_S)) +#define DMA_INFIFO_RDATA_CH2_V 0xFFF +#define DMA_INFIFO_RDATA_CH2_S 0 + +#define DMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/* DMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH2 (BIT(24)) +#define DMA_INLINK_PARK_CH2_M (BIT(24)) +#define DMA_INLINK_PARK_CH2_V 0x1 +#define DMA_INLINK_PARK_CH2_S 24 +/* DMA_INLINK_RESTART_CH2 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH2 (BIT(23)) +#define DMA_INLINK_RESTART_CH2_M (BIT(23)) +#define DMA_INLINK_RESTART_CH2_V 0x1 +#define DMA_INLINK_RESTART_CH2_S 23 +/* DMA_INLINK_START_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH2 (BIT(22)) +#define DMA_INLINK_START_CH2_M (BIT(22)) +#define DMA_INLINK_START_CH2_V 0x1 +#define DMA_INLINK_START_CH2_S 22 +/* DMA_INLINK_STOP_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH2 (BIT(21)) +#define DMA_INLINK_STOP_CH2_M (BIT(21)) +#define DMA_INLINK_STOP_CH2_V 0x1 +#define DMA_INLINK_STOP_CH2_S 21 +/* DMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH2_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH2_V 0x1 +#define DMA_INLINK_AUTO_RET_CH2_S 20 +/* DMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH2 0x000FFFFF +#define DMA_INLINK_ADDR_CH2_M ((DMA_INLINK_ADDR_CH2_V)<<(DMA_INLINK_ADDR_CH2_S)) +#define DMA_INLINK_ADDR_CH2_V 0xFFFFF +#define DMA_INLINK_ADDR_CH2_S 0 + +#define DMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/* DMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH2 0x00000007 +#define DMA_IN_STATE_CH2_M ((DMA_IN_STATE_CH2_V)<<(DMA_IN_STATE_CH2_S)) +#define DMA_IN_STATE_CH2_V 0x7 +#define DMA_IN_STATE_CH2_S 20 +/* DMA_IN_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH2 0x00000003 +#define DMA_IN_DSCR_STATE_CH2_M ((DMA_IN_DSCR_STATE_CH2_V)<<(DMA_IN_DSCR_STATE_CH2_S)) +#define DMA_IN_DSCR_STATE_CH2_V 0x3 +#define DMA_IN_DSCR_STATE_CH2_S 18 +/* DMA_INLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_M ((DMA_INLINK_DSCR_ADDR_CH2_V)<<(DMA_INLINK_DSCR_ADDR_CH2_S)) +#define DMA_INLINK_DSCR_ADDR_CH2_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M ((DMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH2_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20C) +/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M ((DMA_IN_ERR_EOF_DES_ADDR_CH2_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH2_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +#define DMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/* DMA_INLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_M ((DMA_INLINK_DSCR_CH2_V)<<(DMA_INLINK_DSCR_CH2_S)) +#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_S 0 + +#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/* DMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_M ((DMA_INLINK_DSCR_BF0_CH2_V)<<(DMA_INLINK_DSCR_BF0_CH2_S)) +#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_S 0 + +#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/* DMA_INLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_M ((DMA_INLINK_DSCR_BF1_CH2_V)<<(DMA_INLINK_DSCR_BF1_CH2_S)) +#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_S 0 + +#define DMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21C) +/* DMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 2. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH2 0x0000000F +#define DMA_RX_PRI_CH2_M ((DMA_RX_PRI_CH2_V)<<(DMA_RX_PRI_CH2_S)) +#define DMA_RX_PRI_CH2_V 0xF +#define DMA_RX_PRI_CH2_S 0 + +#define DMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/* DMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 2. + 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ +#define DMA_PERI_IN_SEL_CH2 0x0000003F +#define DMA_PERI_IN_SEL_CH2_M ((DMA_PERI_IN_SEL_CH2_V)<<(DMA_PERI_IN_SEL_CH2_S)) +#define DMA_PERI_IN_SEL_CH2_V 0x3F +#define DMA_PERI_IN_SEL_CH2_S 0 + +#define DMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/* DMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 2 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH2_M (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH2_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH2_S 5 +/* DMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 2 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH2_M (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH2_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH2_S 4 +/* DMA_OUT_EOF_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH2_M (BIT(3)) +#define DMA_OUT_EOF_MODE_CH2_V 0x1 +#define DMA_OUT_EOF_MODE_CH2_S 3 +/* DMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH2_M (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH2_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH2_S 2 +/* DMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH2_M (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH2_V 0x1 +#define DMA_OUT_LOOP_TEST_CH2_S 1 +/* DMA_OUT_RST_CH2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH2 (BIT(0)) +#define DMA_OUT_RST_CH2_M (BIT(0)) +#define DMA_OUT_RST_CH2_V 0x1 +#define DMA_OUT_RST_CH2_S 0 + +#define DMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/* DMA_OUT_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH2_M (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH2_V 0x1 +#define DMA_OUT_CHECK_OWNER_CH2_S 12 + +#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH2_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH2_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH2_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH2_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/* DMA_OUTFIFO_CNT_CH2 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.*/ +#define DMA_OUTFIFO_CNT_CH2 0x0000003F +#define DMA_OUTFIFO_CNT_CH2_M ((DMA_OUTFIFO_CNT_CH2_V)<<(DMA_OUTFIFO_CNT_CH2_S)) +#define DMA_OUTFIFO_CNT_CH2_V 0x3F +#define DMA_OUTFIFO_CNT_CH2_S 2 +/* DMA_OUTFIFO_EMPTY_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 2.*/ +#define DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH2_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH2_V 0x1 +#define DMA_OUTFIFO_EMPTY_CH2_S 1 +/* DMA_OUTFIFO_FULL_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 2.*/ +#define DMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH2_M (BIT(0)) +#define DMA_OUTFIFO_FULL_CH2_V 0x1 +#define DMA_OUTFIFO_FULL_CH2_S 0 + +#define DMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25C) +/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH2_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH2_V 0x1 +#define DMA_OUTFIFO_PUSH_CH2_S 9 +/* DMA_OUTFIFO_WDATA_CH2 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH2 0x000001FF +#define DMA_OUTFIFO_WDATA_CH2_M ((DMA_OUTFIFO_WDATA_CH2_V)<<(DMA_OUTFIFO_WDATA_CH2_S)) +#define DMA_OUTFIFO_WDATA_CH2_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH2_S 0 + +#define DMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/* DMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH2 (BIT(23)) +#define DMA_OUTLINK_PARK_CH2_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH2_V 0x1 +#define DMA_OUTLINK_PARK_CH2_S 23 +/* DMA_OUTLINK_RESTART_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH2_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH2_V 0x1 +#define DMA_OUTLINK_RESTART_CH2_S 22 +/* DMA_OUTLINK_START_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH2 (BIT(21)) +#define DMA_OUTLINK_START_CH2_M (BIT(21)) +#define DMA_OUTLINK_START_CH2_V 0x1 +#define DMA_OUTLINK_START_CH2_S 21 +/* DMA_OUTLINK_STOP_CH2 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH2 (BIT(20)) +#define DMA_OUTLINK_STOP_CH2_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH2_V 0x1 +#define DMA_OUTLINK_STOP_CH2_S 20 +/* DMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH2_M ((DMA_OUTLINK_ADDR_CH2_V)<<(DMA_OUTLINK_ADDR_CH2_S)) +#define DMA_OUTLINK_ADDR_CH2_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH2_S 0 + +#define DMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/* DMA_OUT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH2 0x00000007 +#define DMA_OUT_STATE_CH2_M ((DMA_OUT_STATE_CH2_V)<<(DMA_OUT_STATE_CH2_S)) +#define DMA_OUT_STATE_CH2_V 0x7 +#define DMA_OUT_STATE_CH2_S 20 +/* DMA_OUT_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH2 0x00000003 +#define DMA_OUT_DSCR_STATE_CH2_M ((DMA_OUT_DSCR_STATE_CH2_V)<<(DMA_OUT_DSCR_STATE_CH2_S)) +#define DMA_OUT_DSCR_STATE_CH2_V 0x3 +#define DMA_OUT_DSCR_STATE_CH2_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_M ((DMA_OUTLINK_DSCR_ADDR_CH2_V)<<(DMA_OUTLINK_DSCR_ADDR_CH2_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/* DMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_M ((DMA_OUT_EOF_DES_ADDR_CH2_V)<<(DMA_OUT_EOF_DES_ADDR_CH2_S)) +#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26C) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH2_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +#define DMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/* DMA_OUTLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_M ((DMA_OUTLINK_DSCR_CH2_V)<<(DMA_OUTLINK_DSCR_CH2_S)) +#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_S 0 + +#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/* DMA_OUTLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_M ((DMA_OUTLINK_DSCR_BF0_CH2_V)<<(DMA_OUTLINK_DSCR_BF0_CH2_S)) +#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_S 0 + +#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/* DMA_OUTLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_M ((DMA_OUTLINK_DSCR_BF1_CH2_V)<<(DMA_OUTLINK_DSCR_BF1_CH2_S)) +#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_S 0 + +#define DMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27C) +/* DMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 2. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH2 0x0000000F +#define DMA_TX_PRI_CH2_M ((DMA_TX_PRI_CH2_V)<<(DMA_TX_PRI_CH2_S)) +#define DMA_TX_PRI_CH2_V 0xF +#define DMA_TX_PRI_CH2_S 0 + +#define DMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/* DMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 2. + 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ +#define DMA_PERI_OUT_SEL_CH2 0x0000003F +#define DMA_PERI_OUT_SEL_CH2_M ((DMA_PERI_OUT_SEL_CH2_V)<<(DMA_PERI_OUT_SEL_CH2_S)) +#define DMA_PERI_OUT_SEL_CH2_V 0x3F +#define DMA_PERI_OUT_SEL_CH2_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_DMA_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/gdma_struct.h b/components/soc/esp32h2/include/soc/gdma_struct.h new file mode 100644 index 0000000000..446ff4c112 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gdma_struct.h @@ -0,0 +1,331 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + struct { + union { + struct { + uint32_t in_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ + uint32_t in_suc_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ + uint32_t in_err_eof: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ + uint32_t out_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ + uint32_t out_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ + uint32_t in_dscr_err: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ + uint32_t out_dscr_err: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ + uint32_t in_dscr_empty: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ + uint32_t out_total_eof: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ + uint32_t infifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/ + uint32_t infifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/ + uint32_t outfifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/ + uint32_t outfifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } raw; + union { + struct { + uint32_t in_done: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_ovf: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } st; + union { + struct { + uint32_t in_done: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_ovf: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } ena; + union { + struct { + uint32_t in_done: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_ovf: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } clr; + } intr[3]; + uint32_t reserved_30; + uint32_t reserved_34; + uint32_t reserved_38; + uint32_t reserved_3c; + union { + struct { + uint32_t ahb_testmode: 3; /*reserved*/ + uint32_t reserved3: 1; /*reserved*/ + uint32_t ahb_testaddr: 2; /*reserved*/ + uint32_t reserved6: 26; /*reserved*/ + }; + uint32_t val; + } ahb_test; + union { + struct { + uint32_t ahbm_rst_inter: 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/ + uint32_t reserved1: 1; + uint32_t arb_pri_dis: 1; /*Set this bit to disable priority arbitration function.*/ + uint32_t clk_en: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } misc_conf; + uint32_t date; /**/ + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + struct { + struct { + union { + struct { + uint32_t in_rst: 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ + uint32_t in_loop_test: 1; /*reserved*/ + uint32_t indscr_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/ + uint32_t in_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/ + uint32_t mem_trans_en: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved5: 27; /*reserved*/ + }; + uint32_t val; + } in_conf0; + union { + struct { + uint32_t reserved0: 12; + uint32_t in_check_owner: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_conf1; + union { + struct { + uint32_t infifo_full: 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty: 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_cnt: 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ + uint32_t reserved8: 15; /*reserved*/ + uint32_t in_remain_under_1b: 1; /*reserved*/ + uint32_t in_remain_under_2b: 1; /*reserved*/ + uint32_t in_remain_under_3b: 1; /*reserved*/ + uint32_t in_remain_under_4b: 1; /*reserved*/ + uint32_t in_buf_hungry: 1; /*reserved*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } infifo_status; + union { + struct { + uint32_t infifo_rdata: 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop: 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_pop; + union { + struct { + uint32_t addr: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t auto_ret: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ + uint32_t stop: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t park: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } in_link; + union { + struct { + uint32_t inlink_dscr_addr: 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state: 2; /*reserved*/ + uint32_t in_state: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } in_state; + uint32_t in_suc_eof_des_addr; /**/ + uint32_t in_err_eof_des_addr; /**/ + uint32_t in_dscr; /**/ + uint32_t in_dscr_bf0; /**/ + uint32_t in_dscr_bf1; /**/ + union { + struct { + uint32_t rx_pri: 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } in_pri; + union { + struct { + uint32_t sel: 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } in_peri_sel; + } in; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + struct { + union { + struct { + uint32_t out_rst: 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ + uint32_t out_loop_test: 1; /*reserved*/ + uint32_t out_auto_wrback: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/ + uint32_t out_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } out_conf0; + union { + struct { + uint32_t reserved0: 12; + uint32_t out_check_owner: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } out_conf1; + union { + struct { + uint32_t outfifo_full: 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty: 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_cnt: 6; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ + uint32_t reserved8: 15; /*reserved*/ + uint32_t out_remain_under_1b: 1; /*reserved*/ + uint32_t out_remain_under_2b: 1; /*reserved*/ + uint32_t out_remain_under_3b: 1; /*reserved*/ + uint32_t out_remain_under_4b: 1; /*reserved*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status; + union { + struct { + uint32_t outfifo_wdata: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push: 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } out_push; + union { + struct { + uint32_t addr: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t stop: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t restart: 1; /*Set this bit to restart a new outlink from the last address.*/ + uint32_t park: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } out_link; + union { + struct { + uint32_t outlink_dscr_addr: 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state: 2; /*reserved*/ + uint32_t out_state: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } out_state; + uint32_t out_eof_des_addr; /**/ + uint32_t out_eof_bfr_des_addr; /**/ + uint32_t out_dscr; /**/ + uint32_t out_dscr_bf0; /**/ + uint32_t out_dscr_bf1; /**/ + union { + struct { + uint32_t tx_pri: 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } out_pri; + union { + struct { + uint32_t sel: 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } out_peri_sel; + } out; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + } channel[3]; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_pins.h b/components/soc/esp32h2/include/soc/gpio_pins.h new file mode 100644 index 0000000000..f5a35b9975 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_pins.h @@ -0,0 +1,27 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_reg.h b/components/soc/esp32h2/include/soc/gpio_reg.h new file mode 100644 index 0000000000..a674277f99 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_reg.h @@ -0,0 +1,4588 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_REG_H_ +#define _SOC_GPIO_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define GPIO_PIN_CONFIG_MSB 12 +#define GPIO_PIN_CONFIG_LSB 11 +#define GPIO_PIN_CONFIG_MASK 0x00001800 +#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) +#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) + +#define GPIO_WAKEUP_ENABLE 1 +#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) +#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) +#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) + +#define GPIO_PIN_INT_TYPE_MASK 0x380 +#define GPIO_PIN_INT_TYPE_MSB 9 +#define GPIO_PIN_INT_TYPE_LSB 7 +#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) + +#define GPIO_PAD_DRIVER_ENABLE 1 +#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) +#define GPIO_PIN_PAD_DRIVER_MSB 2 +#define GPIO_PIN_PAD_DRIVER_LSB 2 +#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) +#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) + +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_OUT_DATA 0x03FFFFFF +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0x3FFFFFF +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_OUT_W1TS 0x03FFFFFF +#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) +#define GPIO_OUT_W1TS_V 0x3FFFFFF +#define GPIO_OUT_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xC) +/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_OUT_W1TC 0x03FFFFFF +#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) +#define GPIO_OUT_W1TC_V 0x3FFFFFF +#define GPIO_OUT_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1C) +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xFF +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_ENABLE_DATA 0x03FFFFFF +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0x3FFFFFF +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_ENABLE_W1TS 0x03FFFFFF +#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) +#define GPIO_ENABLE_W1TS_V 0x3FFFFFF +#define GPIO_ENABLE_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_ENABLE_W1TC 0x03FFFFFF +#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) +#define GPIO_ENABLE_W1TC_V 0x3FFFFFF +#define GPIO_ENABLE_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ +/*description: */ +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xFFFF +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3C) +/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default: ; */ +/*description: */ +#define GPIO_IN_DATA 0x03FFFFFF +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0x3FFFFFF +#define GPIO_IN_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_STATUS_INT 0x03FFFFFF +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0x3FFFFFF +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_STATUS_W1TS 0x03FFFFFF +#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) +#define GPIO_STATUS_W1TS_V 0x3FFFFFF +#define GPIO_STATUS_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4C) +/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_STATUS_W1TC 0x03FFFFFF +#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) +#define GPIO_STATUS_W1TC_V 0x3FFFFFF +#define GPIO_STATUS_W1TC_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) +/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_PROCPU_INT 0x03FFFFFF +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0x3FFFFFF +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_PROCPU_NMI_INT 0x03FFFFFF +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0x3FFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_SDIO_INT 0x03FFFFFF +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0x3FFFFFF +#define GPIO_SDIO_INT_S 0 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1F +#define GPIO_PIN0_INT_ENA_S 13 +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 +/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 +/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC2_BYPASS_S 0 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1F +#define GPIO_PIN1_INT_ENA_S 13 +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 +/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 +/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC2_BYPASS_S 0 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7C) +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1F +#define GPIO_PIN2_INT_ENA_S 13 +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 +/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 +/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC2_BYPASS_S 0 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1F +#define GPIO_PIN3_INT_ENA_S 13 +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 +/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 +/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC2_BYPASS_S 0 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1F +#define GPIO_PIN4_INT_ENA_S 13 +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 +/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 +/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC2_BYPASS_S 0 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1F +#define GPIO_PIN5_INT_ENA_S 13 +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 +/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 +/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC2_BYPASS_S 0 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8C) +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1F +#define GPIO_PIN6_INT_ENA_S 13 +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 +/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 +/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC2_BYPASS_S 0 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1F +#define GPIO_PIN7_INT_ENA_S 13 +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 +/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 +/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC2_BYPASS_S 0 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1F +#define GPIO_PIN8_INT_ENA_S 13 +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 +/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 +/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC2_BYPASS_S 0 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1F +#define GPIO_PIN9_INT_ENA_S 13 +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 +/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 +/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC2_BYPASS_S 0 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9C) +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1F +#define GPIO_PIN10_INT_ENA_S 13 +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 +/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 +/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC2_BYPASS_S 0 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xA0) +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1F +#define GPIO_PIN11_INT_ENA_S 13 +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 +/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 +/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC2_BYPASS_S 0 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xA4) +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1F +#define GPIO_PIN12_INT_ENA_S 13 +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 +/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 +/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC2_BYPASS_S 0 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xA8) +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1F +#define GPIO_PIN13_INT_ENA_S 13 +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 +/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 +/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC2_BYPASS_S 0 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xAC) +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1F +#define GPIO_PIN14_INT_ENA_S 13 +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 +/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 +/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC2_BYPASS_S 0 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xB0) +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1F +#define GPIO_PIN15_INT_ENA_S 13 +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 +/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 +/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC2_BYPASS_S 0 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xB4) +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1F +#define GPIO_PIN16_INT_ENA_S 13 +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 +/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 +/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC2_BYPASS_S 0 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xB8) +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1F +#define GPIO_PIN17_INT_ENA_S 13 +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 +/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 +/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC2_BYPASS_S 0 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xBC) +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1F +#define GPIO_PIN18_INT_ENA_S 13 +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 +/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 +/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC2_BYPASS_S 0 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xC0) +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1F +#define GPIO_PIN19_INT_ENA_S 13 +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 +/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 +/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC2_BYPASS_S 0 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xC4) +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1F +#define GPIO_PIN20_INT_ENA_S 13 +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 +/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 +/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC2_BYPASS_S 0 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xC8) +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1F +#define GPIO_PIN21_INT_ENA_S 13 +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 +/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 +/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC2_BYPASS_S 0 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xCC) +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1F +#define GPIO_PIN22_INT_ENA_S 13 +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 +/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 +/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC2_BYPASS_S 0 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xD0) +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1F +#define GPIO_PIN23_INT_ENA_S 13 +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 +/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 +/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC2_BYPASS_S 0 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xD4) +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1F +#define GPIO_PIN24_INT_ENA_S 13 +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 +/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 +/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC2_BYPASS_S 0 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xD8) +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1F +#define GPIO_PIN25_INT_ENA_S 13 +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 +/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 +/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC2_BYPASS_S 0 + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) +/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: */ +#define GPIO_STATUS_INTERRUPT_NEXT 0x03FFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3FFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG0_IN_SEL (BIT(6)) +#define GPIO_SIG0_IN_SEL_M (BIT(6)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 6 +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 5 +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC0_IN_SEL 0x0000001F +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x1F +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG1_IN_SEL (BIT(6)) +#define GPIO_SIG1_IN_SEL_M (BIT(6)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 6 +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 5 +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC1_IN_SEL 0x0000001F +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x1F +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15C) +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG2_IN_SEL (BIT(6)) +#define GPIO_SIG2_IN_SEL_M (BIT(6)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 6 +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 5 +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC2_IN_SEL 0x0000001F +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x1F +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG3_IN_SEL (BIT(6)) +#define GPIO_SIG3_IN_SEL_M (BIT(6)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 6 +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 5 +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC3_IN_SEL 0x0000001F +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x1F +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG4_IN_SEL (BIT(6)) +#define GPIO_SIG4_IN_SEL_M (BIT(6)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 6 +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 5 +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC4_IN_SEL 0x0000001F +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x1F +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG5_IN_SEL (BIT(6)) +#define GPIO_SIG5_IN_SEL_M (BIT(6)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 6 +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 5 +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC5_IN_SEL 0x0000001F +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x1F +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16C) +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG6_IN_SEL (BIT(6)) +#define GPIO_SIG6_IN_SEL_M (BIT(6)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 6 +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 5 +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC6_IN_SEL 0x0000001F +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x1F +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG7_IN_SEL (BIT(6)) +#define GPIO_SIG7_IN_SEL_M (BIT(6)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 6 +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 5 +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC7_IN_SEL 0x0000001F +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x1F +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG8_IN_SEL (BIT(6)) +#define GPIO_SIG8_IN_SEL_M (BIT(6)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 6 +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 5 +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC8_IN_SEL 0x0000001F +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x1F +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG9_IN_SEL (BIT(6)) +#define GPIO_SIG9_IN_SEL_M (BIT(6)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 6 +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 5 +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC9_IN_SEL 0x0000001F +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x1F +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17C) +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG10_IN_SEL (BIT(6)) +#define GPIO_SIG10_IN_SEL_M (BIT(6)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 6 +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 5 +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC10_IN_SEL 0x0000001F +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x1F +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG11_IN_SEL (BIT(6)) +#define GPIO_SIG11_IN_SEL_M (BIT(6)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 6 +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 5 +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC11_IN_SEL 0x0000001F +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x1F +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG12_IN_SEL (BIT(6)) +#define GPIO_SIG12_IN_SEL_M (BIT(6)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 6 +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 5 +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC12_IN_SEL 0x0000001F +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x1F +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG13_IN_SEL (BIT(6)) +#define GPIO_SIG13_IN_SEL_M (BIT(6)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 6 +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 5 +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC13_IN_SEL 0x0000001F +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x1F +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18C) +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG14_IN_SEL (BIT(6)) +#define GPIO_SIG14_IN_SEL_M (BIT(6)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 6 +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 5 +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC14_IN_SEL 0x0000001F +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x1F +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG15_IN_SEL (BIT(6)) +#define GPIO_SIG15_IN_SEL_M (BIT(6)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 6 +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 5 +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC15_IN_SEL 0x0000001F +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x1F +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG16_IN_SEL (BIT(6)) +#define GPIO_SIG16_IN_SEL_M (BIT(6)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 6 +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 5 +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC16_IN_SEL 0x0000001F +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x1F +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG17_IN_SEL (BIT(6)) +#define GPIO_SIG17_IN_SEL_M (BIT(6)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 6 +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 5 +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC17_IN_SEL 0x0000001F +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x1F +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19C) +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG18_IN_SEL (BIT(6)) +#define GPIO_SIG18_IN_SEL_M (BIT(6)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 6 +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 5 +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC18_IN_SEL 0x0000001F +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x1F +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A0) +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG19_IN_SEL (BIT(6)) +#define GPIO_SIG19_IN_SEL_M (BIT(6)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 6 +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 5 +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC19_IN_SEL 0x0000001F +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x1F +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A4) +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG20_IN_SEL (BIT(6)) +#define GPIO_SIG20_IN_SEL_M (BIT(6)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 6 +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 5 +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC20_IN_SEL 0x0000001F +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x1F +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A8) +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG21_IN_SEL (BIT(6)) +#define GPIO_SIG21_IN_SEL_M (BIT(6)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 6 +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 5 +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC21_IN_SEL 0x0000001F +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x1F +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1AC) +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG22_IN_SEL (BIT(6)) +#define GPIO_SIG22_IN_SEL_M (BIT(6)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 6 +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 5 +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC22_IN_SEL 0x0000001F +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x1F +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B0) +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG23_IN_SEL (BIT(6)) +#define GPIO_SIG23_IN_SEL_M (BIT(6)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 6 +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 5 +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC23_IN_SEL 0x0000001F +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x1F +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B4) +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG24_IN_SEL (BIT(6)) +#define GPIO_SIG24_IN_SEL_M (BIT(6)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 6 +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 5 +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC24_IN_SEL 0x0000001F +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x1F +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B8) +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG25_IN_SEL (BIT(6)) +#define GPIO_SIG25_IN_SEL_M (BIT(6)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 6 +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 5 +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC25_IN_SEL 0x0000001F +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x1F +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1BC) +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG26_IN_SEL (BIT(6)) +#define GPIO_SIG26_IN_SEL_M (BIT(6)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 6 +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 5 +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC26_IN_SEL 0x0000001F +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x1F +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C0) +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG27_IN_SEL (BIT(6)) +#define GPIO_SIG27_IN_SEL_M (BIT(6)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 6 +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 5 +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC27_IN_SEL 0x0000001F +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x1F +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C4) +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG28_IN_SEL (BIT(6)) +#define GPIO_SIG28_IN_SEL_M (BIT(6)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 6 +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 5 +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC28_IN_SEL 0x0000001F +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x1F +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C8) +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG29_IN_SEL (BIT(6)) +#define GPIO_SIG29_IN_SEL_M (BIT(6)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 6 +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 5 +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC29_IN_SEL 0x0000001F +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x1F +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1CC) +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG30_IN_SEL (BIT(6)) +#define GPIO_SIG30_IN_SEL_M (BIT(6)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 6 +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 5 +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC30_IN_SEL 0x0000001F +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x1F +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D0) +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG31_IN_SEL (BIT(6)) +#define GPIO_SIG31_IN_SEL_M (BIT(6)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 6 +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 5 +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC31_IN_SEL 0x0000001F +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x1F +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D4) +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG32_IN_SEL (BIT(6)) +#define GPIO_SIG32_IN_SEL_M (BIT(6)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 6 +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 5 +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC32_IN_SEL 0x0000001F +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x1F +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D8) +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG33_IN_SEL (BIT(6)) +#define GPIO_SIG33_IN_SEL_M (BIT(6)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 6 +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 5 +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC33_IN_SEL 0x0000001F +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x1F +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1DC) +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG34_IN_SEL (BIT(6)) +#define GPIO_SIG34_IN_SEL_M (BIT(6)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 6 +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 5 +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC34_IN_SEL 0x0000001F +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x1F +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E0) +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG35_IN_SEL (BIT(6)) +#define GPIO_SIG35_IN_SEL_M (BIT(6)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 6 +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 5 +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC35_IN_SEL 0x0000001F +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x1F +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E4) +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG36_IN_SEL (BIT(6)) +#define GPIO_SIG36_IN_SEL_M (BIT(6)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 6 +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 5 +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC36_IN_SEL 0x0000001F +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x1F +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E8) +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG37_IN_SEL (BIT(6)) +#define GPIO_SIG37_IN_SEL_M (BIT(6)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 6 +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 5 +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC37_IN_SEL 0x0000001F +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x1F +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1EC) +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG38_IN_SEL (BIT(6)) +#define GPIO_SIG38_IN_SEL_M (BIT(6)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 6 +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 5 +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC38_IN_SEL 0x0000001F +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x1F +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F0) +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG39_IN_SEL (BIT(6)) +#define GPIO_SIG39_IN_SEL_M (BIT(6)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 6 +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 5 +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC39_IN_SEL 0x0000001F +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x1F +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F4) +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG40_IN_SEL (BIT(6)) +#define GPIO_SIG40_IN_SEL_M (BIT(6)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 6 +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 5 +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC40_IN_SEL 0x0000001F +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x1F +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F8) +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG41_IN_SEL (BIT(6)) +#define GPIO_SIG41_IN_SEL_M (BIT(6)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 6 +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 5 +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC41_IN_SEL 0x0000001F +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x1F +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1FC) +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG42_IN_SEL (BIT(6)) +#define GPIO_SIG42_IN_SEL_M (BIT(6)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 6 +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 5 +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC42_IN_SEL 0x0000001F +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x1F +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG43_IN_SEL (BIT(6)) +#define GPIO_SIG43_IN_SEL_M (BIT(6)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 6 +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 5 +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC43_IN_SEL 0x0000001F +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x1F +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG44_IN_SEL (BIT(6)) +#define GPIO_SIG44_IN_SEL_M (BIT(6)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 6 +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 5 +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC44_IN_SEL 0x0000001F +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x1F +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG45_IN_SEL (BIT(6)) +#define GPIO_SIG45_IN_SEL_M (BIT(6)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 6 +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 5 +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC45_IN_SEL 0x0000001F +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x1F +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20C) +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG46_IN_SEL (BIT(6)) +#define GPIO_SIG46_IN_SEL_M (BIT(6)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 6 +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 5 +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC46_IN_SEL 0x0000001F +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x1F +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG47_IN_SEL (BIT(6)) +#define GPIO_SIG47_IN_SEL_M (BIT(6)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 6 +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 5 +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC47_IN_SEL 0x0000001F +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x1F +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG48_IN_SEL (BIT(6)) +#define GPIO_SIG48_IN_SEL_M (BIT(6)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 6 +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 5 +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC48_IN_SEL 0x0000001F +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x1F +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG49_IN_SEL (BIT(6)) +#define GPIO_SIG49_IN_SEL_M (BIT(6)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 6 +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 5 +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC49_IN_SEL 0x0000001F +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x1F +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21C) +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG50_IN_SEL (BIT(6)) +#define GPIO_SIG50_IN_SEL_M (BIT(6)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 6 +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 5 +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC50_IN_SEL 0x0000001F +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x1F +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG51_IN_SEL (BIT(6)) +#define GPIO_SIG51_IN_SEL_M (BIT(6)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 6 +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 5 +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC51_IN_SEL 0x0000001F +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x1F +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG52_IN_SEL (BIT(6)) +#define GPIO_SIG52_IN_SEL_M (BIT(6)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 6 +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 5 +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC52_IN_SEL 0x0000001F +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x1F +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG53_IN_SEL (BIT(6)) +#define GPIO_SIG53_IN_SEL_M (BIT(6)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 6 +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 5 +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC53_IN_SEL 0x0000001F +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x1F +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22C) +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG54_IN_SEL (BIT(6)) +#define GPIO_SIG54_IN_SEL_M (BIT(6)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 6 +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 5 +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC54_IN_SEL 0x0000001F +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x1F +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG55_IN_SEL (BIT(6)) +#define GPIO_SIG55_IN_SEL_M (BIT(6)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 6 +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 5 +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC55_IN_SEL 0x0000001F +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x1F +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG56_IN_SEL (BIT(6)) +#define GPIO_SIG56_IN_SEL_M (BIT(6)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 6 +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 5 +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC56_IN_SEL 0x0000001F +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x1F +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG57_IN_SEL (BIT(6)) +#define GPIO_SIG57_IN_SEL_M (BIT(6)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 6 +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 5 +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC57_IN_SEL 0x0000001F +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x1F +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23C) +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG58_IN_SEL (BIT(6)) +#define GPIO_SIG58_IN_SEL_M (BIT(6)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 6 +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 5 +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC58_IN_SEL 0x0000001F +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x1F +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG59_IN_SEL (BIT(6)) +#define GPIO_SIG59_IN_SEL_M (BIT(6)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 6 +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 5 +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC59_IN_SEL 0x0000001F +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x1F +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG60_IN_SEL (BIT(6)) +#define GPIO_SIG60_IN_SEL_M (BIT(6)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 6 +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 5 +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC60_IN_SEL 0x0000001F +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x1F +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG61_IN_SEL (BIT(6)) +#define GPIO_SIG61_IN_SEL_M (BIT(6)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 6 +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 5 +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC61_IN_SEL 0x0000001F +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x1F +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24C) +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG62_IN_SEL (BIT(6)) +#define GPIO_SIG62_IN_SEL_M (BIT(6)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 6 +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 5 +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC62_IN_SEL 0x0000001F +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x1F +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG63_IN_SEL (BIT(6)) +#define GPIO_SIG63_IN_SEL_M (BIT(6)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 6 +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 5 +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC63_IN_SEL 0x0000001F +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x1F +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG64_IN_SEL (BIT(6)) +#define GPIO_SIG64_IN_SEL_M (BIT(6)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 6 +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 5 +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC64_IN_SEL 0x0000001F +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x1F +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG65_IN_SEL (BIT(6)) +#define GPIO_SIG65_IN_SEL_M (BIT(6)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 6 +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 5 +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC65_IN_SEL 0x0000001F +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x1F +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25C) +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG66_IN_SEL (BIT(6)) +#define GPIO_SIG66_IN_SEL_M (BIT(6)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 6 +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 5 +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC66_IN_SEL 0x0000001F +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x1F +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG67_IN_SEL (BIT(6)) +#define GPIO_SIG67_IN_SEL_M (BIT(6)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 6 +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 5 +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC67_IN_SEL 0x0000001F +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x1F +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG68_IN_SEL (BIT(6)) +#define GPIO_SIG68_IN_SEL_M (BIT(6)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 6 +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 5 +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC68_IN_SEL 0x0000001F +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x1F +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG69_IN_SEL (BIT(6)) +#define GPIO_SIG69_IN_SEL_M (BIT(6)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 6 +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 5 +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC69_IN_SEL 0x0000001F +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x1F +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26C) +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG70_IN_SEL (BIT(6)) +#define GPIO_SIG70_IN_SEL_M (BIT(6)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 6 +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 5 +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC70_IN_SEL 0x0000001F +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x1F +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG71_IN_SEL (BIT(6)) +#define GPIO_SIG71_IN_SEL_M (BIT(6)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 6 +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 5 +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC71_IN_SEL 0x0000001F +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x1F +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG72_IN_SEL (BIT(6)) +#define GPIO_SIG72_IN_SEL_M (BIT(6)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 6 +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 5 +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC72_IN_SEL 0x0000001F +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x1F +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG73_IN_SEL (BIT(6)) +#define GPIO_SIG73_IN_SEL_M (BIT(6)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 6 +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 5 +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC73_IN_SEL 0x0000001F +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x1F +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27C) +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG74_IN_SEL (BIT(6)) +#define GPIO_SIG74_IN_SEL_M (BIT(6)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 6 +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 5 +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC74_IN_SEL 0x0000001F +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x1F +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG75_IN_SEL (BIT(6)) +#define GPIO_SIG75_IN_SEL_M (BIT(6)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 6 +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 5 +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC75_IN_SEL 0x0000001F +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x1F +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG76_IN_SEL (BIT(6)) +#define GPIO_SIG76_IN_SEL_M (BIT(6)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 6 +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 5 +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC76_IN_SEL 0x0000001F +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x1F +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG77_IN_SEL (BIT(6)) +#define GPIO_SIG77_IN_SEL_M (BIT(6)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 6 +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 5 +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC77_IN_SEL 0x0000001F +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x1F +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28C) +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG78_IN_SEL (BIT(6)) +#define GPIO_SIG78_IN_SEL_M (BIT(6)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 6 +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 5 +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC78_IN_SEL 0x0000001F +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x1F +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG79_IN_SEL (BIT(6)) +#define GPIO_SIG79_IN_SEL_M (BIT(6)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 6 +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 5 +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC79_IN_SEL 0x0000001F +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x1F +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG80_IN_SEL (BIT(6)) +#define GPIO_SIG80_IN_SEL_M (BIT(6)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 6 +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 5 +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC80_IN_SEL 0x0000001F +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x1F +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG81_IN_SEL (BIT(6)) +#define GPIO_SIG81_IN_SEL_M (BIT(6)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 6 +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 5 +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC81_IN_SEL 0x0000001F +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x1F +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29C) +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG82_IN_SEL (BIT(6)) +#define GPIO_SIG82_IN_SEL_M (BIT(6)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 6 +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 5 +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC82_IN_SEL 0x0000001F +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x1F +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A0) +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG83_IN_SEL (BIT(6)) +#define GPIO_SIG83_IN_SEL_M (BIT(6)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 6 +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 5 +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC83_IN_SEL 0x0000001F +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x1F +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A4) +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG84_IN_SEL (BIT(6)) +#define GPIO_SIG84_IN_SEL_M (BIT(6)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 6 +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 5 +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC84_IN_SEL 0x0000001F +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x1F +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A8) +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG85_IN_SEL (BIT(6)) +#define GPIO_SIG85_IN_SEL_M (BIT(6)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 6 +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 5 +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC85_IN_SEL 0x0000001F +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x1F +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2AC) +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG86_IN_SEL (BIT(6)) +#define GPIO_SIG86_IN_SEL_M (BIT(6)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 6 +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 5 +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC86_IN_SEL 0x0000001F +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x1F +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B0) +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG87_IN_SEL (BIT(6)) +#define GPIO_SIG87_IN_SEL_M (BIT(6)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 6 +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 5 +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC87_IN_SEL 0x0000001F +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x1F +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B4) +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG88_IN_SEL (BIT(6)) +#define GPIO_SIG88_IN_SEL_M (BIT(6)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 6 +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 5 +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC88_IN_SEL 0x0000001F +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x1F +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B8) +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG89_IN_SEL (BIT(6)) +#define GPIO_SIG89_IN_SEL_M (BIT(6)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 6 +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 5 +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC89_IN_SEL 0x0000001F +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x1F +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2BC) +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG90_IN_SEL (BIT(6)) +#define GPIO_SIG90_IN_SEL_M (BIT(6)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 6 +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 5 +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC90_IN_SEL 0x0000001F +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x1F +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C0) +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG91_IN_SEL (BIT(6)) +#define GPIO_SIG91_IN_SEL_M (BIT(6)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 6 +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 5 +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC91_IN_SEL 0x0000001F +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x1F +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C4) +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG92_IN_SEL (BIT(6)) +#define GPIO_SIG92_IN_SEL_M (BIT(6)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 6 +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 5 +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC92_IN_SEL 0x0000001F +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x1F +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C8) +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG93_IN_SEL (BIT(6)) +#define GPIO_SIG93_IN_SEL_M (BIT(6)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 6 +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 5 +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC93_IN_SEL 0x0000001F +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x1F +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2CC) +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG94_IN_SEL (BIT(6)) +#define GPIO_SIG94_IN_SEL_M (BIT(6)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 6 +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 5 +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC94_IN_SEL 0x0000001F +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x1F +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D0) +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG95_IN_SEL (BIT(6)) +#define GPIO_SIG95_IN_SEL_M (BIT(6)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 6 +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 5 +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC95_IN_SEL 0x0000001F +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x1F +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D4) +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG96_IN_SEL (BIT(6)) +#define GPIO_SIG96_IN_SEL_M (BIT(6)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 6 +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 5 +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC96_IN_SEL 0x0000001F +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x1F +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D8) +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG97_IN_SEL (BIT(6)) +#define GPIO_SIG97_IN_SEL_M (BIT(6)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 6 +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 5 +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC97_IN_SEL 0x0000001F +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x1F +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2DC) +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG98_IN_SEL (BIT(6)) +#define GPIO_SIG98_IN_SEL_M (BIT(6)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 6 +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 5 +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC98_IN_SEL 0x0000001F +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x1F +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E0) +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG99_IN_SEL (BIT(6)) +#define GPIO_SIG99_IN_SEL_M (BIT(6)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 6 +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 5 +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC99_IN_SEL 0x0000001F +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x1F +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E4) +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG100_IN_SEL (BIT(6)) +#define GPIO_SIG100_IN_SEL_M (BIT(6)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 6 +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 5 +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC100_IN_SEL 0x0000001F +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x1F +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E8) +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG101_IN_SEL (BIT(6)) +#define GPIO_SIG101_IN_SEL_M (BIT(6)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 6 +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 5 +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC101_IN_SEL 0x0000001F +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x1F +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2EC) +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG102_IN_SEL (BIT(6)) +#define GPIO_SIG102_IN_SEL_M (BIT(6)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 6 +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 5 +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC102_IN_SEL 0x0000001F +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x1F +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F0) +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG103_IN_SEL (BIT(6)) +#define GPIO_SIG103_IN_SEL_M (BIT(6)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 6 +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 5 +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC103_IN_SEL 0x0000001F +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x1F +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F4) +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG104_IN_SEL (BIT(6)) +#define GPIO_SIG104_IN_SEL_M (BIT(6)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 6 +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 5 +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC104_IN_SEL 0x0000001F +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x1F +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F8) +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG105_IN_SEL (BIT(6)) +#define GPIO_SIG105_IN_SEL_M (BIT(6)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 6 +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 5 +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC105_IN_SEL 0x0000001F +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x1F +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2FC) +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG106_IN_SEL (BIT(6)) +#define GPIO_SIG106_IN_SEL_M (BIT(6)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 6 +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 5 +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC106_IN_SEL 0x0000001F +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x1F +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG107_IN_SEL (BIT(6)) +#define GPIO_SIG107_IN_SEL_M (BIT(6)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 6 +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 5 +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC107_IN_SEL 0x0000001F +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x1F +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG108_IN_SEL (BIT(6)) +#define GPIO_SIG108_IN_SEL_M (BIT(6)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 6 +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 5 +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC108_IN_SEL 0x0000001F +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x1F +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG109_IN_SEL (BIT(6)) +#define GPIO_SIG109_IN_SEL_M (BIT(6)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 6 +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 5 +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC109_IN_SEL 0x0000001F +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x1F +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30C) +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG110_IN_SEL (BIT(6)) +#define GPIO_SIG110_IN_SEL_M (BIT(6)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 6 +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 5 +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC110_IN_SEL 0x0000001F +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x1F +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG111_IN_SEL (BIT(6)) +#define GPIO_SIG111_IN_SEL_M (BIT(6)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 6 +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 5 +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC111_IN_SEL 0x0000001F +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x1F +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG112_IN_SEL (BIT(6)) +#define GPIO_SIG112_IN_SEL_M (BIT(6)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 6 +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 5 +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC112_IN_SEL 0x0000001F +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x1F +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG113_IN_SEL (BIT(6)) +#define GPIO_SIG113_IN_SEL_M (BIT(6)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 6 +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 5 +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC113_IN_SEL 0x0000001F +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x1F +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31C) +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG114_IN_SEL (BIT(6)) +#define GPIO_SIG114_IN_SEL_M (BIT(6)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 6 +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 5 +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC114_IN_SEL 0x0000001F +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x1F +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG115_IN_SEL (BIT(6)) +#define GPIO_SIG115_IN_SEL_M (BIT(6)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 6 +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 5 +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC115_IN_SEL 0x0000001F +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x1F +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG116_IN_SEL (BIT(6)) +#define GPIO_SIG116_IN_SEL_M (BIT(6)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 6 +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 5 +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC116_IN_SEL 0x0000001F +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x1F +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG117_IN_SEL (BIT(6)) +#define GPIO_SIG117_IN_SEL_M (BIT(6)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 6 +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 5 +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC117_IN_SEL 0x0000001F +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x1F +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32C) +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG118_IN_SEL (BIT(6)) +#define GPIO_SIG118_IN_SEL_M (BIT(6)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 6 +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 5 +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC118_IN_SEL 0x0000001F +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x1F +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG119_IN_SEL (BIT(6)) +#define GPIO_SIG119_IN_SEL_M (BIT(6)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 6 +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 5 +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC119_IN_SEL 0x0000001F +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x1F +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG120_IN_SEL (BIT(6)) +#define GPIO_SIG120_IN_SEL_M (BIT(6)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 6 +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 5 +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC120_IN_SEL 0x0000001F +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x1F +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG121_IN_SEL (BIT(6)) +#define GPIO_SIG121_IN_SEL_M (BIT(6)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 6 +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 5 +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC121_IN_SEL 0x0000001F +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x1F +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33C) +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG122_IN_SEL (BIT(6)) +#define GPIO_SIG122_IN_SEL_M (BIT(6)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 6 +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 5 +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC122_IN_SEL 0x0000001F +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x1F +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG123_IN_SEL (BIT(6)) +#define GPIO_SIG123_IN_SEL_M (BIT(6)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 6 +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 5 +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC123_IN_SEL 0x0000001F +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x1F +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG124_IN_SEL (BIT(6)) +#define GPIO_SIG124_IN_SEL_M (BIT(6)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 6 +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 5 +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC124_IN_SEL 0x0000001F +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x1F +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG125_IN_SEL (BIT(6)) +#define GPIO_SIG125_IN_SEL_M (BIT(6)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 6 +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 5 +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC125_IN_SEL 0x0000001F +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x1F +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34C) +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG126_IN_SEL (BIT(6)) +#define GPIO_SIG126_IN_SEL_M (BIT(6)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 6 +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 5 +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC126_IN_SEL 0x0000001F +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x1F +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG127_IN_SEL (BIT(6)) +#define GPIO_SIG127_IN_SEL_M (BIT(6)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 6 +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 5 +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_FUNC127_IN_SEL 0x0000001F +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x1F +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 10 +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 9 +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC0_OUT_SEL 0x000000FF +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0xFF +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 10 +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 9 +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC1_OUT_SEL 0x000000FF +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0xFF +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55C) +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 10 +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 9 +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC2_OUT_SEL 0x000000FF +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0xFF +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 10 +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 9 +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC3_OUT_SEL 0x000000FF +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0xFF +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 10 +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 9 +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC4_OUT_SEL 0x000000FF +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0xFF +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 10 +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 9 +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC5_OUT_SEL 0x000000FF +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0xFF +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56C) +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 10 +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 9 +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC6_OUT_SEL 0x000000FF +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0xFF +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 10 +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 9 +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC7_OUT_SEL 0x000000FF +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0xFF +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 10 +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 9 +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC8_OUT_SEL 0x000000FF +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0xFF +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 10 +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 9 +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC9_OUT_SEL 0x000000FF +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0xFF +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57C) +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 10 +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 9 +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC10_OUT_SEL 0x000000FF +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0xFF +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 10 +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 9 +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC11_OUT_SEL 0x000000FF +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0xFF +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 10 +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 9 +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC12_OUT_SEL 0x000000FF +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0xFF +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 10 +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 9 +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC13_OUT_SEL 0x000000FF +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0xFF +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58C) +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 10 +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 9 +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC14_OUT_SEL 0x000000FF +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0xFF +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 10 +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 9 +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC15_OUT_SEL 0x000000FF +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0xFF +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 10 +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 9 +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC16_OUT_SEL 0x000000FF +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0xFF +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 10 +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 9 +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC17_OUT_SEL 0x000000FF +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0xFF +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59C) +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 10 +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 9 +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC18_OUT_SEL 0x000000FF +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0xFF +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A0) +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 10 +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 9 +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC19_OUT_SEL 0x000000FF +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0xFF +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A4) +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 10 +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 9 +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC20_OUT_SEL 0x000000FF +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0xFF +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A8) +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 10 +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 9 +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC21_OUT_SEL 0x000000FF +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0xFF +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5AC) +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 10 +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 9 +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC22_OUT_SEL 0x000000FF +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0xFF +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B0) +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 10 +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 9 +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC23_OUT_SEL 0x000000FF +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0xFF +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B4) +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 10 +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 9 +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC24_OUT_SEL 0x000000FF +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0xFF +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B8) +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 10 +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 9 +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC25_OUT_SEL 0x000000FF +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0xFF +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62C) +/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (BIT(0)) +#define GPIO_CLK_EN_V 0x1 +#define GPIO_CLK_EN_S 0 + +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) +/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */ +/*description: */ +#define GPIO_DATE 0x0FFFFFFF +#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) +#define GPIO_DATE_V 0xFFFFFFF +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_GPIO_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/gpio_sd_reg.h b/components/soc/esp32h2/include/soc/gpio_sd_reg.h new file mode 100644 index 0000000000..e1293c918d --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_sd_reg.h @@ -0,0 +1,114 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_REG_H_ +#define _SOC_GPIO_SD_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) +/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD0_PRESCALE 0x000000FF +#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S)) +#define GPIO_SD0_PRESCALE_V 0xFF +#define GPIO_SD0_PRESCALE_S 8 +/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD0_IN 0x000000FF +#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S)) +#define GPIO_SD0_IN_V 0xFF +#define GPIO_SD0_IN_S 0 + +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004) +/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD1_PRESCALE 0x000000FF +#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S)) +#define GPIO_SD1_PRESCALE_V 0xFF +#define GPIO_SD1_PRESCALE_S 8 +/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD1_IN 0x000000FF +#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S)) +#define GPIO_SD1_IN_V 0xFF +#define GPIO_SD1_IN_S 0 + +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008) +/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD2_PRESCALE 0x000000FF +#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S)) +#define GPIO_SD2_PRESCALE_V 0xFF +#define GPIO_SD2_PRESCALE_S 8 +/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD2_IN 0x000000FF +#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S)) +#define GPIO_SD2_IN_V 0xFF +#define GPIO_SD2_IN_S 0 + +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c) +/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD3_PRESCALE 0x000000FF +#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S)) +#define GPIO_SD3_PRESCALE_V 0xFF +#define GPIO_SD3_PRESCALE_S 8 +/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD3_IN 0x000000FF +#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S)) +#define GPIO_SD3_IN_V 0xFF +#define GPIO_SD3_IN_S 0 + +#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020) +/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SD_CLK_EN (BIT(31)) +#define GPIO_SD_CLK_EN_M (BIT(31)) +#define GPIO_SD_CLK_EN_V 0x1 +#define GPIO_SD_CLK_EN_S 31 + +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024) +/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (BIT(31)) +#define GPIO_SPI_SWAP_V 0x1 +#define GPIO_SPI_SWAP_S 31 +/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: */ +#define GPIO_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_M (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_V 0x1 +#define GPIO_FUNCTION_CLK_EN_S 30 + +#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028) +/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006230 ; */ +/*description: */ +#define GPIO_SD_DATE 0x0FFFFFFF +#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S)) +#define GPIO_SD_DATE_V 0xFFFFFFF +#define GPIO_SD_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_GPIO_SD_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/gpio_sd_struct.h b/components/soc/esp32h2/include/soc/gpio_sd_struct.h new file mode 100644 index 0000000000..cc73cebd03 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_sd_struct.h @@ -0,0 +1,61 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_STRUCT_H_ +#define _SOC_GPIO_SD_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t duty: 8; + uint32_t prescale: 8; + uint32_t reserved16: 16; + }; + uint32_t val; + } channel[4]; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + uint32_t reserved_1c; + union { + struct { + uint32_t reserved0: 31; + uint32_t clk_en: 1; + }; + uint32_t val; + } cg; + union { + struct { + uint32_t reserved0: 30; + uint32_t function_clk_en: 1; + uint32_t spi_swap: 1; + }; + uint32_t val; + } misc; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } version; +} gpio_sd_dev_t; +extern gpio_sd_dev_t SIGMADELTA; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/gpio_sig_map.h b/components/soc/esp32h2/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..45be68b3e5 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_sig_map.h @@ -0,0 +1,184 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SIG_MAP_H_ +#define _SOC_GPIO_SIG_MAP_H_ + +#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX +#define SPIQ_IN_IDX 0 +#define SPIQ_OUT_IDX 0 +#define SPID_IN_IDX 1 +#define SPID_OUT_IDX 1 +#define SPIHD_IN_IDX 2 +#define SPIHD_OUT_IDX 2 +#define SPIWP_IN_IDX 3 +#define SPIWP_OUT_IDX 3 +#define SPICLK_OUT_IDX 4 +#define SPICS0_OUT_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define GPIO_BT_PRIORITY_IDX 18 +#define GPIO_WLAN_PRIO_IDX 18 +#define GPIO_BT_ACTIVE_IDX 19 +#define GPIO_WLAN_ACTIVE_IDX 19 +#define BB_DIAG0_IDX 20 +#define BB_DIAG1_IDX 21 +#define BB_DIAG2_IDX 22 +#define BB_DIAG3_IDX 23 +#define BB_DIAG4_IDX 24 +#define BB_DIAG5_IDX 25 +#define BB_DIAG6_IDX 26 +#define BB_DIAG7_IDX 27 +#define BB_DIAG8_IDX 28 +#define BB_DIAG9_IDX 29 +#define BB_DIAG10_IDX 30 +#define BB_DIAG11_IDX 31 +#define BB_DIAG12_IDX 32 +#define BB_DIAG13_IDX 33 +#define BB_DIAG14_IDX 34 +#define BB_DIAG15_IDX 35 +#define BB_DIAG16_IDX 36 +#define BB_DIAG17_IDX 37 +#define BB_DIAG18_IDX 38 +#define BB_DIAG19_IDX 39 +#define USB_EXTPHY_VP_IDX 40 +#define USB_EXTPHY_OEN_IDX 40 +#define USB_EXTPHY_VM_IDX 41 +#define USB_EXTPHY_SPEED_IDX 41 +#define USB_EXTPHY_RCV_IDX 42 +#define USB_EXTPHY_VPO_IDX 42 +#define USB_EXTPHY_VMO_IDX 43 +#define USB_EXTPHY_SUSPND_IDX 44 +#define EXT_ADC_START_IDX 45 +#define LEDC_LS_SIG_OUT0_IDX 45 +#define LEDC_LS_SIG_OUT1_IDX 46 +#define LEDC_LS_SIG_OUT2_IDX 47 +#define LEDC_LS_SIG_OUT3_IDX 48 +#define LEDC_LS_SIG_OUT4_IDX 49 +#define LEDC_LS_SIG_OUT5_IDX 50 +#define RMT_SIG_IN0_IDX 51 +#define RMT_SIG_OUT0_IDX 51 +#define RMT_SIG_IN1_IDX 52 +#define RMT_SIG_OUT1_IDX 52 +#define I2CEXT0_SCL_IN_IDX 53 +#define I2CEXT0_SCL_OUT_IDX 53 +#define I2CEXT0_SDA_IN_IDX 54 +#define I2CEXT0_SDA_OUT_IDX 54 +#define GPIO_SD0_OUT_IDX 55 +#define GPIO_SD1_OUT_IDX 56 +#define GPIO_SD2_OUT_IDX 57 +#define GPIO_SD3_OUT_IDX 58 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define FSPICS1_OUT_IDX 69 +#define FSPICS2_OUT_IDX 70 +#define FSPICS3_OUT_IDX 71 +#define FSPICS4_OUT_IDX 72 +#define FSPICS5_OUT_IDX 73 +#define TWAI_RX_IDX 74 +#define TWAI_TX_IDX 74 +#define TWAI_BUS_OFF_ON_IDX 75 +#define TWAI_CLKOUT_IDX 76 +#define PCMFSYNC_IN_IDX 77 +#define BT_AUDIO0_IRQ_IDX 77 +#define PCMCLK_IN_IDX 78 +#define BT_AUDIO1_IRQ_IDX 78 +#define PCMDIN_IDX 79 +#define BT_AUDIO2_IRQ_IDX 79 +#define RW_WAKEUP_REQ_IDX 80 +#define BLE_AUDIO0_IRQ_IDX 80 +#define BLE_AUDIO1_IRQ_IDX 81 +#define BLE_AUDIO2_IRQ_IDX 82 +#define PCMFSYNC_OUT_IDX 83 +#define PCMCLK_OUT_IDX 84 +#define PCMDOUT_IDX 85 +#define BLE_AUDIO_SYNC0_P_IDX 86 +#define BLE_AUDIO_SYNC1_P_IDX 87 +#define BLE_AUDIO_SYNC2_P_IDX 88 +#define ANT_SEL0_IDX 89 +#define ANT_SEL1_IDX 90 +#define ANT_SEL2_IDX 91 +#define ANT_SEL3_IDX 92 +#define ANT_SEL4_IDX 93 +#define ANT_SEL5_IDX 94 +#define ANT_SEL6_IDX 95 +#define ANT_SEL7_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define SYNCERR_IDX 101 +#define SYNCFOUND_FLAG_IDX 102 +#define EVT_CNTL_IMMEDIATE_ABORT_IDX 103 +#define LINKLBL_IDX 104 +#define DATA_EN_IDX 105 +#define DATA_IDX 106 +#define PKT_TX_ON_IDX 107 +#define PKT_RX_ON_IDX 108 +#define RW_TX_ON_IDX 109 +#define RW_RX_ON_IDX 110 +#define EVT_REQ_P_IDX 111 +#define EVT_STOP_P_IDX 112 +#define BT_MODE_ON_IDX 113 +#define GPIO_LC_DIAG0_IDX 114 +#define GPIO_LC_DIAG1_IDX 115 +#define GPIO_LC_DIAG2_IDX 116 +#define CH_IDX_IDX 117 +#define RX_WINDOW_IDX 118 +#define UPDATE_RX_IDX 119 +#define RX_STATUS_IDX 120 +#define CLK_GPIO_IDX 121 +#define NBT_BLE_IDX 122 +#define CLK_OUT_OUT1_IDX 123 +#define CLK_OUT_OUT2_IDX 124 +#define CLK_OUT_OUT3_IDX 125 +#define SPICS1_OUT_IDX 126 +#define SIG_GPIO_OUT_IDX 128 +#define GPIO_MAP_DATE_IDX 0x2006130 +#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32h2/include/soc/gpio_struct.h b/components/soc/esp32h2/include/soc/gpio_struct.h new file mode 100644 index 0000000000..f260adbd2a --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_struct.h @@ -0,0 +1,437 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_STRUCT_H_ +#define _SOC_GPIO_STRUCT_H_ +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t bt_select; /**/ + union { + struct { + uint32_t data: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } out; + union { + struct { + uint32_t out_w1ts: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } out_w1ts; + union { + struct { + uint32_t out_w1tc: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } out_w1tc; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + union { + struct { + uint32_t sel: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } sdio_select; + union { + struct { + uint32_t data: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } enable; + union { + struct { + uint32_t enable_w1ts:26; + uint32_t reserved26: 6; + }; + uint32_t val; + } enable_w1ts; + union { + struct { + uint32_t enable_w1tc:26; + uint32_t reserved26: 6; + }; + uint32_t val; + } enable_w1tc; + uint32_t reserved_2c; + uint32_t reserved_30; + uint32_t reserved_34; + union { + struct { + uint32_t strapping: 16; + uint32_t reserved16:16; + }; + uint32_t val; + } strap; + union { + struct { + uint32_t data: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } in; + uint32_t reserved_40; + union { + struct { + uint32_t intr_st: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } status; + union { + struct { + uint32_t status_w1ts:26; + uint32_t reserved26: 6; + }; + uint32_t val; + } status_w1ts; + union { + struct { + uint32_t status_w1tc:26; + uint32_t reserved26: 6; + }; + uint32_t val; + } status_w1tc; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + union { + struct { + uint32_t intr: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } pcpu_int; + union { + struct { + uint32_t intr: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } pcpu_nmi_int; + union { + struct { + uint32_t intr: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } cpusdio_int; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + union { + struct { + uint32_t sync2_bypass: 2; + uint32_t pad_driver: 1; + uint32_t sync1_bypass: 2; + uint32_t reserved5: 2; + uint32_t int_type: 3; + uint32_t wakeup_enable: 1; + uint32_t config: 2; + uint32_t int_ena: 5; + uint32_t reserved18: 14; + }; + uint32_t val; + } pin[26]; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + union { + struct { + uint32_t intr_st_next: 26; + uint32_t reserved26: 6; + }; + uint32_t val; + } status_next; + uint32_t reserved_150; + union { + struct { + uint32_t func_sel: 5; + uint32_t sig_in_inv: 1; + uint32_t sig_in_sel: 1; + uint32_t reserved7: 25; + }; + uint32_t val; + } func_in_sel_cfg[128]; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + union { + struct { + uint32_t func_sel: 8; + uint32_t inv_sel: 1; + uint32_t oen_sel: 1; + uint32_t oen_inv_sel: 1; + uint32_t reserved11: 21; + }; + uint32_t val; + } func_out_sel_cfg[26]; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } clock_gate; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} gpio_dev_t; +extern gpio_dev_t GPIO; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/hwcrypto_reg.h b/components/soc/esp32h2/include/soc/hwcrypto_reg.h new file mode 100644 index 0000000000..6844627388 --- /dev/null +++ b/components/soc/esp32h2/include/soc/hwcrypto_reg.h @@ -0,0 +1,186 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __HWCRYPTO_REG_H__ +#define __HWCRYPTO_REG_H__ + +#include "soc.h" + +/* registers for RSA acceleration via Multiple Precision Integer ops */ +#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) +/* RB & Z use the same memory block, depending on phase of operation */ +#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) +#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) +#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400) +#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600) + +/* Configuration registers */ +#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800) +#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804) +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) + +/* Initialization registers */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) + +/* Calculation start registers */ +#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) +#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810) +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) + +/* Interrupt registers */ +#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818) +#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C) +#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x82C) + +#define SHA_MODE_SHA1 0 +#define SHA_MODE_SHA224 1 +#define SHA_MODE_SHA256 2 + +/* SHA acceleration registers */ +#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00) +#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C) +#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10) +#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14) +#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18) +#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C) +#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20) +#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24) +#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28) +#define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C) + +#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40) +#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80) + +/* AES Block operation modes */ +#define AES_BLOCK_MODE_ECB 0 +#define AES_BLOCK_MODE_CBC 1 +#define AES_BLOCK_MODE_OFB 2 +#define AES_BLOCK_MODE_CTR 3 +#define AES_BLOCK_MODE_CFB8 4 +#define AES_BLOCK_MODE_CFB128 5 + +/* AES Block operation modes (used with DMA) */ +#define AES_BLOCK_MODE_ECB 0 +#define AES_BLOCK_MODE_CBC 1 +#define AES_BLOCK_MODE_OFB 2 +#define AES_BLOCK_MODE_CTR 3 +#define AES_BLOCK_MODE_CFB8 4 +#define AES_BLOCK_MODE_CFB128 5 + +/* AES acceleration registers */ +#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40) +#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44) +#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48) +#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c) +#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) +#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) +#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) +#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) +#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) +#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) +#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) +#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) +#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) +#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) + +#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) +#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) +#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) +#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) +#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) +#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) +#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) + +#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00) +#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20) +#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) +#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) +#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60) +#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) +#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) + +#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) +#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) +#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) + +/* AES_STATE_REG values */ +#define AES_STATE_IDLE 0 +#define AES_STATE_BUSY 1 +#define AES_STATE_DONE 2 + +/* HMAC Module */ +#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) +#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44) +#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48) +#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c) +#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50) +#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54) +#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58) +#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c) +#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60) +#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64) +#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68) +#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c) + +#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80) +#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0) +#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0) +#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4) + +#define HMAC_SOFT_JTAG_CTRL_REG ((DR_REG_HMAC_BASE) + 0xF8) +#define HMAC_WR_JTAG_REG ((DR_REG_HMAC_BASE) + 0xFC) + +#define HMAC_DATE_REG ((DR_REG_HMAC_BASE) + 0xF8) + + +/* AES-XTS registers */ +#define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00) +#define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40) +#define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44) +#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48) + +#define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C) +#define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50) +#define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54) +#define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58) +#define AES_XTS_DATE_REG ((DR_REG_AES_XTS_BASE) + 0x5C) + +/* Digital Signature registers and memory blocks */ +#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) +#define DS_C_Y_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) +#define DS_C_M_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 ) +#define DS_C_RB_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 ) +#define DS_C_BOX_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 ) +#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 ) +#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 ) +#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 ) + +#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00) +#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04) +#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08) + +#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C) +#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10) +#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14) + +#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0) +#define DS_QUERY_CHECK_INVALID_PADDING (1<<1) + +#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20) + +#endif diff --git a/components/soc/esp32h2/include/soc/i2c_reg.h b/components/soc/esp32h2/include/soc/i2c_reg.h new file mode 100644 index 0000000000..6a45d00827 --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2c_reg.h @@ -0,0 +1,1062 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_REG_H_ +#define _SOC_I2C_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SCL_LOW_PERIOD 0x000001FF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x1FF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) +/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_V 0x1 +#define I2C_ADDR_BROADCASTING_EN_S 14 +/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_V 0x1 +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (BIT(11)) +#define I2C_CONF_UPGATE_V 0x1 +#define I2C_CONF_UPGATE_S 11 +/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (BIT(10)) +#define I2C_FSM_RST_V 0x1 +#define I2C_FSM_RST_S 10 +/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (BIT(9)) +#define I2C_ARBITRATION_EN_V 0x1 +#define I2C_ARBITRATION_EN_S 9 +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 +/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 +/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_V 0x1 +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: .*/ +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 +/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ +/*description: .*/ +#define I2C_STRETCH_CAUSE 0x00000003 +#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) +#define I2C_STRETCH_CAUSE_V 0x3 +#define I2C_STRETCH_CAUSE_S 14 +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 +/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (BIT(0)) +#define I2C_RESP_REC_V 0x1 +#define I2C_RESP_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) +/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (BIT(5)) +#define I2C_TIME_OUT_EN_V 0x1 +#define I2C_TIME_OUT_EN_S 5 +/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ +/*description: .*/ +#define I2C_TIME_OUT_REG 0x0000001F +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S)) +#define I2C_TIME_OUT_REG_V 0x1F +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) +/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_RW_POINT 0x000000FF +#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) +#define I2C_SLAVE_RW_POINT_V 0xFF +#define I2C_SLAVE_RW_POINT_S 22 +/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WADDR 0x0000001F +#define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) +#define I2C_TXFIFO_WADDR_V 0x1F +#define I2C_TXFIFO_WADDR_S 15 +/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_RADDR 0x0000001F +#define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) +#define I2C_TXFIFO_RADDR_V 0x1F +#define I2C_TXFIFO_RADDR_S 10 +/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WADDR 0x0000001F +#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) +#define I2C_RXFIFO_WADDR_V 0x1F +#define I2C_RXFIFO_WADDR_S 5 +/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_RADDR 0x0000001F +#define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) +#define I2C_RXFIFO_RADDR_V 0x1F +#define I2C_RXFIFO_RADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) +/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (BIT(14)) +#define I2C_FIFO_PRT_EN_V 0x1 +#define I2C_FIFO_PRT_EN_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 +/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_THRHD 0x0000001F +#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) +#define I2C_TXFIFO_WM_THRHD_V 0x1F +#define I2C_TXFIFO_WM_THRHD_S 5 +/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_THRHD 0x0000001F +#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) +#define I2C_RXFIFO_WM_THRHD_V 0x1F +#define I2C_RXFIFO_WM_THRHD_S 0 + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: .*/ +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) +/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_V 0x1 +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (BIT(15)) +#define I2C_DET_START_INT_RAW_V 0x1 +#define I2C_DET_START_INT_RAW_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (BIT(10)) +#define I2C_NACK_INT_RAW_V 0x1 +#define I2C_NACK_INT_RAW_S 10 +/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 +/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 +/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 +/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_V 0x1 +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_V 0x1 +#define I2C_RXFIFO_WM_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) +/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_V 0x1 +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (BIT(15)) +#define I2C_DET_START_INT_CLR_V 0x1 +#define I2C_DET_START_INT_CLR_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (BIT(10)) +#define I2C_NACK_INT_CLR_V 0x1 +#define I2C_NACK_INT_CLR_S 10 +/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 +/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 +/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 +/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_V 0x1 +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_V 0x1 +#define I2C_RXFIFO_WM_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) +/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_V 0x1 +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (BIT(15)) +#define I2C_DET_START_INT_ENA_V 0x1 +#define I2C_DET_START_INT_ENA_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (BIT(10)) +#define I2C_NACK_INT_ENA_V 0x1 +#define I2C_NACK_INT_ENA_S 10 +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_V 0x1 +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_V 0x1 +#define I2C_RXFIFO_WM_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) +/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_V 0x1 +#define I2C_GENERAL_CALL_INT_ST_S 17 +/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (BIT(15)) +#define I2C_DET_START_INT_ST_V 0x1 +#define I2C_DET_START_INT_ST_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_ST_TO_INT_ST_S 13 +/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_V 0x1 +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_V 0x1 +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (BIT(10)) +#define I2C_NACK_INT_ST_V 0x1 +#define I2C_NACK_INT_ST_S 10 +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_V 0x1 +#define I2C_TXFIFO_WM_INT_ST_S 1 +/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_V 0x1 +#define I2C_RXFIFO_WM_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SDA_HOLD_TIME 0x000001FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x1FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SDA_SAMPLE_TIME 0x000001FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x1FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) +/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ +/*description: .*/ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F +#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SCL_HIGH_PERIOD 0x000001FF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x1FF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_START_HOLD_TIME 0x000001FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x1FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x1FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (BIT(9)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 9 +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (BIT(8)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 8 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: .*/ +#define I2C_SDA_FILTER_THRES 0x0000000F +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0xF +#define I2C_SDA_FILTER_THRES_S 4 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: .*/ +#define I2C_SCL_FILTER_THRES 0x0000000F +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0xF +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) +/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (BIT(21)) +#define I2C_SCLK_ACTIVE_V 0x1 +#define I2C_SCLK_ACTIVE_S 21 +/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (BIT(20)) +#define I2C_SCLK_SEL_V 0x1 +#define I2C_SCLK_SEL_S 20 +/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_SCLK_DIV_B 0x0000003F +#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) +#define I2C_SCLK_DIV_B_V 0x3F +#define I2C_SCLK_DIV_B_S 14 +/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_SCLK_DIV_A 0x0000003F +#define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) +#define I2C_SCLK_DIV_A_V 0x3F +#define I2C_SCLK_DIV_A_S 8 +/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: .*/ +#define I2C_SCLK_DIV_NUM 0x000000FF +#define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) +#define I2C_SCLK_DIV_NUM_V 0xFF +#define I2C_SCLK_DIV_NUM_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) +/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) +/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) +/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) +/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) +/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) +/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) +/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) +/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) +/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ +/*description: no more than 23.*/ +#define I2C_SCL_ST_TO_REG 0x0000001F +#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) +#define I2C_SCL_ST_TO_REG_V 0x1F +#define I2C_SCL_ST_TO_REG_S 0 + +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) +/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ +/*description: no more than 23.*/ +#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F +#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) +#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F +#define I2C_SCL_MAIN_ST_TO_REG_S 0 + +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) +/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (BIT(7)) +#define I2C_SDA_PD_EN_V 0x1 +#define I2C_SDA_PD_EN_S 7 +/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (BIT(6)) +#define I2C_SCL_PD_EN_V 0x1 +#define I2C_SCL_PD_EN_S 6 +/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_SCL_RST_SLV_NUM 0x0000001F +#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) +#define I2C_SCL_RST_SLV_NUM_V 0x1F +#define I2C_SCL_RST_SLV_NUM_S 1 +/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (BIT(0)) +#define I2C_SCL_RST_SLV_EN_V 0x1 +#define I2C_SCL_RST_SLV_EN_S 0 + +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) +/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 +/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: .*/ +#define I2C_STRETCH_PROTECT_NUM 0x000003FF +#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) +#define I2C_STRETCH_PROTECT_NUM_V 0x3FF +#define I2C_STRETCH_PROTECT_NUM_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ +/*description: .*/ +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) + +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_I2C_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/i2c_struct.h b/components/soc/esp32h2/include/soc/i2c_struct.h new file mode 100644 index 0000000000..22c6c47041 --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2c_struct.h @@ -0,0 +1,407 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_STRUCT_H_ +#define _SOC_I2C_STRUCT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +typedef volatile struct { + union { + struct { + uint32_t period : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } scl_low_period; + union { + struct { + uint32_t sda_force_out : 1; + uint32_t scl_force_out : 1; + uint32_t sample_scl_level : 1; + uint32_t rx_full_ack_level : 1; + uint32_t ms_mode : 1; + uint32_t trans_start : 1; + uint32_t tx_lsb_first : 1; + uint32_t rx_lsb_first : 1; + uint32_t clk_en : 1; + uint32_t arbitration_en : 1; + uint32_t fsm_rst : 1; + uint32_t conf_upgate : 1; + uint32_t slv_tx_auto_start_en : 1; + uint32_t addr_10bit_rw_check_en : 1; + uint32_t addr_broadcasting_en : 1; + uint32_t reserved15 : 17; + }; + uint32_t val; + } ctr; + union { + struct { + uint32_t resp_rec : 1; + uint32_t slave_rw : 1; + uint32_t reserved2 : 1; + uint32_t arb_lost : 1; + uint32_t bus_busy : 1; + uint32_t slave_addressed : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t rx_fifo_cnt : 6; + uint32_t stretch_cause : 2; + uint32_t reserved16 : 2; + uint32_t tx_fifo_cnt : 6; + uint32_t scl_main_state_last : 3; + uint32_t reserved27 : 1; + uint32_t scl_state_last : 3; + uint32_t reserved31 : 1; + }; + uint32_t val; + } sr; + union { + struct { + uint32_t time_out_value : 5; + uint32_t time_out_en : 1; + uint32_t reserved6 : 26; + }; + uint32_t val; + } timeout; + union { + struct { + uint32_t addr : 15; + uint32_t reserved15 : 16; + uint32_t en_10bit : 1; + }; + uint32_t val; + } slave_addr; + union { + struct { + uint32_t rx_fifo_raddr : 5; + uint32_t rx_fifo_waddr : 5; + uint32_t tx_fifo_raddr : 5; + uint32_t tx_fifo_waddr : 5; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t slave_rw_point : 8; + uint32_t reserved30 : 2; + }; + uint32_t val; + } fifo_st; + union { + struct { + uint32_t rx_fifo_wm_thrhd : 5; + uint32_t tx_fifo_wm_thrhd : 5; + uint32_t nonfifo_en : 1; + uint32_t fifo_addr_cfg_en : 1; + uint32_t rx_fifo_rst : 1; + uint32_t tx_fifo_rst : 1; + uint32_t fifo_prt_en : 1; + uint32_t reserved15 : 5; + uint32_t reserved20 : 6; + uint32_t reserved26 : 1; + uint32_t reserved27 : 5; + }; + uint32_t val; + } fifo_conf; + union { + struct { + uint32_t data : 8; + uint32_t reserved8 : 24; + }; + uint32_t val; + } fifo_data; + union { + struct { + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; + }; + uint32_t val; + } int_status; + union { + struct { + uint32_t time : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } sda_hold; + union { + struct { + uint32_t time : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } sda_sample; + union { + struct { + uint32_t period : 9; + uint32_t scl_wait_high_period : 7; + uint32_t reserved16 : 16; + }; + uint32_t val; + } scl_high_period; + uint32_t reserved_3c; + union { + struct { + uint32_t time : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } scl_start_hold; + union { + struct { + uint32_t time : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } scl_rstart_setup; + union { + struct { + uint32_t time : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } scl_stop_hold; + union { + struct { + uint32_t time : 9; + uint32_t reserved9 : 23; + }; + uint32_t val; + } scl_stop_setup; + union { + struct { + uint32_t scl_thres : 4; + uint32_t sda_thres : 4; + uint32_t scl_en : 1; + uint32_t sda_en : 1; + uint32_t reserved10 : 22; + }; + uint32_t val; + } filter_cfg; + union { + struct { + uint32_t sclk_div_num : 8; + uint32_t sclk_div_a : 6; + uint32_t sclk_div_b : 6; + uint32_t sclk_sel : 1; + uint32_t sclk_active : 1; + uint32_t reserved22 : 10; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t command0 : 14; + uint32_t reserved14 : 17; + uint32_t command0_done : 1; + }; + uint32_t val; + } command[8]; + union { + struct { + uint32_t scl_st_to : 5; /*no more than 23*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } scl_st_time_out; + union { + struct { + uint32_t scl_main_st_to : 5; /*no more than 23*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } scl_main_st_time_out; + union { + struct { + uint32_t scl_rst_slv_en : 1; + uint32_t scl_rst_slv_num : 5; + uint32_t scl_pd_en : 1; + uint32_t sda_pd_en : 1; + uint32_t reserved8 : 24; + }; + uint32_t val; + } scl_sp_conf; + union { + struct { + uint32_t stretch_protect_num : 10; + uint32_t slave_scl_stretch_en : 1; + uint32_t slave_scl_stretch_clr : 1; + uint32_t slave_byte_ack_ctl_en : 1; + uint32_t slave_byte_ack_level : 1; + uint32_t reserved14 : 18; + }; + uint32_t val; + } scl_stretch_conf; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t date; + uint32_t reserved_fc; + uint32_t txfifo_start_addr; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t rxfifo_start_addr; +} i2c_dev_t; +extern i2c_dev_t I2C0; +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_I2C_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/i2s_reg.h b/components/soc/esp32h2/include/soc/i2s_reg.h new file mode 100644 index 0000000000..a5c4ed3e35 --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2s_reg.h @@ -0,0 +1,1051 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_REG_H_ +#define _SOC_I2S_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) +/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_V 0x1 +#define I2S_TX_HUNG_INT_RAW_S 3 +/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_V 0x1 +#define I2S_RX_HUNG_INT_RAW_S 2 +/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (BIT(1)) +#define I2S_TX_DONE_INT_RAW_V 0x1 +#define I2S_TX_DONE_INT_RAW_S 1 +/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (BIT(0)) +#define I2S_RX_DONE_INT_RAW_V 0x1 +#define I2S_RX_DONE_INT_RAW_S 0 + +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) +/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (BIT(3)) +#define I2S_TX_HUNG_INT_ST_V 0x1 +#define I2S_TX_HUNG_INT_ST_S 3 +/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (BIT(2)) +#define I2S_RX_HUNG_INT_ST_V 0x1 +#define I2S_RX_HUNG_INT_ST_S 2 +/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (BIT(1)) +#define I2S_TX_DONE_INT_ST_V 0x1 +#define I2S_TX_DONE_INT_ST_S 1 +/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (BIT(0)) +#define I2S_RX_DONE_INT_ST_V 0x1 +#define I2S_RX_DONE_INT_ST_S 0 + +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) +/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_V 0x1 +#define I2S_TX_HUNG_INT_ENA_S 3 +/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_V 0x1 +#define I2S_RX_HUNG_INT_ENA_S 2 +/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (BIT(1)) +#define I2S_TX_DONE_INT_ENA_V 0x1 +#define I2S_TX_DONE_INT_ENA_S 1 +/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (BIT(0)) +#define I2S_RX_DONE_INT_ENA_V 0x1 +#define I2S_RX_DONE_INT_ENA_S 0 + +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) +/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_V 0x1 +#define I2S_TX_HUNG_INT_CLR_S 3 +/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_V 0x1 +#define I2S_RX_HUNG_INT_CLR_S 2 +/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (BIT(1)) +#define I2S_TX_DONE_INT_CLR_V 0x1 +#define I2S_TX_DONE_INT_CLR_S 1 +/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (BIT(0)) +#define I2S_RX_DONE_INT_CLR_V 0x1 +#define I2S_RX_DONE_INT_CLR_S 0 + +#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) +/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (BIT(20)) +#define I2S_RX_PDM_EN_V 0x1 +#define I2S_RX_PDM_EN_S 20 +/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (BIT(19)) +#define I2S_RX_TDM_EN_V 0x1 +#define I2S_RX_TDM_EN_S 19 +/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: I2S Rx bit endian. 1:small endian the LSB is received first. + 0:big endian the MSB is received first.*/ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (BIT(18)) +#define I2S_RX_BIT_ORDER_V 0x1 +#define I2S_RX_BIT_ORDER_S 18 +/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: 0: WS should be 0 when receiving left channel data and WS is + 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (BIT(17)) +#define I2S_RX_WS_IDLE_POL_V 0x1 +#define I2S_RX_WS_IDLE_POL_S 17 +/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (BIT(16)) +#define I2S_RX_24_FILL_EN_V 0x1 +#define I2S_RX_24_FILL_EN_S 16 +/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (BIT(15)) +#define I2S_RX_LEFT_ALIGN_V 0x1 +#define I2S_RX_LEFT_ALIGN_S 15 +/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */ +/*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop + when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ +#define I2S_RX_STOP_MODE 0x00000003 +#define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S)) +#define I2S_RX_STOP_MODE_V 0x3 +#define I2S_RX_STOP_MODE_S 13 +/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to bypass Compress/Decompress module for received data.*/ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (BIT(12)) +#define I2S_RX_PCM_BYPASS_V 0x1 +#define I2S_RX_PCM_BYPASS_S 12 +/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */ +/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law + decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ +#define I2S_RX_PCM_CONF 0x00000003 +#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) +#define I2S_RX_PCM_CONF_V 0x3 +#define I2S_RX_PCM_CONF_S 10 +/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: 1: The first channel data value is valid in I2S RX mono mode. + 0: The second channel data value is valid in I2S RX mono mode.*/ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (BIT(9)) +#define I2S_RX_MONO_FST_VLD_V 0x1 +#define I2S_RX_MONO_FST_VLD_S 9 +/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set 1 to update I2S RX registers from APB clock domain to I2S + RX clock domain. This bit will be cleared by hardware after update register done.*/ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (BIT(8)) +#define I2S_RX_UPDATE_V 0x1 +#define I2S_RX_UPDATE_S 8 +/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: I2S Rx byte endian 1: low addr value to high addr. 0: low addr + with low addr value.*/ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (BIT(7)) +#define I2S_RX_BIG_ENDIAN_V 0x1 +#define I2S_RX_BIG_ENDIAN_S 7 +/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable receiver in mono mode*/ +#define I2S_RX_MONO (BIT(5)) +#define I2S_RX_MONO_M (BIT(5)) +#define I2S_RX_MONO_V 0x1 +#define I2S_RX_MONO_S 5 +/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable slave receiver mode*/ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (BIT(3)) +#define I2S_RX_SLAVE_MOD_V 0x1 +#define I2S_RX_SLAVE_MOD_S 3 +/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to start receiving data*/ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (BIT(2)) +#define I2S_RX_START_V 0x1 +#define I2S_RX_START_S 2 +/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Rx AFIFO*/ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (BIT(1)) +#define I2S_RX_FIFO_RESET_V 0x1 +#define I2S_RX_FIFO_RESET_S 1 +/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset receiver*/ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (BIT(0)) +#define I2S_RX_RESET_V 0x1 +#define I2S_RX_RESET_S 0 + +#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0024) +/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable signal loop back mode with transmitter module and receiver + module sharing the same WS and BCK signals.*/ +#define I2S_SIG_LOOPBACK (BIT(27)) +#define I2S_SIG_LOOPBACK_M (BIT(27)) +#define I2S_SIG_LOOPBACK_V 0x1 +#define I2S_SIG_LOOPBACK_S 27 +/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: I2S transmitter channel mode configuration bits.*/ +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) +#define I2S_TX_CHAN_MOD_V 0x7 +#define I2S_TX_CHAN_MOD_S 24 +/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (BIT(20)) +#define I2S_TX_PDM_EN_V 0x1 +#define I2S_TX_PDM_EN_S 20 +/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (BIT(19)) +#define I2S_TX_TDM_EN_V 0x1 +#define I2S_TX_TDM_EN_S 19 +/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big + endian the MSB is sent first.*/ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (BIT(18)) +#define I2S_TX_BIT_ORDER_V 0x1 +#define I2S_TX_BIT_ORDER_S 18 +/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: 0: WS should be 0 when sending left channel data and WS is 1in + right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (BIT(17)) +#define I2S_TX_WS_IDLE_POL_V 0x1 +#define I2S_TX_WS_IDLE_POL_S 17 +/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (BIT(16)) +#define I2S_TX_24_FILL_EN_V 0x1 +#define I2S_TX_24_FILL_EN_S 16 +/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (BIT(15)) +#define I2S_TX_LEFT_ALIGN_V 0x1 +#define I2S_TX_LEFT_ALIGN_S 15 +/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to stop disable output BCK signal and WS signal + when tx FIFO is emtpy*/ +#define I2S_TX_STOP_EN (BIT(13)) +#define I2S_TX_STOP_EN_M (BIT(13)) +#define I2S_TX_STOP_EN_V 0x1 +#define I2S_TX_STOP_EN_S 13 +/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (BIT(12)) +#define I2S_TX_PCM_BYPASS_V 0x1 +#define I2S_TX_PCM_BYPASS_S 12 +/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law + decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ +#define I2S_TX_PCM_CONF 0x00000003 +#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) +#define I2S_TX_PCM_CONF_V 0x3 +#define I2S_TX_PCM_CONF_S 10 +/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: 1: The first channel data value is valid in I2S TX mono mode. + 0: The second channel data value is valid in I2S TX mono mode.*/ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (BIT(9)) +#define I2S_TX_MONO_FST_VLD_V 0x1 +#define I2S_TX_MONO_FST_VLD_S 9 +/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set 1 to update I2S TX registers from APB clock domain to I2S + TX clock domain. This bit will be cleared by hardware after update register done.*/ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (BIT(8)) +#define I2S_TX_UPDATE_V 0x1 +#define I2S_TX_UPDATE_S 8 +/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: I2S Tx byte endian 1: low addr value to high addr. 0: low addr + with low addr value.*/ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (BIT(7)) +#define I2S_TX_BIG_ENDIAN_V 0x1 +#define I2S_TX_BIG_ENDIAN_S 7 +/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: The value of Left channel data is equal to the value of right + channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ +#define I2S_TX_CHAN_EQUAL (BIT(6)) +#define I2S_TX_CHAN_EQUAL_M (BIT(6)) +#define I2S_TX_CHAN_EQUAL_V 0x1 +#define I2S_TX_CHAN_EQUAL_S 6 +/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable transmitter in mono mode*/ +#define I2S_TX_MONO (BIT(5)) +#define I2S_TX_MONO_M (BIT(5)) +#define I2S_TX_MONO_V 0x1 +#define I2S_TX_MONO_S 5 +/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable slave transmitter mode*/ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (BIT(3)) +#define I2S_TX_SLAVE_MOD_V 0x1 +#define I2S_TX_SLAVE_MOD_S 3 +/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to start transmitting data*/ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (BIT(2)) +#define I2S_TX_START_V 0x1 +#define I2S_TX_START_S 2 +/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Tx AFIFO*/ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (BIT(1)) +#define I2S_TX_FIFO_RESET_V 0x1 +#define I2S_TX_FIFO_RESET_S 1 +/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset transmitter*/ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (BIT(0)) +#define I2S_TX_RESET_V 0x1 +#define I2S_TX_RESET_S 0 + +#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0028) +/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to enable receiver in Phillips standard mode*/ +#define I2S_RX_MSB_SHIFT (BIT(29)) +#define I2S_RX_MSB_SHIFT_M (BIT(29)) +#define I2S_RX_MSB_SHIFT_V 0x1 +#define I2S_RX_MSB_SHIFT_S 29 +/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ +/*description: The Rx bit number for each channel minus 1in TDM mode.*/ +#define I2S_RX_TDM_CHAN_BITS 0x0000001F +#define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S)) +#define I2S_RX_TDM_CHAN_BITS_V 0x1F +#define I2S_RX_TDM_CHAN_BITS_S 24 +/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ +/*description: I2S Rx half sample bits -1.*/ +#define I2S_RX_HALF_SAMPLE_BITS 0x0000003F +#define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S)) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x3F +#define I2S_RX_HALF_SAMPLE_BITS_S 18 +/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ +/*description: Set the bits to configure bit length of I2S receiver channel.*/ +#define I2S_RX_BITS_MOD 0x0000001F +#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) +#define I2S_RX_BITS_MOD_V 0x1F +#define I2S_RX_BITS_MOD_S 13 +/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ +/*description: Bit clock configuration bits in receiver mode.*/ +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) +#define I2S_RX_BCK_DIV_NUM_V 0x3F +#define I2S_RX_BCK_DIV_NUM_S 7 +/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ +#define I2S_RX_TDM_WS_WIDTH 0x0000007F +#define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S)) +#define I2S_RX_TDM_WS_WIDTH_V 0x7F +#define I2S_RX_TDM_WS_WIDTH_S 0 + +#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x002C) +/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to enable transmitter in Phillips standard mode*/ +#define I2S_TX_MSB_SHIFT (BIT(29)) +#define I2S_TX_MSB_SHIFT_M (BIT(29)) +#define I2S_TX_MSB_SHIFT_V 0x1 +#define I2S_TX_MSB_SHIFT_S 29 +/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ +/*description: The Tx bit number for each channel minus 1in TDM mode.*/ +#define I2S_TX_TDM_CHAN_BITS 0x0000001F +#define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S)) +#define I2S_TX_TDM_CHAN_BITS_V 0x1F +#define I2S_TX_TDM_CHAN_BITS_S 24 +/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ +/*description: I2S Tx half sample bits -1.*/ +#define I2S_TX_HALF_SAMPLE_BITS 0x0000003F +#define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S)) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x3F +#define I2S_TX_HALF_SAMPLE_BITS_S 18 +/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ +/*description: Set the bits to configure bit length of I2S transmitter channel.*/ +#define I2S_TX_BITS_MOD 0x0000001F +#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) +#define I2S_TX_BITS_MOD_V 0x1F +#define I2S_TX_BITS_MOD_S 13 +/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ +/*description: Bit clock configuration bits in transmitter mode.*/ +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) +#define I2S_TX_BCK_DIV_NUM_V 0x3F +#define I2S_TX_BCK_DIV_NUM_S 7 +/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ +#define I2S_TX_TDM_WS_WIDTH 0x0000007F +#define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S)) +#define I2S_TX_TDM_WS_WIDTH_V 0x7F +#define I2S_TX_TDM_WS_WIDTH_S 0 + +#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0030) +/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module + clock as I2S_MCLK_OUT.*/ +#define I2S_MCLK_SEL (BIT(29)) +#define I2S_MCLK_SEL_M (BIT(29)) +#define I2S_MCLK_SEL_V 0x1 +#define I2S_MCLK_SEL_S 29 +/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. + 3: I2S_MCLK_in.*/ +#define I2S_RX_CLK_SEL 0x00000003 +#define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S)) +#define I2S_RX_CLK_SEL_V 0x3 +#define I2S_RX_CLK_SEL_S 27 +/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: I2S Rx module clock enable signal.*/ +#define I2S_RX_CLK_ACTIVE (BIT(26)) +#define I2S_RX_CLK_ACTIVE_M (BIT(26)) +#define I2S_RX_CLK_ACTIVE_V 0x1 +#define I2S_RX_CLK_ACTIVE_S 26 +/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: Integral I2S clock divider value*/ +#define I2S_RX_CLKM_DIV_NUM 0x000000FF +#define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S)) +#define I2S_RX_CLKM_DIV_NUM_V 0xFF +#define I2S_RX_CLKM_DIV_NUM_S 0 + +#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0034) +/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable clk gate*/ +#define I2S_CLK_EN (BIT(29)) +#define I2S_CLK_EN_M (BIT(29)) +#define I2S_CLK_EN_V 0x1 +#define I2S_CLK_EN_S 29 +/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: + CLK160. 3: I2S_MCLK_in.*/ +#define I2S_TX_CLK_SEL 0x00000003 +#define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S)) +#define I2S_TX_CLK_SEL_V 0x3 +#define I2S_TX_CLK_SEL_S 27 +/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: I2S Tx module clock enable signal.*/ +#define I2S_TX_CLK_ACTIVE (BIT(26)) +#define I2S_TX_CLK_ACTIVE_M (BIT(26)) +#define I2S_TX_CLK_ACTIVE_V 0x1 +#define I2S_TX_CLK_ACTIVE_S 26 +/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). + There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ +#define I2S_TX_CLKM_DIV_NUM 0x000000FF +#define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S)) +#define I2S_TX_CLKM_DIV_NUM_V 0xFF +#define I2S_TX_CLKM_DIV_NUM_S 0 + +#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x0038) +/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > + a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ +#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_M (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_V 0x1 +#define I2S_RX_CLKM_DIV_YN1_S 27 +/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For + b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ +#define I2S_RX_CLKM_DIV_X 0x000001FF +#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S)) +#define I2S_RX_CLKM_DIV_X_V 0x1FF +#define I2S_RX_CLKM_DIV_X_S 18 +/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b + > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ +#define I2S_RX_CLKM_DIV_Y 0x000001FF +#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S)) +#define I2S_RX_CLKM_DIV_Y_V 0x1FF +#define I2S_RX_CLKM_DIV_Y_S 9 +/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 + the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ +#define I2S_RX_CLKM_DIV_Z 0x000001FF +#define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S)) +#define I2S_RX_CLKM_DIV_Z_V 0x1FF +#define I2S_RX_CLKM_DIV_Z_S 0 + +#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x003C) +/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > + a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ +#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_M (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_V 0x1 +#define I2S_TX_CLKM_DIV_YN1_S 27 +/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For + b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ +#define I2S_TX_CLKM_DIV_X 0x000001FF +#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S)) +#define I2S_TX_CLKM_DIV_X_V 0x1FF +#define I2S_TX_CLKM_DIV_X_S 18 +/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b + > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ +#define I2S_TX_CLKM_DIV_Y 0x000001FF +#define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S)) +#define I2S_TX_CLKM_DIV_Y_V 0x1FF +#define I2S_TX_CLKM_DIV_Y_S 9 +/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 + the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ +#define I2S_TX_CLKM_DIV_Z 0x000001FF +#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S)) +#define I2S_TX_CLKM_DIV_Z_V 0x1FF +#define I2S_TX_CLKM_DIV_Z_S 0 + +#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x040) +/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: I2S TX PDM Converter enable.*/ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_V 0x1 +#define I2S_PCM2PDM_CONV_EN_S 25 +/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: I2S TX PDM dac 2channel enable.*/ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x1 +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: I2S TX PDM dac mode enable.*/ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x1 +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: I2S TX PDM sigmadelta dither value.*/ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x1 +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: I2S TX PDM sigmadelta dither2 value.*/ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x1 +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */ +/*description: I2S TX PDM prescale for sigmadelta.*/ +#define I2S_TX_PDM_PRESCALE 0x000000FF +#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) +#define I2S_TX_PDM_PRESCALE_V 0xFF +#define I2S_TX_PDM_PRESCALE_S 5 +/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */ +/*description: I2S TX PDM OSR2 value.*/ +#define I2S_TX_PDM_SINC_OSR2 0x0000000F +#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) +#define I2S_TX_PDM_SINC_OSR2_V 0xF +#define I2S_TX_PDM_SINC_OSR2_S 1 +/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/ +#define I2S_TX_PDM_HP_BYPASS (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_M (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_V 0x1 +#define I2S_TX_PDM_HP_BYPASS_S 0 + +#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44) +/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */ +/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL +T12_0[2:0]).*/ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007 +#define I2S_TX_IIR_HP_MULT12_0_M ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S)) +#define I2S_TX_IIR_HP_MULT12_0_V 0x7 +#define I2S_TX_IIR_HP_MULT12_0_S 23 +/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */ +/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL +T12_5[2:0]).*/ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007 +#define I2S_TX_IIR_HP_MULT12_5_M ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S)) +#define I2S_TX_IIR_HP_MULT12_5_V 0x7 +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */ +/*description: I2S TX PDM Fs.*/ +#define I2S_TX_PDM_FS 0x000003FF +#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) +#define I2S_TX_PDM_FS_V 0x3FF +#define I2S_TX_PDM_FS_S 10 +/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */ +/*description: I2S TX PDM Fp.*/ +#define I2S_TX_PDM_FP 0x000003FF +#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) +#define I2S_TX_PDM_FP_V 0x3FF +#define I2S_TX_PDM_FP_S 0 + +#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x050) +/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: The total channel number of I2S TX TDM mode.*/ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F +#define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S)) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 +/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_V 0x1 +#define I2S_RX_TDM_CHAN15_EN_S 15 +/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_V 0x1 +#define I2S_RX_TDM_CHAN14_EN_S 14 +/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_V 0x1 +#define I2S_RX_TDM_CHAN13_EN_S 13 +/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_V 0x1 +#define I2S_RX_TDM_CHAN12_EN_S 12 +/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_V 0x1 +#define I2S_RX_TDM_CHAN11_EN_S 11 +/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_V 0x1 +#define I2S_RX_TDM_CHAN10_EN_S 10 +/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_V 0x1 +#define I2S_RX_TDM_CHAN9_EN_S 9 +/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_V 0x1 +#define I2S_RX_TDM_CHAN8_EN_S 8 +/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 + +#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0054) +/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x1 +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 +/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: The total channel number minus 1 of I2S TX TDM mode.*/ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F +#define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S)) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_V 0x1 +#define I2S_TX_TDM_CHAN15_EN_S 15 +/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_V 0x1 +#define I2S_TX_TDM_CHAN14_EN_S 14 +/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_V 0x1 +#define I2S_TX_TDM_CHAN13_EN_S 13 +/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_V 0x1 +#define I2S_TX_TDM_CHAN12_EN_S 12 +/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_V 0x1 +#define I2S_TX_TDM_CHAN11_EN_S 11 +/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_V 0x1 +#define I2S_TX_TDM_CHAN10_EN_S 10 +/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_V 0x1 +#define I2S_TX_TDM_CHAN9_EN_S 9 +/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_V 0x1 +#define I2S_TX_TDM_CHAN8_EN_S 8 +/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_V 0x1 +#define I2S_TX_TDM_CHAN7_EN_S 7 +/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_V 0x1 +#define I2S_TX_TDM_CHAN6_EN_S 6 +/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_V 0x1 +#define I2S_TX_TDM_CHAN5_EN_S 5 +/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_V 0x1 +#define I2S_TX_TDM_CHAN4_EN_S 4 +/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_V 0x1 +#define I2S_TX_TDM_CHAN3_EN_S 3 +/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_V 0x1 +#define I2S_TX_TDM_CHAN2_EN_S 2 +/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_V 0x1 +#define I2S_TX_TDM_CHAN1_EN_S 1 +/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_V 0x1 +#define I2S_TX_TDM_CHAN0_EN_S 0 + +#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x0058) +/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_BCK_IN_DM 0x00000003 +#define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S)) +#define I2S_RX_BCK_IN_DM_V 0x3 +#define I2S_RX_BCK_IN_DM_S 28 +/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_WS_IN_DM 0x00000003 +#define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S)) +#define I2S_RX_WS_IN_DM_V 0x3 +#define I2S_RX_WS_IN_DM_S 24 +/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_BCK_OUT_DM 0x00000003 +#define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S)) +#define I2S_RX_BCK_OUT_DM_V 0x3 +#define I2S_RX_BCK_OUT_DM_S 20 +/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_WS_OUT_DM 0x00000003 +#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S)) +#define I2S_RX_WS_OUT_DM_V 0x3 +#define I2S_RX_WS_OUT_DM_S 16 +/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD_IN_DM 0x00000003 +#define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S)) +#define I2S_RX_SD_IN_DM_V 0x3 +#define I2S_RX_SD_IN_DM_S 0 + +#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x005C) +/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_BCK_IN_DM 0x00000003 +#define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S)) +#define I2S_TX_BCK_IN_DM_V 0x3 +#define I2S_TX_BCK_IN_DM_S 28 +/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_WS_IN_DM 0x00000003 +#define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S)) +#define I2S_TX_WS_IN_DM_V 0x3 +#define I2S_TX_WS_IN_DM_S 24 +/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_BCK_OUT_DM 0x00000003 +#define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S)) +#define I2S_TX_BCK_OUT_DM_V 0x3 +#define I2S_TX_BCK_OUT_DM_S 20 +/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_WS_OUT_DM 0x00000003 +#define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S)) +#define I2S_TX_WS_OUT_DM_V 0x3 +#define I2S_TX_WS_OUT_DM_S 16 +/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + delay by neg edge. 3: not used..*/ +#define I2S_TX_SD1_OUT_DM 0x00000003 +#define I2S_TX_SD1_OUT_DM_M ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S)) +#define I2S_TX_SD1_OUT_DM_V 0x3 +#define I2S_TX_SD1_OUT_DM_S 4 +/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_SD_OUT_DM 0x00000003 +#define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S)) +#define I2S_TX_SD_OUT_DM_V 0x3 +#define I2S_TX_SD_OUT_DM_S 0 + +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) +/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: The enable bit for FIFO timeout*/ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 +/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: The bits are used to scale tick counter threshold. The tick counter + is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt + will be triggered when fifo hung counter is equal to this value*/ +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) +#define I2S_LC_FIFO_TIMEOUT_V 0xFF +#define I2S_LC_FIFO_TIMEOUT_S 0 + +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0064) +/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */ +/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ +#define I2S_RX_EOF_NUM 0x00000FFF +#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) +#define I2S_RX_EOF_NUM_V 0xFFF +#define I2S_RX_EOF_NUM_S 0 + +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068) +/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: the right channel or left channel put out constant value stored + in this register according to tx_chan_mod and reg_tx_msb_right*/ +#define I2S_SINGLE_DATA 0xFFFFFFFF +#define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S)) +#define I2S_SINGLE_DATA_V 0xFFFFFFFF +#define I2S_SINGLE_DATA_S 0 + +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x006C) +/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (BIT(0)) +#define I2S_TX_IDLE_V 0x1 +#define I2S_TX_IDLE_S 0 + +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x0080) +/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */ +/*description: Version control register*/ +#define I2S_DATE 0x0FFFFFFF +#define I2S_DATE_M ((I2S_DATE_V)<<(I2S_DATE_S)) +#define I2S_DATE_V 0xFFFFFFF +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/include/soc/i2s_struct.h new file mode 100644 index 0000000000..2f9c862b85 --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2s_struct.h @@ -0,0 +1,336 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_STRUCT_H_ +#define _SOC_I2S_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + union { + struct { + uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_clr; + uint32_t reserved_1c; + union { + struct { + uint32_t rx_reset: 1; /*Set this bit to reset receiver*/ + uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/ + uint32_t rx_start: 1; /*Set this bit to start receiving data*/ + uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/ + uint32_t reserved4: 1; /*Reserved*/ + uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/ + uint32_t reserved6: 1; + uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ + uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/ + uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/ + uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ + uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/ + uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ + uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ + uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ + uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ + uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/ + uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/ + uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/ + uint32_t reserved23: 11; /*Reserve*/ + }; + uint32_t val; + } rx_conf; + union { + struct { + uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/ + uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/ + uint32_t tx_start: 1; /*Set this bit to start transmitting data*/ + uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/ + uint32_t reserved4: 1; /*Reserved*/ + uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/ + uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ + uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ + uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/ + uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ + uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ + uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ + uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ + uint32_t reserved14: 1; + uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ + uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ + uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ + uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/ + uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/ + uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/ + uint32_t reserved21: 3; /*Reserved*/ + uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/ + uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } tx_conf; + union { + struct { + uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ + uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/ + uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/ + uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/ + uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/ + uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } rx_conf1; + union { + struct { + uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ + uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/ + uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/ + uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/ + uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/ + uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/ + uint32_t tx_bck_no_dly: 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/ + uint32_t reserved31: 1; /* Reserved*/ + }; + uint32_t val; + } tx_conf1; + union { + struct { + uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/ + uint32_t reserved8: 18; /*Reserved*/ + uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/ + uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } rx_clkm_conf; + union { + struct { + uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ + uint32_t reserved8: 18; /*Reserved*/ + uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ + uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } tx_clkm_conf; + union { + struct { + uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ + uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ + uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ + uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } rx_clkm_div_conf; + union { + struct { + uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ + uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ + uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ + uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } tx_clkm_div_conf; + union { + struct { + uint32_t tx_pdm_hp_bypass : 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/ + uint32_t tx_pdm_sinc_osr2 : 4; /*I2S TX PDM OSR2 value*/ + uint32_t tx_pdm_prescale : 8; /*I2S TX PDM prescale for sigmadelta*/ + uint32_t tx_pdm_hp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ + uint32_t tx_pdm_lp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ + uint32_t tx_pdm_sinc_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ + uint32_t tx_pdm_sigmadelta_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ + uint32_t tx_pdm_sigmadelta_dither2 : 1; /*I2S TX PDM sigmadelta dither2 value*/ + uint32_t tx_pdm_sigmadelta_dither : 1; /*I2S TX PDM sigmadelta dither value*/ + uint32_t tx_pdm_dac_2out_en : 1; /*I2S TX PDM dac mode enable*/ + uint32_t tx_pdm_dac_mode_en : 1; /*I2S TX PDM dac 2channel enable*/ + uint32_t pcm2pdm_conv_en : 1; /*I2S TX PDM Converter enable*/ + uint32_t reserved26 : 6; /*Reserved*/ + }; + uint32_t val; + } tx_pcm2pdm_conf; + union { + struct { + uint32_t tx_pdm_fp : 10; /*I2S TX PDM Fp*/ + uint32_t tx_pdm_fs : 10; /*I2S TX PDM Fs*/ + uint32_t tx_iir_hp_mult12_5 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/ + uint32_t tx_iir_hp_mult12_0 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/ + uint32_t reserved26 : 6; /*Reserved*/ + }; + uint32_t val; + } tx_pcm2pdm_conf1; + uint32_t reserved_48; + uint32_t reserved_4c; + union { + struct { + uint32_t rx_tdm_pdm_chan0_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan1_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan2_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan3_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan4_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan5_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan6_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_pdm_chan7_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan8_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan9_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan10_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan11_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan12_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan13_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan14_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_chan15_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ + uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } rx_tdm_ctrl; + union { + struct { + uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/ + uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ + uint32_t reserved21: 11; /*Reserved*/ + }; + uint32_t val; + } tx_tdm_ctrl; + union { + struct { + uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved2 : 14; /* Reserved*/ + uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18: 2; + uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22: 2; + uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26: 2; + uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30: 2; + }; + uint32_t val; + } rx_timing; + union { + struct { + uint32_t tx_sd_out_dm : 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved2 : 2; /* Reserved*/ + uint32_t tx_sd1_out_dm : 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved6 : 10; /* Reserved*/ + uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18 : 2; /* Reserved*/ + uint32_t tx_bck_out_dm : 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22 : 2; /* Reserved*/ + uint32_t tx_ws_in_dm : 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26 : 2; /* Reserved*/ + uint32_t tx_bck_in_dm : 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30 : 2; /* Reserved*/ + }; + uint32_t val; + } tx_timing; + union { + struct { + uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/ + uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ + uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } lc_hung_conf; + union { + struct { + uint32_t rx_eof_num:12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ + uint32_t reserved12:20; /*Reserved*/ + }; + uint32_t val; + } rx_eof_num; + uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/ + union { + struct { + uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/ + uint32_t reserved1: 31; /*Reserved*/ + }; + uint32_t val; + } state; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + union { + struct { + uint32_t date: 28; /*Version control register*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } date; +} i2s_dev_t; +extern i2s_dev_t I2S0; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/interrupt_core0_reg.h b/components/soc/esp32h2/include/soc/interrupt_core0_reg.h new file mode 100644 index 0000000000..f606cdafca --- /dev/null +++ b/components/soc/esp32h2/include/soc/interrupt_core0_reg.h @@ -0,0 +1,856 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_INTERRUPT_CORE0_REG_H_ +#define _SOC_INTERRUPT_CORE0_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE + +#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000) +/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S)) +#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004) +/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S)) +#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008) +/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C) +/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010) +/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014) +/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018) +/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C) +/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 + +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020) +/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 + +#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024) +/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028) +/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C) +/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030) +/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034) +/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038) +/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S)) +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C) +/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S)) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048) +/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C) +/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 + +#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050) +/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S)) +#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054) +/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058) +/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C) +/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S)) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060) +/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S)) +#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064) +/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S)) +#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CAN_INT_MAP_S 0 + +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) +/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S)) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C) +/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070) +/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S)) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074) +/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078) +/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 + +#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C) +/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 + +#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080) +/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084) +/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088) +/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C) +/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090) +/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094) +/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) +/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C) +/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0) +/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4) +/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8) +/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC) +/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0) +/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4) +/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8) +/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC) +/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S)) +#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0) +/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S)) +#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_AES_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4) +/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S)) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8) +/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC) +/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0) +/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4) +/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8) +/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC) +/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0) +/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4) +/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) +/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S)) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) +/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S)) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 + +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define INTERRUPT_CORE0_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_CLK_EN_M (BIT(0)) +#define INTERRUPT_CORE0_CLK_EN_V 0x1 +#define INTERRUPT_CORE0_CLK_EN_S 0 + +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S)) +#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0 + +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S)) +#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0 + +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) +/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S)) +#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0 + +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S)) +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) +/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) +/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) +/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) +/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) +/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) +/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) +/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S)) +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF +#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0 +#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) + +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F +#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S)) +#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF +#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0 + +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) +/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S)) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/interrupt_reg.h b/components/soc/esp32h2/include/soc/interrupt_reg.h new file mode 100644 index 0000000000..9d41c72a75 --- /dev/null +++ b/components/soc/esp32h2/include/soc/interrupt_reg.h @@ -0,0 +1 @@ +#include "interrupt_core0_reg.h" diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/include/soc/io_mux_reg.h new file mode 100644 index 0000000000..3f338ea92d --- /dev/null +++ b/components/soc/esp32h2/include/soc/io_mux_reg.h @@ -0,0 +1,274 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_IO_MUX_REG_H_ +#define _SOC_IO_MUX_REG_H_ + +#include "soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U + +/* Value to set in IO Mux to use a pin as GPIO. */ +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U0RXD_GPIO_NUM 20 +#define U0TXD_GPIO_NUM 21 + +#define SPI_HD_GPIO_NUM 12 +#define SPI_WP_GPIO_NUM 13 +#define SPI_CS0_GPIO_NUM 14 +#define SPI_CLK_GPIO_NUM 15 +#define SPI_D_GPIO_NUM 16 +#define SPI_Q_GPIO_NUM 17 + +#define SD_CLK_GPIO_NUM 12 +#define SD_CMD_GPIO_NUM 11 +#define SD_DATA0_GPIO_NUM 13 +#define SD_DATA1_GPIO_NUM 14 +#define SD_DATA2_GPIO_NUM 9 +#define SD_DATA3_GPIO_NUM 10 + +#define MAX_RTC_GPIO_NUM 0 +#define MAX_PAD_GPIO_NUM 22 +#define MAX_GPIO_NUM 22 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + + +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) + +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x04) +#define FUNC_XTAL_32K_P_GPIO0 1 +#define FUNC_XTAL_32K_P_GPIO0_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x08) +#define FUNC_XTAL_32K_N_GPIO1 1 +#define FUNC_XTAL_32K_N_GPIO1_0 0 + +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO2_FSPIQ 2 +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0x14) +#define FUNC_MTMS_FSPIHD 2 +#define FUNC_MTMS_GPIO4 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0x18) +#define FUNC_MTDI_FSPIWP 2 +#define FUNC_MTDI_GPIO5 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0x1c) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO6 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0x20) +#define FUNC_MTDO_FSPID 2 +#define FUNC_MTDO_GPIO7 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO10_FSPICS0 2 +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE +0x30) +#define FUNC_VDD_SPI_GPIO11 1 +#define FUNC_VDD_SPI_GPIO11_0 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x34) +#define FUNC_SPIHD_GPIO12 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x38) +#define FUNC_SPIWP_GPIO13 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x3c) +#define FUNC_SPICS0_GPIO14 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x40) +#define FUNC_SPICLK_GPIO15 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x44) +#define FUNC_SPID_GPIO16 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x48) +#define FUNC_SPIQ_GPIO17 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE +0x4c) +#define FUNC_GPIO18_GPIO18 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO19_GPIO19 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0x54) +#define FUNC_U0RXD_GPIO20 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0x58) +#define FUNC_U0TXD_GPIO21 1 +#define FUNC_U0TXD_U0TXD 0 + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) +#define IO_MUX_DATE 0xFFFFFFFF +#define IO_MUX_DATE_S 0 +#define IO_MUX_DATE_VERSION 0x2006050 + +#endif diff --git a/components/soc/esp32h2/include/soc/ledc_reg.h b/components/soc/esp32h2/include/soc/ledc_reg.h new file mode 100644 index 0000000000..0cc9334130 --- /dev/null +++ b/components/soc/esp32h2/include/soc/ledc_reg.h @@ -0,0 +1,1226 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_REG_H_ +#define _SOC_LEDC_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH0_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH0_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH0_S 16 +/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH0_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH0_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH0_S 15 +/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH0 0x000003FF +#define LEDC_OVF_NUM_LSCH0_M ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S)) +#define LEDC_OVF_NUM_LSCH0_V 0x3FF +#define LEDC_OVF_NUM_LSCH0_S 5 +/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH0 (BIT(4)) +#define LEDC_PARA_UP_LSCH0_M (BIT(4)) +#define LEDC_PARA_UP_LSCH0_V 0x1 +#define LEDC_PARA_UP_LSCH0_S 4 +/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH0 (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_V 0x1 +#define LEDC_IDLE_LV_LSCH0_S 3 +/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH0_S 2 +/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH0 0x00000003 +#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) +#define LEDC_TIMER_SEL_LSCH0_V 0x3 +#define LEDC_TIMER_SEL_LSCH0_S 0 + +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH0 0x00003FFF +#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) +#define LEDC_HPOINT_LSCH0_V 0x3FFF +#define LEDC_HPOINT_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH0 0x0007FFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x7FFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) +/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH0 (BIT(31)) +#define LEDC_DUTY_START_LSCH0_M (BIT(31)) +#define LEDC_DUTY_START_LSCH0_V 0x1 +#define LEDC_DUTY_START_LSCH0_S 31 +/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH0 (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_V 0x1 +#define LEDC_DUTY_INC_LSCH0_S 30 +/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH0 0x000003FF +#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) +#define LEDC_DUTY_NUM_LSCH0_V 0x3FF +#define LEDC_DUTY_NUM_LSCH0_S 20 +/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) +#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH0_S 10 +/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH0 0x000003FF +#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) +#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH0 0x0007FFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x7FFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH1_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH1_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH1_S 16 +/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH1_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH1_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH1_S 15 +/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH1 0x000003FF +#define LEDC_OVF_NUM_LSCH1_M ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S)) +#define LEDC_OVF_NUM_LSCH1_V 0x3FF +#define LEDC_OVF_NUM_LSCH1_S 5 +/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH1 (BIT(4)) +#define LEDC_PARA_UP_LSCH1_M (BIT(4)) +#define LEDC_PARA_UP_LSCH1_V 0x1 +#define LEDC_PARA_UP_LSCH1_S 4 +/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH1 (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_V 0x1 +#define LEDC_IDLE_LV_LSCH1_S 3 +/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH1_S 2 +/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH1 0x00000003 +#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) +#define LEDC_TIMER_SEL_LSCH1_V 0x3 +#define LEDC_TIMER_SEL_LSCH1_S 0 + +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH1 0x00003FFF +#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) +#define LEDC_HPOINT_LSCH1_V 0x3FFF +#define LEDC_HPOINT_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH1 0x0007FFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x7FFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) +/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH1 (BIT(31)) +#define LEDC_DUTY_START_LSCH1_M (BIT(31)) +#define LEDC_DUTY_START_LSCH1_V 0x1 +#define LEDC_DUTY_START_LSCH1_S 31 +/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH1 (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_V 0x1 +#define LEDC_DUTY_INC_LSCH1_S 30 +/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH1 0x000003FF +#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) +#define LEDC_DUTY_NUM_LSCH1_V 0x3FF +#define LEDC_DUTY_NUM_LSCH1_S 20 +/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) +#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH1_S 10 +/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH1 0x000003FF +#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) +#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH1 0x0007FFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x7FFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH2_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH2_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH2_S 16 +/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH2_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH2_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH2_S 15 +/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH2 0x000003FF +#define LEDC_OVF_NUM_LSCH2_M ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S)) +#define LEDC_OVF_NUM_LSCH2_V 0x3FF +#define LEDC_OVF_NUM_LSCH2_S 5 +/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH2 (BIT(4)) +#define LEDC_PARA_UP_LSCH2_M (BIT(4)) +#define LEDC_PARA_UP_LSCH2_V 0x1 +#define LEDC_PARA_UP_LSCH2_S 4 +/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH2 (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_V 0x1 +#define LEDC_IDLE_LV_LSCH2_S 3 +/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH2_S 2 +/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH2 0x00000003 +#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) +#define LEDC_TIMER_SEL_LSCH2_V 0x3 +#define LEDC_TIMER_SEL_LSCH2_S 0 + +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH2 0x00003FFF +#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) +#define LEDC_HPOINT_LSCH2_V 0x3FFF +#define LEDC_HPOINT_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH2 0x0007FFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x7FFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) +/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH2 (BIT(31)) +#define LEDC_DUTY_START_LSCH2_M (BIT(31)) +#define LEDC_DUTY_START_LSCH2_V 0x1 +#define LEDC_DUTY_START_LSCH2_S 31 +/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH2 (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_V 0x1 +#define LEDC_DUTY_INC_LSCH2_S 30 +/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH2 0x000003FF +#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) +#define LEDC_DUTY_NUM_LSCH2_V 0x3FF +#define LEDC_DUTY_NUM_LSCH2_S 20 +/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) +#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH2_S 10 +/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH2 0x000003FF +#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) +#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH2 0x0007FFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x7FFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH3_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH3_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH3_S 16 +/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH3_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH3_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH3_S 15 +/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH3 0x000003FF +#define LEDC_OVF_NUM_LSCH3_M ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S)) +#define LEDC_OVF_NUM_LSCH3_V 0x3FF +#define LEDC_OVF_NUM_LSCH3_S 5 +/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH3 (BIT(4)) +#define LEDC_PARA_UP_LSCH3_M (BIT(4)) +#define LEDC_PARA_UP_LSCH3_V 0x1 +#define LEDC_PARA_UP_LSCH3_S 4 +/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH3 (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_V 0x1 +#define LEDC_IDLE_LV_LSCH3_S 3 +/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH3_S 2 +/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH3 0x00000003 +#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) +#define LEDC_TIMER_SEL_LSCH3_V 0x3 +#define LEDC_TIMER_SEL_LSCH3_S 0 + +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH3 0x00003FFF +#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) +#define LEDC_HPOINT_LSCH3_V 0x3FFF +#define LEDC_HPOINT_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH3 0x0007FFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x7FFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) +/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH3 (BIT(31)) +#define LEDC_DUTY_START_LSCH3_M (BIT(31)) +#define LEDC_DUTY_START_LSCH3_V 0x1 +#define LEDC_DUTY_START_LSCH3_S 31 +/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH3 (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_V 0x1 +#define LEDC_DUTY_INC_LSCH3_S 30 +/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH3 0x000003FF +#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) +#define LEDC_DUTY_NUM_LSCH3_V 0x3FF +#define LEDC_DUTY_NUM_LSCH3_S 20 +/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) +#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH3_S 10 +/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH3 0x000003FF +#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) +#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH3 0x0007FFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x7FFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH4_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH4_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH4_S 16 +/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH4_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH4_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH4_S 15 +/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH4 0x000003FF +#define LEDC_OVF_NUM_LSCH4_M ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S)) +#define LEDC_OVF_NUM_LSCH4_V 0x3FF +#define LEDC_OVF_NUM_LSCH4_S 5 +/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH4 (BIT(4)) +#define LEDC_PARA_UP_LSCH4_M (BIT(4)) +#define LEDC_PARA_UP_LSCH4_V 0x1 +#define LEDC_PARA_UP_LSCH4_S 4 +/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH4 (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_V 0x1 +#define LEDC_IDLE_LV_LSCH4_S 3 +/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH4_S 2 +/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH4 0x00000003 +#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) +#define LEDC_TIMER_SEL_LSCH4_V 0x3 +#define LEDC_TIMER_SEL_LSCH4_S 0 + +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH4 0x00003FFF +#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) +#define LEDC_HPOINT_LSCH4_V 0x3FFF +#define LEDC_HPOINT_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH4 0x0007FFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x7FFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) +/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH4 (BIT(31)) +#define LEDC_DUTY_START_LSCH4_M (BIT(31)) +#define LEDC_DUTY_START_LSCH4_V 0x1 +#define LEDC_DUTY_START_LSCH4_S 31 +/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH4 (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_V 0x1 +#define LEDC_DUTY_INC_LSCH4_S 30 +/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH4 0x000003FF +#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) +#define LEDC_DUTY_NUM_LSCH4_V 0x3FF +#define LEDC_DUTY_NUM_LSCH4_S 20 +/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) +#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH4_S 10 +/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH4 0x000003FF +#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) +#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH4 0x0007FFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x7FFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH5_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH5_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH5_S 16 +/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH5_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH5_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH5_S 15 +/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH5 0x000003FF +#define LEDC_OVF_NUM_LSCH5_M ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S)) +#define LEDC_OVF_NUM_LSCH5_V 0x3FF +#define LEDC_OVF_NUM_LSCH5_S 5 +/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH5 (BIT(4)) +#define LEDC_PARA_UP_LSCH5_M (BIT(4)) +#define LEDC_PARA_UP_LSCH5_V 0x1 +#define LEDC_PARA_UP_LSCH5_S 4 +/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH5 (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_V 0x1 +#define LEDC_IDLE_LV_LSCH5_S 3 +/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH5_S 2 +/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH5 0x00000003 +#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) +#define LEDC_TIMER_SEL_LSCH5_V 0x3 +#define LEDC_TIMER_SEL_LSCH5_S 0 + +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH5 0x00003FFF +#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) +#define LEDC_HPOINT_LSCH5_V 0x3FFF +#define LEDC_HPOINT_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH5 0x0007FFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x7FFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) +/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH5 (BIT(31)) +#define LEDC_DUTY_START_LSCH5_M (BIT(31)) +#define LEDC_DUTY_START_LSCH5_V 0x1 +#define LEDC_DUTY_START_LSCH5_S 31 +/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH5 (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_V 0x1 +#define LEDC_DUTY_INC_LSCH5_S 30 +/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH5 0x000003FF +#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) +#define LEDC_DUTY_NUM_LSCH5_V 0x3FF +#define LEDC_DUTY_NUM_LSCH5_S 20 +/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) +#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH5_S 10 +/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH5 0x000003FF +#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) +#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH5 0x0007FFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x7FFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x00a0) +/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER0_PARA_UP (BIT(25)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER0_PARA_UP_V 0x1 +#define LEDC_LSTIMER0_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER0_V 0x1 +#define LEDC_TICK_SEL_LSTIMER0_S 24 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER0_RST (BIT(23)) +#define LEDC_LSTIMER0_RST_M (BIT(23)) +#define LEDC_LSTIMER0_RST_V 0x1 +#define LEDC_LSTIMER0_RST_S 23 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_PAUSE (BIT(22)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER0_PAUSE_V 0x1 +#define LEDC_LSTIMER0_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER0 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER0_M ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S)) +#define LEDC_CLK_DIV_LSTIMER0_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER0_S 4 +/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER0_DUTY_RES 0x0000000F +#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S)) +#define LEDC_LSTIMER0_DUTY_RES_V 0xF +#define LEDC_LSTIMER0_DUTY_RES_S 0 + +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x00a4) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_CNT 0x00003FFF +#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) +#define LEDC_LSTIMER0_CNT_V 0x3FFF +#define LEDC_LSTIMER0_CNT_S 0 + +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x00a8) +/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER1_PARA_UP (BIT(25)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER1_PARA_UP_V 0x1 +#define LEDC_LSTIMER1_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER1_V 0x1 +#define LEDC_TICK_SEL_LSTIMER1_S 24 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER1_RST (BIT(23)) +#define LEDC_LSTIMER1_RST_M (BIT(23)) +#define LEDC_LSTIMER1_RST_V 0x1 +#define LEDC_LSTIMER1_RST_S 23 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_PAUSE (BIT(22)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER1_PAUSE_V 0x1 +#define LEDC_LSTIMER1_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER1 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER1_M ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S)) +#define LEDC_CLK_DIV_LSTIMER1_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER1_S 4 +/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER1_DUTY_RES 0x0000000F +#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S)) +#define LEDC_LSTIMER1_DUTY_RES_V 0xF +#define LEDC_LSTIMER1_DUTY_RES_S 0 + +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x00aC) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_CNT 0x00003FFF +#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) +#define LEDC_LSTIMER1_CNT_V 0x3FFF +#define LEDC_LSTIMER1_CNT_S 0 + +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x00b0) +/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER2_PARA_UP (BIT(25)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER2_PARA_UP_V 0x1 +#define LEDC_LSTIMER2_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER2_V 0x1 +#define LEDC_TICK_SEL_LSTIMER2_S 24 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER2_RST (BIT(23)) +#define LEDC_LSTIMER2_RST_M (BIT(23)) +#define LEDC_LSTIMER2_RST_V 0x1 +#define LEDC_LSTIMER2_RST_S 23 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_PAUSE (BIT(22)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER2_PAUSE_V 0x1 +#define LEDC_LSTIMER2_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER2 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER2_M ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S)) +#define LEDC_CLK_DIV_LSTIMER2_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER2_S 4 +/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER2_DUTY_RES 0x0000000F +#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S)) +#define LEDC_LSTIMER2_DUTY_RES_V 0xF +#define LEDC_LSTIMER2_DUTY_RES_S 0 + +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x00b4) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_CNT 0x00003FFF +#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) +#define LEDC_LSTIMER2_CNT_V 0x3FFF +#define LEDC_LSTIMER2_CNT_S 0 + +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x00b8) +/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER3_PARA_UP (BIT(25)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER3_PARA_UP_V 0x1 +#define LEDC_LSTIMER3_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER3_V 0x1 +#define LEDC_TICK_SEL_LSTIMER3_S 24 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER3_RST (BIT(23)) +#define LEDC_LSTIMER3_RST_M (BIT(23)) +#define LEDC_LSTIMER3_RST_V 0x1 +#define LEDC_LSTIMER3_RST_S 23 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_PAUSE (BIT(22)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER3_PAUSE_V 0x1 +#define LEDC_LSTIMER3_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER3 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER3_M ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S)) +#define LEDC_CLK_DIV_LSTIMER3_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER3_S 4 +/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER3_DUTY_RES 0x0000000F +#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S)) +#define LEDC_LSTIMER3_DUTY_RES_V 0xF +#define LEDC_LSTIMER3_DUTY_RES_S 0 + +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x00BC) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_CNT 0x00003FFF +#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) +#define LEDC_LSTIMER3_CNT_V 0x3FFF +#define LEDC_LSTIMER3_CNT_S 0 + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x00C0) +/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 15 +/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 14 +/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 13 +/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 12 +/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 11 +/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 4 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 0 + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x00c4) +/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_ST_S 15 +/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_ST_S 14 +/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_ST_S 13 +/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_ST_S 12 +/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_ST_S 11 +/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 4 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ST_S 3 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ST_S 2 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ST_S 1 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ST_S 0 + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xC8) +/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 15 +/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 14 +/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 13 +/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 12 +/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 11 +/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 4 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 0 + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xCC) +/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 15 +/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 14 +/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 13 +/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 12 +/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(11)) +#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 11 +/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(10)) +#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: reg_duty_chng_end_lsch5_int_clr..*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 4 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 0 + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 +/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define LEDC_APB_CLK_SEL 0x00000003 +#define LEDC_APB_CLK_SEL_M ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S)) +#define LEDC_APB_CLK_SEL_V 0x3 +#define LEDC_APB_CLK_SEL_S 0 + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */ +/*description: */ +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_LEDC_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/ledc_struct.h b/components/soc/esp32h2/include/soc/ledc_struct.h new file mode 100644 index 0000000000..9e5a2a96c1 --- /dev/null +++ b/components/soc/esp32h2/include/soc/ledc_struct.h @@ -0,0 +1,220 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_STRUCT_H_ +#define _SOC_LEDC_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + struct { + struct { + union { + struct { + uint32_t timer_sel: 2; + uint32_t sig_out_en: 1; + uint32_t idle_lv: 1; + uint32_t low_speed_update: 1; + uint32_t ovf_num: 10; + uint32_t ovf_cnt_en: 1; + uint32_t ovf_cnt_rst: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t hpoint: 14; + uint32_t reserved14: 18; + }; + uint32_t val; + } hpoint; + union { + struct { + uint32_t duty: 19; + uint32_t reserved19:13; + }; + uint32_t val; + } duty; + union { + struct { + uint32_t duty_scale: 10; + uint32_t duty_cycle: 10; + uint32_t duty_num: 10; + uint32_t duty_inc: 1; + uint32_t duty_start: 1; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t duty_read: 19; + uint32_t reserved19: 13; + }; + uint32_t val; + } duty_rd; + } channel[6]; + } channel_group[1]; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + struct { + struct { + union { + struct { + uint32_t duty_resolution: 4; + uint32_t clock_divider: 18; + uint32_t pause: 1; + uint32_t rst: 1; + uint32_t tick_sel: 1; + uint32_t low_speed_update: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t timer_cnt: 14; + uint32_t reserved14: 18; + }; + uint32_t val; + } value; + } timer[4]; + } timer_group[1]; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_clk_sel: 2; + uint32_t reserved2: 29; + uint32_t clk_en: 1; + }; + uint32_t val; + } conf; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + union { + struct { + uint32_t date: 32; + }; + uint32_t val; + } date; +} ledc_dev_t; +extern ledc_dev_t LEDC; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/mmu.h b/components/soc/esp32h2/include/soc/mmu.h new file mode 100644 index 0000000000..27d646c301 --- /dev/null +++ b/components/soc/esp32h2/include/soc/mmu.h @@ -0,0 +1,42 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/cache_memory.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 1 +#define SOC_MMU_PAGES_PER_REGION 128 +#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK +#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START +#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/nrx_reg.h b/components/soc/esp32h2/include/soc/nrx_reg.h new file mode 100644 index 0000000000..d80cb2a178 --- /dev/null +++ b/components/soc/esp32h2/include/soc/nrx_reg.h @@ -0,0 +1,55 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_CHAN_EST_FORCE_PU (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_M (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_V 1 +#define NRX_CHAN_EST_FORCE_PU_S 7 +#define NRX_CHAN_EST_FORCE_PD (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_M (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_V 1 +#define NRX_CHAN_EST_FORCE_PD_S 6 +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_V 1 +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_M (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_V 1 +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_M (BIT(3)) +#define NRX_VIT_FORCE_PU_V 1 +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_M (BIT(2)) +#define NRX_VIT_FORCE_PD_V 1 +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_M (BIT(1)) +#define NRX_DEMAP_FORCE_PU_V 1 +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_M (BIT(0)) +#define NRX_DEMAP_FORCE_PD_V 1 +#define NRX_DEMAP_FORCE_PD_S 0 diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h new file mode 100644 index 0000000000..da304aef31 --- /dev/null +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -0,0 +1,120 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_SPI2_MODULE, //SPI2 + PERIPH_TWAI_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_WIFI_BT_COMMON_MODULE, + PERIPH_BT_BASEBAND_MODULE, + PERIPH_BT_LC_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_MODULE_MAX +} periph_module_t; + +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ + ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TIMER1_INTR_SOURCE, + ETS_TIMER2_INTR_SOURCE, + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/ + ETS_DMA_CH1_INTR_SOURCE, /**< interrupt of general DMA channel 1, LEVEL*/ + ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_DMA_APBPERI_PMS_INTR_SOURCE, + ETS_CORE0_IRAM0_PMS_INTR_SOURCE, + ETS_CORE0_DRAM0_PMS_INTR_SOURCE, + ETS_CORE0_PIF_PMS_INTR_SOURCE, + ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, + ETS_BAK_PMS_VIOLATE_INTR_SOURCE, + ETS_CACHE_CORE0_ACS_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rmt_reg.h b/components/soc/esp32h2/include/soc/rmt_reg.h new file mode 100644 index 0000000000..4a916e99d0 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rmt_reg.h @@ -0,0 +1,1144 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_REG_H_ +#define _SOC_RMT_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) + +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) + +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) + +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) + +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0010) +/* RMT_CONF_UPDATE_CH0 : WT ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (BIT(24)) +#define RMT_CONF_UPDATE_CH0_V 0x1 +#define RMT_CONF_UPDATE_CH0_S 24 +/* RMT_AFIFO_RST_CH0 : WT ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH0 (BIT(23)) +#define RMT_AFIFO_RST_CH0_M (BIT(23)) +#define RMT_AFIFO_RST_CH0_V 0x1 +#define RMT_AFIFO_RST_CH0_S 23 +/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (BIT(21)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 21 +/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_V 0x1 +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH0 0x00000007 +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0x7 +#define RMT_MEM_SIZE_CH0_S 16 +/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 8 +/* RMT_TX_STOP_CH0 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (BIT(7)) +#define RMT_TX_STOP_CH0_V 0x1 +#define RMT_TX_STOP_CH0_S 7 +/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 6 +/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 5 +/* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 3 +/* RMT_APB_MEM_RST_CH0 : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (BIT(2)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 2 +/* RMT_MEM_RD_RST_CH0 : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (BIT(1)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 1 +/* RMT_TX_START_CH0 : WT ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 + +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0014) +/* RMT_CONF_UPDATE_CH1 : WT ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (BIT(24)) +#define RMT_CONF_UPDATE_CH1_V 0x1 +#define RMT_CONF_UPDATE_CH1_S 24 +/* RMT_AFIFO_RST_CH1 : WT ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH1 (BIT(23)) +#define RMT_AFIFO_RST_CH1_M (BIT(23)) +#define RMT_AFIFO_RST_CH1_V 0x1 +#define RMT_AFIFO_RST_CH1_S 23 +/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (BIT(21)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 21 +/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_V 0x1 +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH1 0x00000007 +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0x7 +#define RMT_MEM_SIZE_CH1_S 16 +/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 8 +/* RMT_TX_STOP_CH1 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (BIT(7)) +#define RMT_TX_STOP_CH1_V 0x1 +#define RMT_TX_STOP_CH1_S 7 +/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 6 +/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 5 +/* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 3 +/* RMT_APB_MEM_RST_CH1 : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (BIT(2)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 2 +/* RMT_MEM_RD_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (BIT(1)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 1 +/* RMT_TX_START_CH1 : WT ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 + +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0018) +/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 29 +/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (BIT(28)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 28 +/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[25:23] ;default: 3'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH2 0x00000007 +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0x7 +#define RMT_MEM_SIZE_CH2_S 23 +/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ +/*description: */ +#define RMT_IDLE_THRES_CH2 0x00007FFF +#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) +#define RMT_IDLE_THRES_CH2_V 0x7FFF +#define RMT_IDLE_THRES_CH2_S 8 +/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 0 + +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x001c) +/* RMT_CONF_UPDATE_CH2 : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH2 (BIT(15)) +#define RMT_CONF_UPDATE_CH2_M (BIT(15)) +#define RMT_CONF_UPDATE_CH2_V 0x1 +#define RMT_CONF_UPDATE_CH2_S 15 +/* RMT_AFIFO_RST_CH2 : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH2 (BIT(14)) +#define RMT_AFIFO_RST_CH2_M (BIT(14)) +#define RMT_AFIFO_RST_CH2_V 0x1 +#define RMT_AFIFO_RST_CH2_S 14 +/* RMT_MEM_RX_WRAP_EN_CH2 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH2_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH2_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH2_S 13 +/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ +/*description: */ +#define RMT_RX_FILTER_THRES_CH2 0x000000FF +#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) +#define RMT_RX_FILTER_THRES_CH2_V 0xFF +#define RMT_RX_FILTER_THRES_CH2_S 5 +/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_RX_FILTER_EN_CH2 (BIT(4)) +#define RMT_RX_FILTER_EN_CH2_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH2_V 0x1 +#define RMT_RX_FILTER_EN_CH2_S 4 +/* RMT_MEM_OWNER_CH2 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_OWNER_CH2 (BIT(3)) +#define RMT_MEM_OWNER_CH2_M (BIT(3)) +#define RMT_MEM_OWNER_CH2_V 0x1 +#define RMT_MEM_OWNER_CH2_S 3 +/* RMT_APB_MEM_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (BIT(2)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 2 +/* RMT_MEM_WR_RST_CH2 : WT ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define RMT_MEM_WR_RST_CH2 (BIT(1)) +#define RMT_MEM_WR_RST_CH2_M (BIT(1)) +#define RMT_MEM_WR_RST_CH2_V 0x1 +#define RMT_MEM_WR_RST_CH2_S 1 +/* RMT_RX_EN_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_RX_EN_CH2 (BIT(0)) +#define RMT_RX_EN_CH2_M (BIT(0)) +#define RMT_RX_EN_CH2_V 0x1 +#define RMT_RX_EN_CH2_S 0 + +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0020) +/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 29 +/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (BIT(28)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 28 +/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[25:23] ;default: 3'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH3 0x00000007 +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0x7 +#define RMT_MEM_SIZE_CH3_S 23 +/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ +/*description: */ +#define RMT_IDLE_THRES_CH3 0x00007FFF +#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) +#define RMT_IDLE_THRES_CH3_V 0x7FFF +#define RMT_IDLE_THRES_CH3_S 8 +/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 0 + +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x0024) +/* RMT_CONF_UPDATE_CH3 : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH3 (BIT(15)) +#define RMT_CONF_UPDATE_CH3_M (BIT(15)) +#define RMT_CONF_UPDATE_CH3_V 0x1 +#define RMT_CONF_UPDATE_CH3_S 15 +/* RMT_AFIFO_RST_CH3 : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH3 (BIT(14)) +#define RMT_AFIFO_RST_CH3_M (BIT(14)) +#define RMT_AFIFO_RST_CH3_V 0x1 +#define RMT_AFIFO_RST_CH3_S 14 +/* RMT_MEM_RX_WRAP_EN_CH3 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH3_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH3_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH3_S 13 +/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ +/*description: */ +#define RMT_RX_FILTER_THRES_CH3 0x000000FF +#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) +#define RMT_RX_FILTER_THRES_CH3_V 0xFF +#define RMT_RX_FILTER_THRES_CH3_S 5 +/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_RX_FILTER_EN_CH3 (BIT(4)) +#define RMT_RX_FILTER_EN_CH3_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH3_V 0x1 +#define RMT_RX_FILTER_EN_CH3_S 4 +/* RMT_MEM_OWNER_CH3 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_OWNER_CH3 (BIT(3)) +#define RMT_MEM_OWNER_CH3_M (BIT(3)) +#define RMT_MEM_OWNER_CH3_V 0x1 +#define RMT_MEM_OWNER_CH3_S 3 +/* RMT_APB_MEM_RST_CH3 : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (BIT(2)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 2 +/* RMT_MEM_WR_RST_CH3 : WT ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define RMT_MEM_WR_RST_CH3 (BIT(1)) +#define RMT_MEM_WR_RST_CH3_M (BIT(1)) +#define RMT_MEM_WR_RST_CH3_V 0x1 +#define RMT_MEM_WR_RST_CH3_S 1 +/* RMT_RX_EN_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_RX_EN_CH3 (BIT(0)) +#define RMT_RX_EN_CH3_M (BIT(0)) +#define RMT_RX_EN_CH3_V 0x1 +#define RMT_RX_EN_CH3_S 0 + +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0028) +/* RMT_APB_MEM_RADDR_CH0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH0 0x000000FF +#define RMT_APB_MEM_RADDR_CH0_M ((RMT_APB_MEM_RADDR_CH0_V)<<(RMT_APB_MEM_RADDR_CH0_S)) +#define RMT_APB_MEM_RADDR_CH0_V 0xFF +#define RMT_APB_MEM_RADDR_CH0_S 24 +/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH0_S 23 +/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_EMPTY_CH0 (BIT(22)) +#define RMT_MEM_EMPTY_CH0_M (BIT(22)) +#define RMT_MEM_EMPTY_CH0_V 0x1 +#define RMT_MEM_EMPTY_CH0_S 22 +/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH0 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH0_M (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH0_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH0_S 21 +/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WADDR_CH0 0x000001FF +#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V)<<(RMT_APB_MEM_WADDR_CH0_S)) +#define RMT_APB_MEM_WADDR_CH0_V 0x1FF +#define RMT_APB_MEM_WADDR_CH0_S 12 +/* RMT_STATE_CH0 : RO ;bitpos:[11:9] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH0 0x00000007 +#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S)) +#define RMT_STATE_CH0_V 0x7 +#define RMT_STATE_CH0_S 9 +/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: */ +#define RMT_MEM_RADDR_EX_CH0 0x000001FF +#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S)) +#define RMT_MEM_RADDR_EX_CH0_V 0x1FF +#define RMT_MEM_RADDR_EX_CH0_S 0 + +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x002c) +/* RMT_APB_MEM_RADDR_CH1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH1 0x000000FF +#define RMT_APB_MEM_RADDR_CH1_M ((RMT_APB_MEM_RADDR_CH1_V)<<(RMT_APB_MEM_RADDR_CH1_S)) +#define RMT_APB_MEM_RADDR_CH1_V 0xFF +#define RMT_APB_MEM_RADDR_CH1_S 24 +/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH1_S 23 +/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_EMPTY_CH1 (BIT(22)) +#define RMT_MEM_EMPTY_CH1_M (BIT(22)) +#define RMT_MEM_EMPTY_CH1_V 0x1 +#define RMT_MEM_EMPTY_CH1_S 22 +/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH1_M (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH1_S 21 +/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WADDR_CH1 0x000001FF +#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V)<<(RMT_APB_MEM_WADDR_CH1_S)) +#define RMT_APB_MEM_WADDR_CH1_V 0x1FF +#define RMT_APB_MEM_WADDR_CH1_S 12 +/* RMT_STATE_CH1 : RO ;bitpos:[11:9] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH1 0x00000007 +#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S)) +#define RMT_STATE_CH1_V 0x7 +#define RMT_STATE_CH1_S 9 +/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: */ +#define RMT_MEM_RADDR_EX_CH1 0x000001FF +#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S)) +#define RMT_MEM_RADDR_EX_CH1_V 0x1FF +#define RMT_MEM_RADDR_EX_CH1_S 0 + +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0030) +/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH2_S 27 +/* RMT_MEM_FULL_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FULL_CH2 (BIT(26)) +#define RMT_MEM_FULL_CH2_M (BIT(26)) +#define RMT_MEM_FULL_CH2_V 0x1 +#define RMT_MEM_FULL_CH2_S 26 +/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_OWNER_ERR_CH2 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH2_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH2_V 0x1 +#define RMT_MEM_OWNER_ERR_CH2_S 25 +/* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH2 0x00000007 +#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S)) +#define RMT_STATE_CH2_V 0x7 +#define RMT_STATE_CH2_S 22 +/* RMT_APB_MEM_RADDR_CH2 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH2 0x000001FF +#define RMT_APB_MEM_RADDR_CH2_M ((RMT_APB_MEM_RADDR_CH2_V)<<(RMT_APB_MEM_RADDR_CH2_S)) +#define RMT_APB_MEM_RADDR_CH2_V 0x1FF +#define RMT_APB_MEM_RADDR_CH2_S 12 +/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: */ +#define RMT_MEM_WADDR_EX_CH2 0x000001FF +#define RMT_MEM_WADDR_EX_CH2_M ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S)) +#define RMT_MEM_WADDR_EX_CH2_V 0x1FF +#define RMT_MEM_WADDR_EX_CH2_S 0 + +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x0034) +/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH3_S 27 +/* RMT_MEM_FULL_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FULL_CH3 (BIT(26)) +#define RMT_MEM_FULL_CH3_M (BIT(26)) +#define RMT_MEM_FULL_CH3_V 0x1 +#define RMT_MEM_FULL_CH3_S 26 +/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_OWNER_ERR_CH3 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH3_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH3_V 0x1 +#define RMT_MEM_OWNER_ERR_CH3_S 25 +/* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH3 0x00000007 +#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S)) +#define RMT_STATE_CH3_V 0x7 +#define RMT_STATE_CH3_S 22 +/* RMT_APB_MEM_RADDR_CH3 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH3 0x000001FF +#define RMT_APB_MEM_RADDR_CH3_M ((RMT_APB_MEM_RADDR_CH3_V)<<(RMT_APB_MEM_RADDR_CH3_S)) +#define RMT_APB_MEM_RADDR_CH3_V 0x1FF +#define RMT_APB_MEM_RADDR_CH3_S 12 +/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: */ +#define RMT_MEM_WADDR_EX_CH3 0x000001FF +#define RMT_MEM_WADDR_EX_CH3_M ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S)) +#define RMT_MEM_WADDR_EX_CH3_V 0x1FF +#define RMT_MEM_WADDR_EX_CH3_S 0 + +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x0038) +/* RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 +/* RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/* RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 11 +/* RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/* RMT_CH3_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 7 +/* RMT_CH2_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 6 +/* RMT_CH1_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 +/* RMT_CH0_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 4 +/* RMT_CH3_RX_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_END_INT_RAW (BIT(3)) +#define RMT_CH3_RX_END_INT_RAW_M (BIT(3)) +#define RMT_CH3_RX_END_INT_RAW_V 0x1 +#define RMT_CH3_RX_END_INT_RAW_S 3 +/* RMT_CH2_RX_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_END_INT_RAW (BIT(2)) +#define RMT_CH2_RX_END_INT_RAW_M (BIT(2)) +#define RMT_CH2_RX_END_INT_RAW_V 0x1 +#define RMT_CH2_RX_END_INT_RAW_S 2 +/* RMT_CH1_TX_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 1 +/* RMT_CH0_TX_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 + +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x003c) +/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH1_TX_LOOP_INT_ST_S 13 +/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/* RMT_CH3_RX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ST_M (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_RX_THR_EVENT_INT_ST_S 11 +/* RMT_CH2_RX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ST_M (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_RX_THR_EVENT_INT_ST_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (BIT(7)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 7 +/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (BIT(6)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 6 +/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 +/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (BIT(4)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 4 +/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_END_INT_ST (BIT(3)) +#define RMT_CH3_RX_END_INT_ST_M (BIT(3)) +#define RMT_CH3_RX_END_INT_ST_V 0x1 +#define RMT_CH3_RX_END_INT_ST_S 3 +/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_END_INT_ST (BIT(2)) +#define RMT_CH2_RX_END_INT_ST_M (BIT(2)) +#define RMT_CH2_RX_END_INT_ST_V 0x1 +#define RMT_CH2_RX_END_INT_ST_S 2 +/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 1 +/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 + +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x0040) +/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 +/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/* RMT_CH3_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 11 +/* RMT_CH2_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 7 +/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 6 +/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 +/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 4 +/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_END_INT_ENA (BIT(3)) +#define RMT_CH3_RX_END_INT_ENA_M (BIT(3)) +#define RMT_CH3_RX_END_INT_ENA_V 0x1 +#define RMT_CH3_RX_END_INT_ENA_S 3 +/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_END_INT_ENA (BIT(2)) +#define RMT_CH2_RX_END_INT_ENA_M (BIT(2)) +#define RMT_CH2_RX_END_INT_ENA_V 0x1 +#define RMT_CH2_RX_END_INT_ENA_S 2 +/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 1 +/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 + +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x0044) +/* RMT_CH1_TX_LOOP_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 +/* RMT_CH0_TX_LOOP_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/* RMT_CH3_RX_THR_EVENT_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 11 +/* RMT_CH2_RX_THR_EVENT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/* RMT_CH3_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 7 +/* RMT_CH2_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 6 +/* RMT_CH1_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 +/* RMT_CH0_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 4 +/* RMT_CH3_RX_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_RX_END_INT_CLR (BIT(3)) +#define RMT_CH3_RX_END_INT_CLR_M (BIT(3)) +#define RMT_CH3_RX_END_INT_CLR_V 0x1 +#define RMT_CH3_RX_END_INT_CLR_S 3 +/* RMT_CH2_RX_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_RX_END_INT_CLR (BIT(2)) +#define RMT_CH2_RX_END_INT_CLR_M (BIT(2)) +#define RMT_CH2_RX_END_INT_CLR_V 0x1 +#define RMT_CH2_RX_END_INT_CLR_S 2 +/* RMT_CH1_TX_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 1 +/* RMT_CH0_TX_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 + +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0048) +/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 +/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 + +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x004c) +/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 +/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 + +#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0050) +/* RMT_CARRIER_HIGH_THRES_CH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH2_M ((RMT_CARRIER_HIGH_THRES_CH2_V)<<(RMT_CARRIER_HIGH_THRES_CH2_S)) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 +/* RMT_CARRIER_LOW_THRES_CH2 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH2_M ((RMT_CARRIER_LOW_THRES_CH2_V)<<(RMT_CARRIER_LOW_THRES_CH2_S)) +#define RMT_CARRIER_LOW_THRES_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH2_S 0 + +#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0054) +/* RMT_CARRIER_HIGH_THRES_CH3 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH3_M ((RMT_CARRIER_HIGH_THRES_CH3_V)<<(RMT_CARRIER_HIGH_THRES_CH3_S)) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 +/* RMT_CARRIER_LOW_THRES_CH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH3_M ((RMT_CARRIER_LOW_THRES_CH3_V)<<(RMT_CARRIER_LOW_THRES_CH3_S)) +#define RMT_CARRIER_LOW_THRES_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH3_S 0 + +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x0058) +/* RMT_LOOP_COUNT_RESET_CH0 : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FF +#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V)<<(RMT_TX_LOOP_NUM_CH0_S)) +#define RMT_TX_LOOP_NUM_CH0_V 0x3FF +#define RMT_TX_LOOP_NUM_CH0_S 9 +/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 + +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x005c) +/* RMT_LOOP_COUNT_RESET_CH1 : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FF +#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V)<<(RMT_TX_LOOP_NUM_CH1_S)) +#define RMT_TX_LOOP_NUM_CH1_V 0x3FF +#define RMT_TX_LOOP_NUM_CH1_S 9 +/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 + +#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x0060) +/* RMT_RX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_RX_LIM_CH2 0x000001FF +#define RMT_RX_LIM_CH2_M ((RMT_RX_LIM_CH2_V)<<(RMT_RX_LIM_CH2_S)) +#define RMT_RX_LIM_CH2_V 0x1FF +#define RMT_RX_LIM_CH2_S 0 + +#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x0064) +/* RMT_RX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_RX_LIM_CH3 0x000001FF +#define RMT_RX_LIM_CH3_M ((RMT_RX_LIM_CH3_V)<<(RMT_RX_LIM_CH3_S)) +#define RMT_RX_LIM_CH3_V 0x1FF +#define RMT_RX_LIM_CH3_S 0 + +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x0068) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */ +/*description: */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (BIT(26)) +#define RMT_SCLK_ACTIVE_V 0x1 +#define RMT_SCLK_ACTIVE_S 26 +/* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */ +/*description: */ +#define RMT_SCLK_SEL 0x00000003 +#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V)<<(RMT_SCLK_SEL_S)) +#define RMT_SCLK_SEL_V 0x3 +#define RMT_SCLK_SEL_S 24 +/* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */ +/*description: */ +#define RMT_SCLK_DIV_B 0x0000003F +#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V)<<(RMT_SCLK_DIV_B_S)) +#define RMT_SCLK_DIV_B_V 0x3F +#define RMT_SCLK_DIV_B_S 18 +/* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */ +/*description: */ +#define RMT_SCLK_DIV_A 0x0000003F +#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V)<<(RMT_SCLK_DIV_A_S)) +#define RMT_SCLK_DIV_A_V 0x3F +#define RMT_SCLK_DIV_A_S 12 +/* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */ +/*description: */ +#define RMT_SCLK_DIV_NUM 0x000000FF +#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V)<<(RMT_SCLK_DIV_NUM_S)) +#define RMT_SCLK_DIV_NUM_V 0xFF +#define RMT_SCLK_DIV_NUM_S 4 +/* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (BIT(3)) +#define RMT_MEM_FORCE_PU_V 0x1 +#define RMT_MEM_FORCE_PU_S 3 +/* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (BIT(2)) +#define RMT_MEM_FORCE_PD_V 0x1 +#define RMT_MEM_FORCE_PD_S 2 +/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_V 0x1 +#define RMT_MEM_CLK_FORCE_ON_S 1 +/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 + +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x006c) +/* RMT_TX_SIM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_EN (BIT(2)) +#define RMT_TX_SIM_EN_M (BIT(2)) +#define RMT_TX_SIM_EN_V 0x1 +#define RMT_TX_SIM_EN_S 2 +/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (BIT(1)) +#define RMT_TX_SIM_CH1_V 0x1 +#define RMT_TX_SIM_CH1_S 1 +/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (BIT(0)) +#define RMT_TX_SIM_CH0_V 0x1 +#define RMT_TX_SIM_CH0_S 0 + +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x0070) +/* RMT_REF_CNT_RST_CH3 : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (BIT(3)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 3 +/* RMT_REF_CNT_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (BIT(2)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 2 +/* RMT_REF_CNT_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (BIT(1)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 1 +/* RMT_REF_CNT_RST_CH0 : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (BIT(0)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00cc) +/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006231 ; */ +/*description: */ +#define RMT_DATE 0x0FFFFFFF +#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFF +#define RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_RMT_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rmt_struct.h b/components/soc/esp32h2/include/soc/rmt_struct.h new file mode 100644 index 0000000000..7fc1890b12 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rmt_struct.h @@ -0,0 +1,308 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_STRUCT_H_ +#define _SOC_RMT_STRUCT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + uint32_t data_ch[4]; /**/ + union { + struct { + uint32_t tx_start: 1; + uint32_t mem_rd_rst: 1; + uint32_t mem_rst: 1; + uint32_t tx_conti_mode: 1; + uint32_t mem_tx_wrap_en: 1; + uint32_t idle_out_lv: 1; + uint32_t idle_out_en: 1; + uint32_t tx_stop: 1; + uint32_t div_cnt: 8; + uint32_t mem_size: 3; + uint32_t reserved19: 1; + uint32_t carrier_eff_en: 1; + uint32_t carrier_en: 1; + uint32_t carrier_out_lv: 1; + uint32_t afifo_rst: 1; + uint32_t conf_update: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } tx_conf[2]; + struct { + union { + struct { + uint32_t div_cnt: 8; + uint32_t idle_thres: 15; + uint32_t mem_size: 3; + uint32_t reserved26: 2; + uint32_t carrier_en: 1; + uint32_t carrier_out_lv: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rx_en: 1; + uint32_t mem_wr_rst: 1; + uint32_t mem_rst: 1; + uint32_t mem_owner: 1; + uint32_t rx_filter_en: 1; + uint32_t rx_filter_thres: 8; + uint32_t mem_rx_wrap_en: 1; + uint32_t afifo_rst: 1; + uint32_t conf_update: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } conf1; + } rx_conf[2]; + union { + struct { + uint32_t mem_raddr_ex: 9; + uint32_t state: 3; + uint32_t waddr: 9; + uint32_t mem_rd_err: 1; + uint32_t mem_empty: 1; + uint32_t mem_wr_err: 1; + uint32_t raddr: 8; + }; + uint32_t val; + } tx_status[2]; + union { + struct { + uint32_t mem_waddr_ex: 9; + uint32_t reserved9: 3; + uint32_t mem_raddr: 9; + uint32_t reserved21: 1; + uint32_t state: 3; + uint32_t mem_owner_err: 1; + uint32_t mem_full: 1; + uint32_t mem_rd_err: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } rx_status[2]; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_rx_end: 1; + uint32_t ch3_rx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_rx_thr_event: 1; + uint32_t ch3_rx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_rx_end: 1; + uint32_t ch3_rx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_rx_thr_event: 1; + uint32_t ch3_rx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_rx_end: 1; + uint32_t ch3_rx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_rx_thr_event: 1; + uint32_t ch3_rx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_rx_end: 1; + uint32_t ch3_rx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_rx_thr_event: 1; + uint32_t ch3_rx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t low: 16; + uint32_t high: 16; + }; + uint32_t val; + } tx_carrier[2]; + union { + struct { + uint32_t low_thres: 16; + uint32_t high_thres: 16; + }; + uint32_t val; + } rx_carrier[2]; + union { + struct { + uint32_t limit: 9; + uint32_t tx_loop_num: 10; + uint32_t tx_loop_cnt_en: 1; + uint32_t loop_count_reset: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } tx_lim[2]; + union { + struct { + uint32_t rx_lim: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } rx_lim[2]; + union { + struct { + uint32_t fifo_mask: 1; + uint32_t mem_clk_force_on: 1; + uint32_t mem_force_pd: 1; + uint32_t mem_force_pu: 1; + uint32_t sclk_div_num: 8; + uint32_t sclk_div_a: 6; + uint32_t sclk_div_b: 6; + uint32_t sclk_sel: 2; + uint32_t sclk_active: 1; + uint32_t reserved27: 4; + uint32_t clk_en: 1; + }; + uint32_t val; + } sys_conf; + union { + struct { + uint32_t ch0: 1; + uint32_t ch1: 1; + uint32_t en: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } tx_sim; + union { + struct { + uint32_t ch0: 1; + uint32_t ch1: 1; + uint32_t ch2: 1; + uint32_t ch3: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } ref_cnt_rst; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +typedef struct { + union { + struct { + uint32_t duration0 : 15; + uint32_t level0 : 1; + uint32_t duration1 : 15; + uint32_t level1 : 1; + }; + uint32_t val; + }; +} rmt_item32_t; + +//Allow access to RMT memory using RMTMEM.chan[0].data32[8] +typedef volatile struct { + struct { + union { + rmt_item32_t data32[48]; + }; + } chan[4]; +} rmt_mem_t; + +extern rmt_mem_t RMTMEM; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h new file mode 100644 index 0000000000..3fda6cb8a7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -0,0 +1,861 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +#define RTC_SLOW_CLK_FREQ_150K 150000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias +#define RTC_CNTL_DBIAS_0V90 13 //digital voltage +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact + +#define DELAY_FAST_CLK_SWITCH 3 +#define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + +/* Number of 8M/256 clock cycles to use for XTAL frequency estimation. + * 10 cycles will take approximately 300 microseconds. + */ +#define XTAL_FREQ_EST_CYCLES 10 + +#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 + +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_32M = 32, + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU frequency values + */ +typedef enum { + RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency + RTC_CPU_FREQ_80M = 1, //!< 80 MHz + RTC_CPU_FREQ_160M = 2, //!< 160 MHz + RTC_CPU_FREQ_240M = 3, //!< 240 MHz + RTC_CPU_FREQ_2M = 4, //!< 2 MHz + RTC_CPU_320M_80M = 5, //!< for test + RTC_CPU_320M_160M = 6, //!< for test + RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset +} rtc_cpu_freq_t; + +/** + * @brief CPU clock source + */ +typedef enum { + RTC_CPU_FREQ_SRC_XTAL, //!< XTAL + RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) + RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator + RTC_CPU_FREQ_SRC_APLL //!< APLL +} rtc_cpu_freq_src_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef enum { + RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator + RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL + RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 +} rtc_slow_freq_t; + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef enum { + RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 + RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator +} rtc_fast_freq_t; + +/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ +#define RTC_FAST_CLK_FREQ_APPROX 8500000 + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set + rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = RTC_XTAL_FREQ_40M, \ + .cpu_freq_mhz = 80, \ + .fast_freq = RTC_FAST_FREQ_8M, \ + .slow_freq = RTC_SLOW_FREQ_RTC, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +typedef struct { + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +} x32k_config_t; + +#define X32K_CONFIG_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 3, \ + .dbuf = 1, \ +} + +typedef struct { + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t bt_powerup_cycles : 7; + uint16_t bt_wait_cycles : 9; + uint16_t cpu_top_powerup_cycles : 7; + uint16_t cpu_top_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t dg_peri_powerup_cycles : 7; + uint16_t dg_peri_wait_cycles : 9; +} rtc_init_config_t; + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ + .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + +void rtc_clk_divider_set(uint32_t div); + +void rtc_clk_8m_divider_set(uint32_t div); + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(void); + +/** + * @brief Enable or disable APLL + * + * Output frequency is given by the formula: + * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) + * + * The dividend in this expression should be in the range of 240 - 600 MHz. + * + * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0. + * + * @param enable true to enable, false to disable + * @param sdm0 frequency adjustment parameter, 0..255 + * @param sdm1 frequency adjustment parameter, 0..255 + * @param sdm2 frequency adjustment parameter, 0..63 + * @param o_div frequency divider, 0..31 + */ +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param slow_freq clock source (one of rtc_slow_freq_t values) + */ +void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of rtc_slow_freq_t values) + */ +rtc_slow_freq_t rtc_clk_slow_freq_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 + * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 + * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param fast_freq clock source (one of rtc_fast_freq_t values) + */ +void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of rtc_fast_freq_t values) + */ +rtc_fast_freq_t rtc_clk_fast_freq_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Measure ratio between XTAL frequency and RTC slow clock frequency + * @param cal_clk slow clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average ratio between XTAL frequency and slow clock frequency, + * Q13.19 fixed point format, or 0 if calibration has timed out. + */ +uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +uint64_t rtc_light_slp_time_get(void); + +uint64_t rtc_deep_slp_time_get(void); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(void); + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +void rtc_dig_clk8m_enable(void); + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +void rtc_dig_clk8m_disable(void); + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +uint32_t rtc_clk_freq_cal(uint32_t cal_val); + +/** + * @brief Power down flags for rtc_sleep_pd function + */ +typedef struct { + uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep + uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep + uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep + uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep + uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep + uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep +} rtc_sleep_pu_config_t; + +/** + * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value + */ +#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ + .sram_fpu = (val), \ + .rom_ram_fpu = (val), \ +} + +void rtc_sleep_pu(rtc_sleep_pu_config_t cfg); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t bt_pd_en : 1; //!< power down BT + uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. + uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator + uint32_t deep_slp_reject : 1; + uint32_t light_slp_reject : 1; +} rtc_sleep_config_t; + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ + .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ + .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ + .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_SLP, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_SLP, \ + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ + .deep_slp_reject = 1, \ + .light_slp_reject = 1 \ +}; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU +#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator +#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI +#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT +#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart +#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + +/** + * @brief Low level initialize for rtc state machine waiting cycles after waking up + * + * This function configures the cycles chip need to wait for internal 8MHz + * oscillator and external 40MHz crystal. As we configure fixed time for waiting + * crystal, we need to pass period to calculate cycles. Now this function only + * used in lightsleep mode. + * + * @param slowclk_period re-calibrated slow clock period + */ +void rtc_sleep_low_init(uint32_t slowclk_period); + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_USB_TRIG_EN BIT(14) +#define RTC_BROWNOUT_DET_TRIG_EN BIT(16) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); + +/** + * @brief Enter deep sleep mode + * + * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value + * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake + * stub is valid to execute (if a wake address is set). + * + * No RAM is accessed while calculating the CRC and going into deep sleep, which makes + * this function safe to use even if the caller's stack is in RTC FAST memory. + * + * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will + * have the same effect and takes less time as CRC calculation is skipped. + * + * @note This function should only be called after rtc_sleep_init() has been called to + * configure the system for deep sleep. + * + * @param wakeup_opt - same as for rtc_sleep_start + * @param reject_opt - same as for rtc_sleep_start + * + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; + uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise. +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1, \ + .cali_ocode = 0\ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + +/** + * Structure describing vddsdio configuration + */ +typedef struct { + uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. + uint32_t enable : 1; //!< Enable VDDSDIO regulator + uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator +} rtc_vddsdio_config_t; + +/** + * Get current VDDSDIO configuration + * If VDDSDIO configuration is overridden by RTC, get values from RTC + * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE + * Otherwise, use default values and the level of MTDI bootstrapping pin. + * @return currently used VDDSDIO configuration + */ +rtc_vddsdio_config_t rtc_vddsdio_get_config(void); + +/** + * Set new VDDSDIO configuration using RTC registers. + * If config.force == 1, this overrides configuration done using bootstrapping + * pins and EFUSE. + * + * @param config new VDDSDIO configuration + */ +void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_reg.h b/components/soc/esp32h2/include/soc/rtc_cntl_reg.h new file mode 100644 index 0000000000..b25f644832 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc_cntl_reg.h @@ -0,0 +1,2647 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_REG_H_ +#define _SOC_RTC_CNTL_REG_H_ + +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ +#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 +/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ +#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ +#define RTC_WDT_RESET_LENGTH_100_NS 0 +#define RTC_WDT_RESET_LENGTH_200_NS 1 +#define RTC_WDT_RESET_LENGTH_300_NS 2 +#define RTC_WDT_RESET_LENGTH_400_NS 3 +#define RTC_WDT_RESET_LENGTH_500_NS 4 +#define RTC_WDT_RESET_LENGTH_800_NS 5 +#define RTC_WDT_RESET_LENGTH_1600_NS 6 +#define RTC_WDT_RESET_LENGTH_3200_NS 7 + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 +#define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) +#define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 +#define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: enable to record system reset time*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Enable to record 40M XTAL OFF time*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable to record system stall time*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: leep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: leep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear rtc sleep reject cause*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rtc software interrupt to main cpu*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) +#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_BT_POWERUP_TIMER_S 25 +/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) +#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_BT_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 +/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) +#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_PU_S 22 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) +/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_PROCPU_S 25 +/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_APPCPU_S 24 +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 +/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 +/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 +/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: PROCPU OcdHaltOnReset*/ +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 +/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: APPCPU OcdHaltOnReset*/ +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 +/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: clear APP CPU reset flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 +/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: clear PRO CPU reset_flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 +/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: APP CPU reset flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 +/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: PRO CPU reset_flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 +/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 +/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt raw*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt raw*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Clear super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: XTAL_32K sel. 0: external XTAL_32K*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ +/*description: DAC_XTAL_32K*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: XPD_XTAL_32K*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ +/*description: DRES_XTAL_32K*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: xtal_32k gm control*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 0: single-end buffer 1: differential buffer*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: apply an internal clock to help xtal 32k to start*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Xtal 32k xpd control by sw or fsm*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: xtal 32k switch back xtal when xtal is restarted*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: xtal 32k restart xtal when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: xtal 32k switch to back up clock when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: xtal 32k external xtal clock force on*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog sw reset*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog clock force on*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog enable*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ +/*description: sleep reject enable*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: */ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 +/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 +/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: enable current limit*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: select current limit mode*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: 0 to set init[1:0]=0*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ +/*description: add resistor from ldo output to ground. 0: no res*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ +/*description: ability to prevent LDO from overshoot*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: timer count to apply reg_sdio_dcap after sdio power on*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 +/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8 +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 0 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 + +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 +/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_V 0x1 +#define RTC_CNTL_DIG_CAL_EN_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0084) +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: rtc pad force hold*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 +#define RTC_CNTL_CPU_TOP_PD_EN_S 29 +/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 +#define RTC_CNTL_DG_PERI_PD_EN_S 28 +/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BT_PD_EN (BIT(27)) +#define RTC_CNTL_BT_PD_EN_M (BIT(27)) +#define RTC_CNTL_BT_PD_EN_V 0x1 +#define RTC_CNTL_BT_PD_EN_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 +/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 +/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 +/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 +/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_V 0x1 +#define RTC_CNTL_BT_FORCE_PU_S 12 +/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_V 0x1 +#define RTC_CNTL_BT_FORCE_PD_S 11 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 +/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 +#define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 +/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 +#define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) +#define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 +#define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x008C) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: cpu force no ISO*/ +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: cpu force ISO*/ +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 +/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 +/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 +/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 +#define RTC_CNTL_BT_FORCE_NOISO_S 23 +/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_V 0x1 +#define RTC_CNTL_BT_FORCE_ISO_S 22 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: wdt reset whole chip enable*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ +/*description: chip reset siginal pulse width*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0094) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x0098) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x009C) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: automatically feed swd when int comes*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: disabel SWD*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Sw feed swd*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reset swd reset flag*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ +/*description: adjust signal width send to swd*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 +#define RTC_CNTL_SWD_BYPASS_RST_S 17 +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: swd interrupt for feeding*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: swd reset flag*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ +/*description: */ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: */ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0]*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: rtc main state machine status*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: rtc main state machine is in idle state*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: rtc main state machine is in sleep state*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait xtal state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait pll state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait 8m state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of low power*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of wakeup process*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: rtc main state machine has been waited for some cycles*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: rtc is ready to receive wake up trigger from wake up source*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc main state machine is in states that pll should be running*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: no use any more*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: ulp/cocpu is done*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: ulp/cocpu is in sleep state*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: ulp/cocpu is about to working. Switch rtc main state*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: ulp/cocpu should start to work*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: touch is done*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: touch is in sleep state*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: touch is about to working. Switch rtc main state*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch should start to work*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: digital wrap power down*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: digital wrap iso*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: wifi wrap power down*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: wifi iso*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc peripheral power down*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc peripheral iso*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: External DCDC power down*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rom0 power down*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN5_HOLD_S 5 +/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN4_HOLD_S 4 +/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN3_HOLD_S 3 +/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN2_HOLD_S 2 +/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN1_HOLD_S 1 +/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: clear brown out counter*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ +/*description: brown out interrupt wait cycles*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: xtal 32k watch dog backup clock factor*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: if restarted xtal32k period is smaller than this*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ +/*description: If no clock detected for this amount of time*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ +/*description: cycles to wait to repower on xtal 32k*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: cycles to wait to return noral xtal 32k*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F0) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F8) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0100) +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 +/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 + +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0104) +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 +/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 + +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0108) +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ +/*description: wait cycles for rention operation*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000001F +#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) +#define RTC_CNTL_RETENTION_WAIT_V 0x1F +#define RTC_CNTL_RETENTION_WAIT_S 27 +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_EN (BIT(26)) +#define RTC_CNTL_RETENTION_EN_M (BIT(26)) +#define RTC_CNTL_RETENTION_EN_V 0x1 +#define RTC_CNTL_RETENTION_EN_S 26 +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) +#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 +#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 +#define RTC_CNTL_RETENTION_CLK_SEL_S 18 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: select use analog fib signal*/ +#define RTC_CNTL_FIB_SEL 0x00000007 +#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) +#define RTC_CNTL_FIB_SEL_V 0x7 +#define RTC_CNTL_FIB_SEL_S 0 + +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + +#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) +/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 +/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 +/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 +/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 +/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 +/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 +/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 +/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 +/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 +/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 +/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 +/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 +/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 +#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 +/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 +/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 + +#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0114) +/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL4 0x0000001F +#define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) +#define RTC_CNTL_DEBUG_SEL4_V 0x1F +#define RTC_CNTL_DEBUG_SEL4_S 27 +/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL3 0x0000001F +#define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) +#define RTC_CNTL_DEBUG_SEL3_V 0x1F +#define RTC_CNTL_DEBUG_SEL3_S 22 +/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL2 0x0000001F +#define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) +#define RTC_CNTL_DEBUG_SEL2_V 0x1F +#define RTC_CNTL_DEBUG_SEL2_S 17 +/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL1 0x0000001F +#define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) +#define RTC_CNTL_DEBUG_SEL1_V 0x1F +#define RTC_CNTL_DEBUG_SEL1_S 12 +/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL0 0x0000001F +#define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) +#define RTC_CNTL_DEBUG_SEL0_V 0x1F +#define RTC_CNTL_DEBUG_SEL0_S 7 +/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F +#define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) +#define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F +#define RTC_CNTL_DEBUG_BIT_SEL_S 2 +/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 + +#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0118) +/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 +/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 +/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 +/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 +/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 +/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 +/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 +/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 +/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 +/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 +/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 +/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 + +#define RTC_CNTL_SENSOR_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011C) +/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_XPD_SAR 0x00000003 +#define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S)) +#define RTC_CNTL_FORCE_XPD_SAR_V 0x3 +#define RTC_CNTL_FORCE_XPD_SAR_S 30 +/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_SAR2_PWDET_CCT 0x00000007 +#define RTC_CNTL_SAR2_PWDET_CCT_M ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S)) +#define RTC_CNTL_SAR2_PWDET_CCT_V 0x7 +#define RTC_CNTL_SAR2_PWDET_CCT_S 27 + +#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F +#define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) +#define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F +#define RTC_CNTL_SAR_DEBUG_SEL_S 27 + +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0124) +/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EN_S 31 +/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 +/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 +/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 +/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 +#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) +#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 +#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_RTC_CNTL_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h b/components/soc/esp32h2/include/soc/rtc_cntl_struct.h new file mode 100644 index 0000000000..358ebaded7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc_cntl_struct.h @@ -0,0 +1,843 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ + uint32_t reserved18: 2; + uint32_t ctr_sel: 3; + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; /**/ + union { + struct { + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0: 27; + uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ + uint32_t reserved30: 1; + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time_low0; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time_high0; + union { + struct { + uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ + uint32_t reserved2: 20; + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ + uint32_t reserved23: 5; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*leep wakeup bit*/ + uint32_t slp_reject: 1; /*leep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0: 24; + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t bt_wait_timer: 9; + uint32_t bt_powerup_timer: 7; + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t cpu_top_wait_timer: 9; + uint32_t cpu_top_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t reserved0: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0: 16; + uint32_t dg_peri_wait_timer: 9; + uint32_t dg_peri_powerup_timer: 7; + }; + uint32_t val; + } timer6; + union { + struct { + uint32_t reserved0: 18; + uint32_t i2c_reset_por_force_pd: 1; + uint32_t i2c_reset_por_force_pu: 1; + uint32_t glitch_rst_en: 1; + uint32_t reserved21: 1; /*PLLA force power down*/ + uint32_t sar_i2c_pu: 1; /*PLLA force power up*/ + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ + uint32_t pll_i2c_pu: 1; + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t stat_vector_sel_appcpu: 1; /*APP CPU state vector sel*/ + uint32_t stat_vector_sel_procpu: 1; /*PRO CPU state vector sel*/ + uint32_t all_reset_flag_procpu: 1; /*PRO CPU reset_flag*/ + uint32_t all_reset_flag_appcpu: 1; /*APP CPU reset flag*/ + uint32_t all_reset_flag_clr_procpu: 1; /*clear PRO CPU reset_flag*/ + uint32_t all_reset_flag_clr_appcpu: 1; /*clear APP CPU reset flag*/ + uint32_t ocd_halt_on_reset_appcpu: 1; /*APPCPU OcdHaltOnReset*/ + uint32_t ocd_halt_on_reset_procpu: 1; /*PROCPU OcdHaltOnReset*/ + uint32_t jtag_reset_flag_procpu: 1; + uint32_t jtag_reset_flag_appcpu: 1; + uint32_t jtag_reset_flag_clr_procpu: 1; + uint32_t jtag_reset_flag_clr_appcpu: 1; + uint32_t rtc_dreset_mask_appcpu: 1; + uint32_t rtc_dreset_mask_procpu: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t reserved0: 15; + uint32_t rtc_wakeup_ena:17; /*wakeup enable bitmap*/ + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t reserved2: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4: 5; + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11: 4; /*enable saradc2 interrupt*/ + uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17: 2; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t reserved2: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t reserved4: 5; /*touch inactive interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t reserved11: 4; /*saradc2 interrupt raw*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ + uint32_t reserved17: 2; /*touch timeout interrupt raw*/ + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t reserved4: 5; + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t reserved11: 4; + uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t reserved4: 5; + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved11: 4; + uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_clr; + uint32_t store[4]; /**/ + union { + struct { + uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ + uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ + uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ + uint32_t reserved24: 6; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ + uint32_t ctr_en: 1; + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0: 31; + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0: 12; + uint32_t rtc_sleep_reject_ena:18; /*sleep reject enable*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t reserved0: 1; + uint32_t efuse_clk_force_gating: 1; + uint32_t efuse_clk_force_nogating: 1; + uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t reserved11: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t xtal_global_force_gating: 1; + uint32_t xtal_global_force_nogating: 1; + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ + uint32_t ana_clk_rtc_sel: 2; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ + uint32_t rtc_ana_clk_div: 8; + uint32_t slow_clk_next_edge: 1; + }; + uint32_t val; + } slow_clk_conf; + union { + struct { + uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t reserved8: 1; + uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ + uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ + uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim: 1; /*select current limit mode*/ + uint32_t sdio_encurlim: 1; /*enable current limit*/ + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t dg_vdd_drv_b_slp: 8; + uint32_t dg_vdd_drv_b_slp_en: 1; + uint32_t reserved9: 1; + uint32_t bias_buf_idle: 1; + uint32_t bias_buf_wake: 1; + uint32_t bias_buf_deep_slp: 1; + uint32_t bias_buf_monitor: 1; + uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ + uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ + uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ + uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ + uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ + uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_cal_en: 1; + uint32_t reserved8: 6; + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t reserved22: 6; + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtculator_force_pu: 1; + }; + uint32_t val; + } rtc; + union { + struct { + uint32_t reserved0: 21; + uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ + uint32_t reserved22: 10; + }; + uint32_t val; + } rtc_pwc; + union { + struct { + uint32_t vdd_spi_pwr_drv: 2; + uint32_t vdd_spi_pwr_force: 1; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t reserved5: 6; + uint32_t bt_force_pd: 1; + uint32_t bt_force_pu: 1; + uint32_t dg_peri_force_pd: 1; + uint32_t dg_peri_force_pu: 1; + uint32_t fastmem_force_lpd: 1; + uint32_t fastmem_force_lpu: 1; + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t cpu_top_force_pd: 1; + uint32_t cpu_top_force_pu: 1; + uint32_t reserved23: 4; + uint32_t bt_pd_en: 1; + uint32_t dg_peri_pd_en: 1; + uint32_t cpu_top_pd_en: 1; + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t reserved16: 6; + uint32_t bt_force_iso: 1; + uint32_t bt_force_noiso: 1; + uint32_t dg_peri_force_iso: 1; + uint32_t dg_peri_force_noiso: 1; + uint32_t cpu_top_force_iso: 1; /*cpu force ISO*/ + uint32_t cpu_top_force_noiso: 1; /*cpu force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t stg3: 3; /*1: interrupt stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en*/ + uint32_t en: 1; + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + union { + struct { + uint32_t reserved0: 31; + uint32_t feed: 1; + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t swd_reset_flag: 1; /*swd reset flag*/ + uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ + uint32_t reserved2: 15; + uint32_t swd_bypass_rst: 1; + uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ + uint32_t swd_feed: 1; /*Sw feed swd*/ + uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ + }; + uint32_t val; + } swd_conf; + uint32_t swd_wprotect; /**/ + union { + struct { + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ + uint32_t procpu_c1: 6; + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; /**/ + uint32_t store5; /**/ + uint32_t store6; /**/ + uint32_t store7; /**/ + union { + struct { + uint32_t xpd_rom0: 1; /*rom0 power down*/ + uint32_t reserved1: 1; + uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ + uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ + uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ + uint32_t wifi_iso: 1; /*wifi iso*/ + uint32_t xpd_wifi: 1; /*wifi wrap power down*/ + uint32_t dig_iso: 1; /*digital wrap iso*/ + uint32_t xpd_dig: 1; /*digital wrap power down*/ + uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ + uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ + uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done: 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ + uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ + uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ + uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ + uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ + uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ + uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ + uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ + uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ + uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ + uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ + uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ + uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ + uint32_t rtc_main_state: 4; /*rtc main state machine status*/ + }; + uint32_t val; + } low_power_st; + uint32_t diag0; /**/ + union { + struct { + uint32_t rtc_gpio_pin0_hold: 1; + uint32_t rtc_gpio_pin1_hold: 1; + uint32_t rtc_gpio_pin2_hold: 1; + uint32_t rtc_gpio_pin3_hold: 1; + uint32_t rtc_gpio_pin4_hold: 1; + uint32_t rtc_gpio_pin5_hold: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } pad_hold; + uint32_t dig_pad_hold; /**/ + union { + struct { + uint32_t reserved0: 4; + uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t rst_sel: 1; /*1: 4-pos reset*/ + uint32_t ana_rst_en: 1; + uint32_t cnt_clr: 1; /*clear brown out counter*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; + }; + uint32_t val; + } brown_out; + uint32_t time_low1; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time_high1; + uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ + union { + struct { + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ + uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ + }; + uint32_t val; + } xtal32k_conf; + union { + struct { + uint32_t reserved0: 18; + uint32_t io_mux_reset_disable: 1; + uint32_t reserved19: 13; + }; + uint32_t val; + } usb_conf; + union { + struct { + uint32_t reject_cause:18; /*sleep reject cause*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } slp_reject_cause; + union { + struct { + uint32_t force_download_boot: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } option1; + union { + struct { + uint32_t wakeup_cause:17; /*sleep wakeup cause*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_wakeup_cause; + union { + struct { + uint32_t reserved0: 8; + uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/ + }; + uint32_t val; + } ulp_cp_timer_1; + union { + struct { + uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4: 5; + uint32_t w1ts: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11: 4; + uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal_w1ts: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_ena_w1ts; + union { + struct { + uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4: 5; + uint32_t w1tc: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11: 4; + uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal_w1tc: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_ena_w1tc; + union { + struct { + uint32_t reserved0: 18; + uint32_t retention_clk_sel: 1; + uint32_t retention_done_wait: 3; + uint32_t retention_clkoff_wait: 4; + uint32_t retention_en: 1; + uint32_t retention_wait: 5; /*wait cycles for rention operation*/ + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } fib_sel; + union { + struct { + uint32_t rtc_gpio_wakeup_status: 6; + uint32_t rtc_gpio_wakeup_status_clr: 1; + uint32_t rtc_gpio_pin_clk_gate: 1; + uint32_t rtc_gpio_pin5_int_type: 3; + uint32_t rtc_gpio_pin4_int_type: 3; + uint32_t rtc_gpio_pin3_int_type: 3; + uint32_t rtc_gpio_pin2_int_type: 3; + uint32_t rtc_gpio_pin1_int_type: 3; + uint32_t rtc_gpio_pin0_int_type: 3; + uint32_t rtc_gpio_pin5_wakeup_enable: 1; + uint32_t rtc_gpio_pin4_wakeup_enable: 1; + uint32_t rtc_gpio_pin3_wakeup_enable: 1; + uint32_t rtc_gpio_pin2_wakeup_enable: 1; + uint32_t rtc_gpio_pin1_wakeup_enable: 1; + uint32_t rtc_gpio_pin0_wakeup_enable: 1; + }; + uint32_t val; + } gpio_wakeup; + union { + struct { + uint32_t reserved0: 1; + uint32_t rtc_debug_12m_no_gating: 1; + uint32_t rtc_debug_bit_sel: 5; + uint32_t rtc_debug_sel0: 5; + uint32_t rtc_debug_sel1: 5; + uint32_t rtc_debug_sel2: 5; + uint32_t rtc_debug_sel3: 5; + uint32_t rtc_debug_sel4: 5; + }; + uint32_t val; + } dbg_sel; + union { + struct { + uint32_t reserved0: 2; + uint32_t rtc_gpio_pin5_mux_sel: 1; + uint32_t rtc_gpio_pin4_mux_sel: 1; + uint32_t rtc_gpio_pin3_mux_sel: 1; + uint32_t rtc_gpio_pin2_mux_sel: 1; + uint32_t rtc_gpio_pin1_mux_sel: 1; + uint32_t rtc_gpio_pin0_mux_sel: 1; + uint32_t rtc_gpio_pin5_fun_sel: 4; + uint32_t rtc_gpio_pin4_fun_sel: 4; + uint32_t rtc_gpio_pin3_fun_sel: 4; + uint32_t rtc_gpio_pin2_fun_sel: 4; + uint32_t rtc_gpio_pin1_fun_sel: 4; + uint32_t rtc_gpio_pin0_fun_sel: 4; + }; + uint32_t val; + } dbg_map; + union { + struct { + uint32_t reserved0: 27; + uint32_t sar2_pwdet_cct: 3; + uint32_t force_xpd_sar: 2; + }; + uint32_t val; + } sensor_ctrl; + union { + struct { + uint32_t reserved0: 27; + uint32_t sar_debug_sel: 5; + }; + uint32_t val; + } dbg_sar_sel; + union { + struct { + uint32_t reserved0: 26; + uint32_t power_glitch_dsense: 2; + uint32_t power_glitch_force_pd: 1; + uint32_t power_glitch_force_pu: 1; + uint32_t power_glitch_efuse_sel: 1; + uint32_t power_glitch_en: 1; + }; + uint32_t val; + } pg_ctrl; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; +extern rtc_cntl_dev_t RTCCNTL; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/rtc_i2c_reg.h b/components/soc/esp32h2/include/soc/rtc_i2c_reg.h new file mode 100644 index 0000000000..52bdefc0e5 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc_i2c_reg.h @@ -0,0 +1,684 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_I2C_REG_H_ +#define _SOC_RTC_I2C_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) +/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ +/*description: time period that scl = 0*/ +#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) +#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_S 0 + +#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004) +/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: rtc i2c reg clk gating*/ +#define RTC_I2C_CLK_EN (BIT(31)) +#define RTC_I2C_CLK_EN_M (BIT(31)) +#define RTC_I2C_CLK_EN_V 0x1 +#define RTC_I2C_CLK_EN_S 31 +/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: rtc i2c sw reset*/ +#define RTC_I2C_RESET (BIT(30)) +#define RTC_I2C_RESET_M (BIT(30)) +#define RTC_I2C_RESET_V 0x1 +#define RTC_I2C_RESET_S 30 +/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 +#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 +/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: receive lsb first*/ +#define RTC_I2C_RX_LSB_FIRST (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_V 0x1 +#define RTC_I2C_RX_LSB_FIRST_S 5 +/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: transit lsb first*/ +#define RTC_I2C_TX_LSB_FIRST (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_V 0x1 +#define RTC_I2C_TX_LSB_FIRST_S 4 +/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: force start*/ +#define RTC_I2C_TRANS_START (BIT(3)) +#define RTC_I2C_TRANS_START_M (BIT(3)) +#define RTC_I2C_TRANS_START_V 0x1 +#define RTC_I2C_TRANS_START_S 3 +/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1=master 0=slave*/ +#define RTC_I2C_MS_MODE (BIT(2)) +#define RTC_I2C_MS_MODE_M (BIT(2)) +#define RTC_I2C_MS_MODE_V 0x1 +#define RTC_I2C_MS_MODE_S 2 +/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1=push pull 0=open drain*/ +#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_V 0x1 +#define RTC_I2C_SCL_FORCE_OUT_S 1 +/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1=push pull 0=open drain*/ +#define RTC_I2C_SDA_FORCE_OUT (BIT(0)) +#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) +#define RTC_I2C_SDA_FORCE_OUT_V 0x1 +#define RTC_I2C_SDA_FORCE_OUT_S 0 + +#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008) +/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: scl last status*/ +#define RTC_I2C_SCL_STATE_LAST 0x00000007 +#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S)) +#define RTC_I2C_SCL_STATE_LAST_V 0x7 +#define RTC_I2C_SCL_STATE_LAST_S 28 +/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: i2c last main status*/ +#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S)) +#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 +/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: shifter content*/ +#define RTC_I2C_SHIFT 0x000000FF +#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S)) +#define RTC_I2C_SHIFT_V 0xFF +#define RTC_I2C_SHIFT_S 16 +/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: which operation is working*/ +#define RTC_I2C_OP_CNT 0x00000003 +#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S)) +#define RTC_I2C_OP_CNT_V 0x3 +#define RTC_I2C_OP_CNT_S 6 +/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: One byte transit done*/ +#define RTC_I2C_BYTE_TRANS (BIT(5)) +#define RTC_I2C_BYTE_TRANS_M (BIT(5)) +#define RTC_I2C_BYTE_TRANS_V 0x1 +#define RTC_I2C_BYTE_TRANS_S 5 +/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: slave reg sub address*/ +#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 +#define RTC_I2C_SLAVE_ADDRESSED_S 4 +/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: bus is busy*/ +#define RTC_I2C_BUS_BUSY (BIT(3)) +#define RTC_I2C_BUS_BUSY_M (BIT(3)) +#define RTC_I2C_BUS_BUSY_V 0x1 +#define RTC_I2C_BUS_BUSY_S 3 +/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: arbitration is lost*/ +#define RTC_I2C_ARB_LOST (BIT(2)) +#define RTC_I2C_ARB_LOST_M (BIT(2)) +#define RTC_I2C_ARB_LOST_V 0x1 +#define RTC_I2C_ARB_LOST_S 2 +/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: slave read or write*/ +#define RTC_I2C_SLAVE_RW (BIT(1)) +#define RTC_I2C_SLAVE_RW_M (BIT(1)) +#define RTC_I2C_SLAVE_RW_V 0x1 +#define RTC_I2C_SLAVE_RW_S 1 +/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: ack response*/ +#define RTC_I2C_ACK_REC (BIT(0)) +#define RTC_I2C_ACK_REC_M (BIT(0)) +#define RTC_I2C_ACK_REC_V 0x1 +#define RTC_I2C_ACK_REC_S 0 + +#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c) +/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ +/*description: time out threshold*/ +#define RTC_I2C_TIMEOUT 0x000FFFFF +#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) +#define RTC_I2C_TIMEOUT_V 0xFFFFF +#define RTC_I2C_TIMEOUT_S 0 + +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010) +/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: i2c 10bit mode enable*/ +#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_V 0x1 +#define RTC_I2C_ADDR_10BIT_EN_S 31 +/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: slave address*/ +#define RTC_I2C_SLAVE_ADDR 0x00007FFF +#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) +#define RTC_I2C_SLAVE_ADDR_V 0x7FFF +#define RTC_I2C_SLAVE_ADDR_S 0 + +#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014) +/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ +/*description: time period that scl = 1*/ +#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) +#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_S 0 + +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018) +/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ +/*description: time period for SDA to toggle after SCL goes low*/ +#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF +#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S)) +#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF +#define RTC_I2C_SDA_DUTY_NUM_S 0 + +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c) +/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ +/*description: time period for SCL to toggle after I2C start is triggered*/ +#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) +#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_S 0 + +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020) +/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ +/*description: time period for SCL to stop after I2C end is triggered*/ +#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) +#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_S 0 + +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024) +/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: clear detect start interrupt*/ +#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 +#define RTC_I2C_DETECT_START_INT_CLR_S 8 +/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: clear transit load data complete interrupt*/ +#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 +#define RTC_I2C_TX_DATA_INT_CLR_S 7 +/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: clear receive data interrupt*/ +#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 +#define RTC_I2C_RX_DATA_INT_CLR_S 6 +/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: clear ack error interrupt*/ +#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 +#define RTC_I2C_ACK_ERR_INT_CLR_S 5 +/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: clear time out interrupt*/ +#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 +#define RTC_I2C_TIMEOUT_INT_CLR_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: clear transit complete interrupt*/ +#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: clear master transit complete interrupt*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear arbitration lost interrupt*/ +#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: clear slave transit complete interrupt*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 + +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028) +/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: detect start interrupt raw*/ +#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 +#define RTC_I2C_DETECT_START_INT_RAW_S 8 +/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: transit data interrupt raw*/ +#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 +#define RTC_I2C_TX_DATA_INT_RAW_S 7 +/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: receive data interrupt raw*/ +#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 +#define RTC_I2C_RX_DATA_INT_RAW_S 6 +/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ack error interrupt raw*/ +#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 +#define RTC_I2C_ACK_ERR_INT_RAW_S 5 +/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: time out interrupt raw*/ +#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 +#define RTC_I2C_TIMEOUT_INT_RAW_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: transit complete interrupt raw*/ +#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: master transit complete interrupt raw*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: arbitration lost interrupt raw*/ +#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: slave transit complete interrupt raw*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 + +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c) +/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: detect start interrupt state*/ +#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_V 0x1 +#define RTC_I2C_DETECT_START_INT_ST_S 8 +/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: transit data interrupt state*/ +#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_V 0x1 +#define RTC_I2C_TX_DATA_INT_ST_S 7 +/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: receive data interrupt state*/ +#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_V 0x1 +#define RTC_I2C_RX_DATA_INT_ST_S 6 +/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ack error interrupt state*/ +#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 +#define RTC_I2C_ACK_ERR_INT_ST_S 5 +/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: time out interrupt state*/ +#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 +#define RTC_I2C_TIMEOUT_INT_ST_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: transit complete interrupt state*/ +#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: master transit complete interrupt state*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: arbitration lost interrupt state*/ +#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: slave transit complete interrupt state*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 + +#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030) +/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable detect start interrupt*/ +#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 +#define RTC_I2C_DETECT_START_INT_ENA_S 8 +/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable transit data interrupt*/ +#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 +#define RTC_I2C_TX_DATA_INT_ENA_S 7 +/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable receive data interrupt*/ +#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 +#define RTC_I2C_RX_DATA_INT_ENA_S 6 +/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable eack error interrupt*/ +#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 +#define RTC_I2C_ACK_ERR_INT_ENA_S 5 +/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable time out interrupt*/ +#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 +#define RTC_I2C_TIMEOUT_INT_ENA_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable transit complete interrupt*/ +#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable master transit complete interrupt*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable arbitration lost interrupt*/ +#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable slave transit complete interrupt*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 + +#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034) +/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: i2c done*/ +#define RTC_I2C_DONE (BIT(31)) +#define RTC_I2C_DONE_M (BIT(31)) +#define RTC_I2C_DONE_V 0x1 +#define RTC_I2C_DONE_S 31 +/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: data sent by slave*/ +#define RTC_I2C_SLAVE_TX_DATA 0x000000FF +#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S)) +#define RTC_I2C_SLAVE_TX_DATA_V 0xFF +#define RTC_I2C_SLAVE_TX_DATA_S 8 +/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: data received*/ +#define RTC_I2C_RDATA 0x000000FF +#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S)) +#define RTC_I2C_RDATA_V 0xFF +#define RTC_I2C_RDATA_S 0 + +#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038) +/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command0_done*/ +#define RTC_I2C_COMMAND0_DONE (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_V 0x1 +#define RTC_I2C_COMMAND0_DONE_S 31 +/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ +/*description: command0*/ +#define RTC_I2C_COMMAND0 0x00003FFF +#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S)) +#define RTC_I2C_COMMAND0_V 0x3FFF +#define RTC_I2C_COMMAND0_S 0 + +#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c) +/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command1_done*/ +#define RTC_I2C_COMMAND1_DONE (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_V 0x1 +#define RTC_I2C_COMMAND1_DONE_S 31 +/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command1*/ +#define RTC_I2C_COMMAND1 0x00003FFF +#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S)) +#define RTC_I2C_COMMAND1_V 0x3FFF +#define RTC_I2C_COMMAND1_S 0 + +#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040) +/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command2_done*/ +#define RTC_I2C_COMMAND2_DONE (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_V 0x1 +#define RTC_I2C_COMMAND2_DONE_S 31 +/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ +/*description: command2*/ +#define RTC_I2C_COMMAND2 0x00003FFF +#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S)) +#define RTC_I2C_COMMAND2_V 0x3FFF +#define RTC_I2C_COMMAND2_S 0 + +#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044) +/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command3_done*/ +#define RTC_I2C_COMMAND3_DONE (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_V 0x1 +#define RTC_I2C_COMMAND3_DONE_S 31 +/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ +/*description: command3*/ +#define RTC_I2C_COMMAND3 0x00003FFF +#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S)) +#define RTC_I2C_COMMAND3_V 0x3FFF +#define RTC_I2C_COMMAND3_S 0 + +#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048) +/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command4_done*/ +#define RTC_I2C_COMMAND4_DONE (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_V 0x1 +#define RTC_I2C_COMMAND4_DONE_S 31 +/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ +/*description: command4*/ +#define RTC_I2C_COMMAND4 0x00003FFF +#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S)) +#define RTC_I2C_COMMAND4_V 0x3FFF +#define RTC_I2C_COMMAND4_S 0 + +#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c) +/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command5_done*/ +#define RTC_I2C_COMMAND5_DONE (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_V 0x1 +#define RTC_I2C_COMMAND5_DONE_S 31 +/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ +/*description: command5*/ +#define RTC_I2C_COMMAND5 0x00003FFF +#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S)) +#define RTC_I2C_COMMAND5_V 0x3FFF +#define RTC_I2C_COMMAND5_S 0 + +#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050) +/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command6_done*/ +#define RTC_I2C_COMMAND6_DONE (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_V 0x1 +#define RTC_I2C_COMMAND6_DONE_S 31 +/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command6*/ +#define RTC_I2C_COMMAND6 0x00003FFF +#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S)) +#define RTC_I2C_COMMAND6_V 0x3FFF +#define RTC_I2C_COMMAND6_S 0 + +#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054) +/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command7_done*/ +#define RTC_I2C_COMMAND7_DONE (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_V 0x1 +#define RTC_I2C_COMMAND7_DONE_S 31 +/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ +/*description: command7*/ +#define RTC_I2C_COMMAND7 0x00003FFF +#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S)) +#define RTC_I2C_COMMAND7_V 0x3FFF +#define RTC_I2C_COMMAND7_S 0 + +#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058) +/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command8_done*/ +#define RTC_I2C_COMMAND8_DONE (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_V 0x1 +#define RTC_I2C_COMMAND8_DONE_S 31 +/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command8*/ +#define RTC_I2C_COMMAND8 0x00003FFF +#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S)) +#define RTC_I2C_COMMAND8_V 0x3FFF +#define RTC_I2C_COMMAND8_S 0 + +#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c) +/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command9_done*/ +#define RTC_I2C_COMMAND9_DONE (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_V 0x1 +#define RTC_I2C_COMMAND9_DONE_S 31 +/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ +/*description: command9*/ +#define RTC_I2C_COMMAND9 0x00003FFF +#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S)) +#define RTC_I2C_COMMAND9_V 0x3FFF +#define RTC_I2C_COMMAND9_S 0 + +#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060) +/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command10_done*/ +#define RTC_I2C_COMMAND10_DONE (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_V 0x1 +#define RTC_I2C_COMMAND10_DONE_S 31 +/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ +/*description: command10*/ +#define RTC_I2C_COMMAND10 0x00003FFF +#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S)) +#define RTC_I2C_COMMAND10_V 0x3FFF +#define RTC_I2C_COMMAND10_S 0 + +#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064) +/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command11_done*/ +#define RTC_I2C_COMMAND11_DONE (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_V 0x1 +#define RTC_I2C_COMMAND11_DONE_S 31 +/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ +/*description: command11*/ +#define RTC_I2C_COMMAND11 0x00003FFF +#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S)) +#define RTC_I2C_COMMAND11_V 0x3FFF +#define RTC_I2C_COMMAND11_S 0 + +#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068) +/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command12_done*/ +#define RTC_I2C_COMMAND12_DONE (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_V 0x1 +#define RTC_I2C_COMMAND12_DONE_S 31 +/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ +/*description: command12*/ +#define RTC_I2C_COMMAND12 0x00003FFF +#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S)) +#define RTC_I2C_COMMAND12_V 0x3FFF +#define RTC_I2C_COMMAND12_S 0 + +#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c) +/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command13_done*/ +#define RTC_I2C_COMMAND13_DONE (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_V 0x1 +#define RTC_I2C_COMMAND13_DONE_S 31 +/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command13*/ +#define RTC_I2C_COMMAND13 0x00003FFF +#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S)) +#define RTC_I2C_COMMAND13_V 0x3FFF +#define RTC_I2C_COMMAND13_S 0 + +#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070) +/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command14_done*/ +#define RTC_I2C_COMMAND14_DONE (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_V 0x1 +#define RTC_I2C_COMMAND14_DONE_S 31 +/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: command14*/ +#define RTC_I2C_COMMAND14 0x00003FFF +#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S)) +#define RTC_I2C_COMMAND14_V 0x3FFF +#define RTC_I2C_COMMAND14_S 0 + +#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074) +/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command15_done*/ +#define RTC_I2C_COMMAND15_DONE (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_V 0x1 +#define RTC_I2C_COMMAND15_DONE_S 31 +/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: command15*/ +#define RTC_I2C_COMMAND15 0x00003FFF +#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S)) +#define RTC_I2C_COMMAND15_V 0x3FFF +#define RTC_I2C_COMMAND15_S 0 + +#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) +/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ +/*description: */ +#define RTC_I2C_DATE 0x0FFFFFFF +#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) +#define RTC_I2C_DATE_V 0xFFFFFFF +#define RTC_I2C_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_RTC_I2C_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rtc_i2c_struct.h b/components/soc/esp32h2/include/soc/rtc_i2c_struct.h new file mode 100644 index 0000000000..5141eebcd6 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc_i2c_struct.h @@ -0,0 +1,227 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_I2C_STRUCT_H_ +#define _SOC_RTC_I2C_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t period: 20; /*time period that scl = 0*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_low; + union { + struct { + uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/ + uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/ + uint32_t ms_mode: 1; /*1=master 0=slave*/ + uint32_t trans_start: 1; /*force start*/ + uint32_t tx_lsb_first: 1; /*transit lsb first*/ + uint32_t rx_lsb_first: 1; /*receive lsb first*/ + uint32_t reserved6: 23; + uint32_t i2c_ctrl_clk_gate_en: 1; + uint32_t i2c_reset: 1; /*rtc i2c sw reset*/ + uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t ack_rec: 1; /*ack response*/ + uint32_t slave_rw: 1; /*slave read or write*/ + uint32_t arb_lost: 1; /*arbitration is lost*/ + uint32_t bus_busy: 1; /*bus is busy*/ + uint32_t slave_addressed: 1; /*slave reg sub address*/ + uint32_t byte_trans: 1; /*One byte transit done*/ + uint32_t op_cnt: 2; /*which operation is working*/ + uint32_t reserved8: 8; + uint32_t shift: 8; /*shifter content*/ + uint32_t scl_main_state_last: 3; /*i2c last main status*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*scl last status*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status; + union { + struct { + uint32_t time_out: 20; /*time out threshold*/ + uint32_t reserved20:12; + }; + uint32_t val; + } timeout; + union { + struct { + uint32_t addr: 15; /*slave address*/ + uint32_t reserved15: 16; + uint32_t en_10bit: 1; /*i2c 10bit mode enable*/ + }; + uint32_t val; + } slave_addr; + union { + struct { + uint32_t period: 20; /*time period that scl = 1*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_high; + union { + struct { + uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } sda_duty; + union { + struct { + uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_start_period; + union { + struct { + uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_stop_period; + union { + struct { + uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/ + uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/ + uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/ + uint32_t trans_complete: 1; /*clear transit complete interrupt*/ + uint32_t time_out: 1; /*clear time out interrupt*/ + uint32_t ack_err: 1; /*clear ack error interrupt*/ + uint32_t rx_data: 1; /*clear receive data interrupt*/ + uint32_t tx_data: 1; /*clear transit load data complete interrupt*/ + uint32_t detect_start: 1; /*clear detect start interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/ + uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/ + uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/ + uint32_t trans_complete: 1; /*transit complete interrupt raw*/ + uint32_t time_out: 1; /*time out interrupt raw*/ + uint32_t ack_err: 1; /*ack error interrupt raw*/ + uint32_t rx_data: 1; /*receive data interrupt raw*/ + uint32_t tx_data: 1; /*transit data interrupt raw*/ + uint32_t detect_start: 1; /*detect start interrupt raw*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/ + uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/ + uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/ + uint32_t trans_complete: 1; /*transit complete interrupt state*/ + uint32_t time_out: 1; /*time out interrupt state*/ + uint32_t ack_err: 1; /*ack error interrupt state*/ + uint32_t rx_data: 1; /*receive data interrupt state*/ + uint32_t tx_data: 1; /*transit data interrupt state*/ + uint32_t detect_start: 1; /*detect start interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/ + uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/ + uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/ + uint32_t trans_complete: 1; /*enable transit complete interrupt*/ + uint32_t time_out: 1; /*enable time out interrupt*/ + uint32_t ack_err: 1; /*enable eack error interrupt*/ + uint32_t rx_data: 1; /*enable receive data interrupt*/ + uint32_t tx_data: 1; /*enable transit data interrupt*/ + uint32_t detect_start: 1; /*enable detect start interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t i2c_rdata: 8; /*data received*/ + uint32_t slave_tx_data: 8; /*data sent by slave*/ + uint32_t reserved16: 15; + uint32_t i2c_done: 1; /*i2c done*/ + }; + uint32_t val; + } fifo_data; + union { + struct { + uint32_t command0: 14; /*command0*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*command0_done*/ + }; + uint32_t val; + } command[16]; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + union { + struct { + uint32_t i2c_date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_i2c_dev_t; +extern rtc_i2c_dev_t RTC_I2C; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_RTC_I2C_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/sensitive_reg.h b/components/soc/esp32h2/include/soc/sensitive_reg.h new file mode 100644 index 0000000000..e1ce7d93ef --- /dev/null +++ b/components/soc/esp32h2/include/soc/sensitive_reg.h @@ -0,0 +1,2304 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SENSITIVE_REG_H_ +#define _SOC_SENSITIVE_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) +/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_ROM_TABLE_LOCK (BIT(0)) +#define SENSITIVE_ROM_TABLE_LOCK_M (BIT(0)) +#define SENSITIVE_ROM_TABLE_LOCK_V 0x1 +#define SENSITIVE_ROM_TABLE_LOCK_S 0 + +#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x004) +/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_ROM_TABLE 0xFFFFFFFF +#define SENSITIVE_ROM_TABLE_M ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S)) +#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFF +#define SENSITIVE_ROM_TABLE_S 0 + +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x008) +/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V 0x1 +#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S 0 + +#define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0x00C) +/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_PRIVILEGE_MODE_SEL (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_M (BIT(0)) +#define SENSITIVE_PRIVILEGE_MODE_SEL_V 0x1 +#define SENSITIVE_PRIVILEGE_MODE_SEL_S 0 + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x010) +/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x014) +/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x018) +/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x01C) +/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: ~3'h0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x7 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 +/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: ~1'h0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x020) +/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (BIT(3)) +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 +/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007 +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x7 +#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x024) +/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x028) +/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x02C) +/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 +/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 +/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 +/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 + +#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x030) +/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 + +#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x034) +/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_WR_ACS_S 1 +/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_RD_ACS_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x038) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x03C) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x040) +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x044) +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x048) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x04C) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x050) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x054) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x058) +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x05C) +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x060) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x064) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x068) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x06C) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x070) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x074) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x078) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x07C) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x080) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x084) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x088) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x08C) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x090) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x094) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x098) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x09C) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0A0) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0A4) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0A8) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0AC) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0B0) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0B4) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0B8) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0BC) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0C0) +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0C4) +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0C8) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0CC) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0D0) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0D4) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0D8) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0DC) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0E0) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0E4) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0E8) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0EC) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x0F0) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x0F4) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x0F8) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x0FC) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x100) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x104) +/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x108) +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x10C) +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 +/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x3 +#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x110) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x114) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x118) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x11C) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x120) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x124) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x128) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S 0 + +#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x12C) +/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: */ +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S)) +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFF +#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x130) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x134) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x138) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x13C) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x140) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x144) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x148) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x14C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x150) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S 24 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S 12 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S 2 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x154) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x158) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x15C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S 12 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S 2 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x160) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x164) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x168) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 3 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S 1 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x16C) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xFFFFFFFF +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xFFFFFFFF +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 + +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x170) +/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_CLK_EN (BIT(0)) +#define SENSITIVE_CLK_EN_M (BIT(0)) +#define SENSITIVE_CLK_EN_V 0x1 +#define SENSITIVE_CLK_EN_S 0 + +#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) +/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010200 ; */ +/*description: */ +#define SENSITIVE_DATE 0x0FFFFFFF +#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) +#define SENSITIVE_DATE_V 0xFFFFFFF +#define SENSITIVE_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SENSITIVE_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/sensitive_struct.h b/components/soc/esp32h2/include/soc/sensitive_struct.h new file mode 100644 index 0000000000..a24ccf6402 --- /dev/null +++ b/components/soc/esp32h2/include/soc/sensitive_struct.h @@ -0,0 +1,1912 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SENSITIVE_STRUCT_H_ +#define _SOC_SENSITIVE_STRUCT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +typedef volatile struct { + union { + struct { + uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } rom_table_lock; + uint32_t rom_table; + union { + struct { + uint32_t reg_privilege_mode_sel_lock : 1; /*privilege_mode_sel_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } privilege_mode_sel_lock; + union { + struct { + uint32_t reg_privilege_mode_sel : 1; /*privilege_mode_sel*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } privilege_mode_sel; + union { + struct { + uint32_t reg_apb_peripheral_access_lock: 1; /*apb_peripheral_access_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } apb_peripheral_access_0; + union { + struct { + uint32_t reg_apb_peripheral_access_split_burst: 1; /*apb_peripheral_access_split_burst*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } apb_peripheral_access_1; + union { + struct { + uint32_t reg_internal_sram_usage_lock : 1; /*internal_sram_usage_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } internal_sram_usage_0; + union { + struct { + uint32_t reg_internal_sram_usage_cpu_cache: 1; /*internal_sram_usage_cpu_cache*/ + uint32_t reg_internal_sram_usage_cpu_sram: 3; /*internal_sram_usage_cpu_sram*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } internal_sram_usage_1; + union { + struct { + uint32_t reg_internal_sram_usage_mac_dump_sram: 3; /*internal_sram_usage_mac_dump_sram*/ + uint32_t reg_internal_sram_alloc_mac_dump: 1; /*internal_sram_alloc_mac_dump*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } internal_sram_usage_3; + union { + struct { + uint32_t reg_internal_sram_usage_log_sram: 1; /*internal_sram_usage_log_sram*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } internal_sram_usage_4; + union { + struct { + uint32_t reg_cache_tag_access_lock : 1; /*cache_tag_access_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } cache_tag_access_0; + union { + struct { + uint32_t reg_pro_i_tag_rd_acs : 1; /*pro_i_tag_rd_acs*/ + uint32_t reg_pro_i_tag_wr_acs : 1; /*pro_i_tag_wr_acs*/ + uint32_t reg_pro_d_tag_rd_acs : 1; /*pro_d_tag_rd_acs*/ + uint32_t reg_pro_d_tag_wr_acs : 1; /*pro_d_tag_wr_acs*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } cache_tag_access_1; + union { + struct { + uint32_t reg_cache_mmu_access_lock : 1; /*cache_mmu_access_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } cache_mmu_access_0; + union { + struct { + uint32_t reg_pro_mmu_rd_acs : 1; /*pro_mmu_rd_acs*/ + uint32_t reg_pro_mmu_wr_acs : 1; /*pro_mmu_wr_acs*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } cache_mmu_access_1; + union { + struct { + uint32_t reg_dma_apbperi_spi2_pms_constrain_lock: 1; /*dma_apbperi_spi2_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_spi2_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_spi2_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_uchi0_pms_constrain_lock: 1; /*dma_apbperi_uchi0_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_uchi0_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_uchi0_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_i2s0_pms_constrain_lock: 1; /*dma_apbperi_i2s0_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_i2s0_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_i2s0_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_mac_pms_constrain_lock: 1; /*dma_apbperi_mac_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_mac_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_mac_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_backup_pms_constrain_lock: 1; /*dma_apbperi_backup_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_backup_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_backup_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_lc_pms_constrain_lock: 1; /*dma_apbperi_lc_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_lc_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_lc_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_aes_pms_constrain_lock: 1; /*dma_apbperi_aes_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_aes_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_aes_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_sha_pms_constrain_lock: 1; /*dma_apbperi_sha_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_sha_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_sha_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_lock: 1; /*dma_apbperi_adc_dac_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_adc_dac_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reserved24 : 8; + }; + uint32_t val; + } dma_apbperi_adc_dac_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_pms_monitor_lock: 1; /*dma_apbperi_pms_monitor_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_pms_monitor_0; + union { + struct { + uint32_t reg_dma_apbperi_pms_monitor_violate_clr: 1; /*dma_apbperi_pms_monitor_violate_clr*/ + uint32_t reg_dma_apbperi_pms_monitor_violate_en: 1; /*dma_apbperi_pms_monitor_violate_en*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } dma_apbperi_pms_monitor_1; + union { + struct { + uint32_t reg_dma_apbperi_pms_monitor_violate_intr: 1; /*dma_apbperi_pms_monitor_violate_intr*/ + uint32_t reg_dma_apbperi_pms_monitor_violate_status_world: 2; /*dma_apbperi_pms_monitor_violate_status_world*/ + uint32_t reg_dma_apbperi_pms_monitor_violate_status_addr: 24; /*dma_apbperi_pms_monitor_violate_status_addr*/ + uint32_t reserved27 : 5; + }; + uint32_t val; + } dma_apbperi_pms_monitor_2; + union { + struct { + uint32_t reg_dma_apbperi_pms_monitor_violate_status_wr: 1; /*dma_apbperi_pms_monitor_violate_status_wr*/ + uint32_t reg_dma_apbperi_pms_monitor_violate_status_byteen: 4; /*dma_apbperi_pms_monitor_violate_status_byteen*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } dma_apbperi_pms_monitor_3; + union { + struct { + uint32_t reg_core_x_iram0_dram0_dma_split_line_constrain_lock: 1; /*core_x_iram0_dram0_dma_split_line_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_0; + union { + struct { + uint32_t reg_core_x_iram0_dram0_dma_sram_category_0: 2; /*core_x_iram0_dram0_dma_sram_category_0*/ + uint32_t reg_core_x_iram0_dram0_dma_sram_category_1: 2; /*core_x_iram0_dram0_dma_sram_category_1*/ + uint32_t reg_core_x_iram0_dram0_dma_sram_category_2: 2; /*core_x_iram0_dram0_dma_sram_category_2*/ + uint32_t reserved6 : 8; + uint32_t reg_core_x_iram0_dram0_dma_sram_splitaddr: 8; /*core_x_iram0_dram0_dma_sram_splitaddr*/ + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_1; + union { + struct { + uint32_t reg_core_x_iram0_sram_line_0_category_0: 2; /*core_x_iram0_sram_line_0_category_0*/ + uint32_t reg_core_x_iram0_sram_line_0_category_1: 2; /*core_x_iram0_sram_line_0_category_1*/ + uint32_t reg_core_x_iram0_sram_line_0_category_2: 2; /*core_x_iram0_sram_line_0_category_2*/ + uint32_t reserved6 : 8; + uint32_t reg_core_x_iram0_sram_line_0_splitaddr: 8; /*core_x_iram0_sram_line_0_splitaddr*/ + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_2; + union { + struct { + uint32_t reg_core_x_iram0_sram_line_1_category_0: 2; /*core_x_iram0_sram_line_1_category_0*/ + uint32_t reg_core_x_iram0_sram_line_1_category_1: 2; /*core_x_iram0_sram_line_1_category_1*/ + uint32_t reg_core_x_iram0_sram_line_1_category_2: 2; /*core_x_iram0_sram_line_1_category_2*/ + uint32_t reserved6 : 8; + uint32_t reg_core_x_iram0_sram_line_1_splitaddr: 8; /*core_x_iram0_sram_line_1_splitaddr*/ + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_3; + union { + struct { + uint32_t reg_core_x_dram0_dma_sram_line_0_category_0: 2; /*core_x_dram0_dma_sram_line_0_category_0*/ + uint32_t reg_core_x_dram0_dma_sram_line_0_category_1: 2; /*core_x_dram0_dma_sram_line_0_category_1*/ + uint32_t reg_core_x_dram0_dma_sram_line_0_category_2: 2; /*core_x_dram0_dma_sram_line_0_category_2*/ + uint32_t reserved6 : 8; + uint32_t reg_core_x_dram0_dma_sram_line_0_splitaddr: 8; /*core_x_dram0_dma_sram_line_0_splitaddr*/ + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_4; + union { + struct { + uint32_t reg_core_x_dram0_dma_sram_line_1_category_0: 2; /*core_x_dram0_dma_sram_line_1_category_0*/ + uint32_t reg_core_x_dram0_dma_sram_line_1_category_1: 2; /*core_x_dram0_dma_sram_line_1_category_1*/ + uint32_t reg_core_x_dram0_dma_sram_line_1_category_2: 2; /*core_x_dram0_dma_sram_line_1_category_2*/ + uint32_t reserved6 : 8; + uint32_t reg_core_x_dram0_dma_sram_line_1_splitaddr: 8; /*core_x_dram0_dma_sram_line_1_splitaddr*/ + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_5; + union { + struct { + uint32_t reg_core_x_iram0_pms_constrain_lock: 1; /*core_x_iram0_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_x_iram0_pms_constrain_0; + union { + struct { + uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_1: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_2: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_3: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_3*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0*/ + uint32_t reserved15 : 3; + uint32_t reg_core_x_iram0_pms_constrain_rom_world_1_pms: 3; /*core_x_iram0_pms_constrain_rom_world_1_pms*/ + uint32_t reserved21 : 11; + }; + uint32_t val; + } core_x_iram0_pms_constrain_1; + union { + struct { + uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_1: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_2: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_3: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_3*/ + uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0*/ + uint32_t reserved15 : 3; + uint32_t reg_core_x_iram0_pms_constrain_rom_world_0_pms: 3; /*core_x_iram0_pms_constrain_rom_world_0_pms*/ + uint32_t reserved21 : 11; + }; + uint32_t val; + } core_x_iram0_pms_constrain_2; + union { + struct { + uint32_t reg_core_0_iram0_pms_monitor_lock: 1; /*core_0_iram0_pms_monitor_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_0_iram0_pms_monitor_0; + union { + struct { + uint32_t reg_core_0_iram0_pms_monitor_violate_clr: 1; /*core_0_iram0_pms_monitor_violate_clr*/ + uint32_t reg_core_0_iram0_pms_monitor_violate_en: 1; /*core_0_iram0_pms_monitor_violate_en*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } core_0_iram0_pms_monitor_1; + union { + struct { + uint32_t reg_core_0_iram0_pms_monitor_violate_intr: 1; /*core_0_iram0_pms_monitor_violate_intr*/ + uint32_t reg_core_0_iram0_pms_monitor_violate_status_wr: 1; /*core_0_iram0_pms_monitor_violate_status_wr*/ + uint32_t reg_core_0_iram0_pms_monitor_violate_status_loadstore: 1; /*core_0_iram0_pms_monitor_violate_status_loadstore*/ + uint32_t reg_core_0_iram0_pms_monitor_violate_status_world: 2; /*core_0_iram0_pms_monitor_violate_status_world*/ + uint32_t reg_core_0_iram0_pms_monitor_violate_status_addr: 24; /*core_0_iram0_pms_monitor_violate_status_addr*/ + uint32_t reserved29 : 3; + }; + uint32_t val; + } core_0_iram0_pms_monitor_2; + union { + struct { + uint32_t reg_core_x_dram0_pms_constrain_lock: 1; /*core_x_dram0_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_x_dram0_pms_constrain_0; + union { + struct { + uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_0: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_0*/ + uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_1: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_1*/ + uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_2: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_2*/ + uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_3: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_3*/ + uint32_t reserved8 : 4; + uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_0: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_0*/ + uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_1: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_1*/ + uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_2: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_2*/ + uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_3: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_3*/ + uint32_t reserved20 : 4; + uint32_t reg_core_x_dram0_pms_constrain_rom_world_0_pms: 2; /*core_x_dram0_pms_constrain_rom_world_0_pms*/ + uint32_t reg_core_x_dram0_pms_constrain_rom_world_1_pms: 2; /*core_x_dram0_pms_constrain_rom_world_1_pms*/ + uint32_t reserved28 : 4; + }; + uint32_t val; + } core_x_dram0_pms_constrain_1; + union { + struct { + uint32_t reg_core_0_dram0_pms_monitor_lock: 1; /*core_0_dram0_pms_monitor_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_0_dram0_pms_monitor_0; + union { + struct { + uint32_t reg_core_0_dram0_pms_monitor_violate_clr: 1; /*core_0_dram0_pms_monitor_violate_clr*/ + uint32_t reg_core_0_dram0_pms_monitor_violate_en: 1; /*core_0_dram0_pms_monitor_violate_en*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } core_0_dram0_pms_monitor_1; + union { + struct { + uint32_t reg_core_0_dram0_pms_monitor_violate_intr: 1; /*core_0_dram0_pms_monitor_violate_intr*/ + uint32_t reg_core_0_dram0_pms_monitor_violate_status_lock: 1; /*core_0_dram0_pms_monitor_violate_status_lock*/ + uint32_t reg_core_0_dram0_pms_monitor_violate_status_world: 2; /*core_0_dram0_pms_monitor_violate_status_world*/ + uint32_t reg_core_0_dram0_pms_monitor_violate_status_addr: 24; /*core_0_dram0_pms_monitor_violate_status_addr*/ + uint32_t reserved28 : 4; + }; + uint32_t val; + } core_0_dram0_pms_monitor_2; + union { + struct { + uint32_t reg_core_0_dram0_pms_monitor_violate_status_wr: 1; /*core_0_dram0_pms_monitor_violate_status_wr*/ + uint32_t reg_core_0_dram0_pms_monitor_violate_status_byteen: 4; /*core_0_dram0_pms_monitor_violate_status_byteen*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } core_0_dram0_pms_monitor_3; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_lock: 1; /*core_0_pif_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_0_pif_pms_constrain_0; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_world_0_uart: 2; /*core_0_pif_pms_constrain_world_0_uart*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1: 2; /*core_0_pif_pms_constrain_world_0_g0spi_1*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0: 2; /*core_0_pif_pms_constrain_world_0_g0spi_0*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_gpio: 2; /*core_0_pif_pms_constrain_world_0_gpio*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_fe2: 2; /*core_0_pif_pms_constrain_world_0_fe2*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_fe: 2; /*core_0_pif_pms_constrain_world_0_fe*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_timer: 2; /*core_0_pif_pms_constrain_world_0_timer*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_rtc: 2; /*core_0_pif_pms_constrain_world_0_rtc*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux: 2; /*core_0_pif_pms_constrain_world_0_io_mux*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_wdg: 2; /*core_0_pif_pms_constrain_world_0_wdg*/ + uint32_t reserved20 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_0_misc: 2; /*core_0_pif_pms_constrain_world_0_misc*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_i2c: 2; /*core_0_pif_pms_constrain_world_0_i2c*/ + uint32_t reserved28 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_uart1: 2; /*core_0_pif_pms_constrain_world_0_uart1*/ + }; + uint32_t val; + } core_0_pif_pms_constrain_1; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_world_0_bt: 2; /*core_0_pif_pms_constrain_world_0_bt*/ + uint32_t reserved2 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_i2c_ext0: 2; /*core_0_pif_pms_constrain_world_0_i2c_ext0*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_uhci0: 2; /*core_0_pif_pms_constrain_world_0_uhci0*/ + uint32_t reserved8 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_rmt: 2; /*core_0_pif_pms_constrain_world_0_rmt*/ + uint32_t reserved12 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_0_ledc: 2; /*core_0_pif_pms_constrain_world_0_ledc*/ + uint32_t reserved18 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_0_bb: 2; /*core_0_pif_pms_constrain_world_0_bb*/ + uint32_t reserved24 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup: 2; /*core_0_pif_pms_constrain_world_0_timergroup*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1: 2; /*core_0_pif_pms_constrain_world_0_timergroup1*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_systimer: 2; /*core_0_pif_pms_constrain_world_0_systimer*/ + }; + uint32_t val; + } core_0_pif_pms_constrain_2; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_world_0_spi_2: 2; /*core_0_pif_pms_constrain_world_0_spi_2*/ + uint32_t reserved2 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl: 2; /*core_0_pif_pms_constrain_world_0_apb_ctrl*/ + uint32_t reserved6 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_0_can: 2; /*core_0_pif_pms_constrain_world_0_can*/ + uint32_t reserved12 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1: 2; /*core_0_pif_pms_constrain_world_0_i2s1*/ + uint32_t reserved16 : 6; + uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt: 2; /*core_0_pif_pms_constrain_world_0_rwbt*/ + uint32_t reserved24 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_wifimac: 2; /*core_0_pif_pms_constrain_world_0_wifimac*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_pwr: 2; /*core_0_pif_pms_constrain_world_0_pwr*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_3; + union { + struct { + uint32_t reserved0 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_usb_wrap: 2; /*core_0_pif_pms_constrain_world_0_usb_wrap*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri: 2; /*core_0_pif_pms_constrain_world_0_crypto_peri*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma: 2; /*core_0_pif_pms_constrain_world_0_crypto_dma*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc: 2; /*core_0_pif_pms_constrain_world_0_apb_adc*/ + uint32_t reserved10 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_bt_pwr: 2; /*core_0_pif_pms_constrain_world_0_bt_pwr*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device: 2; /*core_0_pif_pms_constrain_world_0_usb_device*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_system: 2; /*core_0_pif_pms_constrain_world_0_system*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive: 2; /*core_0_pif_pms_constrain_world_0_sensitive*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt: 2; /*core_0_pif_pms_constrain_world_0_interrupt*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy: 2; /*core_0_pif_pms_constrain_world_0_dma_copy*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config: 2; /*core_0_pif_pms_constrain_world_0_cache_config*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_ad: 2; /*core_0_pif_pms_constrain_world_0_ad*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_dio: 2; /*core_0_pif_pms_constrain_world_0_dio*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller: 2; /*core_0_pif_pms_constrain_world_0_world_controller*/ + }; + uint32_t val; + } core_0_pif_pms_constrain_4; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_world_1_uart: 2; /*core_0_pif_pms_constrain_world_1_uart*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1: 2; /*core_0_pif_pms_constrain_world_1_g0spi_1*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0: 2; /*core_0_pif_pms_constrain_world_1_g0spi_0*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_gpio: 2; /*core_0_pif_pms_constrain_world_1_gpio*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_fe2: 2; /*core_0_pif_pms_constrain_world_1_fe2*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_fe: 2; /*core_0_pif_pms_constrain_world_1_fe*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_timer: 2; /*core_0_pif_pms_constrain_world_1_timer*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_rtc: 2; /*core_0_pif_pms_constrain_world_1_rtc*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux: 2; /*core_0_pif_pms_constrain_world_1_io_mux*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_wdg: 2; /*core_0_pif_pms_constrain_world_1_wdg*/ + uint32_t reserved20 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_misc: 2; /*core_0_pif_pms_constrain_world_1_misc*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_i2c: 2; /*core_0_pif_pms_constrain_world_1_i2c*/ + uint32_t reserved28 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_uart1: 2; /*core_0_pif_pms_constrain_world_1_uart1*/ + }; + uint32_t val; + } core_0_pif_pms_constrain_5; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_world_1_bt: 2; /*core_0_pif_pms_constrain_world_1_bt*/ + uint32_t reserved2 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0: 2; /*core_0_pif_pms_constrain_world_1_i2c_ext0*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0: 2; /*core_0_pif_pms_constrain_world_1_uhci0*/ + uint32_t reserved8 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_rmt: 2; /*core_0_pif_pms_constrain_world_1_rmt*/ + uint32_t reserved12 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_ledc: 2; /*core_0_pif_pms_constrain_world_1_ledc*/ + uint32_t reserved18 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_bb: 2; /*core_0_pif_pms_constrain_world_1_bb*/ + uint32_t reserved24 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup: 2; /*core_0_pif_pms_constrain_world_1_timergroup*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1: 2; /*core_0_pif_pms_constrain_world_1_timergroup1*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_systimer: 2; /*core_0_pif_pms_constrain_world_1_systimer*/ + }; + uint32_t val; + } core_0_pif_pms_constrain_6; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2: 2; /*core_0_pif_pms_constrain_world_1_spi_2*/ + uint32_t reserved2 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2; /*core_0_pif_pms_constrain_world_1_apb_ctrl*/ + uint32_t reserved6 : 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2; /*core_0_pif_pms_constrain_world_1_can*/ + uint32_t reserved12 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; /*core_0_pif_pms_constrain_world_1_i2s1*/ + uint32_t reserved16 : 6; + uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; /*core_0_pif_pms_constrain_world_1_rwbt*/ + uint32_t reserved24 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_wifimac: 2; /*core_0_pif_pms_constrain_world_1_wifimac*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_pwr: 2; /*core_0_pif_pms_constrain_world_1_pwr*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_7; + union { + struct { + uint32_t reserved0 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_usb_wrap: 2; /*core_0_pif_pms_constrain_world_1_usb_wrap*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri: 2; /*core_0_pif_pms_constrain_world_1_crypto_peri*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma: 2; /*core_0_pif_pms_constrain_world_1_crypto_dma*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc: 2; /*core_0_pif_pms_constrain_world_1_apb_adc*/ + uint32_t reserved10 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_bt_pwr: 2; /*core_0_pif_pms_constrain_world_1_bt_pwr*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device: 2; /*core_0_pif_pms_constrain_world_1_usb_device*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_system: 2; /*core_0_pif_pms_constrain_world_1_system*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive: 2; /*core_0_pif_pms_constrain_world_1_sensitive*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt: 2; /*core_0_pif_pms_constrain_world_1_interrupt*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy: 2; /*core_0_pif_pms_constrain_world_1_dma_copy*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config: 2; /*core_0_pif_pms_constrain_world_1_cache_config*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_ad: 2; /*core_0_pif_pms_constrain_world_1_ad*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_dio: 2; /*core_0_pif_pms_constrain_world_1_dio*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller: 2; /*core_0_pif_pms_constrain_world_1_world_controller*/ + }; + uint32_t val; + } core_0_pif_pms_constrain_8; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_0*/ + uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_1*/ + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_0_pif_pms_constrain_9; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l: 3; /*core_0_pif_pms_constrain_rtcfast_world_0_l*/ + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h: 3; /*core_0_pif_pms_constrain_rtcfast_world_0_h*/ + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l: 3; /*core_0_pif_pms_constrain_rtcfast_world_1_l*/ + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h: 3; /*core_0_pif_pms_constrain_rtcfast_world_1_h*/ + uint32_t reserved12 : 20; + }; + uint32_t val; + } core_0_pif_pms_constrain_10; + union { + struct { + uint32_t reg_region_pms_constrain_lock : 1; /*region_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } sensitiveion_pms_constrain_0; + union { + struct { + uint32_t reg_region_pms_constrain_world_0_area_0: 2; /*region_pms_constrain_world_0_area_0*/ + uint32_t reg_region_pms_constrain_world_0_area_1: 2; /*region_pms_constrain_world_0_area_1*/ + uint32_t reg_region_pms_constrain_world_0_area_2: 2; /*region_pms_constrain_world_0_area_2*/ + uint32_t reg_region_pms_constrain_world_0_area_3: 2; /*region_pms_constrain_world_0_area_3*/ + uint32_t reg_region_pms_constrain_world_0_area_4: 2; /*region_pms_constrain_world_0_area_4*/ + uint32_t reg_region_pms_constrain_world_0_area_5: 2; /*region_pms_constrain_world_0_area_5*/ + uint32_t reg_region_pms_constrain_world_0_area_6: 2; /*region_pms_constrain_world_0_area_6*/ + uint32_t reserved14 : 18; + }; + uint32_t val; + } sensitiveion_pms_constrain_1; + union { + struct { + uint32_t reg_region_pms_constrain_world_1_area_0: 2; /*region_pms_constrain_world_1_area_0*/ + uint32_t reg_region_pms_constrain_world_1_area_1: 2; /*region_pms_constrain_world_1_area_1*/ + uint32_t reg_region_pms_constrain_world_1_area_2: 2; /*region_pms_constrain_world_1_area_2*/ + uint32_t reg_region_pms_constrain_world_1_area_3: 2; /*region_pms_constrain_world_1_area_3*/ + uint32_t reg_region_pms_constrain_world_1_area_4: 2; /*region_pms_constrain_world_1_area_4*/ + uint32_t reg_region_pms_constrain_world_1_area_5: 2; /*region_pms_constrain_world_1_area_5*/ + uint32_t reg_region_pms_constrain_world_1_area_6: 2; /*region_pms_constrain_world_1_area_6*/ + uint32_t reserved14 : 18; + }; + uint32_t val; + } sensitiveion_pms_constrain_2; + union { + struct { + uint32_t reg_region_pms_constrain_addr_0: 30; /*region_pms_constrain_addr_0*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_3; + union { + struct { + uint32_t reg_region_pms_constrain_addr_1: 30; /*region_pms_constrain_addr_1*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_4; + union { + struct { + uint32_t reg_region_pms_constrain_addr_2: 30; /*region_pms_constrain_addr_2*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_5; + union { + struct { + uint32_t reg_region_pms_constrain_addr_3: 30; /*region_pms_constrain_addr_3*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_6; + union { + struct { + uint32_t reg_region_pms_constrain_addr_4: 30; /*region_pms_constrain_addr_4*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_7; + union { + struct { + uint32_t reg_region_pms_constrain_addr_5: 30; /*region_pms_constrain_addr_5*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_8; + union { + struct { + uint32_t reg_region_pms_constrain_addr_6: 30; /*region_pms_constrain_addr_6*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_9; + union { + struct { + uint32_t reg_region_pms_constrain_addr_7: 30; /*region_pms_constrain_addr_7*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } sensitiveion_pms_constrain_10; + union { + struct { + uint32_t reg_core_0_pif_pms_monitor_lock: 1; /*core_0_pif_pms_monitor_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } core_0_pif_pms_monitor_0; + union { + struct { + uint32_t reg_core_0_pif_pms_monitor_violate_clr: 1; /*core_0_pif_pms_monitor_violate_clr*/ + uint32_t reg_core_0_pif_pms_monitor_violate_en: 1; /*core_0_pif_pms_monitor_violate_en*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } core_0_pif_pms_monitor_1; + union { + struct { + uint32_t reg_core_0_pif_pms_monitor_violate_intr: 1; /*core_0_pif_pms_monitor_violate_intr*/ + uint32_t reg_core_0_pif_pms_monitor_violate_status_hport_0: 1; /*core_0_pif_pms_monitor_violate_status_hport_0*/ + uint32_t reg_core_0_pif_pms_monitor_violate_status_hsize: 3; /*core_0_pif_pms_monitor_violate_status_hsize*/ + uint32_t reg_core_0_pif_pms_monitor_violate_status_hwrite: 1; /*core_0_pif_pms_monitor_violate_status_hwrite*/ + uint32_t reg_core_0_pif_pms_monitor_violate_status_hworld: 2; /*core_0_pif_pms_monitor_violate_status_hworld*/ + uint32_t reserved8 : 24; + }; + uint32_t val; + } core_0_pif_pms_monitor_2; + uint32_t core_0_pif_pms_monitor_3; + union { + struct { + uint32_t reg_core_0_pif_pms_monitor_nonword_violate_clr: 1; /*core_0_pif_pms_monitor_nonword_violate_clr*/ + uint32_t reg_core_0_pif_pms_monitor_nonword_violate_en: 1; /*core_0_pif_pms_monitor_nonword_violate_en*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } core_0_pif_pms_monitor_4; + union { + struct { + uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr: 1; /*core_0_pif_pms_monitor_nonword_violate_intr*/ + uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/ + uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } core_0_pif_pms_monitor_5; + uint32_t core_0_pif_pms_monitor_6; + union { + struct { + uint32_t reg_backup_bus_pms_constrain_lock: 1; /*backup_bus_pms_constrain_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } backup_bus_pms_constrain_0; + union { + struct { + uint32_t reg_backup_bus_pms_constrain_uart: 2; /*backup_bus_pms_constrain_uart*/ + uint32_t reg_backup_bus_pms_constrain_g0spi_1: 2; /*backup_bus_pms_constrain_g0spi_1*/ + uint32_t reg_backup_bus_pms_constrain_g0spi_0: 2; /*backup_bus_pms_constrain_g0spi_0*/ + uint32_t reg_backup_bus_pms_constrain_gpio: 2; /*backup_bus_pms_constrain_gpio*/ + uint32_t reg_backup_bus_pms_constrain_fe2: 2; /*backup_bus_pms_constrain_fe2*/ + uint32_t reg_backup_bus_pms_constrain_fe: 2; /*backup_bus_pms_constrain_fe*/ + uint32_t reg_backup_bus_pms_constrain_timer: 2; /*backup_bus_pms_constrain_timer*/ + uint32_t reg_backup_bus_pms_constrain_rtc: 2; /*backup_bus_pms_constrain_rtc*/ + uint32_t reg_backup_bus_pms_constrain_io_mux: 2; /*backup_bus_pms_constrain_io_mux*/ + uint32_t reg_backup_bus_pms_constrain_wdg: 2; /*backup_bus_pms_constrain_wdg*/ + uint32_t reserved20 : 4; + uint32_t reg_backup_bus_pms_constrain_misc: 2; /*backup_bus_pms_constrain_misc*/ + uint32_t reg_backup_bus_pms_constrain_i2c: 2; /*backup_bus_pms_constrain_i2c*/ + uint32_t reserved28 : 2; + uint32_t reg_backup_bus_pms_constrain_uart1: 2; /*backup_bus_pms_constrain_uart1*/ + }; + uint32_t val; + } backup_bus_pms_constrain_1; + union { + struct { + uint32_t reg_backup_bus_pms_constrain_bt: 2; /*backup_bus_pms_constrain_bt*/ + uint32_t reserved2 : 2; + uint32_t reg_backup_bus_pms_constrain_i2c_ext0: 2; /*backup_bus_pms_constrain_i2c_ext0*/ + uint32_t reg_backup_bus_pms_constrain_uhci0: 2; /*backup_bus_pms_constrain_uhci0*/ + uint32_t reserved8 : 2; + uint32_t reg_backup_bus_pms_constrain_rmt: 2; /*backup_bus_pms_constrain_rmt*/ + uint32_t reserved12 : 4; + uint32_t reg_backup_bus_pms_constrain_ledc: 2; /*backup_bus_pms_constrain_ledc*/ + uint32_t reserved18 : 4; + uint32_t reg_backup_bus_pms_constrain_bb: 2; /*backup_bus_pms_constrain_bb*/ + uint32_t reserved24 : 2; + uint32_t reg_backup_bus_pms_constrain_timergroup: 2; /*backup_bus_pms_constrain_timergroup*/ + uint32_t reg_backup_bus_pms_constrain_timergroup1: 2; /*backup_bus_pms_constrain_timergroup1*/ + uint32_t reg_backup_bus_pms_constrain_systimer: 2; /*backup_bus_pms_constrain_systimer*/ + }; + uint32_t val; + } backup_bus_pms_constrain_2; + union { + struct { + uint32_t reg_backup_bus_pms_constrain_spi_2: 2; /*backup_bus_pms_constrain_spi_2*/ + uint32_t reserved2 : 2; + uint32_t reg_backup_bus_pms_constrain_apb_ctrl: 2; /*backup_bus_pms_constrain_apb_ctrl*/ + uint32_t reserved6 : 4; + uint32_t reg_backup_bus_pms_constrain_can: 2; /*backup_bus_pms_constrain_can*/ + uint32_t reserved12 : 2; + uint32_t reg_backup_bus_pms_constrain_i2s1: 2; /*backup_bus_pms_constrain_i2s1*/ + uint32_t reserved16 : 6; + uint32_t reg_backup_bus_pms_constrain_rwbt: 2; /*backup_bus_pms_constrain_rwbt*/ + uint32_t reserved24 : 2; + uint32_t reg_backup_bus_pms_constrain_wifimac: 2; /*backup_bus_pms_constrain_wifimac*/ + uint32_t reg_backup_bus_pms_constrain_pwr: 2; /*backup_bus_pms_constrain_pwr*/ + uint32_t reserved30 : 2; + }; + uint32_t val; + } backup_bus_pms_constrain_3; + union { + struct { + uint32_t reserved0 : 2; + uint32_t reg_backup_bus_pms_constrain_usb_wrap: 2; /*backup_bus_pms_constrain_usb_wrap*/ + uint32_t reg_backup_bus_pms_constrain_crypto_peri: 2; /*backup_bus_pms_constrain_crypto_peri*/ + uint32_t reg_backup_bus_pms_constrain_crypto_dma: 2; /*backup_bus_pms_constrain_crypto_dma*/ + uint32_t reg_backup_bus_pms_constrain_apb_adc: 2; /*backup_bus_pms_constrain_apb_adc*/ + uint32_t reserved10 : 2; + uint32_t reg_backup_bus_pms_constrain_bt_pwr: 2; /*backup_bus_pms_constrain_bt_pwr*/ + uint32_t reg_backup_bus_pms_constrain_usb_device: 2; /*backup_bus_pms_constrain_usb_device*/ + uint32_t reserved16 : 16; + }; + uint32_t val; + } backup_bus_pms_constrain_4; + union { + struct { + uint32_t reg_backup_bus_pms_monitor_lock: 1; /*backup_bus_pms_monitor_lock*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } backup_bus_pms_monitor_0; + union { + struct { + uint32_t reg_backup_bus_pms_monitor_violate_clr: 1; /*backup_bus_pms_monitor_violate_clr*/ + uint32_t reg_backup_bus_pms_monitor_violate_en: 1; /*backup_bus_pms_monitor_violate_en*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } backup_bus_pms_monitor_1; + union { + struct { + uint32_t reg_backup_bus_pms_monitor_violate_intr: 1; /*backup_bus_pms_monitor_violate_intr*/ + uint32_t reg_backup_bus_pms_monitor_violate_status_htrans: 2; /*backup_bus_pms_monitor_violate_status_htrans*/ + uint32_t reg_backup_bus_pms_monitor_violate_status_hsize: 3; /*backup_bus_pms_monitor_violate_status_hsize*/ + uint32_t reg_backup_bus_pms_monitor_violate_status_hwrite: 1; /*backup_bus_pms_monitor_violate_status_hwrite*/ + uint32_t reserved7 : 25; + }; + uint32_t val; + } backup_bus_pms_monitor_2; + uint32_t backup_bus_pms_monitor_3; + union { + struct { + uint32_t reg_clk_en : 1; /*clk_en*/ + uint32_t reserved1 : 31; + uint32_t reservedNone : None; /*SENSITIVE_CLOCK_GATE_REG_REG*/ + }; + uint32_t val; + } clock_gate; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + uint32_t reserved_554; + uint32_t reserved_558; + uint32_t reserved_55c; + uint32_t reserved_560; + uint32_t reserved_564; + uint32_t reserved_568; + uint32_t reserved_56c; + uint32_t reserved_570; + uint32_t reserved_574; + uint32_t reserved_578; + uint32_t reserved_57c; + uint32_t reserved_580; + uint32_t reserved_584; + uint32_t reserved_588; + uint32_t reserved_58c; + uint32_t reserved_590; + uint32_t reserved_594; + uint32_t reserved_598; + uint32_t reserved_59c; + uint32_t reserved_5a0; + uint32_t reserved_5a4; + uint32_t reserved_5a8; + uint32_t reserved_5ac; + uint32_t reserved_5b0; + uint32_t reserved_5b4; + uint32_t reserved_5b8; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + uint32_t reserved_62c; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + uint32_t reserved_6fc; + uint32_t reserved_700; + uint32_t reserved_704; + uint32_t reserved_708; + uint32_t reserved_70c; + uint32_t reserved_710; + uint32_t reserved_714; + uint32_t reserved_718; + uint32_t reserved_71c; + uint32_t reserved_720; + uint32_t reserved_724; + uint32_t reserved_728; + uint32_t reserved_72c; + uint32_t reserved_730; + uint32_t reserved_734; + uint32_t reserved_738; + uint32_t reserved_73c; + uint32_t reserved_740; + uint32_t reserved_744; + uint32_t reserved_748; + uint32_t reserved_74c; + uint32_t reserved_750; + uint32_t reserved_754; + uint32_t reserved_758; + uint32_t reserved_75c; + uint32_t reserved_760; + uint32_t reserved_764; + uint32_t reserved_768; + uint32_t reserved_76c; + uint32_t reserved_770; + uint32_t reserved_774; + uint32_t reserved_778; + uint32_t reserved_77c; + uint32_t reserved_780; + uint32_t reserved_784; + uint32_t reserved_788; + uint32_t reserved_78c; + uint32_t reserved_790; + uint32_t reserved_794; + uint32_t reserved_798; + uint32_t reserved_79c; + uint32_t reserved_7a0; + uint32_t reserved_7a4; + uint32_t reserved_7a8; + uint32_t reserved_7ac; + uint32_t reserved_7b0; + uint32_t reserved_7b4; + uint32_t reserved_7b8; + uint32_t reserved_7bc; + uint32_t reserved_7c0; + uint32_t reserved_7c4; + uint32_t reserved_7c8; + uint32_t reserved_7cc; + uint32_t reserved_7d0; + uint32_t reserved_7d4; + uint32_t reserved_7d8; + uint32_t reserved_7dc; + uint32_t reserved_7e0; + uint32_t reserved_7e4; + uint32_t reserved_7e8; + uint32_t reserved_7ec; + uint32_t reserved_7f0; + uint32_t reserved_7f4; + uint32_t reserved_7f8; + uint32_t reserved_7fc; + uint32_t reserved_800; + uint32_t reserved_804; + uint32_t reserved_808; + uint32_t reserved_80c; + uint32_t reserved_810; + uint32_t reserved_814; + uint32_t reserved_818; + uint32_t reserved_81c; + uint32_t reserved_820; + uint32_t reserved_824; + uint32_t reserved_828; + uint32_t reserved_82c; + uint32_t reserved_830; + uint32_t reserved_834; + uint32_t reserved_838; + uint32_t reserved_83c; + uint32_t reserved_840; + uint32_t reserved_844; + uint32_t reserved_848; + uint32_t reserved_84c; + uint32_t reserved_850; + uint32_t reserved_854; + uint32_t reserved_858; + uint32_t reserved_85c; + uint32_t reserved_860; + uint32_t reserved_864; + uint32_t reserved_868; + uint32_t reserved_86c; + uint32_t reserved_870; + uint32_t reserved_874; + uint32_t reserved_878; + uint32_t reserved_87c; + uint32_t reserved_880; + uint32_t reserved_884; + uint32_t reserved_888; + uint32_t reserved_88c; + uint32_t reserved_890; + uint32_t reserved_894; + uint32_t reserved_898; + uint32_t reserved_89c; + uint32_t reserved_8a0; + uint32_t reserved_8a4; + uint32_t reserved_8a8; + uint32_t reserved_8ac; + uint32_t reserved_8b0; + uint32_t reserved_8b4; + uint32_t reserved_8b8; + uint32_t reserved_8bc; + uint32_t reserved_8c0; + uint32_t reserved_8c4; + uint32_t reserved_8c8; + uint32_t reserved_8cc; + uint32_t reserved_8d0; + uint32_t reserved_8d4; + uint32_t reserved_8d8; + uint32_t reserved_8dc; + uint32_t reserved_8e0; + uint32_t reserved_8e4; + uint32_t reserved_8e8; + uint32_t reserved_8ec; + uint32_t reserved_8f0; + uint32_t reserved_8f4; + uint32_t reserved_8f8; + uint32_t reserved_8fc; + uint32_t reserved_900; + uint32_t reserved_904; + uint32_t reserved_908; + uint32_t reserved_90c; + uint32_t reserved_910; + uint32_t reserved_914; + uint32_t reserved_918; + uint32_t reserved_91c; + uint32_t reserved_920; + uint32_t reserved_924; + uint32_t reserved_928; + uint32_t reserved_92c; + uint32_t reserved_930; + uint32_t reserved_934; + uint32_t reserved_938; + uint32_t reserved_93c; + uint32_t reserved_940; + uint32_t reserved_944; + uint32_t reserved_948; + uint32_t reserved_94c; + uint32_t reserved_950; + uint32_t reserved_954; + uint32_t reserved_958; + uint32_t reserved_95c; + uint32_t reserved_960; + uint32_t reserved_964; + uint32_t reserved_968; + uint32_t reserved_96c; + uint32_t reserved_970; + uint32_t reserved_974; + uint32_t reserved_978; + uint32_t reserved_97c; + uint32_t reserved_980; + uint32_t reserved_984; + uint32_t reserved_988; + uint32_t reserved_98c; + uint32_t reserved_990; + uint32_t reserved_994; + uint32_t reserved_998; + uint32_t reserved_99c; + uint32_t reserved_9a0; + uint32_t reserved_9a4; + uint32_t reserved_9a8; + uint32_t reserved_9ac; + uint32_t reserved_9b0; + uint32_t reserved_9b4; + uint32_t reserved_9b8; + uint32_t reserved_9bc; + uint32_t reserved_9c0; + uint32_t reserved_9c4; + uint32_t reserved_9c8; + uint32_t reserved_9cc; + uint32_t reserved_9d0; + uint32_t reserved_9d4; + uint32_t reserved_9d8; + uint32_t reserved_9dc; + uint32_t reserved_9e0; + uint32_t reserved_9e4; + uint32_t reserved_9e8; + uint32_t reserved_9ec; + uint32_t reserved_9f0; + uint32_t reserved_9f4; + uint32_t reserved_9f8; + uint32_t reserved_9fc; + uint32_t reserved_a00; + uint32_t reserved_a04; + uint32_t reserved_a08; + uint32_t reserved_a0c; + uint32_t reserved_a10; + uint32_t reserved_a14; + uint32_t reserved_a18; + uint32_t reserved_a1c; + uint32_t reserved_a20; + uint32_t reserved_a24; + uint32_t reserved_a28; + uint32_t reserved_a2c; + uint32_t reserved_a30; + uint32_t reserved_a34; + uint32_t reserved_a38; + uint32_t reserved_a3c; + uint32_t reserved_a40; + uint32_t reserved_a44; + uint32_t reserved_a48; + uint32_t reserved_a4c; + uint32_t reserved_a50; + uint32_t reserved_a54; + uint32_t reserved_a58; + uint32_t reserved_a5c; + uint32_t reserved_a60; + uint32_t reserved_a64; + uint32_t reserved_a68; + uint32_t reserved_a6c; + uint32_t reserved_a70; + uint32_t reserved_a74; + uint32_t reserved_a78; + uint32_t reserved_a7c; + uint32_t reserved_a80; + uint32_t reserved_a84; + uint32_t reserved_a88; + uint32_t reserved_a8c; + uint32_t reserved_a90; + uint32_t reserved_a94; + uint32_t reserved_a98; + uint32_t reserved_a9c; + uint32_t reserved_aa0; + uint32_t reserved_aa4; + uint32_t reserved_aa8; + uint32_t reserved_aac; + uint32_t reserved_ab0; + uint32_t reserved_ab4; + uint32_t reserved_ab8; + uint32_t reserved_abc; + uint32_t reserved_ac0; + uint32_t reserved_ac4; + uint32_t reserved_ac8; + uint32_t reserved_acc; + uint32_t reserved_ad0; + uint32_t reserved_ad4; + uint32_t reserved_ad8; + uint32_t reserved_adc; + uint32_t reserved_ae0; + uint32_t reserved_ae4; + uint32_t reserved_ae8; + uint32_t reserved_aec; + uint32_t reserved_af0; + uint32_t reserved_af4; + uint32_t reserved_af8; + uint32_t reserved_afc; + uint32_t reserved_b00; + uint32_t reserved_b04; + uint32_t reserved_b08; + uint32_t reserved_b0c; + uint32_t reserved_b10; + uint32_t reserved_b14; + uint32_t reserved_b18; + uint32_t reserved_b1c; + uint32_t reserved_b20; + uint32_t reserved_b24; + uint32_t reserved_b28; + uint32_t reserved_b2c; + uint32_t reserved_b30; + uint32_t reserved_b34; + uint32_t reserved_b38; + uint32_t reserved_b3c; + uint32_t reserved_b40; + uint32_t reserved_b44; + uint32_t reserved_b48; + uint32_t reserved_b4c; + uint32_t reserved_b50; + uint32_t reserved_b54; + uint32_t reserved_b58; + uint32_t reserved_b5c; + uint32_t reserved_b60; + uint32_t reserved_b64; + uint32_t reserved_b68; + uint32_t reserved_b6c; + uint32_t reserved_b70; + uint32_t reserved_b74; + uint32_t reserved_b78; + uint32_t reserved_b7c; + uint32_t reserved_b80; + uint32_t reserved_b84; + uint32_t reserved_b88; + uint32_t reserved_b8c; + uint32_t reserved_b90; + uint32_t reserved_b94; + uint32_t reserved_b98; + uint32_t reserved_b9c; + uint32_t reserved_ba0; + uint32_t reserved_ba4; + uint32_t reserved_ba8; + uint32_t reserved_bac; + uint32_t reserved_bb0; + uint32_t reserved_bb4; + uint32_t reserved_bb8; + uint32_t reserved_bbc; + uint32_t reserved_bc0; + uint32_t reserved_bc4; + uint32_t reserved_bc8; + uint32_t reserved_bcc; + uint32_t reserved_bd0; + uint32_t reserved_bd4; + uint32_t reserved_bd8; + uint32_t reserved_bdc; + uint32_t reserved_be0; + uint32_t reserved_be4; + uint32_t reserved_be8; + uint32_t reserved_bec; + uint32_t reserved_bf0; + uint32_t reserved_bf4; + uint32_t reserved_bf8; + uint32_t reserved_bfc; + uint32_t reserved_c00; + uint32_t reserved_c04; + uint32_t reserved_c08; + uint32_t reserved_c0c; + uint32_t reserved_c10; + uint32_t reserved_c14; + uint32_t reserved_c18; + uint32_t reserved_c1c; + uint32_t reserved_c20; + uint32_t reserved_c24; + uint32_t reserved_c28; + uint32_t reserved_c2c; + uint32_t reserved_c30; + uint32_t reserved_c34; + uint32_t reserved_c38; + uint32_t reserved_c3c; + uint32_t reserved_c40; + uint32_t reserved_c44; + uint32_t reserved_c48; + uint32_t reserved_c4c; + uint32_t reserved_c50; + uint32_t reserved_c54; + uint32_t reserved_c58; + uint32_t reserved_c5c; + uint32_t reserved_c60; + uint32_t reserved_c64; + uint32_t reserved_c68; + uint32_t reserved_c6c; + uint32_t reserved_c70; + uint32_t reserved_c74; + uint32_t reserved_c78; + uint32_t reserved_c7c; + uint32_t reserved_c80; + uint32_t reserved_c84; + uint32_t reserved_c88; + uint32_t reserved_c8c; + uint32_t reserved_c90; + uint32_t reserved_c94; + uint32_t reserved_c98; + uint32_t reserved_c9c; + uint32_t reserved_ca0; + uint32_t reserved_ca4; + uint32_t reserved_ca8; + uint32_t reserved_cac; + uint32_t reserved_cb0; + uint32_t reserved_cb4; + uint32_t reserved_cb8; + uint32_t reserved_cbc; + uint32_t reserved_cc0; + uint32_t reserved_cc4; + uint32_t reserved_cc8; + uint32_t reserved_ccc; + uint32_t reserved_cd0; + uint32_t reserved_cd4; + uint32_t reserved_cd8; + uint32_t reserved_cdc; + uint32_t reserved_ce0; + uint32_t reserved_ce4; + uint32_t reserved_ce8; + uint32_t reserved_cec; + uint32_t reserved_cf0; + uint32_t reserved_cf4; + uint32_t reserved_cf8; + uint32_t reserved_cfc; + uint32_t reserved_d00; + uint32_t reserved_d04; + uint32_t reserved_d08; + uint32_t reserved_d0c; + uint32_t reserved_d10; + uint32_t reserved_d14; + uint32_t reserved_d18; + uint32_t reserved_d1c; + uint32_t reserved_d20; + uint32_t reserved_d24; + uint32_t reserved_d28; + uint32_t reserved_d2c; + uint32_t reserved_d30; + uint32_t reserved_d34; + uint32_t reserved_d38; + uint32_t reserved_d3c; + uint32_t reserved_d40; + uint32_t reserved_d44; + uint32_t reserved_d48; + uint32_t reserved_d4c; + uint32_t reserved_d50; + uint32_t reserved_d54; + uint32_t reserved_d58; + uint32_t reserved_d5c; + uint32_t reserved_d60; + uint32_t reserved_d64; + uint32_t reserved_d68; + uint32_t reserved_d6c; + uint32_t reserved_d70; + uint32_t reserved_d74; + uint32_t reserved_d78; + uint32_t reserved_d7c; + uint32_t reserved_d80; + uint32_t reserved_d84; + uint32_t reserved_d88; + uint32_t reserved_d8c; + uint32_t reserved_d90; + uint32_t reserved_d94; + uint32_t reserved_d98; + uint32_t reserved_d9c; + uint32_t reserved_da0; + uint32_t reserved_da4; + uint32_t reserved_da8; + uint32_t reserved_dac; + uint32_t reserved_db0; + uint32_t reserved_db4; + uint32_t reserved_db8; + uint32_t reserved_dbc; + uint32_t reserved_dc0; + uint32_t reserved_dc4; + uint32_t reserved_dc8; + uint32_t reserved_dcc; + uint32_t reserved_dd0; + uint32_t reserved_dd4; + uint32_t reserved_dd8; + uint32_t reserved_ddc; + uint32_t reserved_de0; + uint32_t reserved_de4; + uint32_t reserved_de8; + uint32_t reserved_dec; + uint32_t reserved_df0; + uint32_t reserved_df4; + uint32_t reserved_df8; + uint32_t reserved_dfc; + uint32_t reserved_e00; + uint32_t reserved_e04; + uint32_t reserved_e08; + uint32_t reserved_e0c; + uint32_t reserved_e10; + uint32_t reserved_e14; + uint32_t reserved_e18; + uint32_t reserved_e1c; + uint32_t reserved_e20; + uint32_t reserved_e24; + uint32_t reserved_e28; + uint32_t reserved_e2c; + uint32_t reserved_e30; + uint32_t reserved_e34; + uint32_t reserved_e38; + uint32_t reserved_e3c; + uint32_t reserved_e40; + uint32_t reserved_e44; + uint32_t reserved_e48; + uint32_t reserved_e4c; + uint32_t reserved_e50; + uint32_t reserved_e54; + uint32_t reserved_e58; + uint32_t reserved_e5c; + uint32_t reserved_e60; + uint32_t reserved_e64; + uint32_t reserved_e68; + uint32_t reserved_e6c; + uint32_t reserved_e70; + uint32_t reserved_e74; + uint32_t reserved_e78; + uint32_t reserved_e7c; + uint32_t reserved_e80; + uint32_t reserved_e84; + uint32_t reserved_e88; + uint32_t reserved_e8c; + uint32_t reserved_e90; + uint32_t reserved_e94; + uint32_t reserved_e98; + uint32_t reserved_e9c; + uint32_t reserved_ea0; + uint32_t reserved_ea4; + uint32_t reserved_ea8; + uint32_t reserved_eac; + uint32_t reserved_eb0; + uint32_t reserved_eb4; + uint32_t reserved_eb8; + uint32_t reserved_ebc; + uint32_t reserved_ec0; + uint32_t reserved_ec4; + uint32_t reserved_ec8; + uint32_t reserved_ecc; + uint32_t reserved_ed0; + uint32_t reserved_ed4; + uint32_t reserved_ed8; + uint32_t reserved_edc; + uint32_t reserved_ee0; + uint32_t reserved_ee4; + uint32_t reserved_ee8; + uint32_t reserved_eec; + uint32_t reserved_ef0; + uint32_t reserved_ef4; + uint32_t reserved_ef8; + uint32_t reserved_efc; + uint32_t reserved_f00; + uint32_t reserved_f04; + uint32_t reserved_f08; + uint32_t reserved_f0c; + uint32_t reserved_f10; + uint32_t reserved_f14; + uint32_t reserved_f18; + uint32_t reserved_f1c; + uint32_t reserved_f20; + uint32_t reserved_f24; + uint32_t reserved_f28; + uint32_t reserved_f2c; + uint32_t reserved_f30; + uint32_t reserved_f34; + uint32_t reserved_f38; + uint32_t reserved_f3c; + uint32_t reserved_f40; + uint32_t reserved_f44; + uint32_t reserved_f48; + uint32_t reserved_f4c; + uint32_t reserved_f50; + uint32_t reserved_f54; + uint32_t reserved_f58; + uint32_t reserved_f5c; + uint32_t reserved_f60; + uint32_t reserved_f64; + uint32_t reserved_f68; + uint32_t reserved_f6c; + uint32_t reserved_f70; + uint32_t reserved_f74; + uint32_t reserved_f78; + uint32_t reserved_f7c; + uint32_t reserved_f80; + uint32_t reserved_f84; + uint32_t reserved_f88; + uint32_t reserved_f8c; + uint32_t reserved_f90; + uint32_t reserved_f94; + uint32_t reserved_f98; + uint32_t reserved_f9c; + uint32_t reserved_fa0; + uint32_t reserved_fa4; + uint32_t reserved_fa8; + uint32_t reserved_fac; + uint32_t reserved_fb0; + uint32_t reserved_fb4; + uint32_t reserved_fb8; + uint32_t reserved_fbc; + uint32_t reserved_fc0; + uint32_t reserved_fc4; + uint32_t reserved_fc8; + uint32_t reserved_fcc; + uint32_t reserved_fd0; + uint32_t reserved_fd4; + uint32_t reserved_fd8; + uint32_t reserved_fdc; + uint32_t reserved_fe0; + uint32_t reserved_fe4; + uint32_t reserved_fe8; + uint32_t reserved_fec; + uint32_t reserved_ff0; + uint32_t reserved_ff4; + uint32_t reserved_ff8; + union { + struct { + uint32_t reg_date : 28; /*reg_date*/ + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} sensitive_dev_t; +extern sensitive_dev_t SENSITIVE; +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SENSITIVE_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h new file mode 100644 index 0000000000..8c1963c3f9 --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc.h @@ -0,0 +1,340 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#include "esp_bit_defs.h" +#endif + +#include "sdkconfig.h" + +#define PRO_CPU_NUM (0) + +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_GDMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_I2S0_BASE 0x6002D000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_AES_XTS_BASE 0x600CC000 + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ +#define BIT(nr) (1UL << (nr)) +#else +#define BIT(nr) (1 << (nr)) +#endif + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) ({ \ + (*(volatile uint32_t *)(_r)) = (_v); \ + }) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) |= (_b)); \ + }) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) &= ~(_b)); \ + }) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) ({ \ + (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ + }) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) ({ \ + (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ + }) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + }) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) ({ \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + }) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) ({ \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + }) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ + (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ + }) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define UART_CLK_FREQ_ROM ( 40*1000000) +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ APB_CLK_FREQ +#if CONFIG_IDF_ENV_FPGA +#define APB_CLK_FREQ ( 40*1000000 ) +#else +#define APB_CLK_FREQ ( 80*1000000 ) +#endif +#define REF_CLK_FREQ ( 1000000 ) +#define RTC_CLK_FREQ (20*1000000) +#define XTAL_CLK_FREQ (40*1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 40 // CPU is 80MHz +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +#define SOC_DROM_LOW 0x3C000000 +#define SOC_DROM_HIGH 0x3C800000 +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x42800000 +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40060000 +#define SOC_DROM_MASK_LOW 0x3FF00000 +#define SOC_DROM_MASK_HIGH 0x3FF20000 +#define SOC_IRAM_LOW 0x4037C000 +#define SOC_IRAM_HIGH 0x403E0000 +#define SOC_DRAM_LOW 0x3FC80000 +#define SOC_DRAM_HIGH 0x3FCE0000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C3 only has RTC slow memory +#define SOC_RTC_IRAM_HIGH 0x50002000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50002000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40380000 +#define SOC_DIRAM_IRAM_HIGH 0x403E0000 +#define SOC_DIRAM_DRAM_LOW 0x3FC80000 +#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x3FC88000 +#define SOC_DMA_HIGH 0x3FD00000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x3FC80000 +#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 +#define SOC_MEM_INTERNAL_LOW1 0x40370000 +#define SOC_MEM_INTERNAL_HIGH1 0x403E0000 +#define SOC_MEM_INTERNAL_LOW2 0x600FE000 +#define SOC_MEM_INTERNAL_HIGH2 0x60100000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x3fcebf10 + +//interrupt cpu using table, Please see the core-isa.h +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage + * 0 1 extern level Panic + * 1 1 extern level WMAC + * 2 1 extern level + * 3 1 extern level + * 4 1 extern level WBB + * 5 1 extern level BT/BLE Controller + * 6 1 timer FreeRTOS Tick(L1) + * 7 1 software + * 8 1 extern level BT/BLE BB(RX/TX) + * 9 1 extern level + * 10 1 extern edge + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved + * 15 3 timer FreeRTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level TG1_WDT + * 25 4 extern level CACHEERR + * 26 5 extern level + * 27 3 extern level Reserved + * 28 4 extern edge Reserved + * 29 3 software Reserved + * 30 4 extern edge Reserved + * 31 5 extern level + ************************************************************************************************************* + */ + +//CPU0 Interrupt number reserved, not touch this. +#define ETS_WMAC_INUM 1 +//#define ETS_BT_HOST_INUM 1 +#define ETS_WBB_INUM 4 +#define ETS_SYSTICK_INUM 9 +#define ETS_TG0_T1_INUM 10 /* use edge interrupt */ +#define ETS_CPU_INTR0_INUM 12 /* used as freertos soft intr */ +#define ETS_FRC1_INUM 22 +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#ifdef CONFIG_IDF_TARGET_ESP32C3 +#define ETS_MEMPROT_ERR_INUM 26 +#endif +#define ETS_DPORT_INUM 28 + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h new file mode 100644 index 0000000000..cfda89c29f --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -0,0 +1,271 @@ +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. + +#pragma once + +#define SOC_CPU_CORES_NUM 1 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_TWAI_SUPPORTED 1 +#define SOC_BT_SUPPORTED 1 +#define SOC_DIG_SIGN_SUPPORTED 1 +#define SOC_HMAC_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define SOC_USB_SERIAL_JTAG_SUPPORTED 1 + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +#define SOC_SUPPORTS_SECURE_DL_MODE 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 + + +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_PATT_LEN_MAX (16) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_MAX_CHANNEL_NUM (5) +#define SOC_ADC_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */ +#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1 +//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (1) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_BREAKPOINTS_NUM 8 +#define SOC_CPU_WATCHPOINTS_NUM 8 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 + +#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_GDMA_GROUPS (1) // Number of GDMA groups +#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group +#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C3 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1) +#define SOC_GPIO_PIN_COUNT (22) + +// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC +// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. +#define GPIO_SUPPORTS_RTC_INDEPENDENT (1) +// Force hold is a new function of ESP32-C3 +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) +#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) + +#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported + * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ +#define SOC_RTCIO_PIN_COUNT 0 + +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +/*-------------------------- SIGMA DELTA CAPS --------------------------------*/ +#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral +#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels + +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// Peripheral supports output given level during its "dummy phase" +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) + + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) + +/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ +#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 16384 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C3 has 2 UARTs +#define SOC_UART_NUM (2) + +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_RTC_CLK (1) +#define SOC_UART_SUPPORT_XTAL_CLK (1) + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/ +#define SOC_WIFI_HW_TSF (1) + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) +#define SOC_MAC_BB_PD_MEM_SIZE (192*4) + +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) + +#define SOC_PM_SUPPORT_BT_WAKEUP (1) + +#define SOC_PM_SUPPORT_CPU_PD (1) + +#define SOC_PM_SUPPORT_WIFI_PD (1) + +#define SOC_PM_SUPPORT_BT_PD (1) diff --git a/components/soc/esp32h2/include/soc/soc_pins.h b/components/soc/esp32h2/include/soc/soc_pins.h new file mode 100644 index 0000000000..fccf303153 --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_pins.h @@ -0,0 +1,24 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* + * Pin definition header file. The long term plan is to have a single soc_pins.h for all + * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each + * peripheral and include them here to avoid developing conflicts in those header files. + */ + +#pragma once + +#include "soc/gpio_pins.h" +#include "soc/spi_pins.h" diff --git a/components/soc/esp32h2/include/soc/soc_ulp.h b/components/soc/esp32h2/include/soc/soc_ulp.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/soc/esp32h2/include/soc/spi_mem_reg.h b/components/soc/esp32h2/include/soc/spi_mem_reg.h new file mode 100644 index 0000000000..fcf3e29248 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_mem_reg.h @@ -0,0 +1,1220 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_MEM_REG_H_ +#define _SOC_SPI_MEM_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the + bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is + set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). + Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from + the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared + once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 +/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: In user mode it is set to indicate that program/erase operation + will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 +/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state + 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/ +#define SPI_MEM_SLV_ST 0x0000000F +#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) +#define SPI_MEM_SLV_ST_V 0xF +#define SPI_MEM_SLV_ST_S 4 +/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The current status of SPI1 master FSM.*/ +#define SPI_MEM_MST_ST 0x0000000F +#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) +#define SPI_MEM_MST_ST_V 0xF +#define SPI_MEM_MST_ST_S 0 + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x004) +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: In user mode it is the memory address. other then the bit0-bit23 + is the memory address the bit24-bit31 are the byte length of a transfer.*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x008) +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is + set. 1: enable 0: disable.*/ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity 1: high 0 low*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity 1: high 0 low*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_MEM_RD_STATUS register this + bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio + spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 +/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1 enable crc32 when writing encrypted data to flash. + 1: enable 0:disable*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 +/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI1 initialize crc32 module before writing encrypted data + to flash. Active low.*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 +/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Apply 2 signals during command phase 1:enable 0: disable*/ +#define SPI_MEM_FCMD_DUAL (BIT(7)) +#define SPI_MEM_FCMD_DUAL_M (BIT(7)) +#define SPI_MEM_FCMD_DUAL_V 0x1 +#define SPI_MEM_FCMD_DUAL_S 7 +/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ +#define SPI_MEM_FDUMMY_OUT (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_V 0x1 +#define SPI_MEM_FDUMMY_OUT_S 3 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C) +/* SPI_MEM_RXFIFO_WFULL_ERR : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SPI0 RX FIFO write full error Cache/EDMA do not read all + the data out. 0: Not error.*/ +#define SPI_MEM_RXFIFO_WFULL_ERR (BIT(31)) +#define SPI_MEM_RXFIFO_WFULL_ERR_M (BIT(31)) +#define SPI_MEM_RXFIFO_WFULL_ERR_V 0x1 +#define SPI_MEM_RXFIFO_WFULL_ERR_S 31 +/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: SPI0 RX FIFO reset signal.*/ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ +/*description: After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] + * 512) SPI_CLK cycles.*/ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x010) +/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The FSM will be reset.*/ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between + SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ +/*description: Spi cs signal is delayed to inactive by spi clock this bits are + combined with spi_mem_cs_hold bit.*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ +/*description: (cycles-1) of prepare phase by spi clock this bits are combined + with spi_mem_cs_setup bit.*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x014) +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit in 1-division mode.reserved for spi1*/ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk + frequency is system/(spi_mem_clkcnt_N+1)*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018) +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation.*/ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation.*/ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation.*/ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation.*/ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation.*/ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable.*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. + 1: enable 0: disable.*/ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. + 1: enable 0: disable.*/ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals.*/ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals.*/ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals*/ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals*/ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi + signal delay mode.*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x01C) +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ +/*description: The length in spi_mem_clk cycles of dummy phase. The register + value shall be (cycle_num-1).*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x020) +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command.*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x024) +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x028) +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x02C) +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode + bit.*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x034) +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set.*/ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/* SPI_MEM_SLV_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt of spi0_slv_st controlled + transmitting is done.*/ +#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA (BIT(6)) +#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_M (BIT(6)) +#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_S 6 +/* SPI_MEM_SLV_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the spi0_slv_st controlled transmitting is done.*/ +#define SPI_MEM_SLV_ST_TRANS_END (BIT(5)) +#define SPI_MEM_SLV_ST_TRANS_END_M (BIT(5)) +#define SPI_MEM_SLV_ST_TRANS_END_V 0x1 +#define SPI_MEM_SLV_ST_TRANS_END_S 5 +/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt of SPI0 cspi_st controlled + transmitting is done.*/ +#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA (BIT(4)) +#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S 4 +/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the SPI0 cspi_st controlled transmitting is done.*/ +#define SPI_MEM_CSPI_ST_TRANS_END (BIT(3)) +#define SPI_MEM_CSPI_ST_TRANS_END_M (BIT(3)) +#define SPI_MEM_CSPI_ST_TRANS_END_V 0x1 +#define SPI_MEM_CSPI_ST_TRANS_END_S 3 +/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt of SPI0 em_st controlled + transmitting is done.*/ +#define SPI_MEM_TRANS_END_INT_ENA (BIT(2)) +#define SPI_MEM_TRANS_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_TRANS_END_INT_ENA_S 2 +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active + to select SPI device such as flash external RAM and so on.*/ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI_CS0 pin enable 1: disable SPI_CS0 0: SPI_CS0 pin is active + to select SPI device such as flash external RAM and so on.*/ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x038) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: For SPI1 the value of crc32.*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x03C) +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI1 address phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio.*/ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI1 dout phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio.*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: For SPI1 din phase apply 4 signals. 1: enable 0: disable. The + bit is the same with spi_mem_fread_qio.*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: For SPI1 address phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio.*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI1 dout phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_fread_dio.*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI1 din phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_fread_dio.*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash with 4 bytes address 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_REQ_EN (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_V 0x1 +#define SPI_MEM_CACHE_REQ_EN_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x054) +/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ +/*description: The lock delay time of SPI0/1 arbiter by cspi_st after PER is sent by SPI1.*/ +#define SPI_MEM_CSPI_LOCK_DELAY_TIME 0x0000001F +#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S)) +#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V 0x1F +#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S 7 +/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The current status of SPI0 master FSM: cspi_st. 0: idle state + 1:EM_CACHE_GRANT 2: program/erase suspend state 3: SPI0 read data state 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO 5: SPI0 write data state.*/ +#define SPI_MEM_EM_ST 0x00000007 +#define SPI_MEM_EM_ST_M ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S)) +#define SPI_MEM_EM_ST_V 0x7 +#define SPI_MEM_EM_ST_S 4 +/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: The current status of SPI0 slave FSM: cspi_st. 0: idle state + 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/ +#define SPI_MEM_CSPI_ST 0x0000000F +#define SPI_MEM_CSPI_ST_M ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S)) +#define SPI_MEM_CSPI_ST_V 0xF +#define SPI_MEM_CSPI_ST_S 0 + +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x058) +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x05C) +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x060) +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x064) +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x068) +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x06C) +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x070) +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x074) +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x078) +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x07C) +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x080) +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x084) +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x088) +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x08C) +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x090) +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x094) +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x098) +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: The dummy cycle length when wait flash idle(RDSR).*/ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */ +/*description: The command to wait flash idle(RDSR).*/ +#define SPI_MEM_WAITI_CMD 0x000000FF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFF +#define SPI_MEM_WAITI_CMD_S 2 +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The dummy phase enable when wait flash idle (RDSR)*/ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x09C) +/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ +/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] + times it will be treated as check pass.*/ +#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F +#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) +#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F +#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 +/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure + the suspend status of flash. 0: Only need to check WIP is 0.*/ +#define SPI_MEM_PES_END_EN (BIT(24)) +#define SPI_MEM_PES_END_EN_M (BIT(24)) +#define SPI_MEM_PES_END_EN_V 0x1 +#define SPI_MEM_PES_END_EN_S 24 +/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure + the resume status of flash. 0: Only need to check WIP is 0.*/ +#define SPI_MEM_PER_END_EN (BIT(23)) +#define SPI_MEM_PER_END_EN_M (BIT(23)) +#define SPI_MEM_PER_END_EN_V 0x1 +#define SPI_MEM_PER_END_EN_S 23 +/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. + 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ +#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_M (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_V 0x1 +#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ +/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read + status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out status_in[15:0] is valid when two bytes of data are read out) SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ +#define SPI_MEM_PESR_END_MSK 0x0000FFFF +#define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) +#define SPI_MEM_PESR_END_MSK_V 0xFFFF +#define SPI_MEM_PESR_END_MSK_S 6 +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable Auto-suspending function.*/ +#define SPI_MEM_FLASH_PES_EN (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 5 +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable PES transfer trigger PES transfer option. + If this bit is 0 application should send PER after PES is done.*/ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] + * 4) SPI_CLK cycles after program erase suspend.*/ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] + * 4) SPI_CLK cycles after program erase resume.*/ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program erase suspend bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 +/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: program erase resume bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A0) +/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should + be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ +#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF +#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) +#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF +#define SPI_MEM_WAIT_PESR_COMMAND_S 16 +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */ +/*description: Program/Erase suspend command.*/ +#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PES_COMMAND_S 8 +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */ +/*description: Program/Erase resume command.*/ +#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PER_COMMAND_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A4) +/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/ +#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_V 0x1 +#define SPI_MEM_SPI0_LOCK_EN_S 7 +/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] + * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ +#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_128_S 6 +/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] + * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ +#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_128_S 5 +/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK + cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ +#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_128_S 4 +/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK + cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ +#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_128_S 3 +/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK + cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ +#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_128_S 2 +/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 + bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/ +#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 +#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status of flash suspend only used in SPI1.*/ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8) +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: add extra dummy spi clock cycle length for spi clock calibration.*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable timing auto-calibration for all reading operations.*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable timing adjust clock for all reading operations.*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC) +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN3_MODE 0x00000003 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x3 +#define SPI_MEM_DIN3_MODE_S 6 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN2_MODE 0x00000003 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x3 +#define SPI_MEM_DIN2_MODE_S 4 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN1_MODE 0x00000003 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x3 +#define SPI_MEM_DIN1_MODE_S 2 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN0_MODE 0x00000003 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x3 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B0) +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B4) +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C0) +/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ +#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_V 0x1 +#define SPI_MEM_WPE_END_INT_ENA_S 2 +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PES_END_INT interrupt.*/ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PER_END_INT interrupt.*/ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 + +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C4) +/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ +#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_V 0x1 +#define SPI_MEM_WPE_END_INT_CLR_S 2 +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PES_END_INT interrupt.*/ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PER_END_INT interrupt.*/ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 + +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C8) +/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered + when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered + when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when + WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ +#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_V 0x1 +#define SPI_MEM_WPE_END_INT_RAW_S 2 +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when + Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when + Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 + +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0x0CC) +/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_WPE_END_INT interrupt.*/ +#define SPI_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_V 0x1 +#define SPI_MEM_WPE_END_INT_ST_S 2 +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PES_END_INT interrupt.*/ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PER_END_INT interrupt.*/ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC) +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Register clock gate enable signal. 1: Enable. 0: Disable.*/ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0E0) +/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: When the digital system clock selects PLL clock and the frequency + of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ +#define SPI_MEM_SPI01_CLK_SEL 0x00000003 +#define SPI_MEM_SPI01_CLK_SEL_M ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S)) +#define SPI_MEM_SPI01_CLK_SEL_V 0x3 +#define SPI_MEM_SPI01_CLK_SEL_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007170 ; */ +/*description: Version control register*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SPI_MEM_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/spi_mem_struct.h b/components/soc/esp32h2/include/soc/spi_mem_struct.h new file mode 100644 index 0000000000..e0f62b0d15 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_mem_struct.h @@ -0,0 +1,569 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_MEM_STRUCT_H_ +#define _SOC_SPI_MEM_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/ + uint32_t st: 4; /*The current status of SPI1 slave FSM: mspi_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/ + uint32_t reserved8: 9; /*reserved*/ + uint32_t flash_pe: 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ + uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + }; + uint32_t val; + } cmd; + uint32_t addr; /*SPI1 address register*/ + union { + struct { + uint32_t reserved0: 3; /*reserved*/ + uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ + uint32_t reserved4: 3; /*reserved*/ + uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t reserved9: 1; /*reserved*/ + uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12: 1; /*reserved*/ + uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/ + uint32_t reserved16: 2; /*reserved*/ + uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ + uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t reserved25: 7; /*reserved*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t cs_hold_dly_res: 10; /*After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ + uint32_t reserved2: 18; /*reserved*/ + uint32_t rxfifo_rst: 1; /*SPI0 RX FIFO reset signal.*/ + uint32_t rxfifo_wfull_err: 1; /*1: SPI0 RX FIFO write full error Cache/EDMA do not read all the data out. 0: Not error.*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t reserved10: 15; /*reserved*/ + uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset: 1; /*The FSM will be reset.*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/ + uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24: 7; /*reserved*/ + uint32_t clk_equ_sysclk: 1; /*Set this bit in 1-division mode.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t reserved0: 6; /*reserved*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ + uint32_t reserved8: 1; /*reserved*/ + uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/ + uint32_t reserved10: 2; /*reserved*/ + uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t reserved16: 8; /*reserved*/ + uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/ + uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/ + uint32_t usr_dummy_idle: 1; /*SPI clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen: 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t reserved6: 20; /*reserved*/ + uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value: 16; /*The value of command.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_bit_len: 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_bit_len: 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + union { + struct { + uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ + uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } rd_status; + uint32_t reserved_30; + union { + struct { + uint32_t cs0_dis: 1; /*SPI_CS0 pin enable 1: disable SPI_CS0 0: SPI_CS0 pin is active to select SPI device such as flash external RAM and so on.*/ + uint32_t cs1_dis: 1; /*SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active to select SPI device such as flash external RAM and so on.*/ + uint32_t reserved2: 1; /*reserved*/ + uint32_t mst_st_trans_end: 1; /*The bit is used to indicate the spi0_mst_st controlled transmitting is done.*/ + uint32_t mst_st_trans_end_en: 1; /*The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.*/ + uint32_t st_trans_end: 1; /*The bit is used to indicate the spi0_slv_st controlled transmitting is done.*/ + uint32_t st_trans_end_en: 1; /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/ + uint32_t reserved7: 2; /*reserved*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } misc; + uint32_t tx_crc; /*SPI1 TX CRC data register.*/ + union { + struct { + uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + uint32_t usr_addr_4byte: 1; /*For SPI1 cache read flash with 4 bytes address 1: enable 0:disable.*/ + uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + uint32_t fdin_dual: 1; /*For SPI1 din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdout_dual: 1; /*For SPI1 dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t faddr_dual: 1; /*For SPI1 address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdin_quad: 1; /*For SPI1 din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t fdout_quad: 1; /*For SPI1 dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t faddr_quad: 1; /*For SPI1 address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } cache_fctrl; + uint32_t reserved_40; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + union { + struct { + uint32_t spi0_st: 4; /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/ + uint32_t spi0_mst_st: 3; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state 1:EM_CACHE_GRANT 2: program/erase suspend state 3: SPI0 read data state 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO 5: SPI0 write data state.*/ + uint32_t cspi_lock_delay_time: 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st after PER is sent by SPI1.*/ + uint32_t reserved12: 20; /*reserved*/ + }; + uint32_t val; + } fsm; + uint32_t data_buf[16]; + union { + struct { + uint32_t reserved0: 1; /*reserved*/ + uint32_t waiti_dummy: 1; /*The dummy phase enable when wait flash idle (RDSR)*/ + uint32_t waiti_cmd: 8; /*The command to wait flash idle(RDSR).*/ + uint32_t waiti_dummy_cyclelen: 6; /*The dummy cycle length when wait flash idle(RDSR).*/ + uint32_t reserved16: 16; /*reserved*/ + }; + uint32_t val; + } flash_waiti_ctrl; + union { + struct { + uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_per_wait_en: 1; /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/ + uint32_t flash_pes_wait_en: 1; /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/ + uint32_t pes_per_en: 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0 application should send PER after PES is done.*/ + uint32_t flash_pes_en: 1; /*Set this bit to enable Auto-suspending function.*/ + uint32_t pesr_end_msk: 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out status_in[15:0] is valid when two bytes of data are read out) SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ + uint32_t frd_sus_2b: 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ + uint32_t per_end_en: 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ + uint32_t pes_end_en: 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ + uint32_t sus_timeout_cnt: 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times it will be treated as check pass.*/ + }; + uint32_t val; + } flash_sus_ctrl; + union { + struct { + uint32_t flash_per_command: 8; /*Program/Erase resume command.*/ + uint32_t flash_pes_command: 8; /*Program/Erase suspend command.*/ + uint32_t wait_pesr_command: 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ + }; + uint32_t val; + } flash_sus_cmd; + union { + struct { + uint32_t flash_sus: 1; /*The status of flash suspend only used in SPI1.*/ + uint32_t reserved1: 31; /*reserved*/ + }; + uint32_t val; + } sus_status; + union { + struct { + uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reserved5: 27; /*reserved*/ + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t reserved8: 24; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved8: 24; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } dout_mode; + uint32_t reserved_b8; + uint32_t reserved_bc; + union { + struct { + uint32_t per_end_int_ena: 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_int_ena: 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end_int_ena: 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t st_end_int_ena: 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end_int_ena: 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t reserved5: 27; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t per_end: 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end: 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end: 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t st_end: 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end: 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t reserved5: 27; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t per_end: 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/ + uint32_t pes_end: 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/ + uint32_t wpe_end: 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ + uint32_t st_end: 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ + uint32_t mst_st_end: 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/ + uint32_t reserved5: 27; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t per_end: 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end: 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end: 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t st_end: 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end: 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t reserved5: 27; /*reserved*/ + }; + uint32_t val; + } int_st; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + union { + struct { + uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1: 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + union { + struct { + uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ + uint32_t reserved2: 30; /*reserved*/ + }; + uint32_t val; + } core_clk_sel; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + union { + struct { + uint32_t date: 28; /*Version control register*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_mem_dev_t; +extern spi_mem_dev_t SPIMEM0; +extern spi_mem_dev_t SPIMEM1; + +_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!"); + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_SPI_MEM_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/spi_pins.h b/components/soc/esp32h2/include/soc/spi_pins.h new file mode 100644 index 0000000000..665dfabde3 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_pins.h @@ -0,0 +1,34 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_SPI_PINS_H_ +#define _SOC_SPI_PINS_H_ + +#define SPI_FUNC_NUM 0 +#define SPI_IOMUX_PIN_NUM_HD 12 +#define SPI_IOMUX_PIN_NUM_CS 14 +#define SPI_IOMUX_PIN_NUM_MOSI 16 +#define SPI_IOMUX_PIN_NUM_CLK 15 +#define SPI_IOMUX_PIN_NUM_MISO 17 +#define SPI_IOMUX_PIN_NUM_WP 13 + +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 10 + +#endif diff --git a/components/soc/esp32h2/include/soc/spi_reg.h b/components/soc/esp32h2/include/soc/spi_reg.h new file mode 100644 index 0000000000..a08cb24f3c --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_reg.h @@ -0,0 +1,1443 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_REG_H_ +#define _SOC_SPI_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when the bit is set. + The bit will be cleared once the operation done.1: enable 0: disable. Can not b +e changed by CONF_buf..*/ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (BIT(24)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 24 +/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module +clock domain, which is only used in SPI master mode..*/ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (BIT(23)) +#define SPI_UPDATE_V 0x1 +#define SPI_UPDATE_S 23 +/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state..*/ +#define SPI_CONF_BITLEN 0x0003FFFF +#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S)) +#define SPI_CONF_BITLEN_V 0x3FFFF +#define SPI_CONF_BITLEN_S 0 + +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Address to slave. Can be configured in CONF state..*/ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S)) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 + +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con +figured in CONF state..*/ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s +tate..*/ +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 +/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. C +an be configured in CONF state..*/ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (BIT(21)) +#define SPI_WP_POL_V 0x1 +#define SPI_WP_POL_S 21 +/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co +nfigured in CONF state..*/ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (BIT(20)) +#define SPI_HOLD_POL_V 0x1 +#define SPI_HOLD_POL_S 20 +/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in +CONF state..*/ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (BIT(19)) +#define SPI_D_POL_V 0x1 +#define SPI_D_POL_S 19 +/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in +CONF state..*/ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (BIT(18)) +#define SPI_Q_POL_V 0x1 +#define SPI_Q_POL_S 18 +/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable. C +an be configured in CONF state..*/ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (BIT(15)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 15 +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C +an be configured in CONF state..*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 +/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C +ONF state..*/ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (BIT(9)) +#define SPI_FCMD_QUAD_V 0x1 +#define SPI_FCMD_QUAD_S 9 +/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C +ONF state..*/ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (BIT(8)) +#define SPI_FCMD_DUAL_V 0x1 +#define SPI_FCMD_DUAL_S 8 +/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + state..*/ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (BIT(6)) +#define SPI_FADDR_QUAD_V 0x1 +#define SPI_FADDR_QUAD_S 6 +/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + state..*/ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (BIT(5)) +#define SPI_FADDR_DUAL_V 0x1 +#define SPI_FADDR_DUAL_S 5 +/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the dummy phase the signal level of spi is output by the spi controller. Can +be configured in CONF state..*/ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (BIT(3)) +#define SPI_DUMMY_OUT_V 0x1 +#define SPI_DUMMY_OUT_S 3 + +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst +em clock. Can be configured in CONF state..*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF stat +e..*/ +#define SPI_CLKDIV_PRE 0x0000000F +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0xF +#define SPI_CLKDIV_PRE_S 18 +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/ +(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it +must be 0. Can be configured in CONF state..*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b +e 0. Can be configured in CONF state..*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation. Can be configured in CONF sta +te..*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation. Can be configured in CONF sta +te..*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state +..*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s +tate..*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation. Can be configured in CONF +state..*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in + CONF state..*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl +e 0: disable. Can be configured in CONF state..*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + 0: disable. Can be configured in CONF state..*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 +/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha +re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (BIT(17)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 17 +/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans +will continue. 0: The seg-trans will end after the current SPI seg-trans or this + is not seg-trans mode. Can be configured in CONF state..*/ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (BIT(15)) +#define SPI_USR_CONF_NXT_V 0x1 +#define SPI_USR_CONF_NXT_S 15 +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO +NF state..*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO +NF state..*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca +n be configured in CONF state..*/ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (BIT(9)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 9 +/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck += !spi_ck_i. 1:rsck = spi_ck_i..*/ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (BIT(8)) +#define SPI_RSCK_I_EDGE_V 0x1 +#define SPI_RSCK_I_EDGE_S 8 +/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be co +nfigured in CONF state..*/ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (BIT(7)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 7 +/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be config +ured in CONF state..*/ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (BIT(6)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 6 +/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck += spi_ck_i. 1:tsck = !spi_ck_i..*/ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (BIT(5)) +#define SPI_TSCK_I_EDGE_V 0x1 +#define SPI_TSCK_I_EDGE_S 5 +/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others +. Can be configured in CONF state..*/ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (BIT(3)) +#define SPI_QPI_MODE_V 0x1 +#define SPI_QPI_MODE_S 3 +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co +nfigured in CONF state..*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) +/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca +n be configured in CONF state..*/ +#define SPI_USR_ADDR_BITLEN 0x0000001F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x1F +#define SPI_USR_ADDR_BITLEN_S 27 +/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */ +/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + Can be configured in CONF state..*/ +#define SPI_CS_HOLD_TIME 0x0000001F +#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S)) +#define SPI_CS_HOLD_TIME_V 0x1F +#define SPI_CS_HOLD_TIME_S 22 +/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ +/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu +p bit. Can be configured in CONF state..*/ +#define SPI_CS_SETUP_TIME 0x0000001F +#define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S)) +#define SPI_CS_SETUP_TIME_V 0x1F +#define SPI_CS_SETUP_TIME_S 17 +/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid + in GP-SPI master FD/HD-mode..*/ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_V 0x1 +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ +/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_ +num-1). Can be configured in CONF state..*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca +n be configured in CONF state..*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m +aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro +r is valid in GP-SPI master FD/HD-mode..*/ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x1 +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command. Can be configured in CONF state..*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C) +/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: The value of these bits is the configured SPI transmission data bit length in ma +ster mode DMA controlled transfer or CPU controlled transfer. The value is also +the configured bit length in slave mode DMA RX controlled transfer. The register + value shall be (bit_num-1). Can be configured in CONF state..*/ +#define SPI_MS_DATA_BITLEN 0x0003FFFF +#define SPI_MS_DATA_BITLEN_M ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S)) +#define SPI_MS_DATA_BITLEN_V 0x3FFFF +#define SPI_MS_DATA_BITLEN_S 0 + +#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) +/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: spi quad input swap enable 0: spi quad input swap disable. Can be configur +ed in CONF state..*/ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x1 +#define SPI_QUAD_DIN_PIN_SWAP_S 31 +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be c +onfigured in CONF state..*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 +/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: spi slave input cs polarity select. 1: inv 0: not change. Can be configured in +CONF state..*/ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (BIT(23)) +#define SPI_SLAVE_CS_POL_V 0x1 +#define SPI_SLAVE_CS_POL_S 23 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva +lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/ +#define SPI_MASTER_CS_POL 0x0000003F +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x3F +#define SPI_MASTER_CS_POL_S 7 +/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state..*/ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (BIT(6)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 6 +/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (BIT(5)) +#define SPI_CS5_DIS_V 0x1 +#define SPI_CS5_DIS_S 5 +/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (BIT(4)) +#define SPI_CS4_DIS_V 0x1 +#define SPI_CS4_DIS_S 4 +/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (BIT(3)) +#define SPI_CS3_DIS_V 0x1 +#define SPI_CS3_DIS_S 3 +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) +/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in C +ONF state..*/ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_V 0x1 +#define SPI_TIMING_HCLK_ACTIVE_S 16 +/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN3_MODE 0x00000003 +#define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S)) +#define SPI_DIN3_MODE_V 0x3 +#define SPI_DIN3_MODE_S 6 +/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN2_MODE 0x00000003 +#define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S)) +#define SPI_DIN2_MODE_V 0x3 +#define SPI_DIN2_MODE_S 4 +/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN1_MODE 0x00000003 +#define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S)) +#define SPI_DIN1_MODE_V 0x3 +#define SPI_DIN1_MODE_S 2 +/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN0_MODE 0x00000003 +#define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S)) +#define SPI_DIN0_MODE_V 0x3 +#define SPI_DIN0_MODE_S 0 + +#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) +/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN3_NUM 0x00000003 +#define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S)) +#define SPI_DIN3_NUM_V 0x3 +#define SPI_DIN3_NUM_S 6 +/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN2_NUM 0x00000003 +#define SPI_DIN2_NUM_M ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S)) +#define SPI_DIN2_NUM_V 0x3 +#define SPI_DIN2_NUM_S 4 +/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN1_NUM 0x00000003 +#define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S)) +#define SPI_DIN1_NUM_V 0x3 +#define SPI_DIN1_NUM_S 2 +/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN0_NUM 0x00000003 +#define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S)) +#define SPI_DIN0_NUM_V 0x3 +#define SPI_DIN0_NUM_S 0 + +#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2C) +/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (BIT(3)) +#define SPI_DOUT3_MODE_V 0x1 +#define SPI_DOUT3_MODE_S 3 +/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (BIT(2)) +#define SPI_DOUT2_MODE_V 0x1 +#define SPI_DOUT2_MODE_S 2 +/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (BIT(1)) +#define SPI_DOUT1_MODE_V 0x1 +#define SPI_DOUT1_MODE_S 1 +/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (BIT(0)) +#define SPI_DOUT0_MODE_V 0x1 +#define SPI_DOUT0_MODE_S 0 + +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) +/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave +DMA controlled mode transfer..*/ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (BIT(31)) +#define SPI_DMA_AFIFO_RST_V 0x1 +#define SPI_DMA_AFIFO_RST_S 31 +/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + controlled mode transfer and master mode transfer..*/ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (BIT(30)) +#define SPI_BUF_AFIFO_RST_V 0x1 +#define SPI_BUF_AFIFO_RST_S 30 +/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and +slave mode transfer..*/ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (BIT(29)) +#define SPI_RX_AFIFO_RST_V 0x1 +#define SPI_RX_AFIFO_RST_S 29 +/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI DMA controlled send data mode..*/ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (BIT(28)) +#define SPI_DMA_TX_ENA_V 0x1 +#define SPI_DMA_TX_ENA_S 28 +/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Set this bit to enable SPI DMA controlled receive data mode..*/ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (BIT(27)) +#define SPI_DMA_RX_ENA_V 0x1 +#define SPI_DMA_RX_ENA_S 27 +/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t +o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_d +ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don +e in seg-trans..*/ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (BIT(21)) +#define SPI_RX_EOF_EN_V 0x1 +#define SPI_RX_EOF_EN_S 21 +/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e +mpty_vld is cleared by spi_trans_done..*/ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full +_vld is cleared by spi_trans_done..*/ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 + +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) +/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (BIT(20)) +#define SPI_APP1_INT_ENA_V 0x1 +#define SPI_APP1_INT_ENA_S 20 +/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (BIT(19)) +#define SPI_APP2_INT_ENA_V 0x1 +#define SPI_APP2_INT_ENA_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1 +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_V 0x1 +#define SPI_TRANS_DONE_INT_ENA_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_V 0x1 +#define SPI_SLV_CMDA_INT_ENA_S 7 +/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_V 0x1 +#define SPI_SLV_CMD9_INT_ENA_S 6 +/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_V 0x1 +#define SPI_SLV_CMD8_INT_ENA_S 5 +/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_V 0x1 +#define SPI_SLV_CMD7_INT_ENA_S 4 +/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x1 +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x1 +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 + +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38) +/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (BIT(20)) +#define SPI_APP1_INT_CLR_V 0x1 +#define SPI_APP1_INT_CLR_S 20 +/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (BIT(19)) +#define SPI_APP2_INT_CLR_V 0x1 +#define SPI_APP2_INT_CLR_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x1 +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_V 0x1 +#define SPI_TRANS_DONE_INT_CLR_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_V 0x1 +#define SPI_SLV_CMDA_INT_CLR_S 7 +/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_V 0x1 +#define SPI_SLV_CMD9_INT_CLR_S 6 +/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_V 0x1 +#define SPI_SLV_CMD8_INT_CLR_S 5 +/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_V 0x1 +#define SPI_SLV_CMD7_INT_CLR_S 4 +/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x1 +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x1 +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 + +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3C) +/* SPI_APP1_INT_RAW : R/W/WTC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by applicat +ion..*/ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (BIT(20)) +#define SPI_APP1_INT_RAW_V 0x1 +#define SPI_APP1_INT_RAW_S 20 +/* SPI_APP2_INT_RAW : R/W/WTC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by applicat +ion..*/ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (BIT(19)) +#define SPI_APP2_INT_RAW_V 0x1 +#define SPI_APP2_INT_RAW_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF +AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + write-full error when SPI inputs data in master mode. 0: Others..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/* SPI_SLV_CMD_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + current SPI slave HD mode transmission is not supported. 0: Others..*/ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres +s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission + is bigger than 63. 0: Others..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff +er is error in the DMA seg-conf-trans. 0: others..*/ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-du +plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da +ta has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is +not ended or not occurred. .*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/* SPI_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + ended. 0: others..*/ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_V 0x1 +#define SPI_TRANS_DONE_INT_RAW_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran +smission is ended. 0: Others..*/ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran +smission is ended. 0: Others..*/ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran +smission is ended. 0: Others..*/ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran +smission is ended. 0: Others..*/ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/* SPI_SLV_CMDA_INT_RAW : R/W/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_V 0x1 +#define SPI_SLV_CMDA_INT_RAW_S 7 +/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_V 0x1 +#define SPI_SLV_CMD9_INT_RAW_S 6 +/* SPI_SLV_CMD8_INT_RAW : R/W/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_V 0x1 +#define SPI_SLV_CMD8_INT_RAW_S 5 +/* SPI_SLV_CMD7_INT_RAW : R/W/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_V 0x1 +#define SPI_SLV_CMD7_INT_RAW_S 4 +/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio +n is ended. 0: Others..*/ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x1 +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/* SPI_SLV_EX_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio +n is ended. 0: Others..*/ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x1 +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + master mode and send out all 0 in slave mode. 0: Others. .*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose +the receive data. 0: Others. .*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40) +/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The status bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (BIT(20)) +#define SPI_APP1_INT_ST_V 0x1 +#define SPI_APP1_INT_ST_S 20 +/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The status bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (BIT(19)) +#define SPI_APP2_INT_ST_V 0x1 +#define SPI_APP2_INT_ST_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x1 +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_V 0x1 +#define SPI_TRANS_DONE_INT_ST_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_V 0x1 +#define SPI_SLV_CMDA_INT_ST_S 7 +/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_V 0x1 +#define SPI_SLV_CMD9_INT_ST_S 6 +/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_V 0x1 +#define SPI_SLV_CMD8_INT_ST_S 5 +/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_V 0x1 +#define SPI_SLV_CMD7_INT_ST_S 4 +/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_V 0x1 +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_V 0x1 +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98) +/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9C) +/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xA0) +/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xA4) +/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xA8) +/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xAC) +/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xB0) +/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xB4) +/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xB8) +/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xBC) +/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xC0) +/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xC4) +/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xC8) +/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xCC) +/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xD0) +/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xD4) +/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xE0) +/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra +ns will start. 0: This is not seg-trans mode..*/ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (BIT(28)) +#define SPI_USR_CONF_V 0x1 +#define SPI_USR_CONF_S 28 +/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c +onfigured in CONF state..*/ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (BIT(27)) +#define SPI_SOFT_RESET_V 0x1 +#define SPI_SOFT_RESET_S 27 +/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set SPI work mode. 1: slave mode 0: master mode..*/ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (BIT(26)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 26 +/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */ +/*description: The magic value of BM table in master DMA seg-trans..*/ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F +#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S)) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng +th in CPU controlled mode(Wr_BUF). 0: others.*/ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x1 +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i +n CPU controlled mode(Rd_BUF). 0: others.*/ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x1 +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng +th in DMA controlled mode(Wr_DMA). 0: others.*/ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1 +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i +n DMA controlled mode(Rd_DMA). 0: others.*/ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x1 +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose +dge 0: output data at tsck posedge .*/ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (BIT(3)) +#define SPI_RSCK_DATA_OUT_V 0x1 +#define SPI_RSCK_DATA_OUT_S 3 +/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. + 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (BIT(2)) +#define SPI_CLK_MODE_13_V 0x1 +#define SPI_CLK_MODE_13_S 2 +/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ +#define SPI_CLK_MODE 0x00000003 +#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) +#define SPI_CLK_MODE_V 0x3 +#define SPI_CLK_MODE_S 0 + +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xE4) +/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */ +/*description: In the slave mode it is the value of address..*/ +#define SPI_SLV_LAST_ADDR 0x0000003F +#define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S)) +#define SPI_SLV_LAST_ADDR_V 0x3F +#define SPI_SLV_LAST_ADDR_S 26 +/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of command..*/ +#define SPI_SLV_LAST_COMMAND 0x000000FF +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0xFF +#define SPI_SLV_LAST_COMMAND_S 18 +/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: The transferred data bit length in SPI slave FD and HD mode. .*/ +#define SPI_SLV_DATA_BITLEN 0x0003FFFF +#define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S)) +#define SPI_SLV_DATA_BITLEN_V 0x3FFFF +#define SPI_SLV_DATA_BITLEN_S 0 + +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xE8) +/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80 +M. 0: XTAL CLK..*/ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (BIT(2)) +#define SPI_MST_CLK_SEL_V 0x1 +#define SPI_MST_CLK_SEL_S 2 +/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to power on the SPI module clock..*/ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (BIT(1)) +#define SPI_MST_CLK_ACTIVE_V 0x1 +#define SPI_MST_CLK_ACTIVE_S 1 +/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable clk gate.*/ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (BIT(0)) +#define SPI_CLK_EN_V 0x1 +#define SPI_CLK_EN_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xF0) +/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007220 ; */ +/*description: SPI register version..*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SPI_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/spi_struct.h b/components/soc/esp32h2/include/soc/spi_struct.h new file mode 100644 index 0000000000..cc22595dd0 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_struct.h @@ -0,0 +1,381 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_STRUCT_H_ +#define _SOC_SPI_STRUCT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ + uint32_t reserved18 : 5; /*reserved*/ + uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/ + uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ + uint32_t reserved25 : 7; /*reserved*/ + }; + uint32_t val; + } cmd; + uint32_t addr; + union { + struct { + uint32_t reserved0 : 3; /*reserved*/ + uint32_t dummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ + uint32_t reserved4 : 1; /*reserved*/ + uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved7 : 1; /*reserved*/ + uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved10 : 4; /*reserved*/ + uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved16 : 1; /*reserved*/ + uint32_t reserved17 : 1; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ + uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ + uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ + uint32_t reserved22 : 3; /*reserved*/ + uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ + uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ + uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ + uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ + uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ + uint32_t reserved22 : 9; /*reserved*/ + uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved1 : 2; /*reserved*/ + uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ + uint32_t reserved4 : 1; /*reserved*/ + uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ + uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ + uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ + uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ + uint32_t reserved14 : 1; /*reserved*/ + uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ + uint32_t reserved16 : 1; /*reserved*/ + uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved18 : 6; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ + uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ + uint32_t reserved8 : 8; /*reserved*/ + uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/ + uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ + uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ + uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/ + uint32_t reserved16 : 11; /*reserved*/ + uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } ms_dlen; + union { + struct { + uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/ + uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ + uint32_t reserved13 : 10; /*reserved*/ + uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ + uint32_t reserved24 : 5; /*reserved*/ + uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ + uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ + uint32_t quad_din_pin_swap : 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/ + }; + uint32_t val; + } misc; + union { + struct { + uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t reserved8 : 8; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t reserved4 : 28; /*reserved*/ + }; + uint32_t val; + } dout_mode; + union { + struct { + uint32_t reserved0 : 18; /*reserved*/ + uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ + uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ + uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ + uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ + uint32_t reserved22 : 5; /*reserved*/ + uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ + uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ + uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/ + uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ + uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/ + uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } dma_int_ena; + union { + struct { + uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/ + uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } dma_int_clr; + union { + struct { + uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */ + uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */ + uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ + uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ + uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ + uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ + uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ + uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ + uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ + uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ + uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ + uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ + uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ + uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */ + uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ + uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ + uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/ + uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.*/ + uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } dma_int_raw; + union { + struct { + uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/ + uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } dma_int_st; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t data_buf[16]; + uint32_t reserved_d8; + uint32_t reserved_dc; + union { + struct { + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ + uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ + uint32_t reserved4 : 4; /*reserved*/ + uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ + uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ + uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ + uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ + uint32_t reserved12 : 10; /*reserved*/ + uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/ + uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ + uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ + uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } slave; + union { + struct { + uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */ + uint32_t last_command : 8; /*In the slave mode it is the value of command.*/ + uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/ + }; + uint32_t val; + } slave1; + union { + struct { + uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ + uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/ + uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } clk_gate; + uint32_t reserved_ec; + union { + struct { + uint32_t date : 28; /*SPI register version.*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SPI_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/syscon_reg.h b/components/soc/esp32h2/include/soc/syscon_reg.h new file mode 100644 index 0000000000..cc5a3c68cb --- /dev/null +++ b/components/soc/esp32h2/include/soc/syscon_reg.h @@ -0,0 +1,628 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYSCON_REG_H_ +#define _SOC_SYSCON_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) +/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_RST_TICK_CNT (BIT(12)) +#define SYSCON_RST_TICK_CNT_M (BIT(12)) +#define SYSCON_RST_TICK_CNT_V 0x1 +#define SYSCON_RST_TICK_CNT_S 12 +/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_EN (BIT(11)) +#define SYSCON_CLK_EN_M (BIT(11)) +#define SYSCON_CLK_EN_V 0x1 +#define SYSCON_CLK_EN_S 11 +/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_320M_EN (BIT(10)) +#define SYSCON_CLK_320M_EN_M (BIT(10)) +#define SYSCON_CLK_320M_EN_V 0x1 +#define SYSCON_CLK_320M_EN_S 10 +/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define SYSCON_PRE_DIV_CNT 0x000003FF +#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) +#define SYSCON_PRE_DIV_CNT_V 0x3FF +#define SYSCON_PRE_DIV_CNT_S 0 + +#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) +/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define SYSCON_TICK_ENABLE (BIT(16)) +#define SYSCON_TICK_ENABLE_M (BIT(16)) +#define SYSCON_TICK_ENABLE_V 0x1 +#define SYSCON_TICK_ENABLE_S 16 +/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ +/*description: */ +#define SYSCON_CK8M_TICK_NUM 0x000000FF +#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) +#define SYSCON_CK8M_TICK_NUM_V 0xFF +#define SYSCON_CK8M_TICK_NUM_S 8 +/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define SYSCON_XTAL_TICK_NUM 0x000000FF +#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) +#define SYSCON_XTAL_TICK_NUM_V 0xFF +#define SYSCON_XTAL_TICK_NUM_S 0 + +#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) +/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_XTAL_OEN (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_M (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_V 0x1 +#define SYSCON_CLK_XTAL_OEN_S 10 +/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK40X_BB_OEN (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_M (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_V 0x1 +#define SYSCON_CLK40X_BB_OEN_S 9 +/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_V 0x1 +#define SYSCON_CLK_DAC_CPU_OEN_S 8 +/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_ADC_INF_OEN (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_V 0x1 +#define SYSCON_CLK_ADC_INF_OEN_S 7 +/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_320M_OEN (BIT(6)) +#define SYSCON_CLK_320M_OEN_M (BIT(6)) +#define SYSCON_CLK_320M_OEN_V 0x1 +#define SYSCON_CLK_320M_OEN_S 6 +/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK160_OEN (BIT(5)) +#define SYSCON_CLK160_OEN_M (BIT(5)) +#define SYSCON_CLK160_OEN_V 0x1 +#define SYSCON_CLK160_OEN_S 5 +/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK80_OEN (BIT(4)) +#define SYSCON_CLK80_OEN_M (BIT(4)) +#define SYSCON_CLK80_OEN_V 0x1 +#define SYSCON_CLK80_OEN_S 4 +/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_BB_OEN (BIT(3)) +#define SYSCON_CLK_BB_OEN_M (BIT(3)) +#define SYSCON_CLK_BB_OEN_V 0x1 +#define SYSCON_CLK_BB_OEN_S 3 +/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK44_OEN (BIT(2)) +#define SYSCON_CLK44_OEN_M (BIT(2)) +#define SYSCON_CLK44_OEN_V 0x1 +#define SYSCON_CLK44_OEN_S 2 +/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK22_OEN (BIT(1)) +#define SYSCON_CLK22_OEN_M (BIT(1)) +#define SYSCON_CLK22_OEN_V 0x1 +#define SYSCON_CLK22_OEN_S 1 +/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK20_OEN (BIT(0)) +#define SYSCON_CLK20_OEN_M (BIT(0)) +#define SYSCON_CLK20_OEN_V 0x1 +#define SYSCON_CLK20_OEN_S 0 + +#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) +/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) +#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_S 0 + +#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) +/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) +#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_S 0 + +#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) +/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) +#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_S 0 + +#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) +/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_WIFI_RST 0xFFFFFFFF +#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) +#define SYSCON_WIFI_RST_V 0xFFFFFFFF +#define SYSCON_WIFI_RST_S 0 + +#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG +/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF +#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S)) +#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF +#define SYSTEM_WIFI_CLK_EN_S 0 + +/* Mask for all Wifi clock bits, 6 */ +#define SYSTEM_WIFI_CLK_WIFI_EN 0x0 +#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) +#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 +#define SYSTEM_WIFI_CLK_WIFI_EN_S 0 +/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */ +#define SYSTEM_WIFI_CLK_BT_EN 0x0 +#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) +#define SYSTEM_WIFI_CLK_BT_EN_V 0x0 +#define SYSTEM_WIFI_CLK_BT_EN_S 0 +/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ +#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F + +/* Digital team to check */ +//bluetooth baseband bit11 +#define SYSTEM_BT_BASEBAND_EN BIT(11) +//bluetooth LC bit16 and bit17 +#define SYSTEM_BT_LC_EN (BIT(16)|BIT(17)) + +/* Remaining single bit clock masks */ +#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4) +#define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5) +#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) +#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) +#define SYSTEM_WIFI_CLK_RNG_EN BIT(15) + +#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG +#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG +/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSTEM_BB_RST BIT(0) +#define SYSTEM_FE_RST BIT(1) +#define SYSTEM_MAC_RST BIT(2) +#define SYSTEM_BT_RST BIT(3) +#define SYSTEM_BTMAC_RST BIT(4) +#define SYSTEM_SDIO_RST BIT(5) +#define SYSTEM_EMAC_RST BIT(7) +#define SYSTEM_MACPWR_RST BIT(8) +#define SYSTEM_RW_BTMAC_RST BIT(9) +#define SYSTEM_RW_BTLP_RST BIT(10) +#define BLE_REG_REST_BIT BIT(11) +#define BLE_PWR_REG_REST_BIT BIT(12) +#define BLE_BB_REG_REST_BIT BIT(13) + +#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) +/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SYSCON_PERI_IO_SWAP 0x000000FF +#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) +#define SYSCON_PERI_IO_SWAP_V 0xFF +#define SYSCON_PERI_IO_SWAP_S 0 + +#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) +/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 +#define SYSCON_EXT_MEM_PMS_LOCK_S 0 + +#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) +/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define SYSCON_FLASH_ACE0_ATTR 0x00000003 +#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) +#define SYSCON_FLASH_ACE0_ATTR_V 0x3 +#define SYSCON_FLASH_ACE0_ATTR_S 0 + +#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) +/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define SYSCON_FLASH_ACE1_ATTR 0x00000003 +#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) +#define SYSCON_FLASH_ACE1_ATTR_V 0x3 +#define SYSCON_FLASH_ACE1_ATTR_S 0 + +#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) +/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define SYSCON_FLASH_ACE2_ATTR 0x00000003 +#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) +#define SYSCON_FLASH_ACE2_ATTR_V 0x3 +#define SYSCON_FLASH_ACE2_ATTR_S 0 + +#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034) +/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ +/*description: */ +#define SYSCON_FLASH_ACE3_ATTR 0x00000003 +#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) +#define SYSCON_FLASH_ACE3_ATTR_V 0x3 +#define SYSCON_FLASH_ACE3_ATTR_S 0 + +#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) +/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) +#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) +/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) +#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) +/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) +#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044) +/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) +#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) +/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define SYSCON_FLASH_ACE0_SIZE 0x00001FFF +#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) +#define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF +#define SYSCON_FLASH_ACE0_SIZE_S 0 + +#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) +/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define SYSCON_FLASH_ACE1_SIZE 0x00001FFF +#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) +#define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF +#define SYSCON_FLASH_ACE1_SIZE_S 0 + +#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) +/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define SYSCON_FLASH_ACE2_SIZE 0x00001FFF +#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) +#define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF +#define SYSCON_FLASH_ACE2_SIZE_S 0 + +#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054) +/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ +/*description: */ +#define SYSCON_FLASH_ACE3_SIZE 0x00001FFF +#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) +#define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF +#define SYSCON_FLASH_ACE3_SIZE_S 0 + +#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088) +/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F +#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) +#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F +#define SYSCON_SPI_MEM_REJECT_CDE_S 2 +/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 +#define SYSCON_SPI_MEM_REJECT_CLR_S 1 +/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 +#define SYSCON_SPI_MEM_REJECT_INT_S 0 + +#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C) +/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) +#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 + +#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090) +/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 +#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 + +#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094) +/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSCON_REDCY_ANDOR (BIT(31)) +#define SYSCON_REDCY_ANDOR_M (BIT(31)) +#define SYSCON_REDCY_ANDOR_V 0x1 +#define SYSCON_REDCY_ANDOR_S 31 +/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define SYSCON_REDCY_SIG0 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) +#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_S 0 + +#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098) +/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSCON_REDCY_NANDOR (BIT(31)) +#define SYSCON_REDCY_NANDOR_M (BIT(31)) +#define SYSCON_REDCY_NANDOR_V 0x1 +#define SYSCON_REDCY_NANDOR_S 31 +/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define SYSCON_REDCY_SIG1 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) +#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_S 0 + +#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C) +/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_V 0x1 +#define SYSCON_DC_MEM_FORCE_PD_S 5 +/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_V 0x1 +#define SYSCON_DC_MEM_FORCE_PU_S 4 +/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PD_S 3 +/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PU_S 2 +/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PD_S 1 +/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PU_S 0 + +#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0) +/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) +#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) +#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 +#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 +/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: */ +#define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF +#define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S)) +#define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF +#define SYSCON_RETENTION_LINK_ADDR_S 0 + +#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4) +/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ +/*description: */ +#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F +#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) +#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF +#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2 +/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003 +#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) +#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x3 +#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 + +#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0A8) +/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */ +/*description: */ +#define SYSCON_SRAM_POWER_DOWN 0x0000000F +#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) +#define SYSCON_SRAM_POWER_DOWN_V 0xF +#define SYSCON_SRAM_POWER_DOWN_S 2 +/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SYSCON_ROM_POWER_DOWN 0x00000003 +#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) +#define SYSCON_ROM_POWER_DOWN_V 0x3 +#define SYSCON_ROM_POWER_DOWN_S 0 + +#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0AC) +/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ +/*description: */ +#define SYSCON_SRAM_POWER_UP 0x0000000F +#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) +#define SYSCON_SRAM_POWER_UP_V 0xF +#define SYSCON_SRAM_POWER_UP_S 2 +/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SYSCON_ROM_POWER_UP 0x00000003 +#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) +#define SYSCON_ROM_POWER_UP_V 0x3 +#define SYSCON_ROM_POWER_UP_S 0 + +#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0x0B0) +/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSCON_RND_DATA 0xFFFFFFFF +#define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S)) +#define SYSCON_RND_DATA_V 0xFFFFFFFF +#define SYSCON_RND_DATA_S 0 + +#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0x0B4) +/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_ENA (BIT(31)) +#define SYSCON_PERI_BACKUP_ENA_M (BIT(31)) +#define SYSCON_PERI_BACKUP_ENA_V 0x1 +#define SYSCON_PERI_BACKUP_ENA_S 31 +/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_TO_MEM (BIT(30)) +#define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30)) +#define SYSCON_PERI_BACKUP_TO_MEM_V 0x1 +#define SYSCON_PERI_BACKUP_TO_MEM_S 30 +/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_START (BIT(29)) +#define SYSCON_PERI_BACKUP_START_M (BIT(29)) +#define SYSCON_PERI_BACKUP_START_V 0x1 +#define SYSCON_PERI_BACKUP_START_S 29 +/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_SIZE 0x000003FF +#define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S)) +#define SYSCON_PERI_BACKUP_SIZE_V 0x3FF +#define SYSCON_PERI_BACKUP_SIZE_S 19 +/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF +#define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S)) +#define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF +#define SYSCON_PERI_BACKUP_TOUT_THRES_S 9 +/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F +#define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S)) +#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F +#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 +/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003 +#define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S)) +#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3 +#define SYSCON_PERI_BACKUP_FLOW_ERR_S 1 + +#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8) +/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF +#define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S)) +#define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF +#define SYSCON_BACKUP_APB_START_ADDR_S 0 + +#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC) +/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF +#define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S)) +#define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF +#define SYSCON_BACKUP_MEM_START_ADDR_S 0 + +#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0C0) +/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1 +#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1 +/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1 +#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 + +#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0C4) +/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1 +#define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1 +/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1 +#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 + +#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0C8) +/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1 +#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1 +/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1 +#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 + +#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0D0) +/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) +#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1 +#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1 +/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) +#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1 +#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 + +#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */ +/*description: Version control*/ +#define SYSCON_DATE 0xFFFFFFFF +#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) +#define SYSCON_DATE_V 0xFFFFFFFF +#define SYSCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SYSCON_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/syscon_struct.h b/components/soc/esp32h2/include/soc/syscon_struct.h new file mode 100644 index 0000000000..2a9485aa87 --- /dev/null +++ b/components/soc/esp32h2/include/soc/syscon_struct.h @@ -0,0 +1,482 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYSCON_STRUCT_H_ +#define _SOC_SYSCON_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t apb_ctrl_pre_div_cnt: 10; + uint32_t apb_ctrl_clk_320m_en: 1; + uint32_t clk_en: 1; + uint32_t apb_ctrl_rst_tick_cnt: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } apb_ctrl_sysclk_conf; + union { + struct { + uint32_t apb_ctrl_xtal_tick_num: 8; + uint32_t apb_ctrl_ck8m_tick_num: 8; + uint32_t apb_ctrl_tick_enable: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } apb_ctrl_tick_conf; + union { + struct { + uint32_t clk20_oen: 1; + uint32_t clk22_oen: 1; + uint32_t clk44_oen: 1; + uint32_t clk_bb_oen: 1; + uint32_t clk80_oen: 1; + uint32_t clk160_oen: 1; + uint32_t clk_320m_oen: 1; + uint32_t clk_adc_inf_oen: 1; + uint32_t clk_dac_cpu_oen: 1; + uint32_t clk40x_bb_oen: 1; + uint32_t clk_xtal_oen: 1; + uint32_t reserved11: 21; + }; + uint32_t val; + } apb_ctrl_clk_out_en; + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ + union { + struct { + uint32_t peri_io_swap: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } host_inf_sel; + union { + struct { + uint32_t ext_mem_pms_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } ext_mem_pms_lock; + uint32_t reserved_24; + union { + struct { + uint32_t flash_ace0_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace0_attr; + union { + struct { + uint32_t flash_ace1_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace1_attr; + union { + struct { + uint32_t flash_ace2_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace2_attr; + union { + struct { + uint32_t flash_ace3_attr: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } flash_ace3_attr; + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ + union { + struct { + uint32_t flash_ace0_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace0_size; + union { + struct { + uint32_t flash_ace1_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace1_size; + union { + struct { + uint32_t flash_ace2_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace2_size; + union { + struct { + uint32_t flash_ace3_size:13; + uint32_t reserved13: 19; + }; + uint32_t val; + } flash_ace3_size; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + union { + struct { + uint32_t spi_mem_reject_int: 1; + uint32_t spi_mem_reject_clr: 1; + uint32_t spi_mem_reject_cde: 5; + uint32_t reserved7: 25; + }; + uint32_t val; + } spi_mem_pms_ctrl; + uint32_t spi_mem_reject_addr; /**/ + union { + struct { + uint32_t sdio_win_access_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } apb_ctrl_sdio_ctrl; + union { + struct { + uint32_t redcy_sig0: 31; + uint32_t redcy_andor: 1; + }; + uint32_t val; + } redcy_sig0; + union { + struct { + uint32_t redcy_sig1: 31; + uint32_t redcy_nandor: 1; + }; + uint32_t val; + } redcy_sig1; + union { + struct { + uint32_t agc_mem_force_pu: 1; + uint32_t agc_mem_force_pd: 1; + uint32_t pbus_mem_force_pu: 1; + uint32_t pbus_mem_force_pd: 1; + uint32_t dc_mem_force_pu: 1; + uint32_t dc_mem_force_pd: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } front_end_mem_pd; + union { + struct { + uint32_t retention_link_addr: 27; + uint32_t nobypass_cpu_iso_rst: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t rom_clkgate_force_on: 2; + uint32_t sram_clkgate_force_on: 4; + uint32_t reserved6: 26; + }; + uint32_t val; + } clkgate_force_on; + union { + struct { + uint32_t rom_power_down: 2; + uint32_t sram_power_down: 4; + uint32_t reserved6: 26; + }; + uint32_t val; + } mem_power_down; + union { + struct { + uint32_t rom_power_up: 2; + uint32_t sram_power_up: 4; + uint32_t reserved6: 26; + }; + uint32_t val; + } mem_power_up; + uint32_t rnd_data; /**/ + union { + struct { + uint32_t reserved0: 1; + uint32_t peri_backup_flow_err: 2; + uint32_t reserved3: 1; + uint32_t peri_backup_burst_limit: 5; + uint32_t peri_backup_tout_thres: 10; + uint32_t peri_backup_size: 10; + uint32_t peri_backup_start: 1; + uint32_t peri_backup_to_mem: 1; + uint32_t peri_backup_ena: 1; + }; + uint32_t val; + } peri_backup_config; + uint32_t peri_backup_apb_addr; /**/ + uint32_t peri_backup_mem_addr; /**/ + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_raw; + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_st; + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_ena; + uint32_t reserved_cc; + union { + struct { + uint32_t peri_backup_done: 1; + uint32_t peri_backup_err: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } peri_backup_int_clr; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t apb_ctrl_date; /*Version control*/ +} syscon_dev_t; +extern syscon_dev_t SYSCON; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_SYSCON_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/system_reg.h b/components/soc/esp32h2/include/soc/system_reg.h new file mode 100644 index 0000000000..3a67cb4606 --- /dev/null +++ b/components/soc/esp32h2/include/soc/system_reg.h @@ -0,0 +1,1050 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYSTEM_REG_H_ +#define _SOC_SYSTEM_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004) +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008) +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: */ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_V 0x1 +#define SYSTEM_PLL_FREQ_SEL_S 2 +/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) +#define SYSTEM_CPUPERIOD_SEL_V 0x3 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C) +/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010) +/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ +/*description: */ +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 +/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 +/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 +/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 +/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 +/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 +#define SYSTEM_USB_DEVICE_CLK_EN_S 23 +/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 +/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_V 0x1 +#define SYSTEM_I2S1_CLK_EN_S 21 +/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 +/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 +/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 +/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 +/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 +/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 +/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 +/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 +/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 +/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 +/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 +/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 +/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 +/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 4 +/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 +/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 +/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 +/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014) +/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TSENS_CLK_EN (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_M (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_V 0x1 +#define SYSTEM_TSENS_CLK_EN_S 10 +/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART2_CLK_EN (BIT(9)) +#define SYSTEM_UART2_CLK_EN_M (BIT(9)) +#define SYSTEM_UART2_CLK_EN_V 0x1 +#define SYSTEM_UART2_CLK_EN_S 9 +/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 8 +/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 7 +/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (BIT(6)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 6 +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018) +/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 +/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 +/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 +/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 +/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 +/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 +/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 +/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 +/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_RST (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_M (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_V 0x1 +#define SYSTEM_USB_DEVICE_RST_S 23 +/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 +/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (BIT(21)) +#define SYSTEM_I2S1_RST_V 0x1 +#define SYSTEM_I2S1_RST_S 21 +/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 +/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 +/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 +/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 +/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 +/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 +/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 +/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 +/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 +/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 +/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 +/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 +/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 +/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 +/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 +/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 +/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (BIT(4)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 4 +/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 +/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 +/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 +/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01C) +/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TSENS_RST (BIT(10)) +#define SYSTEM_TSENS_RST_M (BIT(10)) +#define SYSTEM_TSENS_RST_V 0x1 +#define SYSTEM_TSENS_RST_S 10 +/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART2_RST (BIT(9)) +#define SYSTEM_UART2_RST_M (BIT(9)) +#define SYSTEM_UART2_RST_V 0x1 +#define SYSTEM_UART2_RST_S 9 +/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_RST (BIT(8)) +#define SYSTEM_LCD_CAM_RST_M (BIT(8)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 8 +/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_RST (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 7 +/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (BIT(6)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 6 +/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 +/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 +/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 +/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 + +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020) +/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024) +/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_V 0x1 +#define SYSTEM_LPCLK_RTC_EN_S 28 +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_V 0x1 +#define SYSTEM_LPCLK_SEL_8M_S 25 +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) +#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_A_S 12 +/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) +#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_B_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x028) +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x02C) +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x030) +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x034) +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038) +/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 +/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (BIT(0)) +#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_S 0 + +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x03C) +/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (BIT(1)) +#define SYSTEM_EDMA_RESET_V 0x1 +#define SYSTEM_EDMA_RESET_S 1 +/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_S 0 + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x040) +/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (BIT(3)) +#define SYSTEM_DCACHE_RESET_V 0x1 +#define SYSTEM_DCACHE_RESET_S 3 +/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_V 0x1 +#define SYSTEM_DCACHE_CLK_ON_S 2 +/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (BIT(1)) +#define SYSTEM_ICACHE_RESET_V 0x1 +#define SYSTEM_ICACHE_RESET_S 1 +/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_S 0 + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x044) +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x048) +/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 +/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x04C) +/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x050) +/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x054) +/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x058) +/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (BIT(19)) +#define SYSTEM_CLK_DIV_EN_V 0x1 +#define SYSTEM_CLK_DIV_EN_S 19 +/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ +/*description: */ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) +#define SYSTEM_CLK_XTAL_FREQ_V 0x7F +#define SYSTEM_CLK_XTAL_FREQ_S 12 +/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 10 +/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) +#define SYSTEM_PRE_DIV_CNT_V 0x3FF +#define SYSTEM_PRE_DIV_CNT_S 0 + +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x05C) +/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define SYSTEM_MEM_VT_SEL 0x00000003 +#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) +#define SYSTEM_MEM_VT_SEL_V 0x3 +#define SYSTEM_MEM_VT_SEL_S 22 +/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ +/*description: */ +#define SYSTEM_MEM_PATH_LEN 0x0000000F +#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) +#define SYSTEM_MEM_PATH_LEN_V 0xF +#define SYSTEM_MEM_PATH_LEN_S 0 + +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x060) +/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 +/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_LVT_S 0 + +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x064) +/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 +/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_NVT_S 0 + +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x068) +/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 +/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_HVT_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x06C) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x070) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x074) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x078) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x07C) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x080) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x084) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x088) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x08C) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x090) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x094) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x098) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */ +/*description: */ +#define SYSTEM_DATE 0x0FFFFFFF +#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) +#define SYSTEM_DATE_V 0xFFFFFFF +#define SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SYSTEM_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/system_struct.h b/components/soc/esp32h2/include/soc/system_struct.h new file mode 100644 index 0000000000..f07fab0aff --- /dev/null +++ b/components/soc/esp32h2/include/soc/system_struct.h @@ -0,0 +1,1412 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYSTEM_STRUCT_H_ +#define _SOC_SYSTEM_STRUCT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +typedef volatile struct { + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t reg_clk_en_assist_debug : 1; /*reg_clk_en_assist_debug*/ + uint32_t reg_clk_en_dedicated_gpio : 1; /*reg_clk_en_dedicated_gpio*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } cpu_peri_clk_en; + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t reg_rst_en_assist_debug : 1; /*reg_rst_en_assist_debug*/ + uint32_t reg_rst_en_dedicated_gpio : 1; /*reg_rst_en_dedicated_gpio*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } cpu_peri_rst_en; + union { + struct { + uint32_t reg_cpuperiod_sel : 2; /*reg_cpuperiod_sel*/ + uint32_t reg_pll_freq_sel : 1; /*reg_pll_freq_sel*/ + uint32_t reg_cpu_wait_mode_force_on : 1; /*reg_cpu_wait_mode_force_on*/ + uint32_t reg_cpu_waiti_delay_num : 4; /*reg_cpu_waiti_delay_num*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } cpu_per_conf; + union { + struct { + uint32_t reg_lslp_mem_pd_mask : 1; /*reg_lslp_mem_pd_mask*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } mem_pd_mask; + union { + struct { + uint32_t reg_timers_clk_en : 1; /*reg_timers_clk_en*/ + uint32_t reg_spi01_clk_en : 1; /*reg_spi01_clk_en*/ + uint32_t reg_uart_clk_en : 1; /*reg_uart_clk_en*/ + uint32_t reg_wdg_clk_en : 1; /*reg_wdg_clk_en*/ + uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/ + uint32_t reg_uart1_clk_en : 1; /*reg_uart1_clk_en*/ + uint32_t reg_spi2_clk_en : 1; /*reg_spi2_clk_en*/ + uint32_t reg_i2c_ext0_clk_en : 1; /*reg_i2c_ext0_clk_en*/ + uint32_t reg_uhci0_clk_en : 1; /*reg_uhci0_clk_en*/ + uint32_t reg_rmt_clk_en : 1; /*reg_rmt_clk_en*/ + uint32_t reg_pcnt_clk_en : 1; /*reg_pcnt_clk_en*/ + uint32_t reg_ledc_clk_en : 1; /*reg_ledc_clk_en*/ + uint32_t reg_uhci1_clk_en : 1; /*reg_uhci1_clk_en*/ + uint32_t reg_timergroup_clk_en : 1; /*reg_timergroup_clk_en*/ + uint32_t reg_efuse_clk_en : 1; /*reg_efuse_clk_en*/ + uint32_t reg_timergroup1_clk_en : 1; /*reg_timergroup1_clk_en*/ + uint32_t reg_spi3_clk_en : 1; /*reg_spi3_clk_en*/ + uint32_t reg_pwm0_clk_en : 1; /*reg_pwm0_clk_en*/ + uint32_t reg_i2c_ext1_clk_en : 1; /*reg_i2c_ext1_clk_en*/ + uint32_t reg_can_clk_en : 1; /*reg_can_clk_en*/ + uint32_t reg_pwm1_clk_en : 1; /*reg_pwm1_clk_en*/ + uint32_t reg_i2s1_clk_en : 1; /*reg_i2s1_clk_en*/ + uint32_t reg_spi2_dma_clk_en : 1; /*reg_spi2_dma_clk_en*/ + uint32_t reg_usb_device_clk_en : 1; /*reg_usb_device_clk_en*/ + uint32_t reg_uart_mem_clk_en : 1; /*reg_uart_mem_clk_en*/ + uint32_t reg_pwm2_clk_en : 1; /*reg_pwm2_clk_en*/ + uint32_t reg_pwm3_clk_en : 1; /*reg_pwm3_clk_en*/ + uint32_t reg_spi3_dma_clk_en : 1; /*reg_spi3_dma_clk_en*/ + uint32_t reg_apb_saradc_clk_en : 1; /*reg_apb_saradc_clk_en*/ + uint32_t reg_systimer_clk_en : 1; /*reg_systimer_clk_en*/ + uint32_t reg_adc2_arb_clk_en : 1; /*reg_adc2_arb_clk_en*/ + uint32_t reg_spi4_clk_en : 1; /*reg_spi4_clk_en*/ + }; + uint32_t val; + } perip_clk_en0; + union { + struct { + uint32_t reserved0 : 1; /*peripheral reset register*/ + uint32_t reg_crypto_aes_clk_en : 1; /*reg_crypto_aes_clk_en*/ + uint32_t reg_crypto_sha_clk_en : 1; /*reg_crypto_sha_clk_en*/ + uint32_t reg_crypto_rsa_clk_en : 1; /*reg_crypto_rsa_clk_en*/ + uint32_t reg_crypto_ds_clk_en : 1; /*reg_crypto_ds_clk_en*/ + uint32_t reg_crypto_hmac_clk_en : 1; /*reg_crypto_hmac_clk_en*/ + uint32_t reg_dma_clk_en : 1; /*reg_dma_clk_en*/ + uint32_t reg_sdio_host_clk_en : 1; /*reg_sdio_host_clk_en*/ + uint32_t reg_lcd_cam_clk_en : 1; /*reg_lcd_cam_clk_en*/ + uint32_t reg_uart2_clk_en : 1; /*reg_uart2_clk_en*/ + uint32_t reg_tsens_clk_en : 1; /*reg_tsens_clk_en*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } perip_clk_en1; + union { + struct { + uint32_t reg_timers_rst : 1; /*reg_timers_rst*/ + uint32_t reg_spi01_rst : 1; /*reg_spi01_rst*/ + uint32_t reg_uart_rst : 1; /*reg_uart_rst*/ + uint32_t reg_wdg_rst : 1; /*reg_wdg_rst*/ + uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/ + uint32_t reg_uart1_rst : 1; /*reg_uart1_rst*/ + uint32_t reg_spi2_rst : 1; /*reg_spi2_rst*/ + uint32_t reg_i2c_ext0_rst : 1; /*reg_i2c_ext0_rst*/ + uint32_t reg_uhci0_rst : 1; /*reg_uhci0_rst*/ + uint32_t reg_rmt_rst : 1; /*reg_rmt_rst*/ + uint32_t reg_pcnt_rst : 1; /*reg_pcnt_rst*/ + uint32_t reg_ledc_rst : 1; /*reg_ledc_rst*/ + uint32_t reg_uhci1_rst : 1; /*reg_uhci1_rst*/ + uint32_t reg_timergroup_rst : 1; /*reg_timergroup_rst*/ + uint32_t reg_efuse_rst : 1; /*reg_efuse_rst*/ + uint32_t reg_timergroup1_rst : 1; /*reg_timergroup1_rst*/ + uint32_t reg_spi3_rst : 1; /*reg_spi3_rst*/ + uint32_t reg_pwm0_rst : 1; /*reg_pwm0_rst*/ + uint32_t reg_i2c_ext1_rst : 1; /*reg_i2c_ext1_rst*/ + uint32_t reg_can_rst : 1; /*reg_can_rst*/ + uint32_t reg_pwm1_rst : 1; /*reg_pwm1_rst*/ + uint32_t reg_i2s1_rst : 1; /*reg_i2s1_rst*/ + uint32_t reg_spi2_dma_rst : 1; /*reg_spi2_dma_rst*/ + uint32_t reg_usb_device_rst : 1; /*reg_usb_device_rst*/ + uint32_t reg_uart_mem_rst : 1; /*reg_uart_mem_rst*/ + uint32_t reg_pwm2_rst : 1; /*reg_pwm2_rst*/ + uint32_t reg_pwm3_rst : 1; /*reg_pwm3_rst*/ + uint32_t reg_spi3_dma_rst : 1; /*reg_spi3_dma_rst*/ + uint32_t reg_apb_saradc_rst : 1; /*reg_apb_saradc_rst*/ + uint32_t reg_systimer_rst : 1; /*reg_systimer_rst*/ + uint32_t reg_adc2_arb_rst : 1; /*reg_adc2_arb_rst*/ + uint32_t reg_spi4_rst : 1; /*reg_spi4_rst*/ + }; + uint32_t val; + } perip_rst_en0; + union { + struct { + uint32_t reserved0 : 1; /*reserved*/ + uint32_t reg_crypto_aes_rst : 1; /*reg_crypto_aes_rst*/ + uint32_t reg_crypto_sha_rst : 1; /*reg_crypto_sha_rst*/ + uint32_t reg_crypto_rsa_rst : 1; /*reg_crypto_rsa_rst*/ + uint32_t reg_crypto_ds_rst : 1; /*reg_crypto_ds_rst*/ + uint32_t reg_crypto_hmac_rst : 1; /*reg_crypto_hmac_rst*/ + uint32_t reg_dma_rst : 1; /*reg_dma_rst*/ + uint32_t reg_sdio_host_rst : 1; /*reg_sdio_host_rst*/ + uint32_t reg_lcd_cam_rst : 1; /*reg_lcd_cam_rst*/ + uint32_t reg_uart2_rst : 1; /*reg_uart2_rst*/ + uint32_t reg_tsens_rst : 1; /*reg_tsens_rst*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } perip_rst_en1; + union { + struct { + uint32_t reg_bt_lpck_div_num : 12; /*reg_bt_lpck_div_num*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } bt_lpck_div_int; + union { + struct { + uint32_t reg_bt_lpck_div_b : 12; /*reg_bt_lpck_div_b*/ + uint32_t reg_bt_lpck_div_a : 12; /*reg_bt_lpck_div_a*/ + uint32_t reg_lpclk_sel_rtc_slow : 1; /*reg_lpclk_sel_rtc_slow*/ + uint32_t reg_lpclk_sel_8m : 1; /*reg_lpclk_sel_8m*/ + uint32_t reg_lpclk_sel_xtal : 1; /*reg_lpclk_sel_xtal*/ + uint32_t reg_lpclk_sel_xtal32k : 1; /*reg_lpclk_sel_xtal32k*/ + uint32_t reg_lpclk_rtc_en : 1; /*reg_lpclk_rtc_en*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } bt_lpck_div_frac; + union { + struct { + uint32_t reg_cpu_intr_from_cpu_0 : 1; /*reg_cpu_intr_from_cpu_0*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } cpu_intr_from_cpu_0; + union { + struct { + uint32_t reg_cpu_intr_from_cpu_1 : 1; /*reg_cpu_intr_from_cpu_1*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } cpu_intr_from_cpu_1; + union { + struct { + uint32_t reg_cpu_intr_from_cpu_2 : 1; /*reg_cpu_intr_from_cpu_2*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } cpu_intr_from_cpu_2; + union { + struct { + uint32_t reg_cpu_intr_from_cpu_3 : 1; /*reg_cpu_intr_from_cpu_3*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } cpu_intr_from_cpu_3; + union { + struct { + uint32_t reg_rsa_mem_pd : 1; /*reg_rsa_mem_pd*/ + uint32_t reg_rsa_mem_force_pu : 1; /*reg_rsa_mem_force_pu*/ + uint32_t reg_rsa_mem_force_pd : 1; /*reg_rsa_mem_force_pd*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } rsa_pd_ctrl; + union { + struct { + uint32_t reg_edma_clk_on : 1; /*reg_edma_clk_on*/ + uint32_t reg_edma_reset : 1; /*reg_edma_reset*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } edma_ctrl; + union { + struct { + uint32_t reg_icache_clk_on : 1; /*reg_icache_clk_on*/ + uint32_t reg_icache_reset : 1; /*reg_icache_reset*/ + uint32_t reg_dcache_clk_on : 1; /*reg_dcache_clk_on*/ + uint32_t reg_dcache_reset : 1; /*reg_dcache_reset*/ + uint32_t reserved4 : 28; /*reserved*/ + }; + uint32_t val; + } cache_control; + union { + struct { + uint32_t reg_enable_spi_manual_encrypt : 1; /*reg_enable_spi_manual_encrypt*/ + uint32_t reg_enable_download_db_encrypt: 1; /*reg_enable_download_db_encrypt*/ + uint32_t reg_enable_download_g0cb_decrypt: 1; /*reg_enable_download_g0cb_decrypt*/ + uint32_t reg_enable_download_manual_encrypt: 1; /*reg_enable_download_manual_encrypt*/ + uint32_t reserved4 : 28; /*reserved*/ + }; + uint32_t val; + } external_device_encrypt_decrypt_control; + union { + struct { + uint32_t reserved0 : 8; /*fast memory crc register*/ + uint32_t reg_rtc_mem_crc_start : 1; /*reg_rtc_mem_crc_start*/ + uint32_t reg_rtc_mem_crc_addr : 11; /*reg_rtc_mem_crc_addr*/ + uint32_t reg_rtc_mem_crc_len : 11; /*reg_rtc_mem_crc_len*/ + uint32_t reg_rtc_mem_crc_finish : 1; /*reg_rtc_mem_crc_finish*/ + }; + uint32_t val; + } rtc_fastmem_config; + uint32_t rtc_fastmem_crc; + union { + struct { + uint32_t reg_redundant_eco_drive : 1; /*reg_redundant_eco_drive*/ + uint32_t reg_redundant_eco_result : 1; /*reg_redundant_eco_result*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } redundant_eco_ctrl; + union { + struct { + uint32_t reg_clk_en : 1; /*reg_clk_en*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + union { + struct { + uint32_t reg_pre_div_cnt : 10; /*reg_pre_div_cnt*/ + uint32_t reg_soc_clk_sel : 2; /*reg_soc_clk_sel*/ + uint32_t reg_clk_xtal_freq : 7; /*reg_clk_xtal_freq*/ + uint32_t reg_clk_div_en : 1; /*reg_clk_div_en*/ + uint32_t reserved20 : 12; /*reserved*/ + }; + uint32_t val; + } sysclk_conf; + union { + struct { + uint32_t reg_mem_path_len : 4; /*reg_mem_path_len*/ + uint32_t reg_mem_err_cnt_clr : 1; /*reg_mem_err_cnt_clr*/ + uint32_t reg_mem_pvt_monitor_en : 1; /*reg_mem_pvt_monitor_en*/ + uint32_t reg_mem_timing_err_cnt : 16; /*reg_mem_timing_err_cnt*/ + uint32_t reg_mem_vt_sel : 2; /*reg_mem_vt_sel*/ + uint32_t reserved24 : 8; /*reserved*/ + }; + uint32_t val; + } mem_pvt; + union { + struct { + uint32_t reg_comb_path_len_lvt : 5; /*reg_comb_path_len_lvt*/ + uint32_t reg_comb_err_cnt_clr_lvt : 1; /*reg_comb_err_cnt_clr_lvt*/ + uint32_t reg_comb_pvt_monitor_en_lvt : 1; /*reg_comb_pvt_monitor_en_lvt*/ + uint32_t reserved7 : 18; /*reserved*/ + uint32_t reserved25 : 7; /*reserved*/ + }; + uint32_t val; + } comb_pvt_lvt_conf; + union { + struct { + uint32_t reg_comb_path_len_nvt : 5; /*reg_comb_path_len_nvt*/ + uint32_t reg_comb_err_cnt_clr_nvt : 1; /*reg_comb_err_cnt_clr_nvt*/ + uint32_t reg_comb_pvt_monitor_en_nvt : 1; /*reg_comb_pvt_monitor_en_nvt*/ + uint32_t reserved7 : 18; /*reserved*/ + uint32_t reserved25 : 7; /*reserved*/ + }; + uint32_t val; + } comb_pvt_nvt_conf; + union { + struct { + uint32_t reg_comb_path_len_hvt : 5; /*reg_comb_path_len_hvt*/ + uint32_t reg_comb_err_cnt_clr_hvt : 1; /*reg_comb_err_cnt_clr_hvt*/ + uint32_t reg_comb_pvt_monitor_en_hvt : 1; /*reg_comb_pvt_monitor_en_hvt*/ + uint32_t reserved7 : 18; /*reserved*/ + uint32_t reserved25 : 7; /*reserved*/ + }; + uint32_t val; + } comb_pvt_hvt_conf; + union { + struct { + uint32_t reg_comb_timing_err_cnt_lvt_site0: 16; /*reg_comb_timing_err_cnt_lvt_site0*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_lvt_site0; + union { + struct { + uint32_t reg_comb_timing_err_cnt_nvt_site0: 16; /*reg_comb_timing_err_cnt_nvt_site0*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_nvt_site0; + union { + struct { + uint32_t reg_comb_timing_err_cnt_hvt_site0: 16; /*reg_comb_timing_err_cnt_hvt_site0*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_hvt_site0; + union { + struct { + uint32_t reg_comb_timing_err_cnt_lvt_site1: 16; /*reg_comb_timing_err_cnt_lvt_site1*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_lvt_site1; + union { + struct { + uint32_t reg_comb_timing_err_cnt_nvt_site1: 16; /*reg_comb_timing_err_cnt_nvt_site1*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_nvt_site1; + union { + struct { + uint32_t reg_comb_timing_err_cnt_hvt_site1: 16; /*reg_comb_timing_err_cnt_hvt_site1*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_hvt_site1; + union { + struct { + uint32_t reg_comb_timing_err_cnt_lvt_site2: 16; /*reg_comb_timing_err_cnt_lvt_site2*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_lvt_site2; + union { + struct { + uint32_t reg_comb_timing_err_cnt_nvt_site2: 16; /*reg_comb_timing_err_cnt_nvt_site2*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_nvt_site2; + union { + struct { + uint32_t reg_comb_timing_err_cnt_hvt_site2: 16; /*reg_comb_timing_err_cnt_hvt_site2*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_hvt_site2; + union { + struct { + uint32_t reg_comb_timing_err_cnt_lvt_site3: 16; /*reg_comb_timing_err_cnt_lvt_site3*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_lvt_site3; + union { + struct { + uint32_t reg_comb_timing_err_cnt_nvt_site3: 16; /*reg_comb_timing_err_cnt_nvt_site3*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_nvt_site3; + union { + struct { + uint32_t reg_comb_timing_err_cnt_hvt_site3: 16; /*reg_comb_timing_err_cnt_hvt_site3*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } comb_pvt_err_hvt_site3; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + uint32_t reserved_554; + uint32_t reserved_558; + uint32_t reserved_55c; + uint32_t reserved_560; + uint32_t reserved_564; + uint32_t reserved_568; + uint32_t reserved_56c; + uint32_t reserved_570; + uint32_t reserved_574; + uint32_t reserved_578; + uint32_t reserved_57c; + uint32_t reserved_580; + uint32_t reserved_584; + uint32_t reserved_588; + uint32_t reserved_58c; + uint32_t reserved_590; + uint32_t reserved_594; + uint32_t reserved_598; + uint32_t reserved_59c; + uint32_t reserved_5a0; + uint32_t reserved_5a4; + uint32_t reserved_5a8; + uint32_t reserved_5ac; + uint32_t reserved_5b0; + uint32_t reserved_5b4; + uint32_t reserved_5b8; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + uint32_t reserved_62c; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + uint32_t reserved_6fc; + uint32_t reserved_700; + uint32_t reserved_704; + uint32_t reserved_708; + uint32_t reserved_70c; + uint32_t reserved_710; + uint32_t reserved_714; + uint32_t reserved_718; + uint32_t reserved_71c; + uint32_t reserved_720; + uint32_t reserved_724; + uint32_t reserved_728; + uint32_t reserved_72c; + uint32_t reserved_730; + uint32_t reserved_734; + uint32_t reserved_738; + uint32_t reserved_73c; + uint32_t reserved_740; + uint32_t reserved_744; + uint32_t reserved_748; + uint32_t reserved_74c; + uint32_t reserved_750; + uint32_t reserved_754; + uint32_t reserved_758; + uint32_t reserved_75c; + uint32_t reserved_760; + uint32_t reserved_764; + uint32_t reserved_768; + uint32_t reserved_76c; + uint32_t reserved_770; + uint32_t reserved_774; + uint32_t reserved_778; + uint32_t reserved_77c; + uint32_t reserved_780; + uint32_t reserved_784; + uint32_t reserved_788; + uint32_t reserved_78c; + uint32_t reserved_790; + uint32_t reserved_794; + uint32_t reserved_798; + uint32_t reserved_79c; + uint32_t reserved_7a0; + uint32_t reserved_7a4; + uint32_t reserved_7a8; + uint32_t reserved_7ac; + uint32_t reserved_7b0; + uint32_t reserved_7b4; + uint32_t reserved_7b8; + uint32_t reserved_7bc; + uint32_t reserved_7c0; + uint32_t reserved_7c4; + uint32_t reserved_7c8; + uint32_t reserved_7cc; + uint32_t reserved_7d0; + uint32_t reserved_7d4; + uint32_t reserved_7d8; + uint32_t reserved_7dc; + uint32_t reserved_7e0; + uint32_t reserved_7e4; + uint32_t reserved_7e8; + uint32_t reserved_7ec; + uint32_t reserved_7f0; + uint32_t reserved_7f4; + uint32_t reserved_7f8; + uint32_t reserved_7fc; + uint32_t reserved_800; + uint32_t reserved_804; + uint32_t reserved_808; + uint32_t reserved_80c; + uint32_t reserved_810; + uint32_t reserved_814; + uint32_t reserved_818; + uint32_t reserved_81c; + uint32_t reserved_820; + uint32_t reserved_824; + uint32_t reserved_828; + uint32_t reserved_82c; + uint32_t reserved_830; + uint32_t reserved_834; + uint32_t reserved_838; + uint32_t reserved_83c; + uint32_t reserved_840; + uint32_t reserved_844; + uint32_t reserved_848; + uint32_t reserved_84c; + uint32_t reserved_850; + uint32_t reserved_854; + uint32_t reserved_858; + uint32_t reserved_85c; + uint32_t reserved_860; + uint32_t reserved_864; + uint32_t reserved_868; + uint32_t reserved_86c; + uint32_t reserved_870; + uint32_t reserved_874; + uint32_t reserved_878; + uint32_t reserved_87c; + uint32_t reserved_880; + uint32_t reserved_884; + uint32_t reserved_888; + uint32_t reserved_88c; + uint32_t reserved_890; + uint32_t reserved_894; + uint32_t reserved_898; + uint32_t reserved_89c; + uint32_t reserved_8a0; + uint32_t reserved_8a4; + uint32_t reserved_8a8; + uint32_t reserved_8ac; + uint32_t reserved_8b0; + uint32_t reserved_8b4; + uint32_t reserved_8b8; + uint32_t reserved_8bc; + uint32_t reserved_8c0; + uint32_t reserved_8c4; + uint32_t reserved_8c8; + uint32_t reserved_8cc; + uint32_t reserved_8d0; + uint32_t reserved_8d4; + uint32_t reserved_8d8; + uint32_t reserved_8dc; + uint32_t reserved_8e0; + uint32_t reserved_8e4; + uint32_t reserved_8e8; + uint32_t reserved_8ec; + uint32_t reserved_8f0; + uint32_t reserved_8f4; + uint32_t reserved_8f8; + uint32_t reserved_8fc; + uint32_t reserved_900; + uint32_t reserved_904; + uint32_t reserved_908; + uint32_t reserved_90c; + uint32_t reserved_910; + uint32_t reserved_914; + uint32_t reserved_918; + uint32_t reserved_91c; + uint32_t reserved_920; + uint32_t reserved_924; + uint32_t reserved_928; + uint32_t reserved_92c; + uint32_t reserved_930; + uint32_t reserved_934; + uint32_t reserved_938; + uint32_t reserved_93c; + uint32_t reserved_940; + uint32_t reserved_944; + uint32_t reserved_948; + uint32_t reserved_94c; + uint32_t reserved_950; + uint32_t reserved_954; + uint32_t reserved_958; + uint32_t reserved_95c; + uint32_t reserved_960; + uint32_t reserved_964; + uint32_t reserved_968; + uint32_t reserved_96c; + uint32_t reserved_970; + uint32_t reserved_974; + uint32_t reserved_978; + uint32_t reserved_97c; + uint32_t reserved_980; + uint32_t reserved_984; + uint32_t reserved_988; + uint32_t reserved_98c; + uint32_t reserved_990; + uint32_t reserved_994; + uint32_t reserved_998; + uint32_t reserved_99c; + uint32_t reserved_9a0; + uint32_t reserved_9a4; + uint32_t reserved_9a8; + uint32_t reserved_9ac; + uint32_t reserved_9b0; + uint32_t reserved_9b4; + uint32_t reserved_9b8; + uint32_t reserved_9bc; + uint32_t reserved_9c0; + uint32_t reserved_9c4; + uint32_t reserved_9c8; + uint32_t reserved_9cc; + uint32_t reserved_9d0; + uint32_t reserved_9d4; + uint32_t reserved_9d8; + uint32_t reserved_9dc; + uint32_t reserved_9e0; + uint32_t reserved_9e4; + uint32_t reserved_9e8; + uint32_t reserved_9ec; + uint32_t reserved_9f0; + uint32_t reserved_9f4; + uint32_t reserved_9f8; + uint32_t reserved_9fc; + uint32_t reserved_a00; + uint32_t reserved_a04; + uint32_t reserved_a08; + uint32_t reserved_a0c; + uint32_t reserved_a10; + uint32_t reserved_a14; + uint32_t reserved_a18; + uint32_t reserved_a1c; + uint32_t reserved_a20; + uint32_t reserved_a24; + uint32_t reserved_a28; + uint32_t reserved_a2c; + uint32_t reserved_a30; + uint32_t reserved_a34; + uint32_t reserved_a38; + uint32_t reserved_a3c; + uint32_t reserved_a40; + uint32_t reserved_a44; + uint32_t reserved_a48; + uint32_t reserved_a4c; + uint32_t reserved_a50; + uint32_t reserved_a54; + uint32_t reserved_a58; + uint32_t reserved_a5c; + uint32_t reserved_a60; + uint32_t reserved_a64; + uint32_t reserved_a68; + uint32_t reserved_a6c; + uint32_t reserved_a70; + uint32_t reserved_a74; + uint32_t reserved_a78; + uint32_t reserved_a7c; + uint32_t reserved_a80; + uint32_t reserved_a84; + uint32_t reserved_a88; + uint32_t reserved_a8c; + uint32_t reserved_a90; + uint32_t reserved_a94; + uint32_t reserved_a98; + uint32_t reserved_a9c; + uint32_t reserved_aa0; + uint32_t reserved_aa4; + uint32_t reserved_aa8; + uint32_t reserved_aac; + uint32_t reserved_ab0; + uint32_t reserved_ab4; + uint32_t reserved_ab8; + uint32_t reserved_abc; + uint32_t reserved_ac0; + uint32_t reserved_ac4; + uint32_t reserved_ac8; + uint32_t reserved_acc; + uint32_t reserved_ad0; + uint32_t reserved_ad4; + uint32_t reserved_ad8; + uint32_t reserved_adc; + uint32_t reserved_ae0; + uint32_t reserved_ae4; + uint32_t reserved_ae8; + uint32_t reserved_aec; + uint32_t reserved_af0; + uint32_t reserved_af4; + uint32_t reserved_af8; + uint32_t reserved_afc; + uint32_t reserved_b00; + uint32_t reserved_b04; + uint32_t reserved_b08; + uint32_t reserved_b0c; + uint32_t reserved_b10; + uint32_t reserved_b14; + uint32_t reserved_b18; + uint32_t reserved_b1c; + uint32_t reserved_b20; + uint32_t reserved_b24; + uint32_t reserved_b28; + uint32_t reserved_b2c; + uint32_t reserved_b30; + uint32_t reserved_b34; + uint32_t reserved_b38; + uint32_t reserved_b3c; + uint32_t reserved_b40; + uint32_t reserved_b44; + uint32_t reserved_b48; + uint32_t reserved_b4c; + uint32_t reserved_b50; + uint32_t reserved_b54; + uint32_t reserved_b58; + uint32_t reserved_b5c; + uint32_t reserved_b60; + uint32_t reserved_b64; + uint32_t reserved_b68; + uint32_t reserved_b6c; + uint32_t reserved_b70; + uint32_t reserved_b74; + uint32_t reserved_b78; + uint32_t reserved_b7c; + uint32_t reserved_b80; + uint32_t reserved_b84; + uint32_t reserved_b88; + uint32_t reserved_b8c; + uint32_t reserved_b90; + uint32_t reserved_b94; + uint32_t reserved_b98; + uint32_t reserved_b9c; + uint32_t reserved_ba0; + uint32_t reserved_ba4; + uint32_t reserved_ba8; + uint32_t reserved_bac; + uint32_t reserved_bb0; + uint32_t reserved_bb4; + uint32_t reserved_bb8; + uint32_t reserved_bbc; + uint32_t reserved_bc0; + uint32_t reserved_bc4; + uint32_t reserved_bc8; + uint32_t reserved_bcc; + uint32_t reserved_bd0; + uint32_t reserved_bd4; + uint32_t reserved_bd8; + uint32_t reserved_bdc; + uint32_t reserved_be0; + uint32_t reserved_be4; + uint32_t reserved_be8; + uint32_t reserved_bec; + uint32_t reserved_bf0; + uint32_t reserved_bf4; + uint32_t reserved_bf8; + uint32_t reserved_bfc; + uint32_t reserved_c00; + uint32_t reserved_c04; + uint32_t reserved_c08; + uint32_t reserved_c0c; + uint32_t reserved_c10; + uint32_t reserved_c14; + uint32_t reserved_c18; + uint32_t reserved_c1c; + uint32_t reserved_c20; + uint32_t reserved_c24; + uint32_t reserved_c28; + uint32_t reserved_c2c; + uint32_t reserved_c30; + uint32_t reserved_c34; + uint32_t reserved_c38; + uint32_t reserved_c3c; + uint32_t reserved_c40; + uint32_t reserved_c44; + uint32_t reserved_c48; + uint32_t reserved_c4c; + uint32_t reserved_c50; + uint32_t reserved_c54; + uint32_t reserved_c58; + uint32_t reserved_c5c; + uint32_t reserved_c60; + uint32_t reserved_c64; + uint32_t reserved_c68; + uint32_t reserved_c6c; + uint32_t reserved_c70; + uint32_t reserved_c74; + uint32_t reserved_c78; + uint32_t reserved_c7c; + uint32_t reserved_c80; + uint32_t reserved_c84; + uint32_t reserved_c88; + uint32_t reserved_c8c; + uint32_t reserved_c90; + uint32_t reserved_c94; + uint32_t reserved_c98; + uint32_t reserved_c9c; + uint32_t reserved_ca0; + uint32_t reserved_ca4; + uint32_t reserved_ca8; + uint32_t reserved_cac; + uint32_t reserved_cb0; + uint32_t reserved_cb4; + uint32_t reserved_cb8; + uint32_t reserved_cbc; + uint32_t reserved_cc0; + uint32_t reserved_cc4; + uint32_t reserved_cc8; + uint32_t reserved_ccc; + uint32_t reserved_cd0; + uint32_t reserved_cd4; + uint32_t reserved_cd8; + uint32_t reserved_cdc; + uint32_t reserved_ce0; + uint32_t reserved_ce4; + uint32_t reserved_ce8; + uint32_t reserved_cec; + uint32_t reserved_cf0; + uint32_t reserved_cf4; + uint32_t reserved_cf8; + uint32_t reserved_cfc; + uint32_t reserved_d00; + uint32_t reserved_d04; + uint32_t reserved_d08; + uint32_t reserved_d0c; + uint32_t reserved_d10; + uint32_t reserved_d14; + uint32_t reserved_d18; + uint32_t reserved_d1c; + uint32_t reserved_d20; + uint32_t reserved_d24; + uint32_t reserved_d28; + uint32_t reserved_d2c; + uint32_t reserved_d30; + uint32_t reserved_d34; + uint32_t reserved_d38; + uint32_t reserved_d3c; + uint32_t reserved_d40; + uint32_t reserved_d44; + uint32_t reserved_d48; + uint32_t reserved_d4c; + uint32_t reserved_d50; + uint32_t reserved_d54; + uint32_t reserved_d58; + uint32_t reserved_d5c; + uint32_t reserved_d60; + uint32_t reserved_d64; + uint32_t reserved_d68; + uint32_t reserved_d6c; + uint32_t reserved_d70; + uint32_t reserved_d74; + uint32_t reserved_d78; + uint32_t reserved_d7c; + uint32_t reserved_d80; + uint32_t reserved_d84; + uint32_t reserved_d88; + uint32_t reserved_d8c; + uint32_t reserved_d90; + uint32_t reserved_d94; + uint32_t reserved_d98; + uint32_t reserved_d9c; + uint32_t reserved_da0; + uint32_t reserved_da4; + uint32_t reserved_da8; + uint32_t reserved_dac; + uint32_t reserved_db0; + uint32_t reserved_db4; + uint32_t reserved_db8; + uint32_t reserved_dbc; + uint32_t reserved_dc0; + uint32_t reserved_dc4; + uint32_t reserved_dc8; + uint32_t reserved_dcc; + uint32_t reserved_dd0; + uint32_t reserved_dd4; + uint32_t reserved_dd8; + uint32_t reserved_ddc; + uint32_t reserved_de0; + uint32_t reserved_de4; + uint32_t reserved_de8; + uint32_t reserved_dec; + uint32_t reserved_df0; + uint32_t reserved_df4; + uint32_t reserved_df8; + uint32_t reserved_dfc; + uint32_t reserved_e00; + uint32_t reserved_e04; + uint32_t reserved_e08; + uint32_t reserved_e0c; + uint32_t reserved_e10; + uint32_t reserved_e14; + uint32_t reserved_e18; + uint32_t reserved_e1c; + uint32_t reserved_e20; + uint32_t reserved_e24; + uint32_t reserved_e28; + uint32_t reserved_e2c; + uint32_t reserved_e30; + uint32_t reserved_e34; + uint32_t reserved_e38; + uint32_t reserved_e3c; + uint32_t reserved_e40; + uint32_t reserved_e44; + uint32_t reserved_e48; + uint32_t reserved_e4c; + uint32_t reserved_e50; + uint32_t reserved_e54; + uint32_t reserved_e58; + uint32_t reserved_e5c; + uint32_t reserved_e60; + uint32_t reserved_e64; + uint32_t reserved_e68; + uint32_t reserved_e6c; + uint32_t reserved_e70; + uint32_t reserved_e74; + uint32_t reserved_e78; + uint32_t reserved_e7c; + uint32_t reserved_e80; + uint32_t reserved_e84; + uint32_t reserved_e88; + uint32_t reserved_e8c; + uint32_t reserved_e90; + uint32_t reserved_e94; + uint32_t reserved_e98; + uint32_t reserved_e9c; + uint32_t reserved_ea0; + uint32_t reserved_ea4; + uint32_t reserved_ea8; + uint32_t reserved_eac; + uint32_t reserved_eb0; + uint32_t reserved_eb4; + uint32_t reserved_eb8; + uint32_t reserved_ebc; + uint32_t reserved_ec0; + uint32_t reserved_ec4; + uint32_t reserved_ec8; + uint32_t reserved_ecc; + uint32_t reserved_ed0; + uint32_t reserved_ed4; + uint32_t reserved_ed8; + uint32_t reserved_edc; + uint32_t reserved_ee0; + uint32_t reserved_ee4; + uint32_t reserved_ee8; + uint32_t reserved_eec; + uint32_t reserved_ef0; + uint32_t reserved_ef4; + uint32_t reserved_ef8; + uint32_t reserved_efc; + uint32_t reserved_f00; + uint32_t reserved_f04; + uint32_t reserved_f08; + uint32_t reserved_f0c; + uint32_t reserved_f10; + uint32_t reserved_f14; + uint32_t reserved_f18; + uint32_t reserved_f1c; + uint32_t reserved_f20; + uint32_t reserved_f24; + uint32_t reserved_f28; + uint32_t reserved_f2c; + uint32_t reserved_f30; + uint32_t reserved_f34; + uint32_t reserved_f38; + uint32_t reserved_f3c; + uint32_t reserved_f40; + uint32_t reserved_f44; + uint32_t reserved_f48; + uint32_t reserved_f4c; + uint32_t reserved_f50; + uint32_t reserved_f54; + uint32_t reserved_f58; + uint32_t reserved_f5c; + uint32_t reserved_f60; + uint32_t reserved_f64; + uint32_t reserved_f68; + uint32_t reserved_f6c; + uint32_t reserved_f70; + uint32_t reserved_f74; + uint32_t reserved_f78; + uint32_t reserved_f7c; + uint32_t reserved_f80; + uint32_t reserved_f84; + uint32_t reserved_f88; + uint32_t reserved_f8c; + uint32_t reserved_f90; + uint32_t reserved_f94; + uint32_t reserved_f98; + uint32_t reserved_f9c; + uint32_t reserved_fa0; + uint32_t reserved_fa4; + uint32_t reserved_fa8; + uint32_t reserved_fac; + uint32_t reserved_fb0; + uint32_t reserved_fb4; + uint32_t reserved_fb8; + uint32_t reserved_fbc; + uint32_t reserved_fc0; + uint32_t reserved_fc4; + uint32_t reserved_fc8; + uint32_t reserved_fcc; + uint32_t reserved_fd0; + uint32_t reserved_fd4; + uint32_t reserved_fd8; + uint32_t reserved_fdc; + uint32_t reserved_fe0; + uint32_t reserved_fe4; + uint32_t reserved_fe8; + uint32_t reserved_fec; + uint32_t reserved_ff0; + uint32_t reserved_ff4; + uint32_t reserved_ff8; + union { + struct { + uint32_t reg_system_reg_date : 28; /*reg_system_reg_date*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } date; +} system_dev_t; +extern system_dev_t SYSTEM; +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_SYSTEM_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/systimer_reg.h b/components/soc/esp32h2/include/soc/systimer_reg.h new file mode 100644 index 0000000000..4e9f64fffa --- /dev/null +++ b/components/soc/esp32h2/include/soc/systimer_reg.h @@ -0,0 +1,567 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * SYSTIMER_CONF. + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * SYSTIMER_UNIT0_OP. + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * SYSTIMER_UNIT1_OP. + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * SYSTIMER_UNIT0_LOAD_HI. + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * SYSTIMER_UNIT0_LOAD_LO. + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * SYSTIMER_UNIT1_LOAD_HI. + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * SYSTIMER_UNIT1_LOAD_LO. + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * SYSTIMER_TARGET0_HI. + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * SYSTIMER_TARGET0_LO. + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * SYSTIMER_TARGET1_HI. + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * SYSTIMER_TARGET1_LO. + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * SYSTIMER_TARGET2_HI. + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * SYSTIMER_TARGET2_LO. + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * SYSTIMER_TARGET0_CONF. + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * SYSTIMER_TARGET1_CONF. + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * SYSTIMER_TARGET2_CONF. + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * SYSTIMER_UNIT0_VALUE_HI. + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * SYSTIMER_UNIT0_VALUE_LO. + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * SYSTIMER_UNIT1_VALUE_HI. + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * SYSTIMER_UNIT1_VALUE_LO. + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * SYSTIMER_COMP0_LOAD. + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 load value + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * SYSTIMER_COMP1_LOAD. + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 load value + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * SYSTIMER_COMP2_LOAD. + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 load value + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * SYSTIMER_UNIT0_LOAD. + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 load value + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * SYSTIMER_UNIT1_LOAD. + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 load value + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * SYSTIMER_INT_ENA. + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * SYSTIMER_INT_RAW. + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * SYSTIMER_INT_CLR. + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * SYSTIMER_INT_ST. + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_DATE_REG register + * SYSTIMER_DATE. + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ +#define SYSTIMER_DATE 0xFFFFFFFF +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFF +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/systimer_struct.h b/components/soc/esp32h2/include/soc/systimer_struct.h new file mode 100644 index 0000000000..af41b1f3e2 --- /dev/null +++ b/components/soc/esp32h2/include/soc/systimer_struct.h @@ -0,0 +1,370 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Configuration Register */ +/** Type of conf register + * SYSTIMER_CONF. + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo: 1; + uint32_t reserved_1: 21; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en: 1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en: 1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en: 1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en: 1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en: 1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en: 1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en: 1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en: 1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en: 1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit_update: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 32 bit + */ + uint32_t timer_unit_load_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of target register + * SYSTIMER_TARGET. + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 32 bit + */ + uint32_t timer_target_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bit + */ + uint32_t timer_unit_value_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp load value + */ + uint32_t timer_comp_load: 1; + }; + uint32_t val; +} systimer_comp_load_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + }; + uint32_t val; +} systimer_unit_load_reg_t; + +/** Interrupt Register */ +/** Type of int_ena register + * SYSTIMER_INT_ENA. + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena: 1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena: 1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * SYSTIMER_INT_RAW. + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw: 1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw: 1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * SYSTIMER_INT_CLR. + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr: 1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr: 1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * SYSTIMER_INT_ST. + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ + uint32_t target0_int_st: 1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ + uint32_t target1_int_st: 1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ + uint32_t target2_int_st: 1; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Version Register */ +/** Type of date register + * SYSTIMER_DATE. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/include/soc/timer_group_reg.h new file mode 100644 index 0000000000..05ae6fb42e --- /dev/null +++ b/components/soc/esp32h2/include/soc/timer_group_reg.h @@ -0,0 +1,441 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_TIMG_REG_H_ +#define _SOC_TIMG_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 + +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 +/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (BIT(12)) +#define TIMG_T0_DIVCNT_RST_V 0x1 +#define TIMG_T0_DIVCNT_RST_S 12 +/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 +/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (BIT(9)) +#define TIMG_T0_USE_XTAL_V 0x1 +#define TIMG_T0_USE_XTAL_S 9 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) +/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T0_HI 0x003FFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0x3FFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) +/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (BIT(31)) +#define TIMG_T0_UPDATE_V 0x1 +#define TIMG_T0_UPDATE_S 31 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T0_ALARM_HI 0x003FFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0x3FFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T0_LOAD_HI 0x003FFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0x3FFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) +/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 +/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x1 +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_USE_XTAL (BIT(21)) +#define TIMG_WDT_USE_XTAL_M (BIT(21)) +#define TIMG_WDT_USE_XTAL_V 0x1 +#define TIMG_WDT_USE_XTAL_S 21 +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ +/*description: */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ +/*description: */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 +/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_V 0x1 +#define TIMG_WDT_DIVCNT_RST_S 0 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ +/*description: */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ +/*description: */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) +/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 +/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070) +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_ENA (BIT(1)) +#define TIMG_WDT_INT_ENA_M (BIT(1)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 1 +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074) +/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_RAW (BIT(1)) +#define TIMG_WDT_INT_RAW_M (BIT(1)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 1 +/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078) +/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_ST (BIT(1)) +#define TIMG_WDT_INT_ST_M (BIT(1)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 1 +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c) +/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_CLR (BIT(1)) +#define TIMG_WDT_INT_CLR_M (BIT(1)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 1 +/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080) +/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */ +/*description: timeout if cali value counts over threshold*/ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S)) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 +/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */ +/*description: Cycles that release calibration timeout reset*/ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: timeout indicator*/ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_V 0x1 +#define TIMG_RTC_CALI_TIMEOUT_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */ +/*description: */ +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 +/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1 +#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 +/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1 +#define TIMG_WDT_CLK_IS_ACTIVE_S 29 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_TIMG_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/timer_group_struct.h b/components/soc/esp32h2/include/soc/timer_group_struct.h new file mode 100644 index 0000000000..6bae30720c --- /dev/null +++ b/components/soc/esp32h2/include/soc/timer_group_struct.h @@ -0,0 +1,222 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_TIMG_STRUCT_H_ +#define _SOC_TIMG_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + struct { + union { + struct { + uint32_t reserved0: 9; + uint32_t use_xtal: 1; + uint32_t alarm_en: 1; + uint32_t reserved11: 1; + uint32_t divcnt_rst: 1; + uint32_t divider: 16; + uint32_t autoreload: 1; + uint32_t increase: 1; + uint32_t enable: 1; + }; + uint32_t val; + } config; + uint32_t cnt_low; /**/ + union { + struct { + uint32_t hi: 22; + uint32_t reserved22:10; + }; + uint32_t val; + } cnt_high; + union { + struct { + uint32_t reserved0: 31; + uint32_t update: 1; + }; + uint32_t val; + } update; + uint32_t alarm_low; /**/ + union { + struct { + uint32_t alarm_hi: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } alarm_high; + uint32_t load_low; /**/ + union { + struct { + uint32_t load_hi: 22; + uint32_t reserved22:10; + }; + uint32_t val; + } load_high; + uint32_t reload; /**/ + } hw_timer[1]; + uint32_t reserved_24; + uint32_t reserved_28; + uint32_t reserved_2c; + uint32_t reserved_30; + uint32_t reserved_34; + uint32_t reserved_38; + uint32_t reserved_3c; + uint32_t reserved_40; + uint32_t reserved_44; + union { + struct { + uint32_t reserved0: 12; + uint32_t appcpu_reset_en: 1; + uint32_t procpu_reset_en: 1; + uint32_t flashboot_mod_en: 1; + uint32_t sys_reset_length: 3; + uint32_t cpu_reset_length: 3; + uint32_t use_xtal: 1; + uint32_t conf_update_en: 1; + uint32_t stg3: 2; + uint32_t stg2: 2; + uint32_t stg1: 2; + uint32_t stg0: 2; + uint32_t en: 1; + }; + uint32_t val; + } wdt_config0; + union { + struct { + uint32_t divcnt_rst: 1; + uint32_t reserved1: 15; + uint32_t clk_prescale: 16; + }; + uint32_t val; + } wdt_config1; + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + uint32_t wdt_config5; /**/ + uint32_t wdt_feed; /**/ + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t reserved0: 12; + uint32_t start_cycling: 1; + uint32_t clk_sel: 2; + uint32_t rdy: 1; + uint32_t max: 15; + uint32_t start: 1; + }; + uint32_t val; + } rtc_cali_cfg; + union { + struct { + uint32_t cycling_data_vld: 1; + uint32_t reserved1: 6; + uint32_t value: 25; + }; + uint32_t val; + } rtc_cali_cfg1; + union { + struct { + uint32_t t0: 1; + uint32_t wdt: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t t0: 1; + uint32_t wdt: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t t0: 1; + uint32_t wdt: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t t0: 1; + uint32_t wdt: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t timeout: 1; /*timeout indicator*/ + uint32_t reserved1: 2; + uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/ + uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/ + }; + uint32_t val; + } rtc_cali_cfg2; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } timg_date; + union { + struct { + uint32_t reserved0: 29; + uint32_t wdt_clk_is_active: 1; + uint32_t timer_clk_is_active: 1; + uint32_t en: 1; + }; + uint32_t val; + } clk; +} timg_dev_t; +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/twai_struct.h b/components/soc/esp32h2/include/soc/twai_struct.h new file mode 100644 index 0000000000..64cb80e5ed --- /dev/null +++ b/components/soc/esp32h2/include/soc/twai_struct.h @@ -0,0 +1,209 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* ---------------------------- Register Layout ------------------------------ */ + +/* The TWAI peripheral's registers are 8bits, however the ESP32-C3 can only access + * peripheral registers every 32bits. Therefore each TWAI register is mapped to + * the least significant byte of every 32bits. + */ + +typedef volatile struct twai_dev_s { + //Configuration and Control Registers + union { + struct { + uint32_t rm: 1; /* MOD.0 Reset Mode */ + uint32_t lom: 1; /* MOD.1 Listen Only Mode */ + uint32_t stm: 1; /* MOD.2 Self Test Mode */ + uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */ + uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ + }; + uint32_t val; + } mode_reg; /* Address 0 */ + union { + struct { + uint32_t tr: 1; /* CMR.0 Transmission Request */ + uint32_t at: 1; /* CMR.1 Abort Transmission */ + uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */ + uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */ + uint32_t srr: 1; /* CMR.4 Self Reception Request */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; + } command_reg; /* Address 1 */ + union { + struct { + uint32_t rbs: 1; /* SR.0 Receive Buffer Status */ + uint32_t dos: 1; /* SR.1 Data Overrun Status */ + uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */ + uint32_t tcs: 1; /* SR.3 Transmission Complete Status */ + uint32_t rs: 1; /* SR.4 Receive Status */ + uint32_t ts: 1; /* SR.5 Transmit Status */ + uint32_t es: 1; /* SR.6 Error Status */ + uint32_t bs: 1; /* SR.7 Bus Status */ + uint32_t ms: 1; /* SR.8 Miss Status */ + uint32_t reserved23: 23; /* Internal Reserved */ + }; + uint32_t val; + } status_reg; /* Address 2 */ + union { + struct { + uint32_t ri: 1; /* IR.0 Receive Interrupt */ + uint32_t ti: 1; /* IR.1 Transmit Interrupt */ + uint32_t ei: 1; /* IR.2 Error Interrupt */ + uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ + uint32_t epi: 1; /* IR.5 Error Passive Interrupt */ + uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */ + uint32_t bei: 1; /* IR.7 Bus Error Interrupt */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } interrupt_reg; /* Address 3 */ + union { + struct { + uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */ + uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */ + uint32_t eie: 1; /* IER.2 Error Interrupt Enable */ + uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ + uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */ + uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */ + uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } interrupt_enable_reg; /* Address 4 */ + uint32_t reserved_05; /* Address 5 */ + union { + struct { + uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */ + uint32_t reserved1: 1; /* Internal Reserved */ + uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/ + uint32_t reserved16: 16; /* Internal Reserved */ + }; + uint32_t val; + } bus_timing_0_reg; /* Address 6 */ + union { + struct { + uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */ + uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */ + uint32_t sam: 1; /* BTR1.7 Sampling*/ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } bus_timing_1_reg; /* Address 7 */ + uint32_t reserved_08; /* Address 8 (Output control not supported) */ + uint32_t reserved_09; /* Address 9 (Test Register not supported) */ + uint32_t reserved_10; /* Address 10 */ + + //Capture and Counter Registers + union { + struct { + uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; + } arbitration_lost_captue_reg; /* Address 11 */ + union { + struct { + uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ + uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */ + uint32_t errc: 2; /* ECC[7:6] Error Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } error_code_capture_reg; /* Address 12 */ + union { + struct { + uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */ + union { + struct { + uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } rx_error_counter_reg; /* Address 12 */ + union { + struct { + uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } tx_error_counter_reg; /* Address 15 */ + + //Shared Registers (TX Buff/RX Buff/Acc Filter) + union { + struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved32[5]; + } acceptance_filter; + union { + struct { + uint32_t byte: 8; + uint32_t reserved24: 24; + }; + uint32_t val; + } tx_rx_buffer[13]; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + + //Misc Registers + union { + struct { + uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */ + uint32_t reserved25: 25; /* Internal Reserved */ + }; + uint32_t val; + } rx_message_counter_reg; /* Address 29 */ + uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */ + union { + struct { + uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */ + uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */ + uint32_t reserved24: 23; /* Internal Reserved */ + }; + uint32_t val; + } clock_divider_reg; /* Address 31 */ +} twai_dev_t; + +_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes"); + +extern twai_dev_t TWAI; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/uart_channel.h b/components/soc/esp32h2/include/soc/uart_channel.h new file mode 100644 index 0000000000..855728262e --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_channel.h @@ -0,0 +1,61 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_UART_CHANNEL_H +#define _SOC_UART_CHANNEL_H + +//UART channels +#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1 +#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3 +#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19 +#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22 + +#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL +#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL +#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL +#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL + +#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10 +#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9 +#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6 +#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11 + +#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL +#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL +#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL +#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL + +#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17 +#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16 +#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8 +#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7 + +#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL +#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL +#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL +#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL + +#endif diff --git a/components/soc/esp32h2/include/soc/uart_reg.h b/components/soc/esp32h2/include/soc/uart_reg.h new file mode 100644 index 0000000000..a0d6c72735 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_reg.h @@ -0,0 +1,1258 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_REG_H_ +#define _SOC_UART_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: UART $n accesses FIFO via this register.*/ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when input rxd edge + changes more times than what reg_active_threshold specifies in light sleeping mode.*/ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (BIT(19)) +#define UART_WAKEUP_INT_RAW_V 0x1 +#define UART_WAKEUP_INT_RAW_S 19 +/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the configured at_cmd char.*/ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when detects a clash + between transmitter and receiver in rs485 mode.*/ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + a data frame error from the echo of transmitter in rs485 mode.*/ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + a parity error from the echo of transmitter in rs485 mode.*/ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + send out all data in FIFO.*/ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + kept the shortest duration after sending the last data.*/ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter completes + sending NULL characters after all data in Tx-FIFO are sent.*/ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + a glitch in the middle of a start bit.*/ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + Xoff char when uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver recevies + Xon char when uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte.*/ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + a 0 after the stop bit.*/ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of CTSn signal.*/ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of DSRn signal.*/ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than the FIFO can store.*/ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + a data frame error .*/ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + a parity error in the data.*/ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */ +/*description: This interrupt raw bit turns to high level when the amount of + data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than what rxfifo_full_thrhd specifies.*/ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena + is set to 1.*/ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (BIT(19)) +#define UART_WAKEUP_INT_ST_V 0x1 +#define UART_WAKEUP_INT_ST_S 19 +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1.*/ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + is set to 1.*/ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena + is set to 1.*/ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena + is set to 1.*/ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1.*/ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1.*/ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1.*/ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1.*/ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1.*/ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1.*/ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the enable bit for uart_wakeup_int_st register.*/ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (BIT(19)) +#define UART_WAKEUP_INT_ENA_V 0x1 +#define UART_WAKEUP_INT_ENA_S 19 +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_clash_int_st register.*/ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_done_int_st register.*/ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_done_int_st register.*/ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the enable bit for glitch_det_int_st register.*/ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xoff_int_st register.*/ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xon_int_st register.*/ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_tout_int_st register.*/ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the enable bit for brk_det_int_st register.*/ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the enable bit for cts_chg_int_st register.*/ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the enable bit for dsr_chg_int_st register.*/ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the enable bit for frm_err_int_st register.*/ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the enable bit for parity_err_int_st register.*/ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the enable bit for txfifo_empty_int_st register.*/ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear the uart_wakeup_int_raw interrupt.*/ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (BIT(19)) +#define UART_WAKEUP_INT_CLR_V 0x1 +#define UART_WAKEUP_INT_CLR_S 19 +/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xoff_int_raw interrupt.*/ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear frm_err_int_raw interrupt.*/ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear parity_err_int_raw interrupt.*/ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: The decimal part of the frequency divider factor.*/ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */ +/*description: The integral part of the frequency divider factor.*/ +#define UART_CLKDIV 0x00000FFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFF +#define UART_CLKDIV_S 0 + +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enable Rx signal filter.*/ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (BIT(8)) +#define UART_GLITCH_FILT_EN_V 0x1 +#define UART_GLITCH_FILT_EN_S 8 +/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */ +/*description: when input pulse width is lower than this value the pulse is ignored.*/ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */ +/*description: This bit represents the level of the internal uart txd signal.*/ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This bit represents the level of the internal uart rts signal.*/ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit represents the level of the internal uart dtr signal.*/ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 +/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */ +/*description: Stores the byte number of data in Tx-FIFO.*/ +#define UART_TXFIFO_CNT 0x000003FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0x3FF +#define UART_TXFIFO_CNT_S 16 +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */ +/*description: This register represent the level value of the internal uart rxd signal.*/ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */ +/*description: This register represent the level value of the internal uart cts signal.*/ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The register represent the level value of the internal uart dsr signal.*/ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 +/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: Stores the byte number of valid data in Rx-FIFO.*/ +#define UART_RXFIFO_CNT 0x000003FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0x3FF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */ +/*description: UART memory clock gate enable signal.*/ +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (BIT(28)) +#define UART_MEM_CLK_EN_V 0x1 +#define UART_MEM_CLK_EN_S 28 +/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This is the enable bit for detecting baudrate.*/ +#define UART_AUTOBAUD_EN (BIT(27)) +#define UART_AUTOBAUD_EN_M (BIT(27)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 27 +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. + 1'h0: Receiver stores the data even if the received data is wrong.*/ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when + application writes registers.*/ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dtr signal.*/ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rts signal.*/ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart txd signal.*/ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dsr signal.*/ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart cts signal.*/ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rxd signal.*/ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Set this bit to reset the uart transmit-FIFO.*/ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Set this bit to reset the uart receive-FIFO.*/ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to enable IrDA protocol.*/ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control function for transmitter.*/ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart loopback test mode.*/ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to invert the level of IrDA receiver.*/ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to invert the level of IrDA transmitter.*/ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. + 1'h0: Set IrDA transmitter's 11th bit to 0.*/ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the start enable bit for IrDA transmitter.*/ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable IrDA loopback mode.*/ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enbale transmitter to send NULL when the process + of sending data is done.*/ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This register is used to configure the software dtr signal which + is used in software flow control.*/ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register is used to configure the software rts signal which + is used in software flow control.*/ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/*description: This register is used to set the length of stop bit.*/ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: This register is used to set the length of data.*/ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart parity check.*/ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register is used to configure the parity check mode.*/ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: This is the enble bit for uart receiver's timeout function.*/ +#define UART_RX_TOUT_EN (BIT(21)) +#define UART_RX_TOUT_EN_M (BIT(21)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 21 +/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This is the flow enable bit for UART receiver.*/ +#define UART_RX_FLOW_EN (BIT(20)) +#define UART_RX_FLOW_EN_M (BIT(20)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 20 +/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ +#define UART_RX_TOUT_FLOW_DIS (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_M (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_V 0x1 +#define UART_RX_TOUT_FLOW_DIS_S 19 +/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Disable UART Rx data overflow detect.*/ +#define UART_DIS_RX_DAT_OVF (BIT(18)) +#define UART_DIS_RX_DAT_OVF_M (BIT(18)) +#define UART_DIS_RX_DAT_OVF_V 0x1 +#define UART_DIS_RX_DAT_OVF_S 18 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */ +/*description: It will produce txfifo_empty_int interrupt when the data amount + in Tx-FIFO is less than this register value.*/ +#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF +#define UART_TXFIFO_EMPTY_THRHD_S 9 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */ +/*description: It will produce rxfifo_full_int interrupt when receiver receives + more data than this register value.*/ +#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x1FF +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: This register stores the value of the minimum duration time of + the low level pulse. It is used in baud rate-detect process.*/ +#define UART_LOWPULSE_MIN_CNT 0x00000FFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: This register stores the value of the maxinum duration time + for the high level pulse. It is used in baud rate-detect process.*/ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register stores the count of rxd edge change. It is used + in baud rate-detect process.*/ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to send Xoff char. It is cleared by hardware automatically.*/ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to send Xon char. It is cleared by hardware automatically.*/ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to stop the transmitter from sending data.*/ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable the transmitter to go on sending data.*/ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to remove flow control char from the received data.*/ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable software flow control. It is used with + register sw_xon or sw_xoff.*/ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: The uart is activated from light sleeping mode when the input + rxd edge changes more times than this register value.*/ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3C) +/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */ +/*description: This register stores the Xoff flow control char.*/ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 9 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */ +/*description: When the data amount in Rx-FIFO is more than this register value + with uart_sw_flow_con_en set to 1 it will send a Xoff char.*/ +#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0x1FF +#define UART_XOFF_THRESHOLD_S 0 + +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */ +/*description: This register stores the Xon flow control char.*/ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 9 +/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: When the data amount in Rx-FIFO is less than this register value + with uart_sw_flow_con_en set to 1 it will send a Xon char.*/ +#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0x1FF +#define UART_XON_THRESHOLD_S 0 + +#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */ +/*description: This register is used to configure the number of 0 to be sent + after the process of sending data is done. It is active when txd_brk is set to 1.*/ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48) +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/*description: This register is used to configure the duration time between transfers.*/ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: It will produce frame end signal when receiver takes more time + to receive one byte data than this register value.*/ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c) +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: This register is used to delay the transmitter's internal data signal.*/ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This register is used to delay the receiver's internal data signal.*/ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable receiver could receive data when the transmitter + is transmitting data in rs485 mode.*/ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to choose the rs485 mode.*/ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ +/*description: This register is used to configure the idle duration time before + the first at_cmd is received by receiver.*/ +#define UART_PRE_IDLE_NUM 0x0000FFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) +/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ +/*description: This register is used to configure the duration time between + the last at_cmd and the next data.*/ +#define UART_POST_IDLE_NUM 0x0000FFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) +/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */ +/*description: This register is used to configure the duration time between the at_cmd chars.*/ +#define UART_RX_GAP_TOUT 0x0000FFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/*description: This register is used to configure the num of continuous at_cmd + chars received by receiver.*/ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/*description: This register is used to configure the content of at_cmd char.*/ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to force power up UART memory.*/ +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (BIT(27)) +#define UART_MEM_FORCE_PU_V 0x1 +#define UART_MEM_FORCE_PU_S 27 +/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to force power down UART memory.*/ +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (BIT(26)) +#define UART_MEM_FORCE_PD_V 0x1 +#define UART_MEM_FORCE_PD_S 26 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */ +/*description: This register is used to configure the threshold time that receiver + takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/ +#define UART_RX_TOUT_THRHD 0x000003FF +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x3FF +#define UART_RX_TOUT_THRHD_S 16 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */ +/*description: This register is used to configure the maximum amount of data + that can be received when hardware flow control works.*/ +#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x1FF +#define UART_RX_FLOW_THRHD_S 7 +/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + for transmit-FIFO. The default number is 128 bytes.*/ +#define UART_TX_SIZE 0x00000007 +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0x7 +#define UART_TX_SIZE_S 4 +/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */ +/*description: This register is used to configure the amount of mem allocated + for receive-FIFO. The default number is 128 bytes.*/ +#define UART_RX_SIZE 0x00000007 +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0x7 +#define UART_RX_SIZE_S 1 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */ +/*description: This register stores the offset address in Tx-FIFO when Tx-FSM + reads data via Tx-FIFO_Ctrl.*/ +#define UART_TX_RADDR 0x000003FF +#define UART_TX_RADDR_M ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S)) +#define UART_TX_RADDR_V 0x3FF +#define UART_TX_RADDR_S 11 +/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register stores the offset address in Tx-FIFO when software + writes Tx-FIFO via APB.*/ +#define UART_APB_TX_WADDR 0x000003FF +#define UART_APB_TX_WADDR_M ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S)) +#define UART_APB_TX_WADDR_V 0x3FF +#define UART_APB_TX_WADDR_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */ +/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl + writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/ +#define UART_RX_WADDR 0x000003FF +#define UART_RX_WADDR_M ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S)) +#define UART_RX_WADDR_V 0x3FF +#define UART_RX_WADDR_S 11 +/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: This register stores the offset address in RX-FIFO when software + reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/ +#define UART_APB_RX_RADDR 0x000003FF +#define UART_APB_RX_RADDR_M ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S)) +#define UART_APB_RX_RADDR_V 0x3FF +#define UART_APB_RX_RADDR_S 0 + +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: This is the status register of transmitter.*/ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 4 +/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: This is the status register of receiver.*/ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: This register stores the minimal input clock count between two + positive edges. It is used in boudrate-detect process.*/ +#define UART_POSEDGE_MIN_CNT 0x00000FFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: This register stores the minimal input clock count between two + negative edges. It is used in boudrate-detect process.*/ +#define UART_NEGEDGE_MIN_CNT 0x00000FFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78) +/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Write 1 then write 0 to this bit reset UART Rx.*/ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (BIT(27)) +#define UART_RX_RST_CORE_V 0x1 +#define UART_RX_RST_CORE_S 27 +/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write 1 then write 0 to this bit reset UART Tx.*/ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (BIT(26)) +#define UART_TX_RST_CORE_V 0x1 +#define UART_TX_RST_CORE_S 26 +/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: Set this bit to enable UART Rx clock.*/ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (BIT(25)) +#define UART_RX_SCLK_EN_V 0x1 +#define UART_RX_SCLK_EN_S 25 +/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: Set this bit to enable UART Tx clock.*/ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (BIT(24)) +#define UART_TX_SCLK_EN_V 0x1 +#define UART_TX_SCLK_EN_S 24 +/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Write 1 then write 0 to this bit reset UART Tx/Rx.*/ +#define UART_RST_CORE (BIT(23)) +#define UART_RST_CORE_M (BIT(23)) +#define UART_RST_CORE_V 0x1 +#define UART_RST_CORE_S 23 +/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: Set this bit to enable UART Tx/Rx clock.*/ +#define UART_SCLK_EN (BIT(22)) +#define UART_SCLK_EN_M (BIT(22)) +#define UART_SCLK_EN_V 0x1 +#define UART_SCLK_EN_S 22 +/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */ +/*description: UART clock source select. 1: 80Mhz 2: 8Mhz 3: XTAL.*/ +#define UART_SCLK_SEL 0x00000003 +#define UART_SCLK_SEL_M ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S)) +#define UART_SCLK_SEL_V 0x3 +#define UART_SCLK_SEL_S 20 +/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */ +/*description: The integral part of the frequency divider factor.*/ +#define UART_SCLK_DIV_NUM 0x000000FF +#define UART_SCLK_DIV_NUM_M ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S)) +#define UART_SCLK_DIV_NUM_V 0xFF +#define UART_SCLK_DIV_NUM_S 12 +/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */ +/*description: The numerator of the frequency divider factor.*/ +#define UART_SCLK_DIV_A 0x0000003F +#define UART_SCLK_DIV_A_M ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S)) +#define UART_SCLK_DIV_A_V 0x3F +#define UART_SCLK_DIV_A_S 6 +/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: The denominator of the frequency divider factor.*/ +#define UART_SCLK_DIV_B 0x0000003F +#define UART_SCLK_DIV_B_M ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S)) +#define UART_SCLK_DIV_B_V 0x3F +#define UART_SCLK_DIV_B_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */ +/*description: This is the version register.*/ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) +/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software write 1 would synchronize registers into UART Core clock + domain and would be cleared by hardware after synchronization is done.*/ +#define UART_UPDATE (BIT(31)) +#define UART_UPDATE_M (BIT(31)) +#define UART_UPDATE_V 0x1 +#define UART_UPDATE_S 31 +/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This bit used to select synchronize mode. 1: Registers are auto + synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers software needs to write 1 to UART_REG_UPDATE to synchronize registers.*/ +#define UART_HIGH_SPEED (BIT(30)) +#define UART_HIGH_SPEED_M (BIT(30)) +#define UART_HIGH_SPEED_V 0x1 +#define UART_HIGH_SPEED_S 30 +/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */ +/*description: This register is used to configure the uart_id.*/ +#define UART_ID 0x3FFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0x3FFFFFFF +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_UART_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/uart_struct.h b/components/soc/esp32h2/include/soc/uart_struct.h new file mode 100644 index 0000000000..ad9ca42ff7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_struct.h @@ -0,0 +1,406 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_STRUCT_H_ +#define _SOC_UART_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t rw_byte; /*a*/ + }; + uint32_t val; + } ahb_fifo; + union { + struct { + uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/ + uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/ + uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/ + uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/ + uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/ + uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/ + uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/ + uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/ + uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/ + uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/ + uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.*/ + uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.*/ + uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/ + uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/ + uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/ + uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/ + uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/ + uint32_t wakeup: 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/ + uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + uint32_t wakeup: 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t txfifo_empty: 1; /*This is the enable bit for txfifo_empty_int_st register.*/ + uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ + uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ + uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ + uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ + uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ + uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ + uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ + uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + uint32_t wakeup: 1; /*This is the enable bit for uart_wakeup_int_st register.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/ + uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + uint32_t wakeup: 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t div_int: 12; /*The integral part of the frequency divider factor.*/ + uint32_t reserved12: 8; + uint32_t div_frag: 4; /*The decimal part of the frequency divider factor.*/ + uint32_t reserved24: 8; /*Reserved*/ + }; + uint32_t val; + } clk_div; + union { + struct { + uint32_t glitch_filt: 8; /*when input pulse width is lower than this value the pulse is ignored.*/ + uint32_t glitch_filt_en: 1; /*Set this bit to enable Rx signal filter.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } rx_filt; + union { + struct { + uint32_t rxfifo_cnt:10; /*Stores the byte number of valid data in Rx-FIFO.*/ + uint32_t reserved10: 3; + uint32_t dsrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ + uint32_t ctsn: 1; /*This register represent the level value of the internal uart cts signal.*/ + uint32_t rxd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + uint32_t txfifo_cnt:10; /*Stores the byte number of data in Tx-FIFO.*/ + uint32_t reserved26: 3; /*Reserved*/ + uint32_t dtrn: 1; /*This bit represents the level of the internal uart dtr signal.*/ + uint32_t rtsn: 1; /*This bit represents the level of the internal uart rts signal.*/ + uint32_t txd: 1; /*This bit represents the level of the internal uart txd signal.*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t parity: 1; /*This register is used to configure the parity check mode.*/ + uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ + uint32_t bit_num: 2; /*This register is used to set the length of data.*/ + uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit.*/ + uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/ + uint32_t txd_brk: 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/ + uint32_t irda_dplx: 1; /*Set this bit to enable IrDA loopback mode.*/ + uint32_t irda_tx_en: 1; /*This is the start enable bit for IrDA transmitter.*/ + uint32_t irda_wctl: 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/ + uint32_t irda_tx_inv: 1; /*Set this bit to invert the level of IrDA transmitter.*/ + uint32_t irda_rx_inv: 1; /*Set this bit to invert the level of IrDA receiver.*/ + uint32_t loopback: 1; /*Set this bit to enable uart loopback test mode.*/ + uint32_t tx_flow_en: 1; /*Set this bit to enable flow control function for transmitter.*/ + uint32_t irda_en: 1; /*Set this bit to enable IrDA protocol.*/ + uint32_t rxfifo_rst: 1; /*Set this bit to reset the uart receive-FIFO.*/ + uint32_t txfifo_rst: 1; /*Set this bit to reset the uart transmit-FIFO.*/ + uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ + uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ + uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ + uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + uint32_t clk_en: 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/ + uint32_t err_wr_mask: 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/ + uint32_t autobaud_en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t mem_clk_en: 1; /*UART memory clock gate enable signal.*/ + uint32_t reserved29: 3; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rxfifo_full_thrhd: 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/ + uint32_t txfifo_empty_thrhd: 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/ + uint32_t dis_rx_dat_ovf: 1; /*Disable UART Rx data overflow detect.*/ + uint32_t rx_tout_flow_dis: 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ + uint32_t rx_flow_en: 1; /*This is the flow enable bit for UART receiver.*/ + uint32_t rx_tout_en: 1; /*This is the enble bit for uart receiver's timeout function.*/ + uint32_t reserved22: 10; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t min_cnt: 12; /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } lowpulse; + union { + struct { + uint32_t min_cnt: 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } highpulse; + union { + struct { + uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/ + uint32_t reserved10: 22; /*Reserved*/ + }; + uint32_t val; + } rxd_cnt; + union { + struct { + uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/ + uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ + uint32_t force_xon: 1; /*Set this bit to enable the transmitter to go on sending data.*/ + uint32_t force_xoff: 1; /*Set this bit to stop the transmitter from sending data.*/ + uint32_t send_xon: 1; /*Set this bit to send Xon char. It is cleared by hardware automatically.*/ + uint32_t send_xoff: 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/ + uint32_t reserved6: 26; /*Reserved*/ + }; + uint32_t val; + } flow_conf; + union { + struct { + uint32_t active_threshold:10; /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/ + uint32_t reserved10: 22; /*Reserved*/ + }; + uint32_t val; + } sleep_conf; + union { + struct { + uint32_t xoff_threshold: 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char.*/ + uint32_t xoff_char: 8; /*This register stores the Xoff flow control char.*/ + uint32_t reserved17: 15; /*Reserved*/ + }; + uint32_t val; + } swfc_conf0; + union { + struct { + uint32_t xon_threshold: 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char.*/ + uint32_t xon_char: 8; /*This register stores the Xon flow control char.*/ + uint32_t reserved17: 15; /*Reserved*/ + }; + uint32_t val; + } swfc_conf1; + union { + struct { + uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } txbrk_conf; + union { + struct { + uint32_t rx_idle_thrhd:10; /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/ + uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } idle_conf; + union { + struct { + uint32_t en: 1; /*Set this bit to choose the rs485 mode.*/ + uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t tx_rx_en: 1; /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.*/ + uint32_t rx_busy_tx_en: 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/ + uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t reserved10: 22; /*Reserved*/ + }; + uint32_t val; + } rs485_conf; + union { + struct { + uint32_t pre_idle_num:16; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver.*/ + uint32_t reserved16: 16; /*Reserved*/ + }; + uint32_t val; + } at_cmd_precnt; + union { + struct { + uint32_t post_idle_num:16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/ + uint32_t reserved16: 16; /*Reserved*/ + }; + uint32_t val; + } at_cmd_postcnt; + union { + struct { + uint32_t rx_gap_tout:16; /*This register is used to configure the duration time between the at_cmd chars.*/ + uint32_t reserved16: 16; /*Reserved*/ + }; + uint32_t val; + } at_cmd_gaptout; + union { + struct { + uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ + uint32_t char_num: 8; /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/ + uint32_t reserved16: 16; /*Reserved*/ + }; + uint32_t val; + } at_cmd_char; + union { + struct { + uint32_t reserved0: 1; + uint32_t rx_size: 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/ + uint32_t tx_size: 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/ + uint32_t rx_flow_thrhd: 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/ + uint32_t rx_tout_thrhd:10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/ + uint32_t force_pd: 1; /*Set this bit to force power down UART memory.*/ + uint32_t force_pu: 1; /*Set this bit to force power up UART memory.*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } mem_conf; + union { + struct { + uint32_t apb_tx_waddr:10; /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/ + uint32_t reserved10: 1; /*Reserved*/ + uint32_t tx_raddr: 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/ + uint32_t reserved21: 11; /*Reserved*/ + }; + uint32_t val; + } mem_tx_status; + union { + struct { + uint32_t apb_rx_raddr:10; /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/ + uint32_t reserved10: 1; /*Reserved*/ + uint32_t rx_waddr: 10; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/ + uint32_t reserved21: 11; /*Reserved*/ + }; + uint32_t val; + } mem_rx_status; + union { + struct { + uint32_t st_urx_out: 4; /*This is the status register of receiver.*/ + uint32_t st_utx_out: 4; /*This is the status register of transmitter.*/ + uint32_t reserved8: 24; /*Reserved*/ + }; + uint32_t val; + } fsm_status; + union { + struct { + uint32_t min_cnt: 12; /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } pospulse; + union { + struct { + uint32_t min_cnt: 12; /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } negpulse; + union { + struct { + uint32_t sclk_div_b: 6; /*The denominator of the frequency divider factor.*/ + uint32_t sclk_div_a: 6; /*The numerator of the frequency divider factor.*/ + uint32_t sclk_div_num: 8; /*The integral part of the frequency divider factor.*/ + uint32_t sclk_sel: 2; /*UART clock source select. 1: 80Mhz 2: 8Mhz 3: XTAL.*/ + uint32_t sclk_en: 1; /*Set this bit to enable UART Tx/Rx clock.*/ + uint32_t rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx/Rx.*/ + uint32_t tx_sclk_en: 1; /*Set this bit to enable UART Tx clock.*/ + uint32_t rx_sclk_en: 1; /*Set this bit to enable UART Rx clock.*/ + uint32_t tx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx.*/ + uint32_t rx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Rx.*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } clk_conf; + uint32_t date; /*UART Version register*/ + union { + struct { + uint32_t id : 30; /*This register is used to configure the uart_id.*/ + uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */ + uint32_t update : 1; /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/ + }; + uint32_t val; + } id; +} uart_dev_t; +extern uart_dev_t UART0; +extern uart_dev_t UART1; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_UART_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/uhci_reg.h b/components/soc/esp32h2/include/soc/uhci_reg.h new file mode 100644 index 0000000000..3a41dedb80 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uhci_reg.h @@ -0,0 +1,748 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_REG_H_ +#define _SOC_UHCI_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: If this bit is set to 1 UHCI will end payload receive process + when NULL frame is received by UART.*/ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 +#define UHCI_UART_RX_BRK_EOF_EN_S 12 +/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1'b1: Force clock on for register. 1'b0: Support clock only when + application writes registers.*/ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (BIT(11)) +#define UHCI_CLK_EN_V 0x1 +#define UHCI_CLK_EN_S 11 +/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: Set this bit to enable data integrity checking by appending a + 16 bit CCITT-CRC to end of the payload.*/ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (BIT(10)) +#define UHCI_ENCODE_CRC_EN_V 0x1 +#define UHCI_ENCODE_CRC_EN_S 10 +/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: If this bit is set to 1 UHCI decoder receiving payload data + is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (BIT(9)) +#define UHCI_LEN_EOF_EN_V 0x1 +#define UHCI_LEN_EOF_EN_S 9 +/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: If this bit is set to 1 UHCI will end the payload receiving + process when UART has been in idle state.*/ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_V 0x1 +#define UHCI_UART_IDLE_EOF_EN_S 8 +/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (BIT(7)) +#define UHCI_CRC_REC_EN_V 0x1 +#define UHCI_CRC_REC_EN_S 7 +/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: Set this bit to encode the data packet with a formatting header.*/ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (BIT(6)) +#define UHCI_HEAD_EN_V 0x1 +#define UHCI_HEAD_EN_S 6 +/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Set this bit to separate the data frame using a special char.*/ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (BIT(5)) +#define UHCI_SEPER_EN_V 0x1 +#define UHCI_SEPER_EN_S 5 +/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to link up HCI and UART1.*/ +#define UHCI_UART1_CE (BIT(3)) +#define UHCI_UART1_CE_M (BIT(3)) +#define UHCI_UART1_CE_V 0x1 +#define UHCI_UART1_CE_S 3 +/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to link up HCI and UART0.*/ +#define UHCI_UART0_CE (BIT(2)) +#define UHCI_UART0_CE_M (BIT(2)) +#define UHCI_UART0_CE_V 0x1 +#define UHCI_UART0_CE_S 2 +/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Write 1 then write 0 to this bit to reset encode state machine.*/ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (BIT(1)) +#define UHCI_RX_RST_V 0x1 +#define UHCI_RX_RST_S 1 +/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Write 1 then write 0 to this bit to reset decode state machine.*/ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (BIT(0)) +#define UHCI_TX_RST_V 0x1 +#define UHCI_TX_RST_S 0 + +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Soft control int raw bit.*/ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_V 0x1 +#define UHCI_APP_CTRL1_INT_RAW_S 8 +/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Soft control int raw bit.*/ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_V 0x1 +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit. Triggered when there are some + errors in EOF in the*/ +#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6 +/* UHCI_SEND_A_Q_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_A_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_RAW_V 0x1 +#define UHCI_SEND_A_Q_INT_RAW_S 5 +/* UHCI_SEND_S_Q_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_S_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_RAW_V 0x1 +#define UHCI_SEND_S_Q_INT_RAW_S 4 +/* UHCI_TX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_V 0x1 +#define UHCI_TX_HUNG_INT_RAW_S 3 +/* UHCI_RX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_V 0x1 +#define UHCI_RX_HUNG_INT_RAW_S 2 +/* UHCI_TX_START_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (BIT(1)) +#define UHCI_TX_START_INT_RAW_V 0x1 +#define UHCI_TX_START_INT_RAW_S 1 +/* UHCI_RX_START_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (BIT(0)) +#define UHCI_RX_START_INT_RAW_V 0x1 +#define UHCI_RX_START_INT_RAW_S 0 + +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_V 0x1 +#define UHCI_APP_CTRL1_INT_ST_S 8 +/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_V 0x1 +#define UHCI_APP_CTRL0_INT_ST_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_A_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_Q_INT_ST_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_ST_V 0x1 +#define UHCI_SEND_A_Q_INT_ST_S 5 +/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_S_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_Q_INT_ST_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_ST_V 0x1 +#define UHCI_SEND_S_Q_INT_ST_S 4 +/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_V 0x1 +#define UHCI_TX_HUNG_INT_ST_S 3 +/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_V 0x1 +#define UHCI_RX_HUNG_INT_ST_S 2 +/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (BIT(1)) +#define UHCI_TX_START_INT_ST_V 0x1 +#define UHCI_TX_START_INT_ST_S 1 +/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (BIT(0)) +#define UHCI_RX_START_INT_ST_V 0x1 +#define UHCI_RX_START_INT_ST_S 0 + +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) +/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_V 0x1 +#define UHCI_APP_CTRL1_INT_ENA_S 8 +/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_V 0x1 +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_A_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_ENA_V 0x1 +#define UHCI_SEND_A_Q_INT_ENA_S 5 +/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_S_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_ENA_V 0x1 +#define UHCI_SEND_S_Q_INT_ENA_S 4 +/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_V 0x1 +#define UHCI_TX_HUNG_INT_ENA_S 3 +/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_V 0x1 +#define UHCI_RX_HUNG_INT_ENA_S 2 +/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (BIT(1)) +#define UHCI_TX_START_INT_ENA_V 0x1 +#define UHCI_TX_START_INT_ENA_S 1 +/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (BIT(0)) +#define UHCI_RX_START_INT_ENA_V 0x1 +#define UHCI_RX_START_INT_ENA_S 0 + +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +/* UHCI_APP_CTRL1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_V 0x1 +#define UHCI_APP_CTRL1_INT_CLR_S 8 +/* UHCI_APP_CTRL0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_V 0x1 +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/* UHCI_SEND_A_Q_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_A_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_CLR_V 0x1 +#define UHCI_SEND_A_Q_INT_CLR_S 5 +/* UHCI_SEND_S_Q_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SEND_S_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_CLR_V 0x1 +#define UHCI_SEND_S_Q_INT_CLR_S 4 +/* UHCI_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_V 0x1 +#define UHCI_TX_HUNG_INT_CLR_S 3 +/* UHCI_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_V 0x1 +#define UHCI_RX_HUNG_INT_CLR_S 2 +/* UHCI_TX_START_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (BIT(1)) +#define UHCI_TX_START_INT_CLR_V 0x1 +#define UHCI_TX_START_INT_CLR_S 1 +/* UHCI_RX_START_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (BIT(0)) +#define UHCI_RX_START_INT_CLR_V 0x1 +#define UHCI_RX_START_INT_CLR_S 0 + +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14) +/* UHCI_SW_START : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (BIT(8)) +#define UHCI_SW_START_V 0x1 +#define UHCI_SW_START_S 8 +/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (BIT(7)) +#define UHCI_WAIT_SW_START_V 0x1 +#define UHCI_WAIT_SW_START_S 7 +/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_V 0x1 +#define UHCI_TX_ACK_NUM_RE_S 5 +/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_V 0x1 +#define UHCI_TX_CHECK_SUM_RE_S 4 +/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (BIT(3)) +#define UHCI_SAVE_HEAD_V 0x1 +#define UHCI_SAVE_HEAD_S 3 +/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (BIT(2)) +#define UHCI_CRC_DISABLE_V 0x1 +#define UHCI_CRC_DISABLE_S 2 +/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (BIT(1)) +#define UHCI_CHECK_SEQ_EN_V 0x1 +#define UHCI_CHECK_SEQ_EN_S 1 +/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (BIT(0)) +#define UHCI_CHECK_SUM_EN_V 0x1 +#define UHCI_CHECK_SUM_EN_S 0 + +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18) +/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: a*/ +#define UHCI_DECODE_STATE 0x00000007 +#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S)) +#define UHCI_DECODE_STATE_V 0x7 +#define UHCI_DECODE_STATE_S 3 +/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: a*/ +#define UHCI_RX_ERR_CAUSE 0x00000007 +#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S)) +#define UHCI_RX_ERR_CAUSE_V 0x7 +#define UHCI_RX_ERR_CAUSE_S 0 + +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1C) +/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: a*/ +#define UHCI_ENCODE_STATE 0x00000007 +#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S)) +#define UHCI_ENCODE_STATE_V 0x7 +#define UHCI_ENCODE_STATE_S 0 + +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20) +/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (BIT(7)) +#define UHCI_RX_13_ESC_EN_V 0x1 +#define UHCI_RX_13_ESC_EN_S 7 +/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (BIT(6)) +#define UHCI_RX_11_ESC_EN_V 0x1 +#define UHCI_RX_11_ESC_EN_S 6 +/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (BIT(5)) +#define UHCI_RX_DB_ESC_EN_V 0x1 +#define UHCI_RX_DB_ESC_EN_S 5 +/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (BIT(4)) +#define UHCI_RX_C0_ESC_EN_V 0x1 +#define UHCI_RX_C0_ESC_EN_S 4 +/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (BIT(3)) +#define UHCI_TX_13_ESC_EN_V 0x1 +#define UHCI_TX_13_ESC_EN_S 3 +/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (BIT(2)) +#define UHCI_TX_11_ESC_EN_V 0x1 +#define UHCI_TX_11_ESC_EN_S 2 +/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (BIT(1)) +#define UHCI_TX_DB_ESC_EN_V 0x1 +#define UHCI_TX_DB_ESC_EN_S 1 +/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (BIT(0)) +#define UHCI_TX_C0_ESC_EN_V 0x1 +#define UHCI_TX_C0_ESC_EN_S 0 + +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) +/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 +/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: a*/ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ +/*description: a*/ +#define UHCI_RXFIFO_TIMEOUT 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S)) +#define UHCI_RXFIFO_TIMEOUT_V 0xFF +#define UHCI_RXFIFO_TIMEOUT_S 12 +/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: a*/ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: a*/ +#define UHCI_TXFIFO_TIMEOUT 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S)) +#define UHCI_TXFIFO_TIMEOUT_V 0xFF +#define UHCI_TXFIFO_TIMEOUT_S 0 + +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28) +/* UHCI_ACK_NUM_LOAD : WT ;bitpos:[3] ;default: 1'b1 ; */ +/*description: a*/ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (BIT(3)) +#define UHCI_ACK_NUM_LOAD_V 0x1 +#define UHCI_ACK_NUM_LOAD_S 3 +/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: */ +#define UHCI_ACK_NUM 0x00000007 +#define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S)) +#define UHCI_ACK_NUM_V 0x7 +#define UHCI_ACK_NUM_S 0 + +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2C) +/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_RX_HEAD 0xFFFFFFFF +#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S)) +#define UHCI_RX_HEAD_V 0xFFFFFFFF +#define UHCI_RX_HEAD_S 0 + +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30) +/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_V 0x1 +#define UHCI_ALWAYS_SEND_EN_S 7 +/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: a*/ +#define UHCI_ALWAYS_SEND_NUM 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S)) +#define UHCI_ALWAYS_SEND_NUM_V 0x7 +#define UHCI_ALWAYS_SEND_NUM_S 4 +/* UHCI_SINGLE_SEND_EN : R/W/SC ;bitpos:[3] ;default: 1'b0 ; */ +/*description: a*/ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (BIT(3)) +#define UHCI_SINGLE_SEND_EN_V 0x1 +#define UHCI_SINGLE_SEND_EN_S 3 +/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: a*/ +#define UHCI_SINGLE_SEND_NUM 0x00000007 +#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S)) +#define UHCI_SINGLE_SEND_NUM_V 0x7 +#define UHCI_SINGLE_SEND_NUM_S 0 + +#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34) +/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S)) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_S 0 + +#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38) +/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S)) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_S 0 + +#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3C) +/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S)) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_S 0 + +#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40) +/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S)) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_S 0 + +#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44) +/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S)) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_S 0 + +#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48) +/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S)) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_S 0 + +#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4C) +/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S)) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_S 0 + +#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50) +/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S)) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_S 0 + +#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54) +/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S)) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_S 0 + +#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58) +/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S)) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_S 0 + +#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5C) +/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S)) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_S 0 + +#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60) +/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S)) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_S 0 + +#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64) +/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S)) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_S 0 + +#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68) +/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: a*/ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S)) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_S 0 + +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6C) +/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ +/*description: a*/ +#define UHCI_SEPER_ESC_CHAR1 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S)) +#define UHCI_SEPER_ESC_CHAR1_V 0xFF +#define UHCI_SEPER_ESC_CHAR1_S 16 +/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: a*/ +#define UHCI_SEPER_ESC_CHAR0 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S)) +#define UHCI_SEPER_ESC_CHAR0_V 0xFF +#define UHCI_SEPER_ESC_CHAR0_S 8 +/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ +/*description: a*/ +#define UHCI_SEPER_CHAR 0x000000FF +#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S)) +#define UHCI_SEPER_CHAR_V 0xFF +#define UHCI_SEPER_CHAR_S 0 + +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70) +/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ +/*description: a*/ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S)) +#define UHCI_ESC_SEQ0_CHAR1_V 0xFF +#define UHCI_ESC_SEQ0_CHAR1_S 16 +/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: a*/ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S)) +#define UHCI_ESC_SEQ0_CHAR0_V 0xFF +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ +/*description: a*/ +#define UHCI_ESC_SEQ0 0x000000FF +#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S)) +#define UHCI_ESC_SEQ0_V 0xFF +#define UHCI_ESC_SEQ0_S 0 + +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74) +/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ +/*description: a*/ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S)) +#define UHCI_ESC_SEQ1_CHAR1_V 0xFF +#define UHCI_ESC_SEQ1_CHAR1_S 16 +/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: a*/ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S)) +#define UHCI_ESC_SEQ1_CHAR0_V 0xFF +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ +/*description: a*/ +#define UHCI_ESC_SEQ1 0x000000FF +#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S)) +#define UHCI_ESC_SEQ1_V 0xFF +#define UHCI_ESC_SEQ1_S 0 + +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78) +/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ +/*description: a*/ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S)) +#define UHCI_ESC_SEQ2_CHAR1_V 0xFF +#define UHCI_ESC_SEQ2_CHAR1_S 16 +/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: a*/ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S)) +#define UHCI_ESC_SEQ2_CHAR0_V 0xFF +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ +/*description: a*/ +#define UHCI_ESC_SEQ2 0x000000FF +#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S)) +#define UHCI_ESC_SEQ2_V 0xFF +#define UHCI_ESC_SEQ2_S 0 + +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7C) +/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ +/*description: a*/ +#define UHCI_PKT_THRS 0x00001FFF +#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S)) +#define UHCI_PKT_THRS_V 0x1FFF +#define UHCI_PKT_THRS_S 0 + +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80) +/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007170 ; */ +/*description: a*/ +#define UHCI_DATE 0xFFFFFFFF +#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S)) +#define UHCI_DATE_V 0xFFFFFFFF +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_UHCI_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/uhci_struct.h b/components/soc/esp32h2/include/soc/uhci_struct.h new file mode 100644 index 0000000000..a89c4d0126 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uhci_struct.h @@ -0,0 +1,230 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_STRUCT_H_ +#define _SOC_UHCI_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/ + uint32_t rx_rst: 1; /*Write 1 then write 0 to this bit to reset encode state machine.*/ + uint32_t uart0_ce: 1; /*Set this bit to link up HCI and UART0.*/ + uint32_t uart1_ce: 1; /*Set this bit to link up HCI and UART1.*/ + uint32_t reserved4: 1; + uint32_t seper_en: 1; /*Set this bit to separate the data frame using a special char.*/ + uint32_t head_en: 1; /*Set this bit to encode the data packet with a formatting header.*/ + uint32_t crc_rec_en: 1; /*Set this bit to enable UHCI to receive the 16 bit CRC.*/ + uint32_t uart_idle_eof_en: 1; /*If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.*/ + uint32_t len_eof_en: 1; /*If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/ + uint32_t encode_crc_en: 1; /*Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.*/ + uint32_t clk_en: 1; /*1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.*/ + uint32_t uart_rx_brk_eof_en: 1; /*If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rx_start: 1; /*a*/ + uint32_t tx_start: 1; /*a*/ + uint32_t rx_hung: 1; /*a*/ + uint32_t tx_hung: 1; /*a*/ + uint32_t send_s_q: 1; /*a*/ + uint32_t send_a_q: 1; /*a*/ + uint32_t outlink_eof_err: 1; /*This is the interrupt raw bit. Triggered when there are some errors in EOF in the*/ + uint32_t app_ctrl0: 1; /*Soft control int raw bit.*/ + uint32_t app_ctrl1: 1; /*Soft control int raw bit.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_start: 1; /*a*/ + uint32_t tx_start: 1; /*a*/ + uint32_t rx_hung: 1; /*a*/ + uint32_t tx_hung: 1; /*a*/ + uint32_t send_s_q: 1; /*a*/ + uint32_t send_a_q: 1; /*a*/ + uint32_t outlink_eof_err: 1; /*a*/ + uint32_t app_ctrl0: 1; /*a*/ + uint32_t app_ctrl1: 1; /*a*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_start: 1; /*a*/ + uint32_t tx_start: 1; /*a*/ + uint32_t rx_hung: 1; /*a*/ + uint32_t tx_hung: 1; /*a*/ + uint32_t send_s_q: 1; /*a*/ + uint32_t send_a_q: 1; /*a*/ + uint32_t outlink_eof_err: 1; /*a*/ + uint32_t app_ctrl0: 1; /*a*/ + uint32_t app_ctrl1: 1; /*a*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_start: 1; /*a*/ + uint32_t tx_start: 1; /*a*/ + uint32_t rx_hung: 1; /*a*/ + uint32_t tx_hung: 1; /*a*/ + uint32_t send_s_q: 1; /*a*/ + uint32_t send_a_q: 1; /*a*/ + uint32_t outlink_eof_err: 1; /*a*/ + uint32_t app_ctrl0: 1; /*a*/ + uint32_t app_ctrl1: 1; /*a*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t check_sum_en: 1; /*a*/ + uint32_t check_seq_en: 1; /*a*/ + uint32_t crc_disable: 1; /*a*/ + uint32_t save_head: 1; /*a*/ + uint32_t tx_check_sum_re: 1; /*a*/ + uint32_t tx_ack_num_re: 1; /*a*/ + uint32_t reserved6: 1; + uint32_t wait_sw_start: 1; /*a*/ + uint32_t sw_start: 1; /*a*/ + uint32_t reserved9: 12; + uint32_t reserved21: 11; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t rx_err_cause: 3; /*a*/ + uint32_t decode_state: 3; /*a*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } state0; + union { + struct { + uint32_t encode_state: 3; /*a*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } state1; + union { + struct { + uint32_t tx_c0_esc_en: 1; /*a*/ + uint32_t tx_db_esc_en: 1; /*a*/ + uint32_t tx_11_esc_en: 1; /*a*/ + uint32_t tx_13_esc_en: 1; /*a*/ + uint32_t rx_c0_esc_en: 1; /*a*/ + uint32_t rx_db_esc_en: 1; /*a*/ + uint32_t rx_11_esc_en: 1; /*a*/ + uint32_t rx_13_esc_en: 1; /*a*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } escape_conf; + union { + struct { + uint32_t txfifo_timeout: 8; /*a*/ + uint32_t txfifo_timeout_shift: 3; /*a*/ + uint32_t txfifo_timeout_ena: 1; /*a*/ + uint32_t rxfifo_timeout: 8; /*a*/ + uint32_t rxfifo_timeout_shift: 3; /*a*/ + uint32_t rxfifo_timeout_ena: 1; /*a*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } hung_conf; + union { + struct { + uint32_t ack_num: 3; + uint32_t ack_num_load: 1; /*a*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } ack_num; + uint32_t rx_head; /*a*/ + union { + struct { + uint32_t single_send_num: 3; /*a*/ + uint32_t single_send_en: 1; /*a*/ + uint32_t always_send_num: 3; /*a*/ + uint32_t always_send_en: 1; /*a*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } quick_sent; + struct { + uint32_t w_data[2]; /*a*/ + } q_data[7]; + union { + struct { + uint32_t seper_char: 8; /*a*/ + uint32_t seper_esc_char0: 8; /*a*/ + uint32_t seper_esc_char1: 8; /*a*/ + uint32_t reserved24: 8; /*a*/ + }; + uint32_t val; + } esc_conf0; + union { + struct { + uint32_t seq0: 8; /*a*/ + uint32_t seq0_char0: 8; /*a*/ + uint32_t seq0_char1: 8; /*a*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf1; + union { + struct { + uint32_t seq1: 8; /*a*/ + uint32_t seq1_char0: 8; /*a*/ + uint32_t seq1_char1: 8; /*a*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf2; + union { + struct { + uint32_t seq2: 8; /*a*/ + uint32_t seq2_char0: 8; /*a*/ + uint32_t seq2_char1: 8; /*a*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf3; + union { + struct { + uint32_t thrs: 13; /*a*/ + uint32_t reserved13:19; + }; + uint32_t val; + } pkt_thres; + uint32_t date; /*a*/ +} uhci_dev_t; +extern uhci_dev_t UHCI0; +extern uhci_dev_t UHCI1; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_UHCI_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..432fe1aa05 --- /dev/null +++ b/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,993 @@ + +/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** Configuration Registers */ + +/** USB_SERIAL_JTAG_EP1_REG register + * USB_SERIAL_JTAG_EP1_REG. + */ +#define USB_SERIAL_JTAG_EP1_REG (SOC_DPORT_USB_BASE + 0x0) +/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. + * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write + * data (up to 64 bytes) into UART Tx FIFO. When + * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check + * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to + * know how many data is received, then read that amount of data from UART + * Rx + * FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FF +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_CONF0_REG register + * USB_SERIAL_JTAG_CONF0_REG. + */ +#define USB_SERIAL_JTAG_CONF0_REG (SOC_DPORT_USB_BASE + 0x18) +/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external + * PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001 +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- + * exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001 +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- + * exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001 +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0; + * Control single-end input high threshold. 1.76V to 2V, step + * 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003 +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003 +#define USB_SERIAL_JTAG_VREFL_S 3 +/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0; + * Control single-end input low threshold. 0.8V to 1.04V, step + * 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003 +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003 +#define USB_SERIAL_JTAG_VREFH_S 5 +/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input + * threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001 +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup + * pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001 +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull + * up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001 +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull + * down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001 +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull + * up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001 +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull + * down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001 +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up + * value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001 +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad + * function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001 +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 + +/** USB_SERIAL_JTAG_TEST_REG register + * USB_SERIAL_JTAG_TEST_REG. + */ +#define USB_SERIAL_JTAG_TEST_REG (SOC_DPORT_USB_BASE + 0x1c) +/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB + * pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001 +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in + * test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001 +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in + * test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001 +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in + * test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001 +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * USB_SERIAL_JTAG_MISC_CONF_REG. + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (SOC_DPORT_USB_BASE + 0x44) +/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when + * application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001 +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * USB_SERIAL_JTAG_MEM_CONF_REG. + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (SOC_DPORT_USB_BASE + 0x48) +/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb + * memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001 +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb + * memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001 +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + + +/** Status Registers */ + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * USB_SERIAL_JTAG_EP1_CONF_REG. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (SOC_DPORT_USB_BASE + 0x4) +/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + * This bit then stays 0 until data in UART Tx FIFO is read by the USB + * Host. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001 +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and data can be written into + * in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the + * data is sent to the USB + * Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx + * FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * USB_SERIAL_JTAG_JFIFO_ST_REG. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (SOC_DPORT_USB_BASE + 0x20) +/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0; + * JTAG in fifo + * counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003 +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003 +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is + * empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001 +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is + * full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001 +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0; + * JTAT out fifo + * counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003 +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003 +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is + * empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is + * full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in + * fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001 +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out + * fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * USB_SERIAL_JTAG_FRAM_NUM_REG. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (SOC_DPORT_USB_BASE + 0x24) +/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0; + * Frame index of received SOF + * frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FF +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * USB_SERIAL_JTAG_IN_EP0_ST_REG. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x28) +/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1; + * State of IN Endpoint + * 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003 +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of IN endpoint + * 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of IN endpoint + * 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * USB_SERIAL_JTAG_IN_EP1_ST_REG. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x2c) +/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1; + * State of IN Endpoint + * 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003 +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of IN endpoint + * 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of IN endpoint + * 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * USB_SERIAL_JTAG_IN_EP2_ST_REG. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x30) +/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1; + * State of IN Endpoint + * 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003 +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of IN endpoint + * 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of IN endpoint + * 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * USB_SERIAL_JTAG_IN_EP3_ST_REG. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (SOC_DPORT_USB_BASE + 0x34) +/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1; + * State of IN Endpoint + * 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003 +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of IN endpoint + * 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of IN endpoint + * 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * USB_SERIAL_JTAG_OUT_EP0_ST_REG. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x38) +/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0; + * State of OUT Endpoint + * 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003 +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of OUT endpoint 0. When + * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are + * USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT + * EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of OUT endpoint + * 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * USB_SERIAL_JTAG_OUT_EP1_ST_REG. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x3c) +/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0; + * State of OUT Endpoint + * 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003 +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of OUT endpoint 1. When + * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are + * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT + * EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of OUT endpoint + * 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is + * received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * USB_SERIAL_JTAG_OUT_EP2_ST_REG. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x40) +/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0; + * State of OUT Endpoint + * 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003 +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003 +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0; + * Write data address of OUT endpoint 2. When + * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are + * USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT + * EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0; + * Read data address of OUT endpoint + * 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007F +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + + +/** Interrupt Registers */ + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * USB_SERIAL_JTAG_INT_RAW_REG. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (SOC_DPORT_USB_BASE + 0x8) +/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when a flush command is + * received for IN endpoint 2 of + * JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when a SOF frame is + * received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the Serial Port OUT + * Endpoint received one + * packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when the Serial Port IN + * Endpoint is + * empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when a PID error is + * detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when a CRC5 error is + * detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when a CRC16 error is + * detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when a bit stuffing error is + * detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when an IN token for IN + * endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when a USB bus reset is + * detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received + * packet with zero + * payload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received + * packet with zero + * payload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * USB_SERIAL_JTAG_INT_ST_REG. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (SOC_DPORT_USB_BASE + 0xc) +/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the + * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the + * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the + * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the + * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * USB_SERIAL_JTAG_INT_ENA_REG. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (SOC_DPORT_USB_BASE + 0x10) +/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the + * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the + * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the + * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the + * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * USB_SERIAL_JTAG_INT_CLR_REG. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (SOC_DPORT_USB_BASE + 0x14) +/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001 +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 + + +/** Version Registers */ + +/** USB_SERIAL_JTAG_DATE_REG register + * USB_SERIAL_JTAG_DATE_REG. + */ +#define USB_SERIAL_JTAG_DATE_REG (SOC_DPORT_USB_BASE + 0x80) +/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872; + * register + * version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF +#define USB_SERIAL_JTAG_DATE_S 0 + + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..72c1005d30 --- /dev/null +++ b/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,263 @@ +// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_ +#define _SOC_USB_SERIAL_JTAG_STRUCT_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +typedef volatile struct { + union { + struct { + uint32_t rdwr_byte : 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } ep1; + union { + struct { + uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done. This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/ + uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/ + uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } ep1_conf; + union { + struct { + uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/ + uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when a SOF frame is received.*/ + uint32_t serial_out_recv_pkt_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/ + uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/ + uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when a PID error is detected.*/ + uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/ + uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/ + uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/ + uint32_t in_token_rec_in_ep1_int_raw : 1; /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/ + uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/ + uint32_t out_ep1_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/ + uint32_t out_ep2_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/ + uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/ + uint32_t serial_out_recv_pkt_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/ + uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/ + uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/ + uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/ + uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/ + uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/ + uint32_t in_token_rec_in_ep1_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ + uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/ + uint32_t out_ep1_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ + uint32_t out_ep2_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/ + uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/ + uint32_t serial_out_recv_pkt_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/ + uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/ + uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/ + uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/ + uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/ + uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/ + uint32_t in_token_rec_in_ep1_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ + uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/ + uint32_t out_ep1_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ + uint32_t out_ep2_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/ + uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/ + uint32_t serial_out_recv_pkt_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/ + uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/ + uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/ + uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/ + uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/ + uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/ + uint32_t in_token_rec_in_ep1_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/ + uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/ + uint32_t out_ep1_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ + uint32_t out_ep2_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t phy_sel : 1; /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/ + uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/ + uint32_t exchg_pins : 1; /*USB D+ D- exchange*/ + uint32_t vrefh : 2; /*Control single-end input high threshold. 1.76V to 2V, step 80mV */ + uint32_t vrefl : 2; /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/ + uint32_t vref_override : 1; /*Enable software control input threshold*/ + uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/ + uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/ + uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/ + uint32_t dm_pullup : 1; /*Control USB D- pull up.*/ + uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/ + uint32_t pullup_value : 1; /*Control pull up value.*/ + uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/ + uint32_t reserved15 : 17; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t test_enable : 1; /*Enable test of the USB pad*/ + uint32_t test_usb_oe : 1; /*USB pad oen in test*/ + uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/ + uint32_t test_tx_dm : 1; /*USB D- tx value in test*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } test; + union { + struct { + uint32_t in_fifo_cnt : 2; /*JTAG in fifo counter.*/ + uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/ + uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/ + uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/ + uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/ + uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/ + uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/ + uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/ + uint32_t reserved10 : 22; + }; + uint32_t val; + } jfifo_st; + union { + struct { + uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/ + uint32_t reserved11 : 21; + }; + uint32_t val; + } fram_num; + union { + struct { + uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/ + uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/ + uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } in_ep0_st; + union { + struct { + uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/ + uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/ + uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } in_ep1_st; + union { + struct { + uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/ + uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/ + uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } in_ep2_st; + union { + struct { + uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/ + uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/ + uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } in_ep3_st; + union { + struct { + uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/ + uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ + uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } out_ep0_st; + union { + struct { + uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/ + uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/ + uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/ + uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/ + uint32_t reserved23 : 9; /*reserved*/ + }; + uint32_t val; + } out_ep1_st; + union { + struct { + uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/ + uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/ + uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/ + uint32_t reserved16 : 16; /*reserved*/ + }; + uint32_t val; + } out_ep2_st; + union { + struct { + uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/ + uint32_t reserved1 : 31; + }; + uint32_t val; + } misc_conf; + union { + struct { + uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/ + uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/ + uint32_t reserved2 : 30; + }; + uint32_t val; + } mem_conf; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t date; +} usb_serial_jtag_dev_t; +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/wdev_reg.h b/components/soc/esp32h2/include/soc/wdev_reg.h new file mode 100644 index 0000000000..6992254b26 --- /dev/null +++ b/components/soc/esp32h2/include/soc/wdev_reg.h @@ -0,0 +1,20 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc.h" + +/* Hardware random number generator register */ +#define WDEV_RND_REG 0x600260b0 diff --git a/components/soc/esp32h2/interrupts.c b/components/soc/esp32h2/interrupts.c new file mode 100644 index 0000000000..93790cc60c --- /dev/null +++ b/components/soc/esp32h2/interrupts.c @@ -0,0 +1,80 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/interrupts.h" + +const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { + [0] = "WIFI_MAC", + [1] = "WIFI_NMI", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "RWBT", + [8] = "RWBLE", + [9] = "RWBT_NMI", + [10] = "RWBLE_NMI", + [11] = "I2C", + [12] = "SLC0", + [13] = "SLC1", + [14] = "APB_CTRL", + [15] = "UHCI0", + [16] = "GPIO", + [17] = "GPIO_NMI", + [18] = "SPI1", + [19] = "SPI2", + [20] = "I2S1", + [21] = "UART0", + [22] = "UART1", + [23] = "LEDC", + [24] = "EFUSE", + [25] = "CAN", + [26] = "USB", + [27] = "RTC_CORE", + [28] = "RMT", + [29] = "I2C_EXT0", + [30] = "TIMER1", + [31] = "TIMER2", + [32] = "TG0_T0_LEVEL", + [33] = "TG0_WDT_LEVEL", + [34] = "TG1_T0_LEVEL", + [35] = "TG1_WDT_LEVEL", + [36] = "CACHE_IA", + [37] = "SYSTIMER_TARGET0_EDGE", + [38] = "SYSTIMER_TARGET1_EDGE", + [39] = "SYSTIMER_TARGET2_EDGE", + [40] = "SPI_MEM_REJECT_CACHE", + [41] = "ICACHE_PRELOAD0", + [42] = "ICACHE_SYNC0", + [43] = "APB_ADC", + [44] = "DMA_CH0", + [45] = "DMA_CH1", + [46] = "DMA_CH2", + [47] = "RSA", + [48] = "AES", + [49] = "SHA", + [50] = "ETS_FROM_CPU_INTR0", + [51] = "ETS_FROM_CPU_INTR1", + [52] = "ETS_FROM_CPU_INTR2", + [53] = "ETS_FROM_CPU_INTR3", + [54] = "ETS_ASSIST_DEBUG", + [55] = "ETS_DMA_APBPERI_PMS", + [56] = "ETS_CORE0_IRAM0_PMS", + [57] = "ETS_CORE0_DRAM0_PMS", + [58] = "ETS_CORE0_PIF_PMS", + [59] = "ETS_CORE0_PIF_PMS_SIZE", + [60] = "ETS_BAK_PMS_VIOLATE", + [61] = "ETS_CACHE_CORE0_ACS", +}; diff --git a/components/soc/esp32h2/ledc_periph.c b/components/soc/esp32h2/ledc_periph.c new file mode 100644 index 0000000000..13f87e5c86 --- /dev/null +++ b/components/soc/esp32h2/ledc_periph.c @@ -0,0 +1,25 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; diff --git a/components/soc/esp32h2/rmt_periph.c b/components/soc/esp32h2/rmt_periph.c new file mode 100644 index 0000000000..1556cf92f4 --- /dev/null +++ b/components/soc/esp32h2/rmt_periph.c @@ -0,0 +1,39 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/rmt_periph.h" +#include "soc/gpio_sig_map.h" + +const rmt_signal_conn_t rmt_periph_signals = { + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = -1 + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = -1 + }, + [2] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN0_IDX + }, + [3] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN1_IDX + }, + } +}; diff --git a/components/soc/esp32h2/sigmadelta_periph.c b/components/soc/esp32h2/sigmadelta_periph.c new file mode 100644 index 0000000000..5c4c8169cb --- /dev/null +++ b/components/soc/esp32h2/sigmadelta_periph.c @@ -0,0 +1,33 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/sigmadelta_periph.h" +#include "soc/gpio_sig_map.h" + +const sigma_delta_signal_conn_t sigma_delta_periph_signals = { + .channels = { + [0] = { + GPIO_SD0_OUT_IDX + }, + [1] = { + GPIO_SD1_OUT_IDX + }, + [2] = { + GPIO_SD2_OUT_IDX + }, + [3] = { + GPIO_SD3_OUT_IDX + } + } +}; diff --git a/components/soc/esp32h2/soc_memory_layout.c b/components/soc/esp32h2/soc_memory_layout.c new file mode 100644 index 0000000000..ba0ae819cb --- /dev/null +++ b/components/soc/esp32h2/soc_memory_layout.c @@ -0,0 +1,99 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef BOOTLOADER_BUILD + +#include +#include +#include "esp_attr.h" +#include "sdkconfig.h" +#include "soc/soc.h" +#include "soc/soc_memory_layout.h" +#include "esp_heap_caps.h" + +/** + * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. + * Each type of memory map consists of one or more regions in the address space. + * Each type contains an array of prioritized capabilities. + * Types with later entries are only taken if earlier ones can't fulfill the memory request. + * + * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. + * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. + * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. + * - Most other malloc caps only fit in one region anyway. + * + */ +const soc_memory_type_desc_t soc_memory_types[] = { + // Type 0: DRAM + { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, + // Type 1: DRAM used for startup stacks + { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + // Type 2: DRAM which has an alias on the I-port + { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, + // Type 3: IRAM + { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, + // Type 4: RTCRAM + { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, +}; + +#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define SOC_MEMORY_TYPE_DEFAULT 0 +#else +#define SOC_MEMORY_TYPE_DEFAULT 2 +#endif + +const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); + +/** + * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. + * + * @note Because of requirements in the coalescing code which merges adjacent regions, + * this list should always be sorted from low to high by start address. + * + */ +const soc_memory_region_t soc_memory_regions[] = { + { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory + { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory + { 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory +#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP + { 0x50000000, 0x2000, 4, 0}, //Fast RTC memory +#endif +}; + +const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); + + +extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; + +/** + * Reserved memory regions. + * These are removed from the soc_memory_regions array when heaps are created. + * + */ + +// Static data region. DRAM used by data+bss and possibly rodata +SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); + +// Target has a big D/IRAM region, the part used by code is reserved +// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address +#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); + +#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP +/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW + region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. +*/ +SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); +#endif + +#endif // BOOTLOADER_BUILD diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c new file mode 100644 index 0000000000..a7c656288b --- /dev/null +++ b/components/soc/esp32h2/spi_periph.c @@ -0,0 +1,71 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/spi_periph.h" +#include "stddef.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + { + .spiclk_out = SPICLK_OUT_MUX_IDX, + .spiclk_in = 0,/* SPI clock is not an input signal*/ + .spid_out = SPID_OUT_IDX, + .spiq_out = SPIQ_OUT_IDX, + .spiwp_out = SPIWP_OUT_IDX, + .spihd_out = SPIHD_OUT_IDX, + .spid_in = SPID_IN_IDX, + .spiq_in = SPIQ_IN_IDX, + .spiwp_in = SPIWP_IN_IDX, + .spihd_in = SPIHD_IN_IDX, + .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ + .spics_in = 0,/* SPI cs is not an input signal*/ + .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, + .irq = ETS_SPI1_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI_MODULE, + .hw = (spi_dev_t *) &SPIMEM1, + .func = SPI_FUNC_NUM, + }, { + .spiclk_out = FSPICLK_OUT_IDX, + .spiclk_in = FSPICLK_IN_IDX, + .spid_out = FSPID_OUT_IDX, + .spiq_out = FSPIQ_OUT_IDX, + .spiwp_out = FSPIWP_OUT_IDX, + .spihd_out = FSPIHD_OUT_IDX, + .spid_in = FSPID_IN_IDX, + .spiq_in = FSPIQ_IN_IDX, + .spiwp_in = FSPIWP_IN_IDX, + .spihd_in = FSPIHD_IN_IDX, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX}, + .spics_in = FSPICS0_IN_IDX, + .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, + .irq = ETS_SPI2_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI2_MODULE, + .hw = &GPSPI2, + .func = SPI2_FUNC_NUM, + } +}; diff --git a/components/soc/esp32h2/timer_periph.c b/components/soc/esp32h2/timer_periph.c new file mode 100644 index 0000000000..661f19514b --- /dev/null +++ b/components/soc/esp32h2/timer_periph.c @@ -0,0 +1,28 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/timer_periph.h" + +const timer_group_signal_conn_t timer_group_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_TIMG0_MODULE, + .t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE + }, + [1] = { + .module = PERIPH_TIMG1_MODULE, + .t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE, + } + } +}; diff --git a/components/soc/esp32h2/uart_periph.c b/components/soc/esp32h2/uart_periph.c new file mode 100644 index 0000000000..999eb69fd8 --- /dev/null +++ b/components/soc/esp32h2/uart_periph.c @@ -0,0 +1,37 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/uart_periph.h" + +/* + Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { + { + .tx_sig = U0TXD_OUT_IDX, + .rx_sig = U0RXD_IN_IDX, + .rts_sig = U0RTS_OUT_IDX, + .cts_sig = U0CTS_IN_IDX, + .irq = ETS_UART0_INTR_SOURCE, + .module = PERIPH_UART0_MODULE, + }, + { + .tx_sig = U1TXD_OUT_IDX, + .rx_sig = U1RXD_IN_IDX, + .rts_sig = U1RTS_OUT_IDX, + .cts_sig = U1CTS_IN_IDX, + .irq = ETS_UART1_INTR_SOURCE, + .module = PERIPH_UART1_MODULE, + } +};