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fix(soc): Fix ESP32-C5's rom mask high and subsystem high memory addresses

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harshal.patil 2024-05-31 21:59:54 +05:30
parent b5762b732b
commit 980ac9bcf5
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GPG Key ID: 5B5EC97C35B9A2E5
2 changed files with 10 additions and 10 deletions
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10
components/esp_hw_support/port/esp32c5/cpu_region_protect.c
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@ -31,10 +31,10 @@ static void esp_cpu_configure_invalid_regions(void)
__attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
// 1. Gap at bottom of address space
PMA_ENTRY_SET_TOR(0, SOC_DEBUG_LOW, PMA_TOR | PMA_NONE);
PMA_ENTRY_SET_TOR(0, SOC_CPU_SUBSYSTEM_LOW, PMA_TOR | PMA_NONE);
// 2. Gap between debug region & IROM
PMA_ENTRY_SET_TOR(1, SOC_DEBUG_HIGH, PMA_NONE);
PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
// 3. Gap between ROM & RAM
@ -66,7 +66,7 @@ void esp_cpu_configure_region_protection(void)
// Configure just the area around 0x0 for now so that we at least get exceptions for
// writes/reads to NULL pointers, as well as code that relies on writes to 0x0
// to abort/assert
PMA_ENTRY_SET_NAPOT(1, 0, SOC_DEBUG_LOW, PMA_NAPOT | PMA_EN);
PMA_ENTRY_SET_NAPOT(1, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_EN);
return;
/* Notes on implementation:
@ -120,9 +120,9 @@ void esp_cpu_configure_region_protection(void)
//
// 1. Debug region
const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_DEBUG_LOW, SOC_DEBUG_HIGH);
const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
_Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region");
_Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU debug region");
// 2.1 I-ROM
PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);

10
components/soc/esp32c5/include/soc/soc.h
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@ -154,9 +154,9 @@
#define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_DROM_HIGH SOC_IROM_HIGH
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40040000
#define SOC_IROM_MASK_HIGH 0x40050000
#define SOC_DROM_MASK_LOW 0x40000000
#define SOC_DROM_MASK_HIGH 0x40040000
#define SOC_DROM_MASK_HIGH 0x40050000
#define SOC_IRAM_LOW 0x40800000
#define SOC_IRAM_HIGH 0x40860000
#define SOC_DRAM_LOW 0x40800000
@ -198,9 +198,9 @@
#define SOC_PERIPHERAL_LOW 0x60000000
#define SOC_PERIPHERAL_HIGH 0x60100000
// Debug region, not used by software
#define SOC_DEBUG_LOW 0x20000000
#define SOC_DEBUG_HIGH 0x28000000
// CPU sub-system region, contains interrupt config registers
#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4085e9a0