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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
RTC WDT: Use target name instead of caps for rtc wdt
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parent
dbba26643f
commit
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@ -22,7 +22,7 @@ if(NOT BOOTLOADER_BUILD)
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# [refactor-todo]: requires "driver" for GPIO and RTC (by sleep_gpio and sleep_modes)
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list(APPEND priv_requires driver)
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if(CONFIG_SOC_RTC_WDT_SUPPORTED)
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if(CONFIG_IDF_TARGET_ESP32 OR CONFIG_IDF_TARGET_ESP32S2)
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list(APPEND srcs "rtc_wdt.c")
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endif()
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@ -45,7 +45,7 @@ without description where were CPUs when it happened.
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#include "soc/rtc_periph.h"
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#include "esp_err.h"
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#if SOC_RTC_WDT_SUPPORTED
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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#ifdef __cplusplus
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extern "C"
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@ -191,4 +191,4 @@ bool rtc_wdt_is_on(void);
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}
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#endif
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#endif // SOC_CAPS_RTC_WDT
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#endif // CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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@ -9,7 +9,7 @@ entries:
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rtc_pm (noflash_text)
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rtc_sleep (noflash_text)
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rtc_time (noflash_text)
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if SOC_RTC_WDT_SUPPORTED = y:
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if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:
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rtc_wdt (noflash_text)
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if IDF_TARGET_ESP32S3 = y:
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if SPIRAM_MODE_QUAD = y:
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@ -9,7 +9,7 @@
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#include "soc/rtc.h"
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#include "hal/efuse_ll.h"
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#if SOC_RTC_WDT_SUPPORTED
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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bool rtc_wdt_get_protect_status(void)
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{
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@ -147,4 +147,4 @@ bool rtc_wdt_is_on(void)
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return (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN) != 0) || (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN) != 0);
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}
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#endif // SOC_RTC_WDT_SUPPORTED
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#endif // CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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@ -83,10 +83,6 @@ config SOC_RTC_SLOW_MEM_SUPPORTED
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bool
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default y
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config SOC_RTC_WDT_SUPPORTED
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bool
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default y
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config SOC_I2S_SUPPORTED
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bool
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default y
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@ -80,7 +80,6 @@
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_RTC_SLOW_MEM_SUPPORTED 1
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#define SOC_RTC_WDT_SUPPORTED 1
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#define SOC_I2S_SUPPORTED 1
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#define SOC_RMT_SUPPORTED 1
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#define SOC_SIGMADELTA_SUPPORTED 1
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@ -107,10 +107,6 @@ config SOC_RTC_SLOW_MEM_SUPPORTED
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bool
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default y
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config SOC_RTC_WDT_SUPPORTED
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bool
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default y
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config SOC_PSRAM_DMA_CAPABLE
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bool
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default y
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@ -65,7 +65,6 @@
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#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_RTC_SLOW_MEM_SUPPORTED 1
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#define SOC_RTC_WDT_SUPPORTED 1
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#define SOC_PSRAM_DMA_CAPABLE 1
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#define SOC_XT_WDT_SUPPORTED 1
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#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
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