diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c index a50d2c3404..2208aed44f 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -41,6 +41,7 @@ #include "hal/cache_hal.h" #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" +#include "modem/modem_lpcon_reg.h" static const char *TAG = "boot.esp32c6"; @@ -225,13 +226,9 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { - // TODO: IDF-5990 copied from C3, need update - // This check is always included in the bootloader so it can - // print the minimum revision error message later in the boot - if (efuse_hal_get_minor_chip_version() < 3) { - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1); - REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12); - } + // TODO: IDF-5990 need update, enable i2c mst clk by force on temporarily + SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); } static inline void bootloader_ana_reset_config(void) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 84463a9a61..0fccbc80ef 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -18,9 +18,14 @@ else() "patches/esp_rom_sys.c" "patches/esp_rom_uart.c" "patches/esp_rom_spiflash.c" - "patches/esp_rom_regi2c.c" "patches/esp_rom_efuse.c") + +# Override regi2c implementation in ROM +if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/patches/esp_rom_regi2c_${target}.c") + list(APPEND sources "patches/esp_rom_regi2c_${target}.c") +endif() + if(CONFIG_HEAP_TLSF_USE_ROM_IMPL AND CONFIG_ESP_ROM_TLSF_CHECK_PATCH) # This file shall be included in the build if TLSF in ROM is activated list(APPEND sources "patches/esp_rom_tlsf.c") diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld index 1805074f0a..04f47bdde3 100644 --- a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld @@ -53,8 +53,3 @@ PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld index 6dba9fd819..94abe7c758 100644 --- a/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld @@ -128,11 +128,7 @@ rom_get_i2c_mst0_mask = 0x400012ac; rom_get_i2c_hostid = 0x400012b0; rom_chip_i2c_readReg_org = 0x400012b4; rom_chip_i2c_readReg = 0x400012b8; -rom_i2c_readReg = 0x400012bc; rom_chip_i2c_writeReg = 0x400012c0; -rom_i2c_writeReg = 0x400012c4; -rom_i2c_readReg_Mask = 0x400012c8; -rom_i2c_writeReg_Mask = 0x400012cc; rom_set_txcap_reg = 0x400012d0; i2c_paral_set_mst0 = 0x400012d4; i2c_paral_set_read = 0x400012d8; diff --git a/components/esp_rom/linker.lf b/components/esp_rom/linker.lf index 38af2aecdc..e8f8d2c0f1 100644 --- a/components/esp_rom/linker.lf +++ b/components/esp_rom/linker.lf @@ -2,7 +2,6 @@ archive: libesp_rom.a entries: esp_rom_spiflash (noflash) - esp_rom_regi2c (noflash) if HEAP_TLSF_USE_ROM_IMPL = y && ESP_ROM_TLSF_CHECK_PATCH = y: esp_rom_tlsf (noflash) if SOC_SYSTIMER_SUPPORTED = y: diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c6.c b/components/esp_rom/patches/esp_rom_regi2c_esp32c6.c new file mode 100644 index 0000000000..4892918a82 --- /dev/null +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32c6.c @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "soc/lp_i2c_ana_mst_reg.h" +#include "modem/modem_lpcon_reg.h" +/** + * BB - 0x67 - BIT0 + * TXRF - 0x6B - BIT1 + * SDM - 0x63 - BIT2 + * PLL - 0x62 - BIT3 + * BIAS - 0x6A - BIT4 + * BBPLL - 0x66 - BIT5 + * ULP - 0x61 - BIT6 + * SAR - 0x69 - BIT7 + * PMU - 0x6d - BIT8 +*/ +#define REGI2C_ULP_CAL_DEVICE_EN (BIT(6)) +#define REGI2C_SAR_I2C_DEVICE_EN (BIT(7)) +#define REGI2C_BBPLL_DEVICE_EN (BIT(5)) +#define REGI2C_BIAS_DEVICE_EN (BIT(4)) +#define REGI2C_DIG_REG_DEVICE_EN (BIT(8)) + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ + +#define REGI2C_BBPLL (0x66) +#define REGI2C_BBPLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_DIG_REG (0x6d) +#define REGI2C_DIG_REG_HOSTID 0 + +#define REGI2C_ULP_CAL (0x61) +#define REGI2C_ULP_CAL_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 + +/* SLAVE END */ + +#define REGI2C_RTC_MAGIC_DEFAULT (0x1C610) + +static IRAM_ATTR void regi2c_enable_block(uint8_t block) +{ + REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + REG_SET_BIT(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN); + + /* Before config I2C register, enable corresponding slave. */ + switch (block) { + case REGI2C_BBPLL : + REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN); + break; + case REGI2C_BIAS : + REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN); + break; + case REGI2C_DIG_REG: + REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN); + break; + case REGI2C_ULP_CAL: + REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN); + break; + case REGI2C_SAR_I2C: + REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN); + break; + default: + return; + } +} + +static IRAM_ATTR void regi2c_disable_block(uint8_t block) +{ + switch (block) { + case REGI2C_BBPLL : + REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN); + break; + case REGI2C_BIAS : + REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN); + break; + case REGI2C_DIG_REG: + REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN); + break; + case REGI2C_ULP_CAL: + REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN); + break; + case REGI2C_SAR_I2C: + REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN); + break; + default: + return; + } + + REG_CLR_BIT(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN); + REG_CLR_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); +} + +uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + regi2c_enable_block(block); + + (void)host_id; + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp); + while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY)); + return REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA); + + regi2c_disable_block(block); +} + +uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + assert(msb - lsb < 8); + regi2c_enable_block(block); + + (void)host_id; + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp); + while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY)); + uint32_t data = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA); + return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + regi2c_disable_block(block); +} + +void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + (void)host_id; + regi2c_enable_block(block); + + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp); + while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY)); + + regi2c_disable_block(block); +} + +void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + (void)host_id; + assert(msb - lsb < 8); + regi2c_enable_block(block); + + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp); + while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY)); + temp = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp); + while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY)); + + regi2c_disable_block(block); +} diff --git a/components/esp_rom/patches/esp_rom_regi2c.c b/components/esp_rom/patches/esp_rom_regi2c_esp32s2.c similarity index 90% rename from components/esp_rom/patches/esp_rom_regi2c.c rename to components/esp_rom/patches/esp_rom_regi2c_esp32s2.c index 90827ab287..045c96dc09 100644 --- a/components/esp_rom/patches/esp_rom_regi2c.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32s2.c @@ -7,9 +7,9 @@ #include #include "esp_bit_defs.h" #include "esp_rom_caps.h" +#include "esp_attr.h" #include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32S2 #include "soc/syscon_reg.h" #define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG) @@ -87,7 +87,7 @@ #define I2C_SAR_ADC 0X69 #define I2C_APLL 0X6D -static void i2c_rtc_enable_block(uint8_t block) +static IRAM_ATTR void i2c_rtc_enable_block(uint8_t block) { REG_SET_FIELD(I2C_RTC_CONFIG0, I2C_RTC_MAGIC_CTRL, I2C_RTC_MAGIC_DEFAULT); REG_SET_FIELD(I2C_RTC_CONFIG1, I2C_RTC_ALL_MASK, I2C_RTC_ALL_MASK_V); @@ -108,7 +108,7 @@ static void i2c_rtc_enable_block(uint8_t block) } } -uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) +uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) { i2c_rtc_enable_block(block); @@ -119,7 +119,7 @@ uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); } -uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { assert(msb - lsb < 8); i2c_rtc_enable_block(block); @@ -132,7 +132,7 @@ uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); } -void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { i2c_rtc_enable_block(block); @@ -144,7 +144,7 @@ void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); } -void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { assert(msb - lsb < 8); i2c_rtc_enable_block(block); @@ -165,4 +165,3 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, REG_WRITE(I2C_RTC_CONFIG2, temp); while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); } -#endif //CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/soc/esp32c6/include/modem/modem_lpcon_reg.h b/components/soc/esp32c6/include/modem/modem_lpcon_reg.h new file mode 100644 index 0000000000..53d4d73a71 --- /dev/null +++ b/components/soc/esp32c6/include/modem/modem_lpcon_reg.h @@ -0,0 +1,383 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "modem/reg_base.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/* MODEM_LPCON_CLK_DEBUG_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_DEBUG_ENA (BIT(1)) +#define MODEM_LPCON_CLK_DEBUG_ENA_M (BIT(1)) +#define MODEM_LPCON_CLK_DEBUG_ENA_V 0x1 +#define MODEM_LPCON_CLK_DEBUG_ENA_S 1 +/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_EN (BIT(0)) +#define MODEM_LPCON_CLK_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_S 0 + +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) +/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M (BIT(0)) +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (BIT(0)) +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S 0 + +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 + +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 +/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_V 0x1 +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 + +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) +/* MODEM_LPCON_CLK_DC_MEM_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_DC_MEM_FO (BIT(9)) +#define MODEM_LPCON_CLK_DC_MEM_FO_M (BIT(9)) +#define MODEM_LPCON_CLK_DC_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_DC_MEM_FO_S 9 +/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_AGC_MEM_FO (BIT(8)) +#define MODEM_LPCON_CLK_AGC_MEM_FO_M (BIT(8)) +#define MODEM_LPCON_CLK_AGC_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_AGC_MEM_FO_S 8 +/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_PBUS_MEM_FO (BIT(7)) +#define MODEM_LPCON_CLK_PBUS_MEM_FO_M (BIT(7)) +#define MODEM_LPCON_CLK_PBUS_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_PBUS_MEM_FO_S 7 +/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO (BIT(6)) +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M (BIT(6)) +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S 6 +/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO (BIT(5)) +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M (BIT(5)) +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S 5 +/* MODEM_LPCON_CLK_BCMEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_BCMEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_BCMEM_FO_M (BIT(4)) +#define MODEM_LPCON_CLK_BCMEM_FO_V 0x1 +#define MODEM_LPCON_CLK_BCMEM_FO_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_V 0x1 +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 + +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 +/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 + +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_V 0x1 +#define MODEM_LPCON_RST_LP_TIMER_S 3 +/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_V 0x1 +#define MODEM_LPCON_RST_I2C_MST_S 2 +/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (BIT(1)) +#define MODEM_LPCON_RST_COEX_V 0x1 +#define MODEM_LPCON_RST_COEX_S 1 +/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_S 0 + +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W ;bitpos:[19:18] ;default: 2'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003 +#define MODEM_LPCON_MODEM_PWR_MEM_RA_M ((MODEM_LPCON_MODEM_PWR_MEM_RA_V)<<(MODEM_LPCON_MODEM_PWR_MEM_RA_S)) +#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x3 +#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18 +/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W ;bitpos:[17:15] ;default: 3'h4 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007 +#define MODEM_LPCON_MODEM_PWR_MEM_WA_M ((MODEM_LPCON_MODEM_PWR_MEM_WA_V)<<(MODEM_LPCON_MODEM_PWR_MEM_WA_S)) +#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x7 +#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15 +/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007 +#define MODEM_LPCON_MODEM_PWR_MEM_WP_M ((MODEM_LPCON_MODEM_PWR_MEM_WP_V)<<(MODEM_LPCON_MODEM_PWR_MEM_WP_S)) +#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x7 +#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12 +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (BIT(11)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11 +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (BIT(10)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10 +/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (BIT(9)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9 +/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (BIT(8)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8 +/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_FORCE_PD (BIT(7)) +#define MODEM_LPCON_BC_MEM_FORCE_PD_M (BIT(7)) +#define MODEM_LPCON_BC_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_BC_MEM_FORCE_PD_S 7 +/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6)) +#define MODEM_LPCON_BC_MEM_FORCE_PU_M (BIT(6)) +#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6 +/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (BIT(5)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5 +/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (BIT(4)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4 +/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3)) +#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (BIT(3)) +#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3 +/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2)) +#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (BIT(2)) +#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2 +/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1)) +#define MODEM_LPCON_DC_MEM_FORCE_PD_M (BIT(1)) +#define MODEM_LPCON_DC_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_PD_S 1 +/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_FORCE_PU (BIT(0)) +#define MODEM_LPCON_DC_MEM_FORCE_PU_M (BIT(0)) +#define MODEM_LPCON_DC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_PU_S 0 + +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) +/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2206240 ; */ +/*description: .*/ +#define MODEM_LPCON_DATE 0x0FFFFFFF +#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) +#define MODEM_LPCON_DATE_V 0xFFFFFFF +#define MODEM_LPCON_DATE_S 0 + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/modem/modem_lpcon_struct.h b/components/soc/esp32c6/include/modem/modem_lpcon_struct.h new file mode 100644 index 0000000000..cee63ef3a1 --- /dev/null +++ b/components/soc/esp32c6/include/modem/modem_lpcon_struct.h @@ -0,0 +1,234 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "modem/reg_base.h" +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t reg_clk_en : 1; + uint32_t reg_clk_debug_ena : 1; + uint32_t reserved2 : 30; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t reg_clk_lp_timer_sel_osc_slow : 1; + uint32_t reg_clk_lp_timer_sel_osc_fast : 1; + uint32_t reg_clk_lp_timer_sel_xtal : 1; + uint32_t reg_clk_lp_timer_sel_xtal32k : 1; + uint32_t reg_clk_lp_timer_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } lp_timer_conf; + union { + struct { + uint32_t reg_clk_coex_lp_sel_osc_slow : 1; + uint32_t reg_clk_coex_lp_sel_osc_fast : 1; + uint32_t reg_clk_coex_lp_sel_xtal : 1; + uint32_t reg_clk_coex_lp_sel_xtal32k : 1; + uint32_t reg_clk_coex_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } coex_lp_clk_conf; + union { + struct { + uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t reg_clk_wifipwr_lp_sel_xtal : 1; + uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t reg_clk_wifipwr_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } wifi_lp_clk_conf; + union { + struct { + uint32_t reg_clk_i2c_mst_sel_160m : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } i2c_mst_clk_conf; + union { + struct { + uint32_t reg_clk_modem_32k_sel : 2; + uint32_t reserved2 : 30; + }; + uint32_t val; + } modem_32k_clk_conf; + union { + struct { + uint32_t reg_clk_wifipwr_en : 1; + uint32_t reg_clk_coex_en : 1; + uint32_t reg_clk_i2c_mst_en : 1; + uint32_t reg_clk_lp_timer_en : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reg_clk_wifipwr_fo : 1; + uint32_t reg_clk_coex_fo : 1; + uint32_t reg_clk_i2c_mst_fo : 1; + uint32_t reg_clk_lp_timer_fo : 1; + uint32_t reg_clk_bcmem_fo : 1; + uint32_t reg_clk_i2c_mst_mem_fo : 1; + uint32_t reg_clk_chan_freq_mem_fo : 1; + uint32_t reg_clk_pbus_mem_fo : 1; + uint32_t reg_clk_agc_mem_fo : 1; + uint32_t reg_clk_dc_mem_fo : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 16; + uint32_t reg_clk_wifipwr_st_map : 4; + uint32_t reg_clk_coex_st_map : 4; + uint32_t reg_clk_i2c_mst_st_map : 4; + uint32_t reg_clk_lp_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t reg_rst_wifipwr : 1; + uint32_t reg_rst_coex : 1; + uint32_t reg_rst_i2c_mst : 1; + uint32_t reg_rst_lp_timer : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } rst_conf; + union { + struct { + uint32_t reg_dc_mem_force_pu : 1; + uint32_t reg_dc_mem_force_pd : 1; + uint32_t reg_agc_mem_force_pu : 1; + uint32_t reg_agc_mem_force_pd : 1; + uint32_t reg_pbus_mem_force_pu : 1; + uint32_t reg_pbus_mem_force_pd : 1; + uint32_t reg_bc_mem_force_pu : 1; + uint32_t reg_bc_mem_force_pd : 1; + uint32_t reg_i2c_mst_mem_force_pu : 1; + uint32_t reg_i2c_mst_mem_force_pd : 1; + uint32_t reg_chan_freq_mem_force_pu : 1; + uint32_t reg_chan_freq_mem_force_pd : 1; + uint32_t reg_modem_pwr_mem_wp : 3; + uint32_t reg_modem_pwr_mem_wa : 3; + uint32_t reg_modem_pwr_mem_ra : 2; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } mem_conf; + union { + struct { + uint32_t reg_date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_lpcon_dev_t; +extern modem_lpcon_dev_t MODEM_LPCON; +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/modem/reg_base.h b/components/soc/esp32c6/include/modem/reg_base.h new file mode 100644 index 0000000000..00efdc7d96 --- /dev/null +++ b/components/soc/esp32c6/include/modem/reg_base.h @@ -0,0 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#define DR_REG_MODEM_LPCON_BASE 0x600AF000 diff --git a/components/soc/esp32c6/ld/esp32c6.peripherals.ld b/components/soc/esp32c6/ld/esp32c6.peripherals.ld index 49596bfb5b..92c6203c47 100644 --- a/components/soc/esp32c6/ld/esp32c6.peripherals.ld +++ b/components/soc/esp32c6/ld/esp32c6.peripherals.ld @@ -58,6 +58,8 @@ PROVIDE ( PCR = 0x60096000 ); PROVIDE ( TEE = 0x60098000 ); PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( MODEM_LPCON = 0x600AF000 ); + PROVIDE ( PMU = 0x600B0000 ); PROVIDE ( LP_CLKRST = 0x600B0400 ); PROVIDE ( EFUSE = 0x600B0800 );