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feat(esp32c5): support to run hello world on esp32c5 beta3

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This commit is contained in:
laokaiyao 2023-12-18 20:43:06 +08:00
parent 11e19f40b9
commit 96a4ead083
8 changed files with 29 additions and 32 deletions
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1
Kconfig
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@ -118,7 +118,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
default "y" if IDF_TARGET="esp32c5" default "y" if IDF_TARGET="esp32c5"
select FREERTOS_UNICORE select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV select IDF_TARGET_ARCH_RISCV
select IDF_ENV_BRINGUP
config IDF_TARGET_ESP32P4 config IDF_TARGET_ESP32P4
bool bool

2
components/esp_driver_uart/src/uart.c
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@ -627,7 +627,7 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id
gpio_iomux_in(io_num, upin->signal); gpio_iomux_in(io_num, upin->signal);
} }
} }
#if (SOC_UART_LP_NUM >= 1) #if (SOC_UART_LP_NUM >= 1) && (SOC_RTCIO_PIN_COUNT >= 1)
else { else {
if (upin->input) { if (upin->input) {
rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_INPUT_ONLY); rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_INPUT_ONLY);

1
components/esp_hw_support/Kconfig
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@ -245,6 +245,7 @@ menu "Hardware Settings"
rsource "./dma/Kconfig.dma" rsource "./dma/Kconfig.dma"
menu "Main XTAL Config" menu "Main XTAL Config"
# TODO: IDF-8943
choice XTAL_FREQ_SEL choice XTAL_FREQ_SEL
prompt "Main XTAL frequency" prompt "Main XTAL frequency"
default XTAL_FREQ_48 if SOC_XTAL_SUPPORT_48M default XTAL_FREQ_48 if SOC_XTAL_SUPPORT_48M

8
components/esp_system/fpga_overrides_clk.c
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@ -29,8 +29,6 @@
#include "esp32p4/rom/rtc.h" #include "esp32p4/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C5 #elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/rtc.h" #include "esp32c5/rom/rtc.h"
#include "hal/clk_tree_ll.h"
#include "soc/clk_tree_defs.h"
#endif #endif
#include "esp_log.h" #include "esp_log.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
@ -59,12 +57,6 @@ void bootloader_clock_configure(void)
REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16)); REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
#endif #endif
REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16)); REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
#if CONFIG_IDF_TARGET_ESP32C5
// The default slow clock source RC_SLOW is unusable on c5, switch to SOC_RTC_SLOW_CLK_SRC_RC32K instead
clk_ll_rtc_slow_set_src(SOC_RTC_SLOW_CLK_SRC_RC32K);
esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
#endif
} }
void esp_clk_init(void) void esp_clk_init(void)

4
components/esp_system/panic.c
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@ -79,7 +79,7 @@ static wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT #if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
#if CONFIG_ESP_CONSOLE_UART #if CONFIG_ESP_CONSOLE_UART && SOC_UART_SUPPORTED
static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 :&UART1 }; static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 :&UART1 };
static void panic_print_char_uart(const char c) static void panic_print_char_uart(const char c)
@ -122,7 +122,7 @@ static void panic_print_char_usb_serial_jtag(const char c)
void panic_print_char(const char c) void panic_print_char(const char c)
{ {
#if CONFIG_ESP_CONSOLE_UART #if CONFIG_ESP_CONSOLE_UART && SOC_UART_SUPPORTED
panic_print_char_uart(c); panic_print_char_uart(c);
#endif #endif
#if CONFIG_ESP_CONSOLE_USB_CDC #if CONFIG_ESP_CONSOLE_USB_CDC

38
components/hal/esp32c5/include/hal/lp_aon_ll.h
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@ -26,9 +26,7 @@ extern "C" {
*/ */
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void) static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
{ {
// TODO: [ESP32C5] IDF-8638, IDF-8640 return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
// return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
return (uint32_t)0;
} }
/** /**
@ -36,8 +34,7 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
*/ */
static inline void lp_aon_ll_ext1_clear_wakeup_status(void) static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
{ {
// TODO: [ESP32C5] IDF-8638, IDF-8640 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
} }
/** /**
@ -50,9 +47,15 @@ static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
*/ */
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
{ {
// TODO: [ESP32C5] IDF-8638, IDF-8640 uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask); wakeup_sel_mask |= io_mask;
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
wakeup_level_mask |= io_mask & level_mask;
wakeup_level_mask &= ~(io_mask & ~level_mask);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
} }
/** /**
@ -60,8 +63,7 @@ static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t lev
*/ */
static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
{ {
// TODO: [ESP32C5] IDF-8638, IDF-8640 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
} }
/** /**
@ -71,9 +73,7 @@ static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
*/ */
static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
{ {
// TODO: [ESP32C5] IDF-8638, IDF-8640 return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
// return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
return (uint32_t)0;
} }
@ -84,12 +84,12 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
*/ */
static inline void lp_aon_ll_inform_wakeup_type(bool dslp) static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
{ {
// TODO: [ESP32C5] IDF-8638, IDF-8640 if (dslp) {
// if (dslp) { REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
// REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
// // } else { } else {
// REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
// } }
} }
#ifdef __cplusplus #ifdef __cplusplus

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -83,6 +83,10 @@ config SOC_CPU_HAS_FLEXIBLE_INTC
bool bool
default y default y
config SOC_INT_PLIC_SUPPORTED
bool
default n
config SOC_INT_CLIC_SUPPORTED config SOC_INT_CLIC_SUPPORTED
bool bool
default y default y

1
components/soc/esp32c5/include/soc/soc_caps.h
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@ -141,6 +141,7 @@
#define SOC_CPU_CORES_NUM (1U) #define SOC_CPU_CORES_NUM (1U)
#define SOC_CPU_INTR_NUM 32 #define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 0 //riscv platform-level interrupt controller
#define SOC_INT_CLIC_SUPPORTED 1 #define SOC_INT_CLIC_SUPPORTED 1
#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting #define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting
#define SOC_BRANCH_PREDICTOR_SUPPORTED 1 #define SOC_BRANCH_PREDICTOR_SUPPORTED 1