mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
remove prefix and postfix
This commit is contained in:
Wangjialin
parent
9938f512f3
commit
94bcb14bcc
@ -16,33 +16,33 @@
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typedef volatile struct {
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union {
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struct {
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uint32_t sd_in: 8;
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uint32_t duty: 8;
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uint32_t prescale: 8;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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}sigmadelta[8];
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}channel[8];
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union {
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struct {
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uint32_t reserved0: 31;
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uint32_t clk_en: 1;
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};
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uint32_t val;
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}sigmadelta_cg;
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}cg;
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union {
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struct {
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uint32_t reserved0: 31;
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uint32_t spi_swap: 1;
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};
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uint32_t val;
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}sigmadelta_misc;
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}misc;
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union {
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struct {
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uint32_t date: 28;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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}sigmadelta_version;
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}version;
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} gpio_sd_dev_t;
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extern gpio_sd_dev_t SIGMADELTA;
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#endif /* _SOC_GPIO_SD_STRUCT_H_ */
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@ -20,28 +20,28 @@ typedef volatile struct {
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uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/
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union {
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struct {
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uint32_t out_data: 8; /*GPIO32~39 output value*/
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uint32_t data: 8; /*GPIO32~39 output value*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}out1;
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union {
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struct {
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uint32_t out_data: 8; /*GPIO32~39 output value write 1 to set*/
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uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}out1_w1ts;
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union {
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struct {
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uint32_t out_data: 8; /*GPIO32~39 output value write 1 to clear*/
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uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}out1_w1tc;
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union {
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struct {
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uint32_t sdio_sel: 8; /*SDIO PADS on/off control from outside*/
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uint32_t sel: 8; /*SDIO PADS on/off control from outside*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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@ -51,21 +51,21 @@ typedef volatile struct {
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uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/
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union {
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struct {
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uint32_t enable_data: 8; /*GPIO32~39 output enable*/
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uint32_t data: 8; /*GPIO32~39 output enable*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}enable1;
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union {
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struct {
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uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to set*/
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uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}enable1_w1ts;
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union {
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struct {
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uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to clear*/
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uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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@ -80,8 +80,8 @@ typedef volatile struct {
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uint32_t in; /*GPIO0~31 input value*/
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union {
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struct {
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uint32_t in_data: 8; /*GPIO32~39 input value*/
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uint32_t reserved8: 24;
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uint32_t data: 8; /*GPIO32~39 input value*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}in1;
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@ -90,22 +90,22 @@ typedef volatile struct {
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uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/
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union {
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struct {
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uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status*/
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uint32_t reserved8: 24;
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uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}status1;
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union {
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struct {
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uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to set*/
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uint32_t reserved8: 24;
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uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}status1_w1ts;
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union {
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struct {
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uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to clear*/
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uint32_t reserved8: 24;
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uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}status1_w1tc;
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@ -117,85 +117,85 @@ typedef volatile struct {
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uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/
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union {
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struct {
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uint32_t appcpu_int: 8; /*GPIO32~39 APP CPU interrupt status*/
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uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}acpu_int1;
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union {
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struct {
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uint32_t appcpu_nmi_int: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/
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uint32_t reserved8: 24;
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uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}acpu_nmi_int1;
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union {
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struct {
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uint32_t procpu_int: 8; /*GPIO32~39 PRO CPU interrupt status*/
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uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}pcpu_int1;
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union {
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struct {
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uint32_t procpu_nmi_int: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/
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uint32_t reserved8: 24;
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uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}pcpu_nmi_int1;
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union {
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struct {
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uint32_t sdio_int: 8; /*SDIO's extent GPIO32~39 interrupt*/
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uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}cpusdio_int1;
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union {
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struct {
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uint32_t reserved0: 2;
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uint32_t pin_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
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uint32_t reserved3: 4;
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uint32_t pin_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
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uint32_t pin_wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/
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uint32_t pin_config: 2; /*NA*/
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uint32_t pin_int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
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uint32_t reserved18: 14;
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uint32_t reserved0: 2;
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uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
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uint32_t reserved3: 4;
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uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
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uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/
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uint32_t config: 2; /*NA*/
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uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
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uint32_t reserved18: 14;
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};
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uint32_t val;
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}pin[40];
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union {
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struct {
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uint32_t cali_rtc_max:10;
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uint32_t rtc_max: 10;
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uint32_t reserved10: 21;
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uint32_t cali_start: 1;
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uint32_t start: 1;
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};
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uint32_t val;
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}cali_conf;
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union {
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struct {
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uint32_t cali_value_sync2:20;
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uint32_t reserved20: 10;
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uint32_t cali_rdy_real: 1;
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uint32_t cali_rdy_sync2: 1;
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uint32_t value_sync2: 20;
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uint32_t reserved20: 10;
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uint32_t rdy_real: 1;
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uint32_t rdy_sync2: 1;
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};
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uint32_t val;
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}cali_data;
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union {
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struct {
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uint32_t func_in_sel: 6; /*select one of the 256 inputs*/
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uint32_t func_in_inv_sel: 1; /*revert the value of the input if you want to revert please set the value to 1*/
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uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/
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uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
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uint32_t func_sel: 6; /*select one of the 256 inputs*/
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uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/
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uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/
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uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
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};
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uint32_t val;
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}func_in_sel_cfg[256];
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union {
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struct {
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uint32_t func_out_sel: 9; /*select one of the 256 output to 40 GPIO*/
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uint32_t func_out_inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/
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uint32_t func_oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/
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uint32_t func_oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/
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uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
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uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/
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uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/
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uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/
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uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/
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uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
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};
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uint32_t val;
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}func_out_sel_cfg[40];
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@ -58,29 +58,29 @@ typedef volatile struct {
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}status_reg;
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union {
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struct {
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uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/
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uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/
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uint32_t reserved20:12;
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};
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uint32_t val;
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}timeout;
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union {
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struct {
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uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
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uint32_t reserved15: 16;
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uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/
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uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
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uint32_t reserved15: 16;
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uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
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};
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uint32_t val;
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}slave_addr;
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union {
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struct {
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uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
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uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
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uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
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uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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}rx_fifo_st;
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}fifo_st;
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union {
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struct {
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uint32_t rx_fifo_full_thrhd: 5;
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@ -97,150 +97,150 @@ typedef volatile struct {
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}fifo_conf;
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union {
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struct {
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uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
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uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}fifo_data;
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union {
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struct {
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uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
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uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
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uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
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uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
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uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
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uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
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uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
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uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
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uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
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uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
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uint32_t reserved13: 19;
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uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
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uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
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uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
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uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
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uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
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uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
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uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
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uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
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uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
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uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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}int_raw;
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||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
|
||||
uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
|
||||
uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
|
||||
uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/
|
||||
uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
|
||||
uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
|
||||
uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
|
||||
uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
|
||||
uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/
|
||||
uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/
|
||||
uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/
|
||||
uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
|
||||
uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
|
||||
uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
|
||||
uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
|
||||
uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/
|
||||
uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
|
||||
uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
|
||||
uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
|
||||
uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
|
||||
uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/
|
||||
uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/
|
||||
uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/
|
||||
uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
|
||||
uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
|
||||
uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
|
||||
uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
|
||||
uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/
|
||||
uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
|
||||
uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/
|
||||
uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/
|
||||
uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/
|
||||
uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/
|
||||
uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/
|
||||
uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/
|
||||
uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/
|
||||
uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
|
||||
uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
|
||||
uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
|
||||
uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/
|
||||
uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
|
||||
uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/
|
||||
uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/
|
||||
uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/
|
||||
uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/
|
||||
uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/
|
||||
uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/
|
||||
uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/
|
||||
uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
|
||||
uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
|
||||
uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
|
||||
uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/
|
||||
uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
|
||||
uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
|
||||
uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
|
||||
uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
|
||||
uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/
|
||||
uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/
|
||||
uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/
|
||||
uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
|
||||
uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
|
||||
uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
|
||||
uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
|
||||
uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/
|
||||
uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
|
||||
uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
|
||||
uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
|
||||
uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
|
||||
uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/
|
||||
uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/
|
||||
uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/
|
||||
uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
|
||||
uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
|
||||
uint32_t reserved10: 22;
|
||||
uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}sda_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
|
||||
uint32_t reserved10: 22;
|
||||
uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}sda_sample;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/
|
||||
uint32_t reserved14: 18;
|
||||
uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
}scl_high_period;
|
||||
uint32_t reserved_3c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
|
||||
uint32_t reserved10: 22;
|
||||
uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}scl_start_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
|
||||
uint32_t reserved10: 22;
|
||||
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}scl_rstart_setup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
|
||||
uint32_t reserved14: 18;
|
||||
uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
}scl_stop_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
|
||||
uint32_t reserved10: 22;
|
||||
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
}scl_stop_setup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
|
||||
uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/
|
||||
uint32_t reserved4: 28;
|
||||
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
|
||||
uint32_t en: 1; /*This is the filter enable bit for SCL.*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
}scl_filter_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
|
||||
uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/
|
||||
uint32_t reserved4: 28;
|
||||
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
|
||||
uint32_t en: 1; /*This is the filter enable bit for SDA.*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
}sda_filter_cfg;
|
||||
@ -252,7 +252,7 @@ typedef volatile struct {
|
||||
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
|
||||
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
|
||||
uint32_t reserved14: 17;
|
||||
uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
|
||||
uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}command[16];
|
||||
|
||||
@ -43,93 +43,93 @@ typedef volatile struct {
|
||||
}conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_take_data_int_raw: 1;
|
||||
uint32_t tx_put_data_int_raw: 1;
|
||||
uint32_t rx_wfull_int_raw: 1;
|
||||
uint32_t rx_rempty_int_raw: 1;
|
||||
uint32_t tx_wfull_int_raw: 1;
|
||||
uint32_t tx_rempty_int_raw: 1;
|
||||
uint32_t rx_hung_int_raw: 1;
|
||||
uint32_t tx_hung_int_raw: 1;
|
||||
uint32_t in_done_int_raw: 1;
|
||||
uint32_t in_suc_eof_int_raw: 1;
|
||||
uint32_t in_err_eof_int_raw: 1;
|
||||
uint32_t out_done_int_raw: 1;
|
||||
uint32_t out_eof_int_raw: 1;
|
||||
uint32_t in_dscr_err_int_raw: 1;
|
||||
uint32_t out_dscr_err_int_raw: 1;
|
||||
uint32_t in_dscr_empty_int_raw: 1;
|
||||
uint32_t out_total_eof_int_raw: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_take_data: 1;
|
||||
uint32_t tx_put_data: 1;
|
||||
uint32_t rx_wfull: 1;
|
||||
uint32_t rx_rempty: 1;
|
||||
uint32_t tx_wfull: 1;
|
||||
uint32_t tx_rempty: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_take_data_int_st: 1;
|
||||
uint32_t tx_put_data_int_st: 1;
|
||||
uint32_t rx_wfull_int_st: 1;
|
||||
uint32_t rx_rempty_int_st: 1;
|
||||
uint32_t tx_wfull_int_st: 1;
|
||||
uint32_t tx_rempty_int_st: 1;
|
||||
uint32_t rx_hung_int_st: 1;
|
||||
uint32_t tx_hung_int_st: 1;
|
||||
uint32_t in_done_int_st: 1;
|
||||
uint32_t in_suc_eof_int_st: 1;
|
||||
uint32_t in_err_eof_int_st: 1;
|
||||
uint32_t out_done_int_st: 1;
|
||||
uint32_t out_eof_int_st: 1;
|
||||
uint32_t in_dscr_err_int_st: 1;
|
||||
uint32_t out_dscr_err_int_st: 1;
|
||||
uint32_t in_dscr_empty_int_st: 1;
|
||||
uint32_t out_total_eof_int_st: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_take_data: 1;
|
||||
uint32_t tx_put_data: 1;
|
||||
uint32_t rx_wfull: 1;
|
||||
uint32_t rx_rempty: 1;
|
||||
uint32_t tx_wfull: 1;
|
||||
uint32_t tx_rempty: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_take_data_int_ena: 1;
|
||||
uint32_t tx_put_data_int_ena: 1;
|
||||
uint32_t rx_wfull_int_ena: 1;
|
||||
uint32_t rx_rempty_int_ena: 1;
|
||||
uint32_t tx_wfull_int_ena: 1;
|
||||
uint32_t tx_rempty_int_ena: 1;
|
||||
uint32_t rx_hung_int_ena: 1;
|
||||
uint32_t tx_hung_int_ena: 1;
|
||||
uint32_t in_done_int_ena: 1;
|
||||
uint32_t in_suc_eof_int_ena: 1;
|
||||
uint32_t in_err_eof_int_ena: 1;
|
||||
uint32_t out_done_int_ena: 1;
|
||||
uint32_t out_eof_int_ena: 1;
|
||||
uint32_t in_dscr_err_int_ena: 1;
|
||||
uint32_t out_dscr_err_int_ena: 1;
|
||||
uint32_t in_dscr_empty_int_ena: 1;
|
||||
uint32_t out_total_eof_int_ena: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_take_data: 1;
|
||||
uint32_t tx_put_data: 1;
|
||||
uint32_t rx_wfull: 1;
|
||||
uint32_t rx_rempty: 1;
|
||||
uint32_t tx_wfull: 1;
|
||||
uint32_t tx_rempty: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t take_data_int_clr: 1;
|
||||
uint32_t put_data_int_clr: 1;
|
||||
uint32_t rx_wfull_int_clr: 1;
|
||||
uint32_t rx_rempty_int_clr: 1;
|
||||
uint32_t tx_wfull_int_clr: 1;
|
||||
uint32_t tx_rempty_int_clr: 1;
|
||||
uint32_t rx_hung_int_clr: 1;
|
||||
uint32_t tx_hung_int_clr: 1;
|
||||
uint32_t in_done_int_clr: 1;
|
||||
uint32_t in_suc_eof_int_clr: 1;
|
||||
uint32_t in_err_eof_int_clr: 1;
|
||||
uint32_t out_done_int_clr: 1;
|
||||
uint32_t out_eof_int_clr: 1;
|
||||
uint32_t in_dscr_err_int_clr: 1;
|
||||
uint32_t out_dscr_err_int_clr: 1;
|
||||
uint32_t in_dscr_empty_int_clr: 1;
|
||||
uint32_t out_total_eof_int_clr: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t take_data: 1;
|
||||
uint32_t put_data: 1;
|
||||
uint32_t rx_wfull: 1;
|
||||
uint32_t rx_rempty: 1;
|
||||
uint32_t tx_wfull: 1;
|
||||
uint32_t tx_rempty: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
@ -178,23 +178,23 @@ typedef volatile struct {
|
||||
}conf_chan;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outlink_addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t outlink_stop: 1;
|
||||
uint32_t outlink_start: 1;
|
||||
uint32_t outlink_restart: 1;
|
||||
uint32_t outlink_park: 1;
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
}out_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t inlink_stop: 1;
|
||||
uint32_t inlink_start: 1;
|
||||
uint32_t inlink_restart: 1;
|
||||
uint32_t inlink_park: 1;
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
}in_link;
|
||||
@ -203,10 +203,10 @@ typedef volatile struct {
|
||||
uint32_t out_eof_bfr_des_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ahb_testmode: 3;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t ahb_testaddr: 2;
|
||||
uint32_t reserved6: 26;
|
||||
uint32_t mode: 3;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t addr: 2;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
}ahb_test;
|
||||
@ -238,19 +238,19 @@ typedef volatile struct {
|
||||
}lc_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_fifo_wdata: 9;
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t out_fifo_push: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t wdata: 9;
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t push: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}out_fifo_push;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_fifo_rdata:12;
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t in_fifo_pop: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rdata: 12;
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t pop: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}in_fifo_pop;
|
||||
@ -258,10 +258,10 @@ typedef volatile struct {
|
||||
uint32_t lc_state1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lc_fifo_timeout: 8;
|
||||
uint32_t lc_fifo_timeout_shift: 3;
|
||||
uint32_t lc_fifo_timeout_ena: 1;
|
||||
uint32_t reserved12: 20;
|
||||
uint32_t fifo_timeout: 8;
|
||||
uint32_t fifo_timeout_shift: 3;
|
||||
uint32_t fifo_timeout_ena: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
}lc_hung_conf;
|
||||
@ -269,15 +269,15 @@ typedef volatile struct {
|
||||
uint32_t reserved_7c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cvsd_y_max:16;
|
||||
uint32_t cvsd_y_min:16;
|
||||
uint32_t y_max:16;
|
||||
uint32_t y_min:16;
|
||||
};
|
||||
uint32_t val;
|
||||
}cvsd_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cvsd_sigma_max:16;
|
||||
uint32_t cvsd_sigma_min:16;
|
||||
uint32_t sigma_max:16;
|
||||
uint32_t sigma_min:16;
|
||||
};
|
||||
uint32_t val;
|
||||
}cvsd_conf1;
|
||||
@ -323,23 +323,23 @@ typedef volatile struct {
|
||||
}plc_conf2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t esco_en: 1;
|
||||
uint32_t esco_chan_mod: 1;
|
||||
uint32_t esco_cvsd_dec_pack_err: 1;
|
||||
uint32_t esco_cvsd_pack_len_8k: 5;
|
||||
uint32_t esco_cvsd_inf_en: 1;
|
||||
uint32_t cvsd_dec_start: 1;
|
||||
uint32_t cvsd_dec_reset: 1;
|
||||
uint32_t plc_en: 1;
|
||||
uint32_t plc2dma_en: 1;
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t en: 1;
|
||||
uint32_t chan_mod: 1;
|
||||
uint32_t cvsd_dec_pack_err: 1;
|
||||
uint32_t cvsd_pack_len_8k: 5;
|
||||
uint32_t cvsd_inf_en: 1;
|
||||
uint32_t cvsd_dec_start: 1;
|
||||
uint32_t cvsd_dec_reset: 1;
|
||||
uint32_t plc_en: 1;
|
||||
uint32_t plc2dma_en: 1;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
}esco_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sco_with_en: 1;
|
||||
uint32_t sco_no_en: 1;
|
||||
uint32_t with_en: 1;
|
||||
uint32_t no_en: 1;
|
||||
uint32_t cvsd_enc_start: 1;
|
||||
uint32_t cvsd_enc_reset: 1;
|
||||
uint32_t reserved4: 28;
|
||||
@ -388,7 +388,7 @@ typedef volatile struct {
|
||||
uint32_t clkm_div_b: 6;
|
||||
uint32_t clkm_div_a: 6;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t clka_ena: 1;
|
||||
uint32_t clka_en: 1;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -405,19 +405,19 @@ typedef volatile struct {
|
||||
}sample_rate_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_pdm_en: 1;
|
||||
uint32_t rx_pdm_en: 1;
|
||||
uint32_t pcm2pdm_conv_en: 1;
|
||||
uint32_t pdm2pcm_conv_en: 1;
|
||||
uint32_t tx_pdm_sinc_osr2: 4;
|
||||
uint32_t tx_pdm_prescale: 8;
|
||||
uint32_t tx_pdm_hp_in_shift: 2;
|
||||
uint32_t tx_pdm_lp_in_shift: 2;
|
||||
uint32_t tx_pdm_sinc_in_shift: 2;
|
||||
uint32_t tx_pdm_sigmadelta_in_shift: 2;
|
||||
uint32_t rx_pdm_sinc_dsr_16_en: 1;
|
||||
uint32_t tx_pdm_hp_bypass: 1;
|
||||
uint32_t reserved26: 6;
|
||||
uint32_t tx_pdm_en: 1;
|
||||
uint32_t rx_pdm_en: 1;
|
||||
uint32_t pcm2pdm_conv_en: 1;
|
||||
uint32_t pdm2pcm_conv_en: 1;
|
||||
uint32_t tx_sinc_osr2: 4;
|
||||
uint32_t tx_prescale: 8;
|
||||
uint32_t tx_hp_in_shift: 2;
|
||||
uint32_t tx_lp_in_shift: 2;
|
||||
uint32_t tx_sinc_in_shift: 2;
|
||||
uint32_t tx_sigmadelta_in_shift: 2;
|
||||
uint32_t rx_sinc_dsr_16_en: 1;
|
||||
uint32_t txhp_bypass: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
}pdm_conf;
|
||||
|
||||
@ -143,121 +143,120 @@ typedef volatile struct {
|
||||
}low_speed_timer[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t hstimer0_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
|
||||
uint32_t hstimer1_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
|
||||
uint32_t hstimer2_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
|
||||
uint32_t hstimer3_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/
|
||||
uint32_t lstimer0_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
|
||||
uint32_t lstimer1_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
|
||||
uint32_t lstimer2_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
|
||||
uint32_t lstimer3_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
|
||||
uint32_t duty_chng_end_hsch0_int_raw: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch1_int_raw: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch2_int_raw: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch3_int_raw: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch4_int_raw: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch5_int_raw: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch6_int_raw: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch7_int_raw: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch0_int_raw: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch1_int_raw: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch2_int_raw: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch3_int_raw: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch4_int_raw: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch5_int_raw: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch6_int_raw: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch7_int_raw: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
|
||||
uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
|
||||
uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
|
||||
uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/
|
||||
uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
|
||||
uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
|
||||
uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
|
||||
uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
|
||||
uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/
|
||||
uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
|
||||
uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t hstimer0_ovf_int_st: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/
|
||||
uint32_t hstimer1_ovf_int_st: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/
|
||||
uint32_t hstimer2_ovf_int_st: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/
|
||||
uint32_t hstimer3_ovf_int_st: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/
|
||||
uint32_t lstimer0_ovf_int_st: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/
|
||||
uint32_t lstimer1_ovf_int_st: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/
|
||||
uint32_t lstimer2_ovf_int_st: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/
|
||||
uint32_t lstimer3_ovf_int_st: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/
|
||||
uint32_t duty_chng_end_hsch0_int_st: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch1_int_st: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch2_int_st: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch3_int_st: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch4_int_st: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch5_int_st: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch6_int_st: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch7_int_st: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch0_int_st: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch1_int_st: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch2_int_st: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch3_int_st: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch4_int_st: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch5_int_st: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch6_int_st: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch7_int_st: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/
|
||||
uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/
|
||||
uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/
|
||||
uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/
|
||||
uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/
|
||||
uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/
|
||||
uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/
|
||||
uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.* uint32_t duty_chng_end_hsch0: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/
|
||||
uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/
|
||||
uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t hstimer0_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
|
||||
uint32_t hstimer1_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
|
||||
uint32_t hstimer2_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
|
||||
uint32_t hstimer3_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/
|
||||
uint32_t lstimer0_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/
|
||||
uint32_t lstimer1_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/
|
||||
uint32_t lstimer2_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/
|
||||
uint32_t lstimer3_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/
|
||||
uint32_t duty_chng_end_hsch0_int_ena: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch1_int_ena: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch2_int_ena: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch3_int_ena: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch4_int_ena: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch5_int_ena: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch6_int_ena: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch7_int_ena: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch0_int_ena: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch1_int_ena: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch2_int_ena: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch3_int_ena: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch4_int_ena: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch5_int_ena: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch6_int_ena: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch7_int_ena: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
|
||||
uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
|
||||
uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
|
||||
uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/
|
||||
uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/
|
||||
uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/
|
||||
uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/
|
||||
uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/
|
||||
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t hstimer0_ovf_int_clr: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/
|
||||
uint32_t hstimer1_ovf_int_clr: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/
|
||||
uint32_t hstimer2_ovf_int_clr: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/
|
||||
uint32_t hstimer3_ovf_int_clr: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/
|
||||
uint32_t lstimer0_ovf_int_clr: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/
|
||||
uint32_t lstimer1_ovf_int_clr: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/
|
||||
uint32_t lstimer2_ovf_int_clr: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/
|
||||
uint32_t lstimer3_ovf_int_clr: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/
|
||||
uint32_t duty_chng_end_hsch0_int_clr: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch1_int_clr: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch2_int_clr: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch3_int_clr: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch4_int_clr: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch5_int_clr: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch6_int_clr: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch7_int_clr: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch0_int_clr: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch1_int_clr: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch2_int_clr: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch3_int_clr: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch4_int_clr: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch5_int_clr: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch6_int_clr: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch7_int_clr: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/
|
||||
uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/
|
||||
uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/
|
||||
uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/
|
||||
uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/
|
||||
uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/
|
||||
uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/
|
||||
uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/
|
||||
uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/
|
||||
uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
|
||||
@ -59,57 +59,57 @@ typedef volatile struct {
|
||||
}cnt_unit[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0_int_raw: 1; /*This is the interrupt raw bit for channel0 event.*/
|
||||
uint32_t cnt_thr_event_u1_int_raw: 1; /*This is the interrupt raw bit for channel1 event.*/
|
||||
uint32_t cnt_thr_event_u2_int_raw: 1; /*This is the interrupt raw bit for channel2 event.*/
|
||||
uint32_t cnt_thr_event_u3_int_raw: 1; /*This is the interrupt raw bit for channel3 event.*/
|
||||
uint32_t cnt_thr_event_u4_int_raw: 1; /*This is the interrupt raw bit for channel4 event.*/
|
||||
uint32_t cnt_thr_event_u5_int_raw: 1; /*This is the interrupt raw bit for channel5 event.*/
|
||||
uint32_t cnt_thr_event_u6_int_raw: 1; /*This is the interrupt raw bit for channel6 event.*/
|
||||
uint32_t cnt_thr_event_u7_int_raw: 1; /*This is the interrupt raw bit for channel7 event.*/
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
|
||||
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
|
||||
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
|
||||
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
|
||||
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/
|
||||
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/
|
||||
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/
|
||||
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0_int_st: 1; /*This is the interrupt status bit for channel0 event.*/
|
||||
uint32_t cnt_thr_event_u1_int_st: 1; /*This is the interrupt status bit for channel1 event.*/
|
||||
uint32_t cnt_thr_event_u2_int_st: 1; /*This is the interrupt status bit for channel2 event.*/
|
||||
uint32_t cnt_thr_event_u3_int_st: 1; /*This is the interrupt status bit for channel3 event.*/
|
||||
uint32_t cnt_thr_event_u4_int_st: 1; /*This is the interrupt status bit for channel4 event.*/
|
||||
uint32_t cnt_thr_event_u5_int_st: 1; /*This is the interrupt status bit for channel5 event.*/
|
||||
uint32_t cnt_thr_event_u6_int_st: 1; /*This is the interrupt status bit for channel6 event.*/
|
||||
uint32_t cnt_thr_event_u7_int_st: 1; /*This is the interrupt status bit for channel7 event.*/
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
|
||||
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
|
||||
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
|
||||
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
|
||||
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/
|
||||
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/
|
||||
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/
|
||||
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0_int_ena: 1; /*This is the interrupt enable bit for channel0 event.*/
|
||||
uint32_t cnt_thr_event_u1_int_ena: 1; /*This is the interrupt enable bit for channel1 event.*/
|
||||
uint32_t cnt_thr_event_u2_int_ena: 1; /*This is the interrupt enable bit for channel2 event.*/
|
||||
uint32_t cnt_thr_event_u3_int_ena: 1; /*This is the interrupt enable bit for channel3 event.*/
|
||||
uint32_t cnt_thr_event_u4_int_ena: 1; /*This is the interrupt enable bit for channel4 event.*/
|
||||
uint32_t cnt_thr_event_u5_int_ena: 1; /*This is the interrupt enable bit for channel5 event.*/
|
||||
uint32_t cnt_thr_event_u6_int_ena: 1; /*This is the interrupt enable bit for channel6 event.*/
|
||||
uint32_t cnt_thr_event_u7_int_ena: 1; /*This is the interrupt enable bit for channel7 event.*/
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
|
||||
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
|
||||
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
|
||||
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
|
||||
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/
|
||||
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/
|
||||
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/
|
||||
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0_int_clr: 1; /*Set this bit to clear channel0 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u1_int_clr: 1; /*Set this bit to clear channel1 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u2_int_clr: 1; /*Set this bit to clear channel2 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u3_int_clr: 1; /*Set this bit to clear channel3 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u4_int_clr: 1; /*Set this bit to clear channel4 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u5_int_clr: 1; /*Set this bit to clear channel5 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u6_int_clr: 1; /*Set this bit to clear channel6 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u7_int_clr: 1; /*Set this bit to clear channel7 event interrupt.*/
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
|
||||
uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
|
||||
@ -52,169 +52,169 @@ typedef volatile struct {
|
||||
uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch0_rx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
|
||||
uint32_t ch0_err_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
|
||||
uint32_t ch1_tx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch1_rx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
|
||||
uint32_t ch1_err_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
|
||||
uint32_t ch2_tx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch2_rx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
|
||||
uint32_t ch2_err_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
|
||||
uint32_t ch3_tx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch3_rx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
|
||||
uint32_t ch3_err_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
|
||||
uint32_t ch4_tx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch4_rx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
|
||||
uint32_t ch4_err_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
|
||||
uint32_t ch5_tx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch5_rx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
|
||||
uint32_t ch5_err_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
|
||||
uint32_t ch6_tx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch6_rx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
|
||||
uint32_t ch6_err_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
|
||||
uint32_t ch7_tx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch7_rx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
|
||||
uint32_t ch7_err_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
|
||||
uint32_t ch0_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch1_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch2_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch3_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch4_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch5_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch6_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch7_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
|
||||
uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
|
||||
uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
|
||||
uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
|
||||
uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
|
||||
uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
|
||||
uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
|
||||
uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
|
||||
uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
|
||||
uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
|
||||
uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
|
||||
uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
|
||||
uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
|
||||
uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
|
||||
uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
|
||||
uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
|
||||
uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end_int_st: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
|
||||
uint32_t ch0_rx_end_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/
|
||||
uint32_t ch0_err_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/
|
||||
uint32_t ch1_tx_end_int_st: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch1_rx_end_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch1_err_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/
|
||||
uint32_t ch2_tx_end_int_st: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch2_rx_end_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch2_err_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/
|
||||
uint32_t ch3_tx_end_int_st: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch3_rx_end_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch3_err_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/
|
||||
uint32_t ch4_tx_end_int_st: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch4_rx_end_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch4_err_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/
|
||||
uint32_t ch5_tx_end_int_st: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch5_rx_end_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch5_err_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/
|
||||
uint32_t ch6_tx_end_int_st: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch6_rx_end_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch6_err_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
|
||||
uint32_t ch7_tx_end_int_st: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch7_rx_end_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch7_err_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/
|
||||
uint32_t ch0_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch1_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch2_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch3_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch4_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch5_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch6_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch7_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
|
||||
uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/
|
||||
uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/
|
||||
uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/
|
||||
uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/
|
||||
uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/
|
||||
uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/
|
||||
uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/
|
||||
uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
|
||||
uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
|
||||
uint32_t ch0_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
|
||||
uint32_t ch0_err_int_ena: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/
|
||||
uint32_t ch1_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
|
||||
uint32_t ch1_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
|
||||
uint32_t ch1_err_int_ena: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/
|
||||
uint32_t ch2_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
|
||||
uint32_t ch2_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
|
||||
uint32_t ch2_err_int_ena: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/
|
||||
uint32_t ch3_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
|
||||
uint32_t ch3_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
|
||||
uint32_t ch3_err_int_ena: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
|
||||
uint32_t ch4_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
|
||||
uint32_t ch4_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
|
||||
uint32_t ch4_err_int_ena: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/
|
||||
uint32_t ch5_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
|
||||
uint32_t ch5_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
|
||||
uint32_t ch5_err_int_ena: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/
|
||||
uint32_t ch6_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
|
||||
uint32_t ch6_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
|
||||
uint32_t ch6_err_int_ena: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
|
||||
uint32_t ch7_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
|
||||
uint32_t ch7_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
|
||||
uint32_t ch7_err_int_ena: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/
|
||||
uint32_t ch0_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
|
||||
uint32_t ch1_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
|
||||
uint32_t ch2_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
|
||||
uint32_t ch3_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
|
||||
uint32_t ch4_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
|
||||
uint32_t ch5_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
|
||||
uint32_t ch6_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
|
||||
uint32_t ch7_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
|
||||
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
|
||||
uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
|
||||
uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/
|
||||
uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
|
||||
uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
|
||||
uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/
|
||||
uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
|
||||
uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
|
||||
uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/
|
||||
uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
|
||||
uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
|
||||
uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
|
||||
uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
|
||||
uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
|
||||
uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/
|
||||
uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
|
||||
uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
|
||||
uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/
|
||||
uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
|
||||
uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
|
||||
uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
|
||||
uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
|
||||
uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
|
||||
uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
|
||||
uint32_t ch0_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
|
||||
uint32_t ch0_err_int_clr: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/
|
||||
uint32_t ch1_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
|
||||
uint32_t ch1_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
|
||||
uint32_t ch1_err_int_clr: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/
|
||||
uint32_t ch2_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
|
||||
uint32_t ch2_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
|
||||
uint32_t ch2_err_int_clr: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/
|
||||
uint32_t ch3_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
|
||||
uint32_t ch3_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
|
||||
uint32_t ch3_err_int_clr: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/
|
||||
uint32_t ch4_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
|
||||
uint32_t ch4_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
|
||||
uint32_t ch4_err_int_clr: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/
|
||||
uint32_t ch5_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
|
||||
uint32_t ch5_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
|
||||
uint32_t ch5_err_int_clr: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
|
||||
uint32_t ch6_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
|
||||
uint32_t ch6_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
|
||||
uint32_t ch6_err_int_clr: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/
|
||||
uint32_t ch7_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
|
||||
uint32_t ch7_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
|
||||
uint32_t ch7_err_int_clr: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/
|
||||
uint32_t ch0_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch1_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch2_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch3_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch4_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch5_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch6_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch7_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
|
||||
uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
|
||||
uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/
|
||||
uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
|
||||
uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
|
||||
uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/
|
||||
uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
|
||||
uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
|
||||
uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/
|
||||
uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
|
||||
uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
|
||||
uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/
|
||||
uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
|
||||
uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
|
||||
uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/
|
||||
uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
|
||||
uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
|
||||
uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
|
||||
uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
|
||||
uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
|
||||
uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/
|
||||
uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
|
||||
uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
|
||||
uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t carrier_low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
|
||||
uint32_t carrier_high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
|
||||
uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
|
||||
uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}carrier_duty_ch[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_lim: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/
|
||||
uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
}tx_lim_ch[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_fifo_mask: 1; /*Set this bit to disable apb fifo access*/
|
||||
uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
|
||||
uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
|
||||
@ -188,79 +188,79 @@ typedef volatile struct {
|
||||
}pin;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slv_rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
|
||||
uint32_t slv_wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
|
||||
uint32_t slv_rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
|
||||
uint32_t slv_wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
|
||||
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
|
||||
uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/
|
||||
uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/
|
||||
uint32_t reserved12: 5; /*reserved*/
|
||||
uint32_t slv_last_command: 3; /*In the slave mode it is the value of command.*/
|
||||
uint32_t slv_last_state: 3; /*In the slave mode it is the state of spi state machine.*/
|
||||
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/
|
||||
uint32_t slv_cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
|
||||
uint32_t slv_wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/
|
||||
uint32_t slv_wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/
|
||||
uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/
|
||||
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
|
||||
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
|
||||
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
|
||||
uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
|
||||
uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
|
||||
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
|
||||
uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/
|
||||
uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/
|
||||
uint32_t reserved12: 5; /*reserved*/
|
||||
uint32_t last_command: 3; /*In the slave mode it is the value of command.*/
|
||||
uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/
|
||||
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/
|
||||
uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
|
||||
uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/
|
||||
uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/
|
||||
uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/
|
||||
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}slave;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slv_rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
|
||||
uint32_t slv_wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
|
||||
uint32_t slv_rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
|
||||
uint32_t slv_wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
|
||||
uint32_t slv_wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
|
||||
uint32_t slv_rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved16: 9; /*reserved*/
|
||||
uint32_t slv_status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/
|
||||
uint32_t slv_status_fast_en: 1; /*In the slave mode enable fast read status.*/
|
||||
uint32_t slv_status_bitlen: 5; /*In the slave mode it is the length of status bit.*/
|
||||
uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
|
||||
uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
|
||||
uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
|
||||
uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
|
||||
uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
|
||||
uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved16: 9; /*reserved*/
|
||||
uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/
|
||||
uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/
|
||||
uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}slave1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slv_rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t slv_wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t slv_rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t slv_wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
}slave2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slv_rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/
|
||||
uint32_t slv_wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/
|
||||
uint32_t slv_rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/
|
||||
uint32_t slv_wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/
|
||||
uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/
|
||||
uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/
|
||||
uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/
|
||||
uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}slave3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slv_wrbuf_dbitlen:24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved24: 8; /*reserved*/
|
||||
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved24: 8; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}slv_wrbuf_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slv_rdbuf_dbitlen:24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved24: 8; /*reserved*/
|
||||
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved24: 8; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}slv_rdbuf_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
|
||||
uint32_t cache_usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
|
||||
uint32_t cache_flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
|
||||
uint32_t cache_flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
|
||||
uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
|
||||
uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
|
||||
uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}cache_fctrl;
|
||||
@ -282,27 +282,27 @@ typedef volatile struct {
|
||||
}cache_sctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
|
||||
uint32_t sram_qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
|
||||
uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
|
||||
uint32_t sram_rstio: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
|
||||
uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
|
||||
uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
|
||||
uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/
|
||||
uint32_t reserved5:27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}sram_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_sram_usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t cache_sram_usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
|
||||
uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
}sram_drd_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_sram_usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t cache_sram_usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
|
||||
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
}sram_dwr_cmd;
|
||||
@ -390,92 +390,92 @@ typedef volatile struct {
|
||||
}dma_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outlink_addr: 20; /*The address of the first outlink descriptor.*/
|
||||
uint32_t reserved20: 8; /*reserved*/
|
||||
uint32_t outlink_stop: 1; /*Set the bit to stop to use outlink descriptor.*/
|
||||
uint32_t outlink_start: 1; /*Set the bit to start to use outlink descriptor.*/
|
||||
uint32_t outlink_restart: 1; /*Set the bit to mount on new outlink descriptors.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
|
||||
uint32_t reserved20: 8; /*reserved*/
|
||||
uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/
|
||||
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
|
||||
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_out_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_addr: 20; /*The address of the first inlink descriptor.*/
|
||||
uint32_t inlink_auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/
|
||||
uint32_t reserved21: 7; /*reserved*/
|
||||
uint32_t inlink_stop: 1; /*Set the bit to stop to use inlink descriptor.*/
|
||||
uint32_t inlink_start: 1; /*Set the bit to start to use inlink descriptor.*/
|
||||
uint32_t inlink_restart: 1; /*Set the bit to mount on new inlink descriptors.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
|
||||
uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/
|
||||
uint32_t reserved21: 7; /*reserved*/
|
||||
uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/
|
||||
uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/
|
||||
uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_in_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dma_rx_en: 1; /*spi dma read data status bit.*/
|
||||
uint32_t dma_tx_en: 1; /*spi dma write data status bit.*/
|
||||
uint32_t rx_en: 1; /*spi dma read data status bit.*/
|
||||
uint32_t tx_en: 1; /*spi dma write data status bit.*/
|
||||
uint32_t reserved2: 30; /*spi dma read data from memory count.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_dscr_empty_int_ena: 1; /*The enable bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error_int_ena: 1; /*The enable bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error_int_ena: 1; /*The enable bit for inlink descriptor error.*/
|
||||
uint32_t in_done_int_ena: 1; /*The enable bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof_int_ena: 1; /*The enable bit for receiving error.*/
|
||||
uint32_t in_suc_eof_int_ena: 1; /*The enable bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done_int_ena: 1; /*The enable bit for completing usage of a outlink descriptor .*/
|
||||
uint32_t out_eof_int_ena: 1; /*The enable bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof_int_ena: 1; /*The enable bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
struct {_int_clr
|
||||
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
|
||||
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
|
||||
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
|
||||
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_dscr_empty_int_raw: 1; /*The raw bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error_int_raw: 1; /*The raw bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error_int_raw: 1; /*The raw bit for inlink descriptor error.*/
|
||||
uint32_t in_done_int_raw: 1; /*The raw bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof_int_raw: 1; /*The raw bit for receiving error.*/
|
||||
uint32_t in_suc_eof_int_raw: 1; /*The raw bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done_int_raw: 1; /*The raw bit for completing usage of a outlink descriptor.*/
|
||||
uint32_t out_eof_int_raw: 1; /*The raw bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof_int_raw: 1; /*The raw bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
|
||||
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
|
||||
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
|
||||
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_dscr_empty_int_st: 1; /*The status bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error_int_st: 1; /*The status bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error_int_st: 1; /*The status bit for inlink descriptor error.*/
|
||||
uint32_t in_done_int_st: 1; /*The status bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof_int_st: 1; /*The status bit for receiving error.*/
|
||||
uint32_t in_suc_eof_int_st: 1; /*The status bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done_int_st: 1; /*The status bit for completing usage of a outlink descriptor.*/
|
||||
uint32_t out_eof_int_st: 1; /*The status bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof_int_st: 1; /*The status bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/
|
||||
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
|
||||
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
|
||||
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_dscr_empty_int_clr: 1; /*The clear bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error_int_clr: 1; /*The clear bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error_int_clr: 1; /*The clear bit for inlink descriptor error.*/
|
||||
uint32_t in_done_int_clr: 1; /*The clear bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof_int_clr: 1; /*The clear bit for receiving error.*/
|
||||
uint32_t in_suc_eof_int_clr: 1; /*The clear bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done_int_clr: 1; /*The clear bit for completing usage of a outlink descriptor.*/
|
||||
uint32_t out_eof_int_clr: 1; /*The clear bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof_int_clr: 1; /*The clear bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
|
||||
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
|
||||
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
|
||||
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
|
||||
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
|
||||
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
|
||||
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
|
||||
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
|
||||
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_int_clr;
|
||||
|
||||
@ -28,35 +28,35 @@ typedef volatile struct {
|
||||
};
|
||||
uint32_t val;
|
||||
}config;
|
||||
uint32_t timer_cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
|
||||
uint32_t timer_cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
|
||||
uint32_t timer_update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
|
||||
uint32_t timer_alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
|
||||
uint32_t timer_alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
|
||||
uint32_t timer_load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
|
||||
uint32_t timer_load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
|
||||
uint32_t timer_reload; /*Write any value will trigger timer 0 time-base counter reload*/
|
||||
uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
|
||||
uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
|
||||
uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
|
||||
uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
|
||||
uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
|
||||
uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
|
||||
uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
|
||||
uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
|
||||
}hw_timer[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 14;
|
||||
uint32_t wdt_flashboot_mod_en: 1; /*When set flash boot protection is enabled*/
|
||||
uint32_t wdt_sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
|
||||
uint32_t wdt_cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
|
||||
uint32_t wdt_level_int_en: 1; /*When set level type interrupt generation is enabled*/
|
||||
uint32_t wdt_edge_int_en: 1; /*When set edge type interrupt generation is enabled*/
|
||||
uint32_t wdt_stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t wdt_stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t wdt_stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t wdt_stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t wdt_en: 1; /*When set SWDT is enabled*/
|
||||
uint32_t reserved0: 14;
|
||||
uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/
|
||||
uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
|
||||
uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
|
||||
uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/
|
||||
uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/
|
||||
uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
|
||||
uint32_t en: 1; /*When set SWDT is enabled*/
|
||||
};
|
||||
uint32_t val;
|
||||
}wdt_config0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16;
|
||||
uint32_t wdt_clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
|
||||
uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
|
||||
};
|
||||
uint32_t val;
|
||||
}wdt_config1;
|
||||
@ -69,41 +69,41 @@ typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 12;
|
||||
uint32_t rtc_cali_start_cycling: 1;
|
||||
uint32_t rtc_cali_clk_sel: 2;
|
||||
uint32_t rtc_cali_rdy: 1;
|
||||
uint32_t rtc_cali_max: 15;
|
||||
uint32_t rtc_cali_start: 1;
|
||||
uint32_t start_cycling: 1;
|
||||
uint32_t clk_sel: 2;
|
||||
uint32_t rdy: 1;
|
||||
uint32_t max: 15;
|
||||
uint32_t start: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
}rtc_cali_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t rtc_cali_value:25;
|
||||
uint32_t value:25;
|
||||
};
|
||||
uint32_t val;
|
||||
}rtc_cali_cfg1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t lact_rtc_only: 1;
|
||||
uint32_t lact_cpst_en: 1;
|
||||
uint32_t lact_lac_en: 1;
|
||||
uint32_t lact_alarm_en: 1;
|
||||
uint32_t lact_level_int_en: 1;
|
||||
uint32_t lact_edge_int_en: 1;
|
||||
uint32_t lact_divider: 16;
|
||||
uint32_t lact_autoreload: 1;
|
||||
uint32_t lact_increase: 1;
|
||||
uint32_t lact_en: 1;
|
||||
uint32_t rtc_only: 1;
|
||||
uint32_t cpst_en: 1;
|
||||
uint32_t lac_en: 1;
|
||||
uint32_t alarm_en: 1;
|
||||
uint32_t level_int_en: 1;
|
||||
uint32_t edge_int_en: 1;
|
||||
uint32_t divider: 16;
|
||||
uint32_t autoreload: 1;
|
||||
uint32_t increase: 1;
|
||||
uint32_t en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
}lactconfig;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 6;
|
||||
uint32_t lact_rtc_step_len:26;
|
||||
uint32_t step_len:26;
|
||||
};
|
||||
uint32_t val;
|
||||
}lactrtc;
|
||||
@ -117,41 +117,41 @@ typedef volatile struct {
|
||||
uint32_t lactload; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t t0_int_ena: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1_int_ena: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt_int_ena: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact_int_ena: 1;
|
||||
uint32_t reserved4: 28;
|
||||
uint32_t t0: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena_timers;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t t0_int_raw: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1_int_raw: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt_int_raw: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact_int_raw: 1;
|
||||
uint32_t reserved4: 28;
|
||||
uint32_t t0: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact: 1;
|
||||
uint32_t reserved4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw_timers;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t t0_int_st: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1_int_st: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt_int_st: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact_int_st: 1;
|
||||
uint32_t reserved4: 28;
|
||||
uint32_t t0: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st_timers;
|
||||
union {
|
||||
struct {
|
||||
uint32_t t0_int_clr: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1_int_clr: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt_int_clr: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact_int_clr: 1;
|
||||
uint32_t reserved4: 28;
|
||||
uint32_t t0: 1; /*interrupt when timer0 alarm*/
|
||||
uint32_t t1: 1; /*interrupt when timer1 alarm*/
|
||||
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
|
||||
uint32_t lact: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr_timers;
|
||||
@ -185,7 +185,7 @@ typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t clk_en: 1; /*Force clock enable for this regfile*/
|
||||
uint32_t en: 1; /*Force clock enable for this regfile*/
|
||||
};
|
||||
uint32_t val;
|
||||
}clk;
|
||||
|
||||
@ -16,122 +16,122 @@
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_rw_byte: 8; /*This register stores one byte data read by rx fifo.*/
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t rw_byte: 8; /*This register stores one byte data read by rx fifo.*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
}fifo;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
|
||||
uint32_t txfifo_empty_int_raw: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
|
||||
uint32_t parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
|
||||
uint32_t frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
|
||||
uint32_t rxfifo_ovf_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
|
||||
uint32_t dsr_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
|
||||
uint32_t cts_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
|
||||
uint32_t brk_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
|
||||
uint32_t rxfifo_tout_int_raw: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
|
||||
uint32_t sw_xon_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t sw_xoff_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t glitch_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
|
||||
uint32_t tx_brk_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/
|
||||
uint32_t tx_brk_idle_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/
|
||||
uint32_t tx_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
|
||||
uint32_t rs485_parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
|
||||
uint32_t rs485_frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
|
||||
uint32_t rs485_clash_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
|
||||
uint32_t at_cmd_char_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
|
||||
uint32_t reserved19: 13;
|
||||
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
|
||||
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
|
||||
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
|
||||
uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
|
||||
uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
|
||||
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
|
||||
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
|
||||
uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
|
||||
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
|
||||
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
|
||||
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/
|
||||
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/
|
||||
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
|
||||
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
|
||||
uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
|
||||
uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
|
||||
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full_int_st: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
|
||||
uint32_t txfifo_empty_int_st: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
|
||||
uint32_t parity_err_int_st: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
|
||||
uint32_t frm_err_int_st: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
|
||||
uint32_t rxfifo_ovf_int_st: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
|
||||
uint32_t dsr_chg_int_st: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
|
||||
uint32_t cts_chg_int_st: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
|
||||
uint32_t brk_det_int_st: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
|
||||
uint32_t rxfifo_tout_int_st: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
|
||||
uint32_t sw_xon_int_st: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
|
||||
uint32_t sw_xoff_int_st: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
|
||||
uint32_t glitch_det_int_st: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_done_int_st: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_idle_done_int_st: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
|
||||
uint32_t tx_done_int_st: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
|
||||
uint32_t rs485_parity_err_int_st: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
|
||||
uint32_t rs485_frm_err_int_st: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
|
||||
uint32_t rs485_clash_int_st: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
|
||||
uint32_t at_cmd_char_det_int_st: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
|
||||
uint32_t reserved19: 13;
|
||||
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
|
||||
uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
|
||||
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
|
||||
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
|
||||
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
|
||||
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
|
||||
uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
|
||||
uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
|
||||
uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
|
||||
uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
|
||||
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
|
||||
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
|
||||
uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
|
||||
uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
|
||||
uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
|
||||
uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
|
||||
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
|
||||
uint32_t txfifo_empty_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
|
||||
uint32_t parity_err_int_ena: 1; /*This is the enable bit for parity_err_int_st register.*/
|
||||
uint32_t frm_err_int_ena: 1; /*This is the enable bit for frm_err_int_st register.*/
|
||||
uint32_t rxfifo_ovf_int_ena: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
|
||||
uint32_t dsr_chg_int_ena: 1; /*This is the enable bit for dsr_chg_int_st register.*/
|
||||
uint32_t cts_chg_int_ena: 1; /*This is the enable bit for cts_chg_int_st register.*/
|
||||
uint32_t brk_det_int_ena: 1; /*This is the enable bit for brk_det_int_st register.*/
|
||||
uint32_t rxfifo_tout_int_ena: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
|
||||
uint32_t sw_xon_int_ena: 1; /*This is the enable bit for sw_xon_int_st register.*/
|
||||
uint32_t sw_xoff_int_ena: 1; /*This is the enable bit for sw_xoff_int_st register.*/
|
||||
uint32_t glitch_det_int_ena: 1; /*This is the enable bit for glitch_det_int_st register.*/
|
||||
uint32_t tx_brk_done_int_ena: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
|
||||
uint32_t tx_brk_idle_done_int_ena: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
|
||||
uint32_t tx_done_int_ena: 1; /*This is the enable bit for tx_done_int_st register.*/
|
||||
uint32_t rs485_parity_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
|
||||
uint32_t rs485_frm_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
|
||||
uint32_t rs485_clash_int_ena: 1; /*This is the enable bit for rs485_clash_int_st register.*/
|
||||
uint32_t at_cmd_char_det_int_ena: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
|
||||
uint32_t reserved19: 13;
|
||||
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
|
||||
uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
|
||||
uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/
|
||||
uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/
|
||||
uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
|
||||
uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/
|
||||
uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/
|
||||
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
|
||||
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
|
||||
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/
|
||||
uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/
|
||||
uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/
|
||||
uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
|
||||
uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
|
||||
uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/
|
||||
uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
|
||||
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
|
||||
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
|
||||
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full_int_clr: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
|
||||
uint32_t txfifo_empty_int_clr: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
|
||||
uint32_t parity_err_int_clr: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
|
||||
uint32_t frm_err_int_clr: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
|
||||
uint32_t rxfifo_ovf_int_clr: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
|
||||
uint32_t dsr_chg_int_clr: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
|
||||
uint32_t cts_chg_int_clr: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
|
||||
uint32_t brk_det_int_clr: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
|
||||
uint32_t rxfifo_tout_int_clr: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
|
||||
uint32_t sw_xon_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
|
||||
uint32_t sw_xoff_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
|
||||
uint32_t glitch_det_int_clr: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
|
||||
uint32_t tx_brk_done_int_clr: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
|
||||
uint32_t tx_brk_idle_done_int_clr: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
|
||||
uint32_t tx_done_int_clr: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
|
||||
uint32_t rs485_parity_err_int_clr: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
|
||||
uint32_t rs485_frm_err_int_clr: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
|
||||
uint32_t rs485_clash_int_clr: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
|
||||
uint32_t at_cmd_char_det_int_clr: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
|
||||
uint32_t reserved19: 13;
|
||||
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
|
||||
uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
|
||||
uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
|
||||
uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
|
||||
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
|
||||
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
|
||||
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
|
||||
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
|
||||
uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
|
||||
uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
|
||||
uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
|
||||
uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
|
||||
uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
|
||||
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
|
||||
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
|
||||
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
|
||||
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
|
||||
uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
|
||||
uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkdiv: 20; /*The register value is the integer part of the frequency divider's factor.*/
|
||||
uint32_t clkdiv_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/
|
||||
uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/
|
||||
uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}clk_div;
|
||||
union {
|
||||
struct {
|
||||
uint32_t auto_baud_en: 1; /*This is the enable bit for detecting baudrate.*/
|
||||
uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/
|
||||
uint32_t reserved1: 7;
|
||||
uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
|
||||
uint32_t reserved16: 16;
|
||||
@ -164,7 +164,7 @@ typedef volatile struct {
|
||||
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
|
||||
uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/
|
||||
uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/
|
||||
uint32_t irda_dplx: 1; /*Set this bit to enable irda loopback mode.*/
|
||||
uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/
|
||||
uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/
|
||||
uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
|
||||
uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/
|
||||
@ -202,21 +202,21 @@ typedef volatile struct {
|
||||
}conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lowpulse_min_cnt:20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
}lowpulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t highpulse_min_cnt:20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
}highpulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxd_edge_cnt:10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
|
||||
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -260,13 +260,13 @@ typedef volatile struct {
|
||||
}idle_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rs485_en: 1; /*Set this bit to choose rs485 mode.*/
|
||||
uint32_t en: 1; /*Set this bit to choose rs485 mode.*/
|
||||
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
|
||||
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
|
||||
uint32_t rs485tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
|
||||
uint32_t rs485rxby_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
|
||||
uint32_t rs485_rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
|
||||
uint32_t rs485_tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
|
||||
uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
|
||||
uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
|
||||
uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
|
||||
uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -294,7 +294,7 @@ typedef volatile struct {
|
||||
}at_cmd_gaptout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t at_cmd_char: 8; /*This register is used to configure the content of at_cmd char.*/
|
||||
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
|
||||
uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
@ -320,44 +320,44 @@ typedef volatile struct {
|
||||
}mem_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mem_tx_status:24;
|
||||
uint32_t status:24;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}mem_tx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mem_rx_status:24;
|
||||
uint32_t status:24;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}mem_rx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_mem_cnt: 3; /*refer to the rxfifo_cnt's description.*/
|
||||
uint32_t tx_mem_cnt: 3; /*refer to the txfifo_cnt's description.*/
|
||||
uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/
|
||||
uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
}mem_cnt_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t posedge_min_cnt:20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
}pospulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t negedge_min_cnt:20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
}negpulse;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t date; /**/
|
||||
uint32_t id; /**/
|
||||
uint32_t date; /**/
|
||||
uint32_t id; /**/
|
||||
} uart_dev_t;
|
||||
extern uart_dev_t UART0;
|
||||
extern uart_dev_t UART1;
|
||||
|
||||
@ -46,168 +46,168 @@ typedef volatile struct {
|
||||
}conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start_int_raw: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
|
||||
uint32_t tx_start_int_raw: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
|
||||
uint32_t rx_hung_int_raw: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
|
||||
uint32_t tx_hung_int_raw: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
|
||||
uint32_t in_done_int_raw: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
|
||||
uint32_t in_suc_eof_int_raw: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/
|
||||
uint32_t in_err_eof_int_raw: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/
|
||||
uint32_t out_done_int_raw: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/
|
||||
uint32_t out_eof_int_raw: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/
|
||||
uint32_t in_dscr_err_int_raw: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
|
||||
uint32_t out_dscr_err_int_raw: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/
|
||||
uint32_t in_dscr_empty_int_raw: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
|
||||
uint32_t outlink_eof_err_int_raw: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/
|
||||
uint32_t out_total_eof_int_raw: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
|
||||
uint32_t send_s_q_int_raw: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
|
||||
uint32_t send_a_q_int_raw: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
|
||||
uint32_t dma_infifo_full_wm_int_raw: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
|
||||
uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
|
||||
uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
|
||||
uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
|
||||
uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
|
||||
uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/
|
||||
uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/
|
||||
uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/
|
||||
uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/
|
||||
uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
|
||||
uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/
|
||||
uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
|
||||
uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/
|
||||
uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
|
||||
uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
|
||||
uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
|
||||
uint32_t dma_in_fifo_full_wm: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start_int_st: 1;
|
||||
uint32_t tx_start_int_st: 1;
|
||||
uint32_t rx_hung_int_st: 1;
|
||||
uint32_t tx_hung_int_st: 1;
|
||||
uint32_t in_done_int_st: 1;
|
||||
uint32_t in_suc_eof_int_st: 1;
|
||||
uint32_t in_err_eof_int_st: 1;
|
||||
uint32_t out_done_int_st: 1;
|
||||
uint32_t out_eof_int_st: 1;
|
||||
uint32_t in_dscr_err_int_st: 1;
|
||||
uint32_t out_dscr_err_int_st: 1;
|
||||
uint32_t in_dscr_empty_int_st: 1;
|
||||
uint32_t outlink_eof_err_int_st: 1;
|
||||
uint32_t out_total_eof_int_st: 1;
|
||||
uint32_t send_s_q_int_st: 1;
|
||||
uint32_t send_a_q_int_st: 1;
|
||||
uint32_t dma_infifo_full_wm_int_st: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t outlink_eof_err: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t send_s_q: 1;
|
||||
uint32_t send_a_q: 1;
|
||||
uint32_t dma_in_fifo_full_wm: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start_int_ena: 1;
|
||||
uint32_t tx_start_int_ena: 1;
|
||||
uint32_t rx_hung_int_ena: 1;
|
||||
uint32_t tx_hung_int_ena: 1;
|
||||
uint32_t in_done_int_ena: 1;
|
||||
uint32_t in_suc_eof_int_ena: 1;
|
||||
uint32_t in_err_eof_int_ena: 1;
|
||||
uint32_t out_done_int_ena: 1;
|
||||
uint32_t out_eof_int_ena: 1;
|
||||
uint32_t in_dscr_err_int_ena: 1;
|
||||
uint32_t out_dscr_err_int_ena: 1;
|
||||
uint32_t in_dscr_empty_int_ena: 1;
|
||||
uint32_t outlink_eof_err_int_ena: 1;
|
||||
uint32_t out_total_eof_int_ena: 1;
|
||||
uint32_t send_s_q_int_ena: 1;
|
||||
uint32_t send_a_q_int_ena: 1;
|
||||
uint32_t dma_infifo_full_wm_int_ena: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t outlink_eof_err: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t send_s_q: 1;
|
||||
uint32_t send_a_q: 1;
|
||||
uint32_t dma_in_fifo_full_wm: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start_int_clr: 1;
|
||||
uint32_t tx_start_int_clr: 1;
|
||||
uint32_t rx_hung_int_clr: 1;
|
||||
uint32_t tx_hung_int_clr: 1;
|
||||
uint32_t in_done_int_clr: 1;
|
||||
uint32_t in_suc_eof_int_clr: 1;
|
||||
uint32_t in_err_eof_int_clr: 1;
|
||||
uint32_t out_done_int_clr: 1;
|
||||
uint32_t out_eof_int_clr: 1;
|
||||
uint32_t in_dscr_err_int_clr: 1;
|
||||
uint32_t out_dscr_err_int_clr: 1;
|
||||
uint32_t in_dscr_empty_int_clr: 1;
|
||||
uint32_t outlink_eof_err_int_clr: 1;
|
||||
uint32_t out_total_eof_int_clr: 1;
|
||||
uint32_t send_s_q_int_clr: 1;
|
||||
uint32_t send_a_q_int_clr: 1;
|
||||
uint32_t dma_infifo_full_wm_int_clr: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_hung: 1;
|
||||
uint32_t tx_hung: 1;
|
||||
uint32_t in_done: 1;
|
||||
uint32_t in_suc_eof: 1;
|
||||
uint32_t in_err_eof: 1;
|
||||
uint32_t out_done: 1;
|
||||
uint32_t out_eof: 1;
|
||||
uint32_t in_dscr_err: 1;
|
||||
uint32_t out_dscr_err: 1;
|
||||
uint32_t in_dscr_empty: 1;
|
||||
uint32_t outlink_eof_err: 1;
|
||||
uint32_t out_total_eof: 1;
|
||||
uint32_t send_s_q: 1;
|
||||
uint32_t send_a_q: 1;
|
||||
uint32_t dma_in_fifo_full_wm: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_full: 1; /*1:DMA out link descriptor's fifo is full.*/
|
||||
uint32_t out_empty: 1; /*1:DMA in link descriptor's fifo is empty.*/
|
||||
uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/
|
||||
uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_out_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outfifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t outfifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/
|
||||
uint32_t reserved17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_out_push;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_full: 1;
|
||||
uint32_t in_empty: 1;
|
||||
uint32_t full: 1;
|
||||
uint32_t empty: 1;
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/
|
||||
uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_in_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_rdata:12; /*This register stores the data pop from in link descriptor's fifo.*/
|
||||
uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t infifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/
|
||||
uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_in_pop;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outlink_addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t outlink_stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/
|
||||
uint32_t outlink_start: 1; /*Set this bit to start dealing with the out link descriptors.*/
|
||||
uint32_t outlink_restart: 1; /*Set this bit to mount on new out link descriptors*/
|
||||
uint32_t outlink_park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
|
||||
uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/
|
||||
uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/
|
||||
uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/
|
||||
uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_out_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/
|
||||
uint32_t inlink_auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
|
||||
uint32_t reserved21: 7;
|
||||
uint32_t inlink_stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/
|
||||
uint32_t inlink_start: 1; /*Set this bit to start dealing with the in link descriptors.*/
|
||||
uint32_t inlink_restart: 1; /*Set this bit to mount on new in link descriptors*/
|
||||
uint32_t inlink_park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/
|
||||
uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/
|
||||
uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
|
||||
uint32_t reserved21: 7;
|
||||
uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/
|
||||
uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/
|
||||
uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/
|
||||
uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/
|
||||
};
|
||||
uint32_t val;
|
||||
}dma_in_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/
|
||||
uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/
|
||||
uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/
|
||||
uint32_t save_head: 1; /*Set this bit to save packet header .*/
|
||||
uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/
|
||||
uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/
|
||||
uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/
|
||||
uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/
|
||||
uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/
|
||||
uint32_t dma_infifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/
|
||||
uint32_t reserved21: 11;
|
||||
uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/
|
||||
uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/
|
||||
uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/
|
||||
uint32_t save_head: 1; /*Set this bit to save packet header .*/
|
||||
uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/
|
||||
uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/
|
||||
uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/
|
||||
uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/
|
||||
uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/
|
||||
uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
}conf1;
|
||||
@ -219,10 +219,10 @@ typedef volatile struct {
|
||||
uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t ahb_testmode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t ahb_testaddr: 2; /*The two bits represent ahb bus address bit[20:19]*/
|
||||
uint32_t reserved6: 26;
|
||||
uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
}ahb_test;
|
||||
@ -271,7 +271,7 @@ typedef volatile struct {
|
||||
uint32_t val;
|
||||
}quick_sent;
|
||||
struct{
|
||||
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
|
||||
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
|
||||
}q_data[7];
|
||||
union {
|
||||
struct {
|
||||
@ -284,34 +284,34 @@ typedef volatile struct {
|
||||
}esc_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t esc_seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/
|
||||
uint32_t esc_seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/
|
||||
uint32_t esc_seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/
|
||||
uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/
|
||||
uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}esc_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t esc_seq1: 8; /*This register stores the flow control char to turn on the flow_control*/
|
||||
uint32_t esc_seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/
|
||||
uint32_t esc_seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/
|
||||
uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/
|
||||
uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}esc_conf2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t esc_seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/
|
||||
uint32_t esc_seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/
|
||||
uint32_t esc_seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/
|
||||
uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/
|
||||
uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
}esc_conf3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pkt_thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
|
||||
uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
|
||||
uint32_t reserved13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user