Merge branch 'bugfix/timer_intr_status_get' into 'master'

bugfix(timer): fix get intr status function

See merge request espressif/esp-idf!6807

components/driver/timer.c

@@ -82,13 +82,10 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
     if (err == ESP_OK) {
         uint16_t div;
         timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
-#ifdef CONFIG_IDF_TARGET_ESP32
-        *time = (double)timer_val * div / TIMER_BASE_CLK;
-#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
+        *time = (double)timer_val * div / rtc_clk_apb_freq_get();
+#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
         if (timer_hal_get_use_xtal(&(p_timer_obj[group_num][timer_num]->hal))) {
             *time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
-        } else {
-            *time = (double)timer_val * div / rtc_clk_apb_freq_get();
         }
 #endif
     }
@@ -327,7 +324,7 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
     //     timer_hal_set_edge_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
     // }
     timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), config->counter_en);
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
     timer_hal_set_use_xtal(&(p_timer_obj[group_num][timer_num]->hal), config->clk_src);
 #endif
     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
@@ -436,7 +433,9 @@ esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
 /* This function is deprecated */
 timer_intr_t IRAM_ATTR timer_group_intr_get_in_isr(timer_group_t group_num)
 {
-    return timer_group_get_intr_status_in_isr(group_num);
+    uint32_t intr_raw_status = 0;
+    timer_hal_get_intr_raw_status(group_num, &intr_raw_status);
+    return intr_raw_status;
 }
 
 uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)

components/soc/esp32/include/hal/timer_ll.h

@@ -296,6 +296,20 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
     *intr_status = hw->int_st_timers.val;
 }
 
+/**
+ * @brief Get interrupt raw status.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param intr_raw_status Interrupt raw status
+ *
+ * @return None
+ */
+FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
+{
+    timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
+    *intr_raw_status = hw->int_raw.val;
+}
+
 /**
  * @brief Set the level interrupt status, enable or disable the level interrupt.
  *

components/soc/esp32/include/soc/timer_group_caps.h

@@ -0,0 +1,15 @@
+// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once

components/soc/esp32s2beta/include/hal/timer_ll.h

@@ -296,6 +296,20 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
     *intr_status = hw->int_st.val;
 }
 
+/**
+ * @brief Get interrupt raw status.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param intr_raw_status Interrupt raw status
+ *
+ * @return None
+ */
+FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
+{
+    timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
+    *intr_raw_status = hw->int_raw.val;
+}
+
 /**
  * @brief Set the level interrupt status, enable or disable the level interrupt.
  *

components/soc/esp32s2beta/include/soc/timer_group_caps.h

@@ -0,0 +1,17 @@
+// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define TIMER_GROUP_SUPPORTS_XTAL_CLOCK

components/soc/include/hal/timer_hal.h

@@ -29,6 +29,7 @@ extern "C" {
 
 #include "hal/timer_ll.h"
 #include "hal/timer_types.h"
+#include "soc/timer_group_caps.h"
 
 /**
  * Context that should be maintained by both the driver and the HAL
@@ -273,6 +274,16 @@ void timer_hal_init(timer_hal_context_t *hal, timer_group_t group_num, timer_idx
  */
 #define timer_hal_get_intr_status(hal, intr_status)  timer_ll_get_intr_status((hal)->dev, intr_status)
 
+/**
+ * @brief Get interrupt raw status.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param intr_raw_status Interrupt raw status
+ *
+ * @return None
+ */
+#define timer_hal_get_intr_raw_status(group_num, intr_raw_status)  timer_ll_get_intr_raw_status(group_num, intr_raw_status)
+
 /**
  * @brief Get interrupt status register address.
  *
@@ -283,7 +294,7 @@ void timer_hal_init(timer_hal_context_t *hal, timer_group_t group_num, timer_idx
  */
 #define timer_hal_get_intr_status_reg(hal, intr_status_reg)  timer_ll_get_intr_status_reg((hal)->dev, intr_status_reg)
 
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
 /**
  * @brief Set clock source.
  *

components/soc/include/hal/timer_types.h

@@ -21,6 +21,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include <esp_bit_defs.h>
+#include "soc/timer_group_caps.h"
 
 /**
  * @brief Selects a Timer-Group out of 2 available groups
@@ -107,7 +108,7 @@ typedef enum {
     TIMER_AUTORELOAD_MAX,
 } timer_autoreload_t;
 
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
 /**
  * @brief Select timer source clock.
  */
@@ -127,7 +128,7 @@ typedef struct {
     timer_count_dir_t counter_dir; /*!< Counter direction  */
     timer_autoreload_t auto_reload;   /*!< Timer auto-reload */
     uint32_t divider;   /*!< Counter clock divider. The divider's range is from from 2 to 65536. */
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
     timer_src_clk_t clk_src;  /*!< Use XTAL as source clock. */
 #endif
 } timer_config_t;

examples/peripherals/timer_group/main/timer_group_example_main.c

@@ -111,7 +111,7 @@ static void example_tg0_timer_init(int timer_idx,
     config.alarm_en = TIMER_ALARM_EN;
     config.intr_type = TIMER_INTR_LEVEL;
     config.auto_reload = auto_reload;
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
     config.clk_src = TIMER_SRC_CLK_APB;
 #endif
     timer_init(TIMER_GROUP_0, timer_idx, &config);