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Merge branch 'test/fix_psram_readid_redundant' into 'master'

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spiram: fix the read id failure

See merge request espressif/esp-idf!9275
This commit is contained in:
Michael (XIAO Xufeng) 2020-06-24 00:34:59 +08:00
commit 91310381d5
2 changed files with 28 additions and 22 deletions
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19
components/esp32/spiram_psram.c
View File

@ -397,11 +397,9 @@ static void psram_disable_qio_mode(psram_spi_num_t spi_num)
psram_cmd_end(spi_num);
}
//read psram id
static void psram_read_id(uint64_t* dev_id)
//read psram id, should issue `psram_disable_qio_mode` before calling this
static void psram_read_id(psram_spi_num_t spi_num, uint64_t* dev_id)
{
psram_spi_num_t spi_num = PSRAM_SPI_1;
psram_disable_qio_mode(spi_num);
uint32_t dummy_bits = 0 + extra_dummy;
uint32_t psram_id[2] = {0};
psram_cmd_t ps_cmd;
@ -901,15 +899,20 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
// GPIO related settings
psram_gpio_config(&psram_io, mode);
/* 16Mbit psram ID read error
* workaround: Issue a pre-condition of dummy read id, then Read ID command
psram_spi_num_t spi_num = PSRAM_SPI_1;
psram_disable_qio_mode(spi_num);
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
/* 16Mbit psram ID read error workaround:
* treat the first read id as a dummy one as the pre-condition,
* Send Read ID command again
*/
psram_read_id(&s_psram_id);
psram_read_id(&s_psram_id);
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id);
return ESP_FAIL;
}
}
if (psram_is_32mbit_ver0()) {
s_clk_mode = PSRAM_CLK_MODE_DCLK;

19
components/esp32s2/spiram_psram.c
View File

@ -306,11 +306,9 @@ bool psram_support_wrap_size(uint32_t wrap_size)
}
//read psram id
static void psram_read_id(uint32_t* dev_id)
//read psram id, should issue `psram_disable_qio_mode` before calling this
static void psram_read_id(int spi_num, uint32_t* dev_id)
{
int spi_num = PSRAM_SPI_1;
psram_disable_qio_mode(spi_num);
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
0, 24, /* address and address bit len*/
@ -433,15 +431,20 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
/* 16Mbit psram ID read error
* workaround: Issue a pre-condition of dummy read id, then Read ID command
int spi_num = PSRAM_SPI_1;
psram_disable_qio_mode(spi_num);
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
/* 16Mbit psram ID read error workaround:
* treat the first read id as a dummy one as the pre-condition,
* Send Read ID command again
*/
psram_read_id(&s_psram_id);
psram_read_id(&s_psram_id);
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
return ESP_FAIL;
}
}
psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX;
if (psram_is_32mbit_ver0()) {