From 911c388cf849b8f9b5e622387eb6f45d6bab3b9e Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 15 Aug 2023 18:43:19 +0800 Subject: [PATCH] feat(etm): add core driver support for esp32-p4 esp_etm core driver support: - channel allocator - gpio etm sub driver - gptimer etm sub driver --- components/esp_hw_support/esp_etm.c | 22 +- .../test_apps/etm/main/test_gptimer_etm.c | 6 +- components/hal/esp32c6/include/hal/etm_ll.h | 24 +- components/hal/esp32h2/include/hal/etm_ll.h | 22 +- components/hal/esp32p4/include/hal/etm_ll.h | 126 + .../hal/esp32p4/include/hal/gpio_etm_ll.h | 119 + components/hal/esp32p4/include/hal/timer_ll.h | 56 + .../esp32p4/include/soc/Kconfig.soc_caps.in | 12 + .../soc/esp32p4/include/soc/gpio_ext_struct.h | 655 +-- components/soc/esp32p4/include/soc/soc_caps.h | 7 +- .../soc/esp32p4/include/soc/soc_etm_struct.h | 3596 +++++------------ 11 files changed, 1468 insertions(+), 3177 deletions(-) create mode 100644 components/hal/esp32p4/include/hal/etm_ll.h create mode 100644 components/hal/esp32p4/include/hal/gpio_etm_ll.h diff --git a/components/esp_hw_support/esp_etm.c b/components/esp_hw_support/esp_etm.c index 4cced5763e..9dfbfc6cb4 100644 --- a/components/esp_hw_support/esp_etm.c +++ b/components/esp_hw_support/esp_etm.c @@ -28,6 +28,13 @@ #define ETM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT +#if CONFIG_IDF_TARGET_ESP32P4 +// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section +#define ETM_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define ETM_RCC_ATOMIC() +#endif + static const char *TAG = "etm"; typedef struct etm_platform_t etm_platform_t; @@ -78,10 +85,12 @@ static etm_group_t *etm_acquire_group_handle(int group_id) // initialize ETM group members group->group_id = group_id; group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; - // enable APB access ETM registers - // if we have multiple ETM groups/instances, we assume the peripheral defines are continuous - periph_module_enable(PERIPH_ETM_MODULE + group_id); - periph_module_reset(PERIPH_ETM_MODULE + group_id); + // enable bus clock for the ETM registers + ETM_RCC_ATOMIC() { + etm_ll_enable_bus_clock(group_id, true); + etm_ll_reset_register(group_id); + } + // initialize HAL context etm_hal_init(&group->hal); } @@ -112,7 +121,10 @@ static void etm_release_group_handle(etm_group_t *group) assert(s_platform.groups[group_id]); do_deinitialize = true; s_platform.groups[group_id] = NULL; // deregister from platform - periph_module_disable(PERIPH_ETM_MODULE + group_id); + // disable the bus clock for the ETM registers + ETM_RCC_ATOMIC() { + etm_ll_enable_bus_clock(group_id, false); + } } _lock_release(&s_platform.mutex); diff --git a/components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c b/components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c index e6c752c12e..536a6e18ad 100644 --- a/components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c +++ b/components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c @@ -342,7 +342,7 @@ TEST_CASE("gptimer_etm_task_capture", "[etm]") TEST_ESP_OK(gptimer_enable(gptimer)); TEST_ESP_OK(gptimer_start(gptimer)); - vTaskDelay(pdMS_TO_TICKS(500)); + esp_rom_delay_us(500 * 1000); // simulate the edge signal by software TEST_ESP_OK(gpio_set_level(input_gpio, 1)); @@ -432,7 +432,7 @@ TEST_CASE("gptimer_start_stop_by_etm_task", "[etm]") // trigger an pos-edge, this should start the gptimer TEST_ESP_OK(gpio_set_level(input_gpio, 1)); - vTaskDelay(pdMS_TO_TICKS(500)); + esp_rom_delay_us(500 * 1000); uint64_t cur_count_val = 0; TEST_ESP_OK(gptimer_get_raw_count(gptimer, &cur_count_val)); printf("cur_count_val: %llu\r\n", cur_count_val); @@ -442,7 +442,7 @@ TEST_CASE("gptimer_start_stop_by_etm_task", "[etm]") TEST_ESP_OK(gpio_set_level(input_gpio, 0)); uint64_t count_val_0 = 0; TEST_ESP_OK(gptimer_get_raw_count(gptimer, &count_val_0)); - vTaskDelay(pdMS_TO_TICKS(500)); + esp_rom_delay_us(500 * 1000); uint64_t count_val_1 = 0; TEST_ESP_OK(gptimer_get_raw_count(gptimer, &count_val_1)); TEST_ASSERT_EQUAL(count_val_0, count_val_1); diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h index 9d95b485c2..22bc835177 100644 --- a/components/hal/esp32c6/include/hal/etm_ll.h +++ b/components/hal/esp32c6/include/hal/etm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,20 +12,34 @@ #include "hal/assert.h" #include "hal/misc.h" #include "soc/soc_etm_struct.h" +#include "soc/pcr_struct.h" #ifdef __cplusplus extern "C" { #endif /** - * @brief Enable the clock for ETM module + * @brief Enable the clock for ETM register * - * @param hw ETM register base address + * @param group_id Group ID * @param enable true to enable, false to disable */ -static inline void etm_ll_enable_clock(soc_etm_dev_t *hw, bool enable) +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) { - hw->clk_en.clk_en = enable; + (void)group_id; + PCR.etm_conf.etm_clk_en = enable; +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.etm_conf.etm_rst_en = 1; + PCR.etm_conf.etm_rst_en = 0; } /** diff --git a/components/hal/esp32h2/include/hal/etm_ll.h b/components/hal/esp32h2/include/hal/etm_ll.h index e15a77f4a2..9d341ae2ed 100644 --- a/components/hal/esp32h2/include/hal/etm_ll.h +++ b/components/hal/esp32h2/include/hal/etm_ll.h @@ -12,20 +12,34 @@ #include "hal/assert.h" #include "hal/misc.h" #include "soc/soc_etm_struct.h" +#include "soc/pcr_struct.h" #ifdef __cplusplus extern "C" { #endif /** - * @brief Enable the clock for ETM module + * @brief Enable the clock for ETM register * - * @param hw ETM register base address + * @param group_id Group ID * @param enable true to enable, false to disable */ -static inline void etm_ll_enable_clock(soc_etm_dev_t *hw, bool enable) +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) { - hw->clk_en.clk_en = enable; + (void)group_id; + PCR.etm_conf.etm_clk_en = enable; +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.etm_conf.etm_rst_en = 1; + PCR.etm_conf.etm_rst_en = 0; } /** diff --git a/components/hal/esp32p4/include/hal/etm_ll.h b/components/hal/esp32p4/include/hal/etm_ll.h new file mode 100644 index 0000000000..fa1dcae8c1 --- /dev/null +++ b/components/hal/esp32p4/include/hal/etm_ll.h @@ -0,0 +1,126 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/soc_etm_struct.h" +#include "soc/hp_sys_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for ETM module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.soc_clk_ctrl3.reg_etm_apb_clk_en = enable; + HP_SYS_CLKRST.soc_clk_ctrl1.reg_etm_sys_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the ETM module + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_etm = 1; + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_etm = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define etm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_reset_register(__VA_ARGS__) + +/** + * @brief Enable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_set.val = 1 << chan; + } else { + hw->ch_ena_ad1_set.val = 1 << (chan - 32); + } +} + +/** + * @brief Disable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_clr.val = 1 << chan; + } else { + hw->ch_ena_ad1_clr.val = 1 << (chan - 32); + } +} + +/** + * @brief Check whether the ETM channel is enabled or not + * + * @param hw ETM register base address + * @param chan Channel ID + * @return true if the channel is enabled, false otherwise + */ +static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + return hw->ch_ena_ad0.val & (1 << chan); + } else { + return hw->ch_ena_ad1.val & (1 << (chan - 32)); + } +} + +/** + * @brief Set the input event for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param event Event ID + */ +static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) +{ + hw->channel[chan].evt_id.evt_id = event; +} + +/** + * @brief Set the output task for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param task Task ID + */ +static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) +{ + hw->channel[chan].task_id.task_id = task; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/gpio_etm_ll.h b/components/hal/esp32p4/include/hal/gpio_etm_ll.h new file mode 100644 index 0000000000..57101ba37f --- /dev/null +++ b/components/hal/esp32p4/include/hal/gpio_etm_ll.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/gpio_ext_struct.h" +#include "soc/soc_etm_source.h" + +#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) + +#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) +#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) +#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set which GPIO to be bounded to the event channel + * + * @param dev Register base address + * @param chan Channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num; +} + +/** + * @brief Wether to enable the event channel + * + * @param dev Register base address + * @param chan Channel number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable; +} + +/** + * @brief Set which GPIO to be bounded to the task channel + * + * @note One channel can be bounded to multiple different GPIOs + * + * @param dev Register base address + * @param chan Channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) +{ + int g_p = gpio_num / 4; + int g_idx = gpio_num % 4; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x07 << (g_idx * 8 + 1)); + reg_val |= ((chan & 0x07) << (g_idx * 8 + 1)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Wether to enable the GPIO to be managed by the task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) +{ + int g_p = gpio_num / 4; + int g_idx = gpio_num % 4; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x01 << (g_idx * 8)); + reg_val |= ((enable & 0x01) << (g_idx * 8)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Check whether a GPIO has been enabled and managed by a task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return True if enabled, false otherwise + */ +static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 4; + int g_idx = gpio_num % 4; + return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 8)); +} + +/** + * @brief Get the channel number that the GPIO is bounded to + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return GPIO ETM Task channel number + */ +static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 4; + int g_idx = gpio_num % 4; + return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 8 + 1)) & 0x07; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/timer_ll.h b/components/hal/esp32p4/include/hal/timer_ll.h index d886e30ce9..60ed09bfc6 100644 --- a/components/hal/esp32p4/include/hal/timer_ll.h +++ b/components/hal/esp32p4/include/hal/timer_ll.h @@ -24,6 +24,62 @@ extern "C" { #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) +#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ + (uint32_t[2][2][GPTIMER_ETM_TASK_MAX]){ \ + { \ + { \ + [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER0, \ + }, \ + { \ + [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER1, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER1, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER1, \ + [GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER1, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER1, \ + }, \ + }, \ + { \ + { \ + [GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER0, \ + }, \ + { \ + [GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER1, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER1, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER1, \ + [GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER1, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER1, \ + }, \ + }, \ + }[group][timer][task] + +#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event) \ + (uint32_t[2][2][GPTIMER_ETM_EVENT_MAX]){ \ + { \ + { \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER0, \ + }, \ + { \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER1, \ + }, \ + }, \ + { \ + { \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER0, \ + }, \ + { \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER1, \ + }, \ + }, \ + }[group][timer][event] + /** * @brief Enable the bus clock for timer group module * diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 6b8cac1893..845e9e611d 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -31,6 +31,10 @@ config SOC_MCPWM_SUPPORTED bool default y +config SOC_ETM_SUPPORTED + bool + default y + config SOC_ASYNC_MEMCPY_SUPPORTED bool default y @@ -271,6 +275,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y +config SOC_GPIO_SUPPORT_ETM + bool + default y + config SOC_GPIO_ETM_EVENTS_PER_GROUP int default 8 @@ -827,6 +835,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS int default 4 +config SOC_TIMER_SUPPORT_ETM + bool + default y + config SOC_TWAI_CONTROLLER_NUM int default 2 diff --git a/components/soc/esp32p4/include/soc/gpio_ext_struct.h b/components/soc/esp32p4/include/soc/gpio_ext_struct.h index c4ea00e07a..c11b0cdec2 100644 --- a/components/soc/esp32p4/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32p4/include/soc/gpio_ext_struct.h @@ -19,12 +19,12 @@ typedef union { /** duty : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ - uint32_t duty:8; + uint32_t duty: 8; /** prescale : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ - uint32_t prescale:8; - uint32_t reserved_16:16; + uint32_t prescale: 8; + uint32_t reserved_16: 16; }; uint32_t val; } gpio_sigmadelta_chn_reg_t; @@ -34,20 +34,19 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:30; + uint32_t reserved_0: 30; /** function_clk_en : R/W; bitpos: [30]; default: 0; * Clock enable bit of sigma delta modulation. */ - uint32_t function_clk_en:1; + uint32_t function_clk_en: 1; /** spi_swap : R/W; bitpos: [31]; default: 0; * Reserved. */ - uint32_t spi_swap:1; + uint32_t spi_swap: 1; }; uint32_t val; } gpio_sigmadelta_misc_reg_t; - /** Group: Glitch filter Configure Registers */ /** Type of glitch_filter_chn register * Glitch Filter Configure Register of Channeln @@ -57,25 +56,24 @@ typedef union { /** filter_chn_en : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ - uint32_t filter_chn_en:1; + uint32_t filter_chn_en: 1; /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ - uint32_t filter_chn_input_io_num:6; + uint32_t filter_chn_input_io_num: 6; /** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ - uint32_t filter_chn_window_thres:6; + uint32_t filter_chn_window_thres: 6; /** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ - uint32_t filter_chn_window_width:6; - uint32_t reserved_19:13; + uint32_t filter_chn_window_width: 6; + uint32_t reserved_19: 13; }; uint32_t val; } gpio_glitch_filter_chn_reg_t; - /** Group: Etm Configure Registers */ /** Type of etm_event_chn_cfg register * Etm Config register of Channeln @@ -85,13 +83,13 @@ typedef union { /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ - uint32_t etm_chn_event_sel:6; - uint32_t reserved_6:1; + uint32_t etm_chn_event_sel: 6; + uint32_t reserved_6: 1; /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ - uint32_t etm_chn_event_en:1; - uint32_t reserved_8:24; + uint32_t etm_chn_event_en: 1; + uint32_t reserved_8: 24; }; uint32_t val; } gpio_etm_event_chn_cfg_reg_t; @@ -104,619 +102,42 @@ typedef union { /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ - uint32_t etm_task_gpio0_en:1; + uint32_t etm_task_gpio0_en: 1; /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ - uint32_t etm_task_gpio0_sel:3; - uint32_t reserved_4:4; + uint32_t etm_task_gpio0_sel: 3; + uint32_t reserved_4: 4; /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ - uint32_t etm_task_gpio1_en:1; + uint32_t etm_task_gpio1_en: 1; /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ - uint32_t etm_task_gpio1_sel:3; - uint32_t reserved_12:4; + uint32_t etm_task_gpio1_sel: 3; + uint32_t reserved_12: 4; /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ - uint32_t etm_task_gpio2_en:1; + uint32_t etm_task_gpio2_en: 1; /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ - uint32_t etm_task_gpio2_sel:3; - uint32_t reserved_20:4; + uint32_t etm_task_gpio2_sel: 3; + uint32_t reserved_20: 4; /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ - uint32_t etm_task_gpio3_en:1; + uint32_t etm_task_gpio3_en: 1; /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ - uint32_t etm_task_gpio3_sel:3; - uint32_t reserved_28:4; + uint32_t etm_task_gpio3_sel: 3; + uint32_t reserved_28: 4; }; uint32_t val; -} gpio_etm_task_p0_cfg_reg_t; - -/** Type of etm_task_p1_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio4_en:1; - /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio4_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio5_en:1; - /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio5_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio6_en:1; - /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio6_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio7_en:1; - /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio7_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p1_cfg_reg_t; - -/** Type of etm_task_p2_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio8_en:1; - /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio8_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio9_en:1; - /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio9_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio10_en:1; - /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio10_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio11_en:1; - /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio11_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p2_cfg_reg_t; - -/** Type of etm_task_p3_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio12_en:1; - /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio12_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio13_en:1; - /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio13_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio14_en:1; - /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio14_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio15_en:1; - /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio15_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p3_cfg_reg_t; - -/** Type of etm_task_p4_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio16_en:1; - /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio16_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio17_en:1; - /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio17_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio18_en:1; - /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio18_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio19_en:1; - /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio19_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p4_cfg_reg_t; - -/** Type of etm_task_p5_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio20_en:1; - /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio20_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio21_en:1; - /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio21_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio22_en:1; - /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio22_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio23_en:1; - /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio23_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p5_cfg_reg_t; - -/** Type of etm_task_p6_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio24_en:1; - /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio24_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio25_en:1; - /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio25_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio26_en:1; - /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio26_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio27_en:1; - /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio27_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p6_cfg_reg_t; - -/** Type of etm_task_p7_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio28_en:1; - /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio28_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio29_en:1; - /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio29_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio30_en:1; - /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio30_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio31_en:1; - /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio31_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p7_cfg_reg_t; - -/** Type of etm_task_p8_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio32_en:1; - /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio32_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio33_en:1; - /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio33_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio34_en:1; - /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio34_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio35_en:1; - /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio35_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p8_cfg_reg_t; - -/** Type of etm_task_p9_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio36_en:1; - /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio36_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio37_en:1; - /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio37_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio38_en:1; - /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio38_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio39_en:1; - /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio39_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p9_cfg_reg_t; - -/** Type of etm_task_p10_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio40_en:1; - /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio40_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio41_en:1; - /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio41_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio42_en:1; - /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio42_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio43_en:1; - /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio43_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p10_cfg_reg_t; - -/** Type of etm_task_p11_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio44_en:1; - /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio44_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio45_en:1; - /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio45_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio46_en:1; - /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio46_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio47_en:1; - /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio47_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p11_cfg_reg_t; - -/** Type of etm_task_p12_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio48_en:1; - /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio48_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio49_en:1; - /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio49_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio50_en:1; - /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio50_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio51_en:1; - /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio51_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_etm_task_p12_cfg_reg_t; - -/** Type of etm_task_p13_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio52_en:1; - /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio52_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio53_en:1; - /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio53_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio54_en:1; - /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio54_sel:3; - uint32_t reserved_20:12; - }; - uint32_t val; -} gpio_etm_task_p13_cfg_reg_t; - +} gpio_etm_task_pn_cfg_reg_t; /** Group: Version Register */ /** Type of version register @@ -727,13 +148,12 @@ typedef union { /** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952; * Version control register. */ - uint32_t gpio_ext_date:28; - uint32_t reserved_28:4; + uint32_t gpio_ext_date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } gpio_ext_version_reg_t; - typedef struct gpio_sd_dev_t { volatile gpio_sigmadelta_chn_reg_t channel[8]; uint32_t reserved_020; @@ -747,20 +167,7 @@ typedef struct gpio_glitch_filter_dev_t { typedef struct gpio_etm_dev_t { volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; uint32_t reserved_080[8]; - volatile gpio_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpio_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpio_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpio_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpio_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpio_etm_task_p5_cfg_reg_t etm_task_p5_cfg; - volatile gpio_etm_task_p6_cfg_reg_t etm_task_p6_cfg; - volatile gpio_etm_task_p7_cfg_reg_t etm_task_p7_cfg; - volatile gpio_etm_task_p8_cfg_reg_t etm_task_p8_cfg; - volatile gpio_etm_task_p9_cfg_reg_t etm_task_p9_cfg; - volatile gpio_etm_task_p10_cfg_reg_t etm_task_p10_cfg; - volatile gpio_etm_task_p11_cfg_reg_t etm_task_p11_cfg; - volatile gpio_etm_task_p12_cfg_reg_t etm_task_p12_cfg; - volatile gpio_etm_task_p13_cfg_reg_t etm_task_p13_cfg; + volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[14]; } gpio_etm_dev_t; typedef struct { diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index b280502efc..2971e0a99d 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -36,7 +36,7 @@ #define SOC_PCNT_SUPPORTED 1 #define SOC_MCPWM_SUPPORTED 1 // #define SOC_TWAI_SUPPORTED 1 //TODO: IDF-7470 -// #define SOC_ETM_SUPPORTED 1 //TODO: IDF-7478 +#define SOC_ETM_SUPPORTED 1 // #define SOC_PARLIO_SUPPORTED 1 //TODO: IDF-7471, TODO: IDF-7472 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // disable usb serial jtag for esp32p4, current image does not support @@ -162,7 +162,7 @@ #define SOC_GDMA_NUM_GROUPS_MAX 2 #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 #define SOC_AXI_GDMA_SUPPORT_PSRAM 1 -// #define SOC_GDMA_SUPPORT_ETM 1 // Both AHB-DMA and AXI-DMA supports ETM //TODO: IDF-7478 +// #define SOC_GDMA_SUPPORT_ETM 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups @@ -177,7 +177,7 @@ #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension -// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: IDF-7841 +#define SOC_GPIO_SUPPORT_ETM 1 #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 @@ -408,6 +408,7 @@ #define SOC_TIMER_GROUP_SUPPORT_XTAL 1 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST 1 #define SOC_TIMER_GROUP_TOTAL_TIMERS 4 +#define SOC_TIMER_SUPPORT_ETM 1 /*-------------------------- TWAI CAPS ---------------------------------------*/ #define SOC_TWAI_CONTROLLER_NUM 2 diff --git a/components/soc/esp32p4/include/soc/soc_etm_struct.h b/components/soc/esp32p4/include/soc/soc_etm_struct.h index ad4a7df3c7..93090a023d 100644 --- a/components/soc/esp32p4/include/soc/soc_etm_struct.h +++ b/components/soc/esp32p4/include/soc/soc_etm_struct.h @@ -19,131 +19,131 @@ typedef union { /** ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0; * Represents ch0 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena0:1; + uint32_t ch_ena0: 1; /** ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0; * Represents ch1 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena1:1; + uint32_t ch_ena1: 1; /** ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0; * Represents ch2 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena2:1; + uint32_t ch_ena2: 1; /** ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0; * Represents ch3 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena3:1; + uint32_t ch_ena3: 1; /** ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0; * Represents ch4 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena4:1; + uint32_t ch_ena4: 1; /** ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0; * Represents ch5 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena5:1; + uint32_t ch_ena5: 1; /** ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0; * Represents ch6 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena6:1; + uint32_t ch_ena6: 1; /** ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0; * Represents ch7 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena7:1; + uint32_t ch_ena7: 1; /** ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0; * Represents ch8 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena8:1; + uint32_t ch_ena8: 1; /** ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0; * Represents ch9 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena9:1; + uint32_t ch_ena9: 1; /** ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0; * Represents ch10 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena10:1; + uint32_t ch_ena10: 1; /** ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0; * Represents ch11 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena11:1; + uint32_t ch_ena11: 1; /** ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0; * Represents ch12 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena12:1; + uint32_t ch_ena12: 1; /** ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0; * Represents ch13 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena13:1; + uint32_t ch_ena13: 1; /** ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0; * Represents ch14 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena14:1; + uint32_t ch_ena14: 1; /** ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0; * Represents ch15 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena15:1; + uint32_t ch_ena15: 1; /** ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0; * Represents ch16 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena16:1; + uint32_t ch_ena16: 1; /** ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0; * Represents ch17 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena17:1; + uint32_t ch_ena17: 1; /** ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0; * Represents ch18 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena18:1; + uint32_t ch_ena18: 1; /** ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0; * Represents ch19 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena19:1; + uint32_t ch_ena19: 1; /** ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0; * Represents ch20 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena20:1; + uint32_t ch_ena20: 1; /** ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0; * Represents ch21 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena21:1; + uint32_t ch_ena21: 1; /** ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0; * Represents ch22 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena22:1; + uint32_t ch_ena22: 1; /** ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0; * Represents ch23 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena23:1; + uint32_t ch_ena23: 1; /** ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0; * Represents ch24 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena24:1; + uint32_t ch_ena24: 1; /** ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0; * Represents ch25 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena25:1; + uint32_t ch_ena25: 1; /** ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0; * Represents ch26 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena26:1; + uint32_t ch_ena26: 1; /** ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0; * Represents ch27 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena27:1; + uint32_t ch_ena27: 1; /** ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0; * Represents ch28 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena28:1; + uint32_t ch_ena28: 1; /** ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0; * Represents ch29 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena29:1; + uint32_t ch_ena29: 1; /** ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0; * Represents ch30 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena30:1; + uint32_t ch_ena30: 1; /** ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0; * Represents ch31 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena31:1; + uint32_t ch_ena31: 1; }; uint32_t val; } soc_etm_ch_ena_ad0_reg_t; @@ -156,76 +156,76 @@ typedef union { /** ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0; * Represents ch32 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena32:1; + uint32_t ch_ena32: 1; /** ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0; * Represents ch33 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena33:1; + uint32_t ch_ena33: 1; /** ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0; * Represents ch34 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena34:1; + uint32_t ch_ena34: 1; /** ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0; * Represents ch35 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena35:1; + uint32_t ch_ena35: 1; /** ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0; * Represents ch36 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena36:1; + uint32_t ch_ena36: 1; /** ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0; * Represents ch37 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena37:1; + uint32_t ch_ena37: 1; /** ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0; * Represents ch38 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena38:1; + uint32_t ch_ena38: 1; /** ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0; * Represents ch39 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena39:1; + uint32_t ch_ena39: 1; /** ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0; * Represents ch40 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena40:1; + uint32_t ch_ena40: 1; /** ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0; * Represents ch41 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena41:1; + uint32_t ch_ena41: 1; /** ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0; * Represents ch42 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena42:1; + uint32_t ch_ena42: 1; /** ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0; * Represents ch43 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena43:1; + uint32_t ch_ena43: 1; /** ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0; * Represents ch44 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena44:1; + uint32_t ch_ena44: 1; /** ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0; * Represents ch45 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena45:1; + uint32_t ch_ena45: 1; /** ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0; * Represents ch46 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena46:1; + uint32_t ch_ena46: 1; /** ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0; * Represents ch47 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena47:1; + uint32_t ch_ena47: 1; /** ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0; * Represents ch48 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena48:1; + uint32_t ch_ena48: 1; /** ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0; * Represents ch49 enable status.\\0: Disable\\1: Enable */ - uint32_t ch_ena49:1; - uint32_t reserved_18:14; + uint32_t ch_ena49: 1; + uint32_t reserved_18: 14; }; uint32_t val; } soc_etm_ch_ena_ad1_reg_t; @@ -238,135 +238,135 @@ typedef union { /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch0_rise_edge_st:1; + uint32_t gpio_evt_ch0_rise_edge_st: 1; /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch1_rise_edge_st:1; + uint32_t gpio_evt_ch1_rise_edge_st: 1; /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch2_rise_edge_st:1; + uint32_t gpio_evt_ch2_rise_edge_st: 1; /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch3_rise_edge_st:1; + uint32_t gpio_evt_ch3_rise_edge_st: 1; /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch4_rise_edge_st:1; + uint32_t gpio_evt_ch4_rise_edge_st: 1; /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch5_rise_edge_st:1; + uint32_t gpio_evt_ch5_rise_edge_st: 1; /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch6_rise_edge_st:1; + uint32_t gpio_evt_ch6_rise_edge_st: 1; /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch7_rise_edge_st:1; + uint32_t gpio_evt_ch7_rise_edge_st: 1; /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch0_fall_edge_st:1; + uint32_t gpio_evt_ch0_fall_edge_st: 1; /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch1_fall_edge_st:1; + uint32_t gpio_evt_ch1_fall_edge_st: 1; /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch2_fall_edge_st:1; + uint32_t gpio_evt_ch2_fall_edge_st: 1; /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch3_fall_edge_st:1; + uint32_t gpio_evt_ch3_fall_edge_st: 1; /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch4_fall_edge_st:1; + uint32_t gpio_evt_ch4_fall_edge_st: 1; /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch5_fall_edge_st:1; + uint32_t gpio_evt_ch5_fall_edge_st: 1; /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch6_fall_edge_st:1; + uint32_t gpio_evt_ch6_fall_edge_st: 1; /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch7_fall_edge_st:1; + uint32_t gpio_evt_ch7_fall_edge_st: 1; /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch0_any_edge_st:1; + uint32_t gpio_evt_ch0_any_edge_st: 1; /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch1_any_edge_st:1; + uint32_t gpio_evt_ch1_any_edge_st: 1; /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch2_any_edge_st:1; + uint32_t gpio_evt_ch2_any_edge_st: 1; /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch3_any_edge_st:1; + uint32_t gpio_evt_ch3_any_edge_st: 1; /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch4_any_edge_st:1; + uint32_t gpio_evt_ch4_any_edge_st: 1; /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch5_any_edge_st:1; + uint32_t gpio_evt_ch5_any_edge_st: 1; /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch6_any_edge_st:1; + uint32_t gpio_evt_ch6_any_edge_st: 1; /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_ch7_any_edge_st:1; + uint32_t gpio_evt_ch7_any_edge_st: 1; /** gpio_evt_zero_det_pos0_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_zero_det_pos0_st:1; + uint32_t gpio_evt_zero_det_pos0_st: 1; /** gpio_evt_zero_det_neg0_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_zero_det_neg0_st:1; + uint32_t gpio_evt_zero_det_neg0_st: 1; /** gpio_evt_zero_det_pos1_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_zero_det_pos1_st:1; + uint32_t gpio_evt_zero_det_pos1_st: 1; /** gpio_evt_zero_det_neg1_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_evt_zero_det_neg1_st:1; + uint32_t gpio_evt_zero_det_neg1_st: 1; /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch0_st:1; + uint32_t ledc_evt_duty_chng_end_ch0_st: 1; /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch1_st:1; + uint32_t ledc_evt_duty_chng_end_ch1_st: 1; /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch2_st:1; + uint32_t ledc_evt_duty_chng_end_ch2_st: 1; /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch3_st:1; + uint32_t ledc_evt_duty_chng_end_ch3_st: 1; }; uint32_t val; } soc_etm_evt_st0_reg_t; @@ -380,134 +380,134 @@ typedef union { * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch4_st:1; + uint32_t ledc_evt_duty_chng_end_ch4_st: 1; /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch5_st:1; + uint32_t ledc_evt_duty_chng_end_ch5_st: 1; /** ledc_evt_duty_chng_end_ch6_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch6_st:1; + uint32_t ledc_evt_duty_chng_end_ch6_st: 1; /** ledc_evt_duty_chng_end_ch7_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_evt_duty_chng_end_ch7_st:1; + uint32_t ledc_evt_duty_chng_end_ch7_st: 1; /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch0_st: 1; /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch1_st: 1; /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch2_st: 1; /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch3_st: 1; /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch4_st: 1; /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch5_st: 1; /** ledc_evt_ovf_cnt_pls_ch6_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch6_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch6_st: 1; /** ledc_evt_ovf_cnt_pls_ch7_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_ovf_cnt_pls_ch7_st:1; + uint32_t ledc_evt_ovf_cnt_pls_ch7_st: 1; /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_time_ovf_timer0_st:1; + uint32_t ledc_evt_time_ovf_timer0_st: 1; /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_time_ovf_timer1_st:1; + uint32_t ledc_evt_time_ovf_timer1_st: 1; /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_time_ovf_timer2_st:1; + uint32_t ledc_evt_time_ovf_timer2_st: 1; /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_time_ovf_timer3_st:1; + uint32_t ledc_evt_time_ovf_timer3_st: 1; /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_timer0_cmp_st:1; + uint32_t ledc_evt_timer0_cmp_st: 1; /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_timer1_cmp_st:1; + uint32_t ledc_evt_timer1_cmp_st: 1; /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_timer2_cmp_st:1; + uint32_t ledc_evt_timer2_cmp_st: 1; /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_evt_timer3_cmp_st:1; + uint32_t ledc_evt_timer3_cmp_st: 1; /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_evt_cnt_cmp_timer0_st:1; + uint32_t tg0_evt_cnt_cmp_timer0_st: 1; /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_evt_cnt_cmp_timer1_st:1; + uint32_t tg0_evt_cnt_cmp_timer1_st: 1; /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_evt_cnt_cmp_timer0_st:1; + uint32_t tg1_evt_cnt_cmp_timer0_st: 1; /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_evt_cnt_cmp_timer1_st:1; + uint32_t tg1_evt_cnt_cmp_timer1_st: 1; /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t systimer_evt_cnt_cmp0_st:1; + uint32_t systimer_evt_cnt_cmp0_st: 1; /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t systimer_evt_cnt_cmp1_st:1; + uint32_t systimer_evt_cnt_cmp1_st: 1; /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t systimer_evt_cnt_cmp2_st:1; + uint32_t systimer_evt_cnt_cmp2_st: 1; /** mcpwm0_evt_timer0_stop_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer0_stop_st:1; + uint32_t mcpwm0_evt_timer0_stop_st: 1; /** mcpwm0_evt_timer1_stop_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer1_stop_st:1; + uint32_t mcpwm0_evt_timer1_stop_st: 1; /** mcpwm0_evt_timer2_stop_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer2_stop_st:1; + uint32_t mcpwm0_evt_timer2_stop_st: 1; /** mcpwm0_evt_timer0_tez_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer0_tez_st:1; + uint32_t mcpwm0_evt_timer0_tez_st: 1; /** mcpwm0_evt_timer1_tez_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer1_tez_st:1; + uint32_t mcpwm0_evt_timer1_tez_st: 1; }; uint32_t val; } soc_etm_evt_st1_reg_t; @@ -520,131 +520,131 @@ typedef union { /** mcpwm0_evt_timer2_tez_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer2_tez_st:1; + uint32_t mcpwm0_evt_timer2_tez_st: 1; /** mcpwm0_evt_timer0_tep_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer0_tep_st:1; + uint32_t mcpwm0_evt_timer0_tep_st: 1; /** mcpwm0_evt_timer1_tep_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer1_tep_st:1; + uint32_t mcpwm0_evt_timer1_tep_st: 1; /** mcpwm0_evt_timer2_tep_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_timer2_tep_st:1; + uint32_t mcpwm0_evt_timer2_tep_st: 1; /** mcpwm0_evt_op0_tea_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op0_tea_st:1; + uint32_t mcpwm0_evt_op0_tea_st: 1; /** mcpwm0_evt_op1_tea_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op1_tea_st:1; + uint32_t mcpwm0_evt_op1_tea_st: 1; /** mcpwm0_evt_op2_tea_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op2_tea_st:1; + uint32_t mcpwm0_evt_op2_tea_st: 1; /** mcpwm0_evt_op0_teb_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op0_teb_st:1; + uint32_t mcpwm0_evt_op0_teb_st: 1; /** mcpwm0_evt_op1_teb_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op1_teb_st:1; + uint32_t mcpwm0_evt_op1_teb_st: 1; /** mcpwm0_evt_op2_teb_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op2_teb_st:1; + uint32_t mcpwm0_evt_op2_teb_st: 1; /** mcpwm0_evt_f0_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_f0_st:1; + uint32_t mcpwm0_evt_f0_st: 1; /** mcpwm0_evt_f1_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_f1_st:1; + uint32_t mcpwm0_evt_f1_st: 1; /** mcpwm0_evt_f2_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_f2_st:1; + uint32_t mcpwm0_evt_f2_st: 1; /** mcpwm0_evt_f0_clr_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_f0_clr_st:1; + uint32_t mcpwm0_evt_f0_clr_st: 1; /** mcpwm0_evt_f1_clr_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_f1_clr_st:1; + uint32_t mcpwm0_evt_f1_clr_st: 1; /** mcpwm0_evt_f2_clr_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_f2_clr_st:1; + uint32_t mcpwm0_evt_f2_clr_st: 1; /** mcpwm0_evt_tz0_cbc_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_tz0_cbc_st:1; + uint32_t mcpwm0_evt_tz0_cbc_st: 1; /** mcpwm0_evt_tz1_cbc_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_tz1_cbc_st:1; + uint32_t mcpwm0_evt_tz1_cbc_st: 1; /** mcpwm0_evt_tz2_cbc_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_tz2_cbc_st:1; + uint32_t mcpwm0_evt_tz2_cbc_st: 1; /** mcpwm0_evt_tz0_ost_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_tz0_ost_st:1; + uint32_t mcpwm0_evt_tz0_ost_st: 1; /** mcpwm0_evt_tz1_ost_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_tz1_ost_st:1; + uint32_t mcpwm0_evt_tz1_ost_st: 1; /** mcpwm0_evt_tz2_ost_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_tz2_ost_st:1; + uint32_t mcpwm0_evt_tz2_ost_st: 1; /** mcpwm0_evt_cap0_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_cap0_st:1; + uint32_t mcpwm0_evt_cap0_st: 1; /** mcpwm0_evt_cap1_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_cap1_st:1; + uint32_t mcpwm0_evt_cap1_st: 1; /** mcpwm0_evt_cap2_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_cap2_st:1; + uint32_t mcpwm0_evt_cap2_st: 1; /** mcpwm0_evt_op0_tee1_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op0_tee1_st:1; + uint32_t mcpwm0_evt_op0_tee1_st: 1; /** mcpwm0_evt_op1_tee1_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op1_tee1_st:1; + uint32_t mcpwm0_evt_op1_tee1_st: 1; /** mcpwm0_evt_op2_tee1_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op2_tee1_st:1; + uint32_t mcpwm0_evt_op2_tee1_st: 1; /** mcpwm0_evt_op0_tee2_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op0_tee2_st:1; + uint32_t mcpwm0_evt_op0_tee2_st: 1; /** mcpwm0_evt_op1_tee2_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op1_tee2_st:1; + uint32_t mcpwm0_evt_op1_tee2_st: 1; /** mcpwm0_evt_op2_tee2_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_evt_op2_tee2_st:1; + uint32_t mcpwm0_evt_op2_tee2_st: 1; /** mcpwm1_evt_timer0_stop_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer0_stop_st:1; + uint32_t mcpwm1_evt_timer0_stop_st: 1; }; uint32_t val; } soc_etm_evt_st2_reg_t; @@ -657,131 +657,131 @@ typedef union { /** mcpwm1_evt_timer1_stop_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer1_stop_st:1; + uint32_t mcpwm1_evt_timer1_stop_st: 1; /** mcpwm1_evt_timer2_stop_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer2_stop_st:1; + uint32_t mcpwm1_evt_timer2_stop_st: 1; /** mcpwm1_evt_timer0_tez_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer0_tez_st:1; + uint32_t mcpwm1_evt_timer0_tez_st: 1; /** mcpwm1_evt_timer1_tez_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer1_tez_st:1; + uint32_t mcpwm1_evt_timer1_tez_st: 1; /** mcpwm1_evt_timer2_tez_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer2_tez_st:1; + uint32_t mcpwm1_evt_timer2_tez_st: 1; /** mcpwm1_evt_timer0_tep_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer0_tep_st:1; + uint32_t mcpwm1_evt_timer0_tep_st: 1; /** mcpwm1_evt_timer1_tep_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer1_tep_st:1; + uint32_t mcpwm1_evt_timer1_tep_st: 1; /** mcpwm1_evt_timer2_tep_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_timer2_tep_st:1; + uint32_t mcpwm1_evt_timer2_tep_st: 1; /** mcpwm1_evt_op0_tea_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op0_tea_st:1; + uint32_t mcpwm1_evt_op0_tea_st: 1; /** mcpwm1_evt_op1_tea_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op1_tea_st:1; + uint32_t mcpwm1_evt_op1_tea_st: 1; /** mcpwm1_evt_op2_tea_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op2_tea_st:1; + uint32_t mcpwm1_evt_op2_tea_st: 1; /** mcpwm1_evt_op0_teb_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op0_teb_st:1; + uint32_t mcpwm1_evt_op0_teb_st: 1; /** mcpwm1_evt_op1_teb_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op1_teb_st:1; + uint32_t mcpwm1_evt_op1_teb_st: 1; /** mcpwm1_evt_op2_teb_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op2_teb_st:1; + uint32_t mcpwm1_evt_op2_teb_st: 1; /** mcpwm1_evt_f0_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_f0_st:1; + uint32_t mcpwm1_evt_f0_st: 1; /** mcpwm1_evt_f1_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_f1_st:1; + uint32_t mcpwm1_evt_f1_st: 1; /** mcpwm1_evt_f2_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_f2_st:1; + uint32_t mcpwm1_evt_f2_st: 1; /** mcpwm1_evt_f0_clr_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_f0_clr_st:1; + uint32_t mcpwm1_evt_f0_clr_st: 1; /** mcpwm1_evt_f1_clr_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_f1_clr_st:1; + uint32_t mcpwm1_evt_f1_clr_st: 1; /** mcpwm1_evt_f2_clr_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_f2_clr_st:1; + uint32_t mcpwm1_evt_f2_clr_st: 1; /** mcpwm1_evt_tz0_cbc_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_tz0_cbc_st:1; + uint32_t mcpwm1_evt_tz0_cbc_st: 1; /** mcpwm1_evt_tz1_cbc_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_tz1_cbc_st:1; + uint32_t mcpwm1_evt_tz1_cbc_st: 1; /** mcpwm1_evt_tz2_cbc_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_tz2_cbc_st:1; + uint32_t mcpwm1_evt_tz2_cbc_st: 1; /** mcpwm1_evt_tz0_ost_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_tz0_ost_st:1; + uint32_t mcpwm1_evt_tz0_ost_st: 1; /** mcpwm1_evt_tz1_ost_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_tz1_ost_st:1; + uint32_t mcpwm1_evt_tz1_ost_st: 1; /** mcpwm1_evt_tz2_ost_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_tz2_ost_st:1; + uint32_t mcpwm1_evt_tz2_ost_st: 1; /** mcpwm1_evt_cap0_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_cap0_st:1; + uint32_t mcpwm1_evt_cap0_st: 1; /** mcpwm1_evt_cap1_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_cap1_st:1; + uint32_t mcpwm1_evt_cap1_st: 1; /** mcpwm1_evt_cap2_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_cap2_st:1; + uint32_t mcpwm1_evt_cap2_st: 1; /** mcpwm1_evt_op0_tee1_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op0_tee1_st:1; + uint32_t mcpwm1_evt_op0_tee1_st: 1; /** mcpwm1_evt_op1_tee1_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op1_tee1_st:1; + uint32_t mcpwm1_evt_op1_tee1_st: 1; /** mcpwm1_evt_op2_tee1_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op2_tee1_st:1; + uint32_t mcpwm1_evt_op2_tee1_st: 1; }; uint32_t val; } soc_etm_evt_st3_reg_t; @@ -794,131 +794,131 @@ typedef union { /** mcpwm1_evt_op0_tee2_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op0_tee2_st:1; + uint32_t mcpwm1_evt_op0_tee2_st: 1; /** mcpwm1_evt_op1_tee2_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op1_tee2_st:1; + uint32_t mcpwm1_evt_op1_tee2_st: 1; /** mcpwm1_evt_op2_tee2_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_evt_op2_tee2_st:1; + uint32_t mcpwm1_evt_op2_tee2_st: 1; /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_conv_cmplt0_st:1; + uint32_t adc_evt_conv_cmplt0_st: 1; /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_eq_above_thresh0_st:1; + uint32_t adc_evt_eq_above_thresh0_st: 1; /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_eq_above_thresh1_st:1; + uint32_t adc_evt_eq_above_thresh1_st: 1; /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_eq_below_thresh0_st:1; + uint32_t adc_evt_eq_below_thresh0_st: 1; /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_eq_below_thresh1_st:1; + uint32_t adc_evt_eq_below_thresh1_st: 1; /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_result_done0_st:1; + uint32_t adc_evt_result_done0_st: 1; /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_stopped0_st:1; + uint32_t adc_evt_stopped0_st: 1; /** adc_evt_started0_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_evt_started0_st:1; + uint32_t adc_evt_started0_st: 1; /** regdma_evt_done0_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_done0_st:1; + uint32_t regdma_evt_done0_st: 1; /** regdma_evt_done1_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_done1_st:1; + uint32_t regdma_evt_done1_st: 1; /** regdma_evt_done2_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_done2_st:1; + uint32_t regdma_evt_done2_st: 1; /** regdma_evt_done3_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_done3_st:1; + uint32_t regdma_evt_done3_st: 1; /** regdma_evt_err0_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_err0_st:1; + uint32_t regdma_evt_err0_st: 1; /** regdma_evt_err1_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_err1_st:1; + uint32_t regdma_evt_err1_st: 1; /** regdma_evt_err2_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_err2_st:1; + uint32_t regdma_evt_err2_st: 1; /** regdma_evt_err3_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_evt_err3_st:1; + uint32_t regdma_evt_err3_st: 1; /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tmpsnsr_evt_over_limit_st:1; + uint32_t tmpsnsr_evt_over_limit_st: 1; /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_evt_rx_done_st:1; + uint32_t i2s0_evt_rx_done_st: 1; /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_evt_tx_done_st:1; + uint32_t i2s0_evt_tx_done_st: 1; /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_evt_x_words_received_st:1; + uint32_t i2s0_evt_x_words_received_st: 1; /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_evt_x_words_sent_st:1; + uint32_t i2s0_evt_x_words_sent_st: 1; /** i2s1_evt_rx_done_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_evt_rx_done_st:1; + uint32_t i2s1_evt_rx_done_st: 1; /** i2s1_evt_tx_done_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_evt_tx_done_st:1; + uint32_t i2s1_evt_tx_done_st: 1; /** i2s1_evt_x_words_received_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_evt_x_words_received_st:1; + uint32_t i2s1_evt_x_words_received_st: 1; /** i2s1_evt_x_words_sent_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_evt_x_words_sent_st:1; + uint32_t i2s1_evt_x_words_sent_st: 1; /** i2s2_evt_rx_done_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_evt_rx_done_st:1; + uint32_t i2s2_evt_rx_done_st: 1; /** i2s2_evt_tx_done_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_evt_tx_done_st:1; + uint32_t i2s2_evt_tx_done_st: 1; /** i2s2_evt_x_words_received_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_evt_x_words_received_st:1; + uint32_t i2s2_evt_x_words_received_st: 1; /** i2s2_evt_x_words_sent_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_evt_x_words_sent_st:1; + uint32_t i2s2_evt_x_words_sent_st: 1; }; uint32_t val; } soc_etm_evt_st4_reg_t; @@ -931,148 +931,148 @@ typedef union { /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ulp_evt_err_intr_st:1; + uint32_t ulp_evt_err_intr_st: 1; /** ulp_evt_halt_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ulp_evt_halt_st:1; + uint32_t ulp_evt_halt_st: 1; /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ulp_evt_start_intr_st:1; + uint32_t ulp_evt_start_intr_st: 1; /** rtc_evt_tick_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_evt_tick_st:1; + uint32_t rtc_evt_tick_st: 1; /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_evt_ovf_st:1; + uint32_t rtc_evt_ovf_st: 1; /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_evt_cmp_st:1; + uint32_t rtc_evt_cmp_st: 1; /** pdma_ahb_evt_in_done_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_in_done_ch0_st:1; + uint32_t pdma_ahb_evt_in_done_ch0_st: 1; /** pdma_ahb_evt_in_done_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_in_done_ch1_st:1; + uint32_t pdma_ahb_evt_in_done_ch1_st: 1; /** pdma_ahb_evt_in_done_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_in_done_ch2_st:1; + uint32_t pdma_ahb_evt_in_done_ch2_st: 1; /** pdma_ahb_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_suc_eof_ch0_st:1; + uint32_t pdma_ahb_evt_in_suc_eof_ch0_st: 1; /** pdma_ahb_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_suc_eof_ch1_st:1; + uint32_t pdma_ahb_evt_in_suc_eof_ch1_st: 1; /** pdma_ahb_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_suc_eof_ch2_st:1; + uint32_t pdma_ahb_evt_in_suc_eof_ch2_st: 1; /** pdma_ahb_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st:1; + uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st: 1; /** pdma_ahb_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st:1; + uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st: 1; /** pdma_ahb_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st:1; + uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st: 1; /** pdma_ahb_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_fifo_full_ch0_st:1; + uint32_t pdma_ahb_evt_in_fifo_full_ch0_st: 1; /** pdma_ahb_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_fifo_full_ch1_st:1; + uint32_t pdma_ahb_evt_in_fifo_full_ch1_st: 1; /** pdma_ahb_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_in_fifo_full_ch2_st:1; + uint32_t pdma_ahb_evt_in_fifo_full_ch2_st: 1; /** pdma_ahb_evt_out_done_ch0_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_out_done_ch0_st:1; + uint32_t pdma_ahb_evt_out_done_ch0_st: 1; /** pdma_ahb_evt_out_done_ch1_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_out_done_ch1_st:1; + uint32_t pdma_ahb_evt_out_done_ch1_st: 1; /** pdma_ahb_evt_out_done_ch2_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_out_done_ch2_st:1; + uint32_t pdma_ahb_evt_out_done_ch2_st: 1; /** pdma_ahb_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_out_eof_ch0_st:1; + uint32_t pdma_ahb_evt_out_eof_ch0_st: 1; /** pdma_ahb_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_out_eof_ch1_st:1; + uint32_t pdma_ahb_evt_out_eof_ch1_st: 1; /** pdma_ahb_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_ahb_evt_out_eof_ch2_st:1; + uint32_t pdma_ahb_evt_out_eof_ch2_st: 1; /** pdma_ahb_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_total_eof_ch0_st:1; + uint32_t pdma_ahb_evt_out_total_eof_ch0_st: 1; /** pdma_ahb_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_total_eof_ch1_st:1; + uint32_t pdma_ahb_evt_out_total_eof_ch1_st: 1; /** pdma_ahb_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_total_eof_ch2_st:1; + uint32_t pdma_ahb_evt_out_total_eof_ch2_st: 1; /** pdma_ahb_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st:1; + uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st: 1; /** pdma_ahb_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st:1; + uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st: 1; /** pdma_ahb_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st:1; + uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st: 1; /** pdma_ahb_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_fifo_full_ch0_st:1; + uint32_t pdma_ahb_evt_out_fifo_full_ch0_st: 1; /** pdma_ahb_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_fifo_full_ch1_st:1; + uint32_t pdma_ahb_evt_out_fifo_full_ch1_st: 1; }; uint32_t val; } soc_etm_evt_st5_reg_t; @@ -1086,149 +1086,149 @@ typedef union { * Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_evt_out_fifo_full_ch2_st:1; + uint32_t pdma_ahb_evt_out_fifo_full_ch2_st: 1; /** pdma_axi_evt_in_done_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_in_done_ch0_st:1; + uint32_t pdma_axi_evt_in_done_ch0_st: 1; /** pdma_axi_evt_in_done_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_in_done_ch1_st:1; + uint32_t pdma_axi_evt_in_done_ch1_st: 1; /** pdma_axi_evt_in_done_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_in_done_ch2_st:1; + uint32_t pdma_axi_evt_in_done_ch2_st: 1; /** pdma_axi_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_suc_eof_ch0_st:1; + uint32_t pdma_axi_evt_in_suc_eof_ch0_st: 1; /** pdma_axi_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_suc_eof_ch1_st:1; + uint32_t pdma_axi_evt_in_suc_eof_ch1_st: 1; /** pdma_axi_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_suc_eof_ch2_st:1; + uint32_t pdma_axi_evt_in_suc_eof_ch2_st: 1; /** pdma_axi_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_fifo_empty_ch0_st:1; + uint32_t pdma_axi_evt_in_fifo_empty_ch0_st: 1; /** pdma_axi_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_fifo_empty_ch1_st:1; + uint32_t pdma_axi_evt_in_fifo_empty_ch1_st: 1; /** pdma_axi_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_fifo_empty_ch2_st:1; + uint32_t pdma_axi_evt_in_fifo_empty_ch2_st: 1; /** pdma_axi_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_fifo_full_ch0_st:1; + uint32_t pdma_axi_evt_in_fifo_full_ch0_st: 1; /** pdma_axi_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_fifo_full_ch1_st:1; + uint32_t pdma_axi_evt_in_fifo_full_ch1_st: 1; /** pdma_axi_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_in_fifo_full_ch2_st:1; + uint32_t pdma_axi_evt_in_fifo_full_ch2_st: 1; /** pdma_axi_evt_out_done_ch0_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_out_done_ch0_st:1; + uint32_t pdma_axi_evt_out_done_ch0_st: 1; /** pdma_axi_evt_out_done_ch1_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_out_done_ch1_st:1; + uint32_t pdma_axi_evt_out_done_ch1_st: 1; /** pdma_axi_evt_out_done_ch2_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_out_done_ch2_st:1; + uint32_t pdma_axi_evt_out_done_ch2_st: 1; /** pdma_axi_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_out_eof_ch0_st:1; + uint32_t pdma_axi_evt_out_eof_ch0_st: 1; /** pdma_axi_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_out_eof_ch1_st:1; + uint32_t pdma_axi_evt_out_eof_ch1_st: 1; /** pdma_axi_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pdma_axi_evt_out_eof_ch2_st:1; + uint32_t pdma_axi_evt_out_eof_ch2_st: 1; /** pdma_axi_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_total_eof_ch0_st:1; + uint32_t pdma_axi_evt_out_total_eof_ch0_st: 1; /** pdma_axi_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_total_eof_ch1_st:1; + uint32_t pdma_axi_evt_out_total_eof_ch1_st: 1; /** pdma_axi_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_total_eof_ch2_st:1; + uint32_t pdma_axi_evt_out_total_eof_ch2_st: 1; /** pdma_axi_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_fifo_empty_ch0_st:1; + uint32_t pdma_axi_evt_out_fifo_empty_ch0_st: 1; /** pdma_axi_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_fifo_empty_ch1_st:1; + uint32_t pdma_axi_evt_out_fifo_empty_ch1_st: 1; /** pdma_axi_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_fifo_empty_ch2_st:1; + uint32_t pdma_axi_evt_out_fifo_empty_ch2_st: 1; /** pdma_axi_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_fifo_full_ch0_st:1; + uint32_t pdma_axi_evt_out_fifo_full_ch0_st: 1; /** pdma_axi_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_fifo_full_ch1_st:1; + uint32_t pdma_axi_evt_out_fifo_full_ch1_st: 1; /** pdma_axi_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_evt_out_fifo_full_ch2_st:1; + uint32_t pdma_axi_evt_out_fifo_full_ch2_st: 1; /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pmu_evt_sleep_weekup_st:1; + uint32_t pmu_evt_sleep_weekup_st: 1; /** dma2d_evt_in_done_ch0_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_in_done_ch0_st:1; + uint32_t dma2d_evt_in_done_ch0_st: 1; /** dma2d_evt_in_done_ch1_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_in_done_ch1_st:1; + uint32_t dma2d_evt_in_done_ch1_st: 1; /** dma2d_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_in_suc_eof_ch0_st:1; + uint32_t dma2d_evt_in_suc_eof_ch0_st: 1; }; uint32_t val; } soc_etm_evt_st6_reg_t; @@ -1241,47 +1241,47 @@ typedef union { /** dma2d_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_in_suc_eof_ch1_st:1; + uint32_t dma2d_evt_in_suc_eof_ch1_st: 1; /** dma2d_evt_out_done_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_out_done_ch0_st:1; + uint32_t dma2d_evt_out_done_ch0_st: 1; /** dma2d_evt_out_done_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_out_done_ch1_st:1; + uint32_t dma2d_evt_out_done_ch1_st: 1; /** dma2d_evt_out_done_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_out_done_ch2_st:1; + uint32_t dma2d_evt_out_done_ch2_st: 1; /** dma2d_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_out_eof_ch0_st:1; + uint32_t dma2d_evt_out_eof_ch0_st: 1; /** dma2d_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_out_eof_ch1_st:1; + uint32_t dma2d_evt_out_eof_ch1_st: 1; /** dma2d_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_evt_out_eof_ch2_st:1; + uint32_t dma2d_evt_out_eof_ch2_st: 1; /** dma2d_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_evt_out_total_eof_ch0_st:1; + uint32_t dma2d_evt_out_total_eof_ch0_st: 1; /** dma2d_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_evt_out_total_eof_ch1_st:1; + uint32_t dma2d_evt_out_total_eof_ch1_st: 1; /** dma2d_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_evt_out_total_eof_ch2_st:1; - uint32_t reserved_10:22; + uint32_t dma2d_evt_out_total_eof_ch2_st: 1; + uint32_t reserved_10: 22; }; uint32_t val; } soc_etm_evt_st7_reg_t; @@ -1294,139 +1294,139 @@ typedef union { /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch0_set_st:1; + uint32_t gpio_task_ch0_set_st: 1; /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch1_set_st:1; + uint32_t gpio_task_ch1_set_st: 1; /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch2_set_st:1; + uint32_t gpio_task_ch2_set_st: 1; /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch3_set_st:1; + uint32_t gpio_task_ch3_set_st: 1; /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch4_set_st:1; + uint32_t gpio_task_ch4_set_st: 1; /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch5_set_st:1; + uint32_t gpio_task_ch5_set_st: 1; /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch6_set_st:1; + uint32_t gpio_task_ch6_set_st: 1; /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch7_set_st:1; + uint32_t gpio_task_ch7_set_st: 1; /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch0_clear_st:1; + uint32_t gpio_task_ch0_clear_st: 1; /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch1_clear_st:1; + uint32_t gpio_task_ch1_clear_st: 1; /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch2_clear_st:1; + uint32_t gpio_task_ch2_clear_st: 1; /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch3_clear_st:1; + uint32_t gpio_task_ch3_clear_st: 1; /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch4_clear_st:1; + uint32_t gpio_task_ch4_clear_st: 1; /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch5_clear_st:1; + uint32_t gpio_task_ch5_clear_st: 1; /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch6_clear_st:1; + uint32_t gpio_task_ch6_clear_st: 1; /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch7_clear_st:1; + uint32_t gpio_task_ch7_clear_st: 1; /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch0_toggle_st:1; + uint32_t gpio_task_ch0_toggle_st: 1; /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch1_toggle_st:1; + uint32_t gpio_task_ch1_toggle_st: 1; /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch2_toggle_st:1; + uint32_t gpio_task_ch2_toggle_st: 1; /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch3_toggle_st:1; + uint32_t gpio_task_ch3_toggle_st: 1; /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch4_toggle_st:1; + uint32_t gpio_task_ch4_toggle_st: 1; /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch5_toggle_st:1; + uint32_t gpio_task_ch5_toggle_st: 1; /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch6_toggle_st:1; + uint32_t gpio_task_ch6_toggle_st: 1; /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t gpio_task_ch7_toggle_st:1; + uint32_t gpio_task_ch7_toggle_st: 1; /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_timer0_res_update_st:1; + uint32_t ledc_task_timer0_res_update_st: 1; /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_timer1_res_update_st:1; + uint32_t ledc_task_timer1_res_update_st: 1; /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_timer2_res_update_st:1; + uint32_t ledc_task_timer2_res_update_st: 1; /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_timer3_res_update_st:1; + uint32_t ledc_task_timer3_res_update_st: 1; /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch0_st:1; + uint32_t ledc_task_duty_scale_update_ch0_st: 1; /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch1_st:1; + uint32_t ledc_task_duty_scale_update_ch1_st: 1; /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch2_st:1; + uint32_t ledc_task_duty_scale_update_ch2_st: 1; /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch3_st:1; + uint32_t ledc_task_duty_scale_update_ch3_st: 1; }; uint32_t val; } soc_etm_task_st0_reg_t; @@ -1440,134 +1440,134 @@ typedef union { * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch4_st:1; + uint32_t ledc_task_duty_scale_update_ch4_st: 1; /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch5_st:1; + uint32_t ledc_task_duty_scale_update_ch5_st: 1; /** ledc_task_duty_scale_update_ch6_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch6_st:1; + uint32_t ledc_task_duty_scale_update_ch6_st: 1; /** ledc_task_duty_scale_update_ch7_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_duty_scale_update_ch7_st:1; + uint32_t ledc_task_duty_scale_update_ch7_st: 1; /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer0_cap_st:1; + uint32_t ledc_task_timer0_cap_st: 1; /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer1_cap_st:1; + uint32_t ledc_task_timer1_cap_st: 1; /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer2_cap_st:1; + uint32_t ledc_task_timer2_cap_st: 1; /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer3_cap_st:1; + uint32_t ledc_task_timer3_cap_st: 1; /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch0_st:1; + uint32_t ledc_task_sig_out_dis_ch0_st: 1; /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch1_st:1; + uint32_t ledc_task_sig_out_dis_ch1_st: 1; /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch2_st:1; + uint32_t ledc_task_sig_out_dis_ch2_st: 1; /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch3_st:1; + uint32_t ledc_task_sig_out_dis_ch3_st: 1; /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch4_st:1; + uint32_t ledc_task_sig_out_dis_ch4_st: 1; /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch5_st:1; + uint32_t ledc_task_sig_out_dis_ch5_st: 1; /** ledc_task_sig_out_dis_ch6_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch6_st:1; + uint32_t ledc_task_sig_out_dis_ch6_st: 1; /** ledc_task_sig_out_dis_ch7_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_sig_out_dis_ch7_st:1; + uint32_t ledc_task_sig_out_dis_ch7_st: 1; /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch0_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch0_st: 1; /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch1_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch1_st: 1; /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch2_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch2_st: 1; /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch3_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch3_st: 1; /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch4_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch4_st: 1; /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch5_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch5_st: 1; /** ledc_task_ovf_cnt_rst_ch6_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch6_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch6_st: 1; /** ledc_task_ovf_cnt_rst_ch7_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_ovf_cnt_rst_ch7_st:1; + uint32_t ledc_task_ovf_cnt_rst_ch7_st: 1; /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer0_rst_st:1; + uint32_t ledc_task_timer0_rst_st: 1; /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer1_rst_st:1; + uint32_t ledc_task_timer1_rst_st: 1; /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer2_rst_st:1; + uint32_t ledc_task_timer2_rst_st: 1; /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer3_rst_st:1; + uint32_t ledc_task_timer3_rst_st: 1; /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer0_resume_st:1; + uint32_t ledc_task_timer0_resume_st: 1; /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer1_resume_st:1; + uint32_t ledc_task_timer1_resume_st: 1; /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer2_resume_st:1; + uint32_t ledc_task_timer2_resume_st: 1; /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer3_resume_st:1; + uint32_t ledc_task_timer3_resume_st: 1; }; uint32_t val; } soc_etm_task_st1_reg_t; @@ -1580,149 +1580,149 @@ typedef union { /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer0_pause_st:1; + uint32_t ledc_task_timer0_pause_st: 1; /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer1_pause_st:1; + uint32_t ledc_task_timer1_pause_st: 1; /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer2_pause_st:1; + uint32_t ledc_task_timer2_pause_st: 1; /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_timer3_pause_st:1; + uint32_t ledc_task_timer3_pause_st: 1; /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch0_st:1; + uint32_t ledc_task_gamma_restart_ch0_st: 1; /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch1_st:1; + uint32_t ledc_task_gamma_restart_ch1_st: 1; /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch2_st:1; + uint32_t ledc_task_gamma_restart_ch2_st: 1; /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch3_st:1; + uint32_t ledc_task_gamma_restart_ch3_st: 1; /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch4_st:1; + uint32_t ledc_task_gamma_restart_ch4_st: 1; /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch5_st:1; + uint32_t ledc_task_gamma_restart_ch5_st: 1; /** ledc_task_gamma_restart_ch6_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch6_st:1; + uint32_t ledc_task_gamma_restart_ch6_st: 1; /** ledc_task_gamma_restart_ch7_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_restart_ch7_st:1; + uint32_t ledc_task_gamma_restart_ch7_st: 1; /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch0_st:1; + uint32_t ledc_task_gamma_pause_ch0_st: 1; /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch1_st:1; + uint32_t ledc_task_gamma_pause_ch1_st: 1; /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch2_st:1; + uint32_t ledc_task_gamma_pause_ch2_st: 1; /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch3_st:1; + uint32_t ledc_task_gamma_pause_ch3_st: 1; /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch4_st:1; + uint32_t ledc_task_gamma_pause_ch4_st: 1; /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch5_st:1; + uint32_t ledc_task_gamma_pause_ch5_st: 1; /** ledc_task_gamma_pause_ch6_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch6_st:1; + uint32_t ledc_task_gamma_pause_ch6_st: 1; /** ledc_task_gamma_pause_ch7_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ledc_task_gamma_pause_ch7_st:1; + uint32_t ledc_task_gamma_pause_ch7_st: 1; /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch0_st:1; + uint32_t ledc_task_gamma_resume_ch0_st: 1; /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch1_st:1; + uint32_t ledc_task_gamma_resume_ch1_st: 1; /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch2_st:1; + uint32_t ledc_task_gamma_resume_ch2_st: 1; /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch3_st:1; + uint32_t ledc_task_gamma_resume_ch3_st: 1; /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch4_st:1; + uint32_t ledc_task_gamma_resume_ch4_st: 1; /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch5_st:1; + uint32_t ledc_task_gamma_resume_ch5_st: 1; /** ledc_task_gamma_resume_ch6_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch6_st:1; + uint32_t ledc_task_gamma_resume_ch6_st: 1; /** ledc_task_gamma_resume_ch7_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t ledc_task_gamma_resume_ch7_st:1; + uint32_t ledc_task_gamma_resume_ch7_st: 1; /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_task_cnt_start_timer0_st:1; + uint32_t tg0_task_cnt_start_timer0_st: 1; /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg0_task_alarm_start_timer0_st:1; + uint32_t tg0_task_alarm_start_timer0_st: 1; /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_task_cnt_stop_timer0_st:1; + uint32_t tg0_task_cnt_stop_timer0_st: 1; /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg0_task_cnt_reload_timer0_st:1; + uint32_t tg0_task_cnt_reload_timer0_st: 1; }; uint32_t val; } soc_etm_task_st2_reg_t; @@ -1735,140 +1735,140 @@ typedef union { /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_task_cnt_cap_timer0_st:1; + uint32_t tg0_task_cnt_cap_timer0_st: 1; /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_task_cnt_start_timer1_st:1; + uint32_t tg0_task_cnt_start_timer1_st: 1; /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg0_task_alarm_start_timer1_st:1; + uint32_t tg0_task_alarm_start_timer1_st: 1; /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_task_cnt_stop_timer1_st:1; + uint32_t tg0_task_cnt_stop_timer1_st: 1; /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg0_task_cnt_reload_timer1_st:1; + uint32_t tg0_task_cnt_reload_timer1_st: 1; /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg0_task_cnt_cap_timer1_st:1; + uint32_t tg0_task_cnt_cap_timer1_st: 1; /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_task_cnt_start_timer0_st:1; + uint32_t tg1_task_cnt_start_timer0_st: 1; /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg1_task_alarm_start_timer0_st:1; + uint32_t tg1_task_alarm_start_timer0_st: 1; /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_task_cnt_stop_timer0_st:1; + uint32_t tg1_task_cnt_stop_timer0_st: 1; /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg1_task_cnt_reload_timer0_st:1; + uint32_t tg1_task_cnt_reload_timer0_st: 1; /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_task_cnt_cap_timer0_st:1; + uint32_t tg1_task_cnt_cap_timer0_st: 1; /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_task_cnt_start_timer1_st:1; + uint32_t tg1_task_cnt_start_timer1_st: 1; /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg1_task_alarm_start_timer1_st:1; + uint32_t tg1_task_alarm_start_timer1_st: 1; /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_task_cnt_stop_timer1_st:1; + uint32_t tg1_task_cnt_stop_timer1_st: 1; /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t tg1_task_cnt_reload_timer1_st:1; + uint32_t tg1_task_cnt_reload_timer1_st: 1; /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tg1_task_cnt_cap_timer1_st:1; + uint32_t tg1_task_cnt_cap_timer1_st: 1; /** mcpwm0_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cmpr0_a_up_st:1; + uint32_t mcpwm0_task_cmpr0_a_up_st: 1; /** mcpwm0_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cmpr1_a_up_st:1; + uint32_t mcpwm0_task_cmpr1_a_up_st: 1; /** mcpwm0_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cmpr2_a_up_st:1; + uint32_t mcpwm0_task_cmpr2_a_up_st: 1; /** mcpwm0_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cmpr0_b_up_st:1; + uint32_t mcpwm0_task_cmpr0_b_up_st: 1; /** mcpwm0_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cmpr1_b_up_st:1; + uint32_t mcpwm0_task_cmpr1_b_up_st: 1; /** mcpwm0_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cmpr2_b_up_st:1; + uint32_t mcpwm0_task_cmpr2_b_up_st: 1; /** mcpwm0_task_gen_stop_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_gen_stop_st:1; + uint32_t mcpwm0_task_gen_stop_st: 1; /** mcpwm0_task_timer0_syn_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_timer0_syn_st:1; + uint32_t mcpwm0_task_timer0_syn_st: 1; /** mcpwm0_task_timer1_syn_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_timer1_syn_st:1; + uint32_t mcpwm0_task_timer1_syn_st: 1; /** mcpwm0_task_timer2_syn_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_timer2_syn_st:1; + uint32_t mcpwm0_task_timer2_syn_st: 1; /** mcpwm0_task_timer0_period_up_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t mcpwm0_task_timer0_period_up_st:1; + uint32_t mcpwm0_task_timer0_period_up_st: 1; /** mcpwm0_task_timer1_period_up_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t mcpwm0_task_timer1_period_up_st:1; + uint32_t mcpwm0_task_timer1_period_up_st: 1; /** mcpwm0_task_timer2_period_up_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t mcpwm0_task_timer2_period_up_st:1; + uint32_t mcpwm0_task_timer2_period_up_st: 1; /** mcpwm0_task_tz0_ost_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_tz0_ost_st:1; + uint32_t mcpwm0_task_tz0_ost_st: 1; /** mcpwm0_task_tz1_ost_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_tz1_ost_st:1; + uint32_t mcpwm0_task_tz1_ost_st: 1; /** mcpwm0_task_tz2_ost_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_tz2_ost_st:1; + uint32_t mcpwm0_task_tz2_ost_st: 1; }; uint32_t val; } soc_etm_task_st3_reg_t; @@ -1881,134 +1881,134 @@ typedef union { /** mcpwm0_task_clr0_ost_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_clr0_ost_st:1; + uint32_t mcpwm0_task_clr0_ost_st: 1; /** mcpwm0_task_clr1_ost_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_clr1_ost_st:1; + uint32_t mcpwm0_task_clr1_ost_st: 1; /** mcpwm0_task_clr2_ost_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_clr2_ost_st:1; + uint32_t mcpwm0_task_clr2_ost_st: 1; /** mcpwm0_task_cap0_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cap0_st:1; + uint32_t mcpwm0_task_cap0_st: 1; /** mcpwm0_task_cap1_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cap1_st:1; + uint32_t mcpwm0_task_cap1_st: 1; /** mcpwm0_task_cap2_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm0_task_cap2_st:1; + uint32_t mcpwm0_task_cap2_st: 1; /** mcpwm1_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cmpr0_a_up_st:1; + uint32_t mcpwm1_task_cmpr0_a_up_st: 1; /** mcpwm1_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cmpr1_a_up_st:1; + uint32_t mcpwm1_task_cmpr1_a_up_st: 1; /** mcpwm1_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cmpr2_a_up_st:1; + uint32_t mcpwm1_task_cmpr2_a_up_st: 1; /** mcpwm1_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cmpr0_b_up_st:1; + uint32_t mcpwm1_task_cmpr0_b_up_st: 1; /** mcpwm1_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cmpr1_b_up_st:1; + uint32_t mcpwm1_task_cmpr1_b_up_st: 1; /** mcpwm1_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cmpr2_b_up_st:1; + uint32_t mcpwm1_task_cmpr2_b_up_st: 1; /** mcpwm1_task_gen_stop_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_gen_stop_st:1; + uint32_t mcpwm1_task_gen_stop_st: 1; /** mcpwm1_task_timer0_syn_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_timer0_syn_st:1; + uint32_t mcpwm1_task_timer0_syn_st: 1; /** mcpwm1_task_timer1_syn_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_timer1_syn_st:1; + uint32_t mcpwm1_task_timer1_syn_st: 1; /** mcpwm1_task_timer2_syn_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_timer2_syn_st:1; + uint32_t mcpwm1_task_timer2_syn_st: 1; /** mcpwm1_task_timer0_period_up_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t mcpwm1_task_timer0_period_up_st:1; + uint32_t mcpwm1_task_timer0_period_up_st: 1; /** mcpwm1_task_timer1_period_up_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t mcpwm1_task_timer1_period_up_st:1; + uint32_t mcpwm1_task_timer1_period_up_st: 1; /** mcpwm1_task_timer2_period_up_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t mcpwm1_task_timer2_period_up_st:1; + uint32_t mcpwm1_task_timer2_period_up_st: 1; /** mcpwm1_task_tz0_ost_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_tz0_ost_st:1; + uint32_t mcpwm1_task_tz0_ost_st: 1; /** mcpwm1_task_tz1_ost_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_tz1_ost_st:1; + uint32_t mcpwm1_task_tz1_ost_st: 1; /** mcpwm1_task_tz2_ost_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_tz2_ost_st:1; + uint32_t mcpwm1_task_tz2_ost_st: 1; /** mcpwm1_task_clr0_ost_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_clr0_ost_st:1; + uint32_t mcpwm1_task_clr0_ost_st: 1; /** mcpwm1_task_clr1_ost_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_clr1_ost_st:1; + uint32_t mcpwm1_task_clr1_ost_st: 1; /** mcpwm1_task_clr2_ost_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_clr2_ost_st:1; + uint32_t mcpwm1_task_clr2_ost_st: 1; /** mcpwm1_task_cap0_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cap0_st:1; + uint32_t mcpwm1_task_cap0_st: 1; /** mcpwm1_task_cap1_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cap1_st:1; + uint32_t mcpwm1_task_cap1_st: 1; /** mcpwm1_task_cap2_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t mcpwm1_task_cap2_st:1; + uint32_t mcpwm1_task_cap2_st: 1; /** adc_task_sample0_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_task_sample0_st:1; + uint32_t adc_task_sample0_st: 1; /** adc_task_sample1_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_task_sample1_st:1; + uint32_t adc_task_sample1_st: 1; /** adc_task_start0_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_task_start0_st:1; + uint32_t adc_task_start0_st: 1; /** adc_task_stop0_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t adc_task_stop0_st:1; + uint32_t adc_task_stop0_st: 1; }; uint32_t val; } soc_etm_task_st4_reg_t; @@ -2021,139 +2021,139 @@ typedef union { /** regdma_task_start0_st : R/WTC/SS; bitpos: [0]; default: 0; * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_task_start0_st:1; + uint32_t regdma_task_start0_st: 1; /** regdma_task_start1_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_task_start1_st:1; + uint32_t regdma_task_start1_st: 1; /** regdma_task_start2_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_task_start2_st:1; + uint32_t regdma_task_start2_st: 1; /** regdma_task_start3_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t regdma_task_start3_st:1; + uint32_t regdma_task_start3_st: 1; /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tmpsnsr_task_start_sample_st:1; + uint32_t tmpsnsr_task_start_sample_st: 1; /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t tmpsnsr_task_stop_sample_st:1; + uint32_t tmpsnsr_task_stop_sample_st: 1; /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_task_start_rx_st:1; + uint32_t i2s0_task_start_rx_st: 1; /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_task_start_tx_st:1; + uint32_t i2s0_task_start_tx_st: 1; /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_task_stop_rx_st:1; + uint32_t i2s0_task_stop_rx_st: 1; /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s0_task_stop_tx_st:1; + uint32_t i2s0_task_stop_tx_st: 1; /** i2s1_task_start_rx_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_task_start_rx_st:1; + uint32_t i2s1_task_start_rx_st: 1; /** i2s1_task_start_tx_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_task_start_tx_st:1; + uint32_t i2s1_task_start_tx_st: 1; /** i2s1_task_stop_rx_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_task_stop_rx_st:1; + uint32_t i2s1_task_stop_rx_st: 1; /** i2s1_task_stop_tx_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s1_task_stop_tx_st:1; + uint32_t i2s1_task_stop_tx_st: 1; /** i2s2_task_start_rx_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_task_start_rx_st:1; + uint32_t i2s2_task_start_rx_st: 1; /** i2s2_task_start_tx_st : R/WTC/SS; bitpos: [15]; default: 0; * Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_task_start_tx_st:1; + uint32_t i2s2_task_start_tx_st: 1; /** i2s2_task_stop_rx_st : R/WTC/SS; bitpos: [16]; default: 0; * Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_task_stop_rx_st:1; + uint32_t i2s2_task_stop_rx_st: 1; /** i2s2_task_stop_tx_st : R/WTC/SS; bitpos: [17]; default: 0; * Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t i2s2_task_stop_tx_st:1; + uint32_t i2s2_task_stop_tx_st: 1; /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [18]; default: 0; * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ulp_task_wakeup_cpu_st:1; + uint32_t ulp_task_wakeup_cpu_st: 1; /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [19]; default: 0; * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t ulp_task_int_cpu_st:1; + uint32_t ulp_task_int_cpu_st: 1; /** rtc_task_start_st : R/WTC/SS; bitpos: [20]; default: 0; * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_task_start_st:1; + uint32_t rtc_task_start_st: 1; /** rtc_task_stop_st : R/WTC/SS; bitpos: [21]; default: 0; * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_task_stop_st:1; + uint32_t rtc_task_stop_st: 1; /** rtc_task_clr_st : R/WTC/SS; bitpos: [22]; default: 0; * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_task_clr_st:1; + uint32_t rtc_task_clr_st: 1; /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [23]; default: 0; * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t rtc_task_triggerflw_st:1; + uint32_t rtc_task_triggerflw_st: 1; /** pdma_ahb_task_in_start_ch0_st : R/WTC/SS; bitpos: [24]; default: 0; * Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_task_in_start_ch0_st:1; + uint32_t pdma_ahb_task_in_start_ch0_st: 1; /** pdma_ahb_task_in_start_ch1_st : R/WTC/SS; bitpos: [25]; default: 0; * Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_task_in_start_ch1_st:1; + uint32_t pdma_ahb_task_in_start_ch1_st: 1; /** pdma_ahb_task_in_start_ch2_st : R/WTC/SS; bitpos: [26]; default: 0; * Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_task_in_start_ch2_st:1; + uint32_t pdma_ahb_task_in_start_ch2_st: 1; /** pdma_ahb_task_out_start_ch0_st : R/WTC/SS; bitpos: [27]; default: 0; * Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_task_out_start_ch0_st:1; + uint32_t pdma_ahb_task_out_start_ch0_st: 1; /** pdma_ahb_task_out_start_ch1_st : R/WTC/SS; bitpos: [28]; default: 0; * Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_task_out_start_ch1_st:1; + uint32_t pdma_ahb_task_out_start_ch1_st: 1; /** pdma_ahb_task_out_start_ch2_st : R/WTC/SS; bitpos: [29]; default: 0; * Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_ahb_task_out_start_ch2_st:1; + uint32_t pdma_ahb_task_out_start_ch2_st: 1; /** pdma_axi_task_in_start_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; * Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_task_in_start_ch0_st:1; + uint32_t pdma_axi_task_in_start_ch0_st: 1; /** pdma_axi_task_in_start_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; * Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_task_in_start_ch1_st:1; + uint32_t pdma_axi_task_in_start_ch1_st: 1; }; uint32_t val; } soc_etm_task_st5_reg_t; @@ -2167,77 +2167,76 @@ typedef union { * Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_task_in_start_ch2_st:1; + uint32_t pdma_axi_task_in_start_ch2_st: 1; /** pdma_axi_task_out_start_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; * Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_task_out_start_ch0_st:1; + uint32_t pdma_axi_task_out_start_ch0_st: 1; /** pdma_axi_task_out_start_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; * Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_task_out_start_ch1_st:1; + uint32_t pdma_axi_task_out_start_ch1_st: 1; /** pdma_axi_task_out_start_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; * Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t pdma_axi_task_out_start_ch2_st:1; + uint32_t pdma_axi_task_out_start_ch2_st: 1; /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [4]; default: 0; * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t pmu_task_sleep_req_st:1; + uint32_t pmu_task_sleep_req_st: 1; /** dma2d_task_in_start_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; * Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_task_in_start_ch0_st:1; + uint32_t dma2d_task_in_start_ch0_st: 1; /** dma2d_task_in_start_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; * Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_task_in_start_ch1_st:1; + uint32_t dma2d_task_in_start_ch1_st: 1; /** dma2d_task_in_dscr_ready_ch0_st : R/WTC/SS; bitpos: [7]; default: 0; * Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_task_in_dscr_ready_ch0_st:1; + uint32_t dma2d_task_in_dscr_ready_ch0_st: 1; /** dma2d_task_in_dscr_ready_ch1_st : R/WTC/SS; bitpos: [8]; default: 0; * Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_task_in_dscr_ready_ch1_st:1; + uint32_t dma2d_task_in_dscr_ready_ch1_st: 1; /** dma2d_task_out_start_ch0_st : R/WTC/SS; bitpos: [9]; default: 0; * Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_task_out_start_ch0_st:1; + uint32_t dma2d_task_out_start_ch0_st: 1; /** dma2d_task_out_start_ch1_st : R/WTC/SS; bitpos: [10]; default: 0; * Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_task_out_start_ch1_st:1; + uint32_t dma2d_task_out_start_ch1_st: 1; /** dma2d_task_out_start_ch2_st : R/WTC/SS; bitpos: [11]; default: 0; * Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered */ - uint32_t dma2d_task_out_start_ch2_st:1; + uint32_t dma2d_task_out_start_ch2_st: 1; /** dma2d_task_out_dscr_ready_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; * Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_task_out_dscr_ready_ch0_st:1; + uint32_t dma2d_task_out_dscr_ready_ch0_st: 1; /** dma2d_task_out_dscr_ready_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; * Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_task_out_dscr_ready_ch1_st:1; + uint32_t dma2d_task_out_dscr_ready_ch1_st: 1; /** dma2d_task_out_dscr_ready_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; * Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1: * Triggered */ - uint32_t dma2d_task_out_dscr_ready_ch2_st:1; - uint32_t reserved_15:17; + uint32_t dma2d_task_out_dscr_ready_ch2_st: 1; + uint32_t reserved_15: 17; }; uint32_t val; } soc_etm_task_st6_reg_t; - /** Group: Configuration Register */ /** Type of ch_ena_ad0_set register * Channel enable set register @@ -2247,131 +2246,131 @@ typedef union { /** ch_set0 : WT; bitpos: [0]; default: 0; * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set0:1; + uint32_t ch_set0: 1; /** ch_set1 : WT; bitpos: [1]; default: 0; * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set1:1; + uint32_t ch_set1: 1; /** ch_set2 : WT; bitpos: [2]; default: 0; * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set2:1; + uint32_t ch_set2: 1; /** ch_set3 : WT; bitpos: [3]; default: 0; * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set3:1; + uint32_t ch_set3: 1; /** ch_set4 : WT; bitpos: [4]; default: 0; * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set4:1; + uint32_t ch_set4: 1; /** ch_set5 : WT; bitpos: [5]; default: 0; * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set5:1; + uint32_t ch_set5: 1; /** ch_set6 : WT; bitpos: [6]; default: 0; * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set6:1; + uint32_t ch_set6: 1; /** ch_set7 : WT; bitpos: [7]; default: 0; * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set7:1; + uint32_t ch_set7: 1; /** ch_set8 : WT; bitpos: [8]; default: 0; * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set8:1; + uint32_t ch_set8: 1; /** ch_set9 : WT; bitpos: [9]; default: 0; * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set9:1; + uint32_t ch_set9: 1; /** ch_set10 : WT; bitpos: [10]; default: 0; * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set10:1; + uint32_t ch_set10: 1; /** ch_set11 : WT; bitpos: [11]; default: 0; * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set11:1; + uint32_t ch_set11: 1; /** ch_set12 : WT; bitpos: [12]; default: 0; * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set12:1; + uint32_t ch_set12: 1; /** ch_set13 : WT; bitpos: [13]; default: 0; * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set13:1; + uint32_t ch_set13: 1; /** ch_set14 : WT; bitpos: [14]; default: 0; * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set14:1; + uint32_t ch_set14: 1; /** ch_set15 : WT; bitpos: [15]; default: 0; * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set15:1; + uint32_t ch_set15: 1; /** ch_set16 : WT; bitpos: [16]; default: 0; * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set16:1; + uint32_t ch_set16: 1; /** ch_set17 : WT; bitpos: [17]; default: 0; * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set17:1; + uint32_t ch_set17: 1; /** ch_set18 : WT; bitpos: [18]; default: 0; * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set18:1; + uint32_t ch_set18: 1; /** ch_set19 : WT; bitpos: [19]; default: 0; * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set19:1; + uint32_t ch_set19: 1; /** ch_set20 : WT; bitpos: [20]; default: 0; * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set20:1; + uint32_t ch_set20: 1; /** ch_set21 : WT; bitpos: [21]; default: 0; * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set21:1; + uint32_t ch_set21: 1; /** ch_set22 : WT; bitpos: [22]; default: 0; * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set22:1; + uint32_t ch_set22: 1; /** ch_set23 : WT; bitpos: [23]; default: 0; * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set23:1; + uint32_t ch_set23: 1; /** ch_set24 : WT; bitpos: [24]; default: 0; * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set24:1; + uint32_t ch_set24: 1; /** ch_set25 : WT; bitpos: [25]; default: 0; * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set25:1; + uint32_t ch_set25: 1; /** ch_set26 : WT; bitpos: [26]; default: 0; * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set26:1; + uint32_t ch_set26: 1; /** ch_set27 : WT; bitpos: [27]; default: 0; * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set27:1; + uint32_t ch_set27: 1; /** ch_set28 : WT; bitpos: [28]; default: 0; * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set28:1; + uint32_t ch_set28: 1; /** ch_set29 : WT; bitpos: [29]; default: 0; * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set29:1; + uint32_t ch_set29: 1; /** ch_set30 : WT; bitpos: [30]; default: 0; * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set30:1; + uint32_t ch_set30: 1; /** ch_set31 : WT; bitpos: [31]; default: 0; * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set31:1; + uint32_t ch_set31: 1; }; uint32_t val; } soc_etm_ch_ena_ad0_set_reg_t; @@ -2384,131 +2383,131 @@ typedef union { /** ch_clr0 : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr0:1; + uint32_t ch_clr0: 1; /** ch_clr1 : WT; bitpos: [1]; default: 0; * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr1:1; + uint32_t ch_clr1: 1; /** ch_clr2 : WT; bitpos: [2]; default: 0; * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr2:1; + uint32_t ch_clr2: 1; /** ch_clr3 : WT; bitpos: [3]; default: 0; * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr3:1; + uint32_t ch_clr3: 1; /** ch_clr4 : WT; bitpos: [4]; default: 0; * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr4:1; + uint32_t ch_clr4: 1; /** ch_clr5 : WT; bitpos: [5]; default: 0; * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr5:1; + uint32_t ch_clr5: 1; /** ch_clr6 : WT; bitpos: [6]; default: 0; * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr6:1; + uint32_t ch_clr6: 1; /** ch_clr7 : WT; bitpos: [7]; default: 0; * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr7:1; + uint32_t ch_clr7: 1; /** ch_clr8 : WT; bitpos: [8]; default: 0; * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr8:1; + uint32_t ch_clr8: 1; /** ch_clr9 : WT; bitpos: [9]; default: 0; * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr9:1; + uint32_t ch_clr9: 1; /** ch_clr10 : WT; bitpos: [10]; default: 0; * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr10:1; + uint32_t ch_clr10: 1; /** ch_clr11 : WT; bitpos: [11]; default: 0; * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr11:1; + uint32_t ch_clr11: 1; /** ch_clr12 : WT; bitpos: [12]; default: 0; * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr12:1; + uint32_t ch_clr12: 1; /** ch_clr13 : WT; bitpos: [13]; default: 0; * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr13:1; + uint32_t ch_clr13: 1; /** ch_clr14 : WT; bitpos: [14]; default: 0; * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr14:1; + uint32_t ch_clr14: 1; /** ch_clr15 : WT; bitpos: [15]; default: 0; * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr15:1; + uint32_t ch_clr15: 1; /** ch_clr16 : WT; bitpos: [16]; default: 0; * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr16:1; + uint32_t ch_clr16: 1; /** ch_clr17 : WT; bitpos: [17]; default: 0; * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr17:1; + uint32_t ch_clr17: 1; /** ch_clr18 : WT; bitpos: [18]; default: 0; * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr18:1; + uint32_t ch_clr18: 1; /** ch_clr19 : WT; bitpos: [19]; default: 0; * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr19:1; + uint32_t ch_clr19: 1; /** ch_clr20 : WT; bitpos: [20]; default: 0; * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr20:1; + uint32_t ch_clr20: 1; /** ch_clr21 : WT; bitpos: [21]; default: 0; * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr21:1; + uint32_t ch_clr21: 1; /** ch_clr22 : WT; bitpos: [22]; default: 0; * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr22:1; + uint32_t ch_clr22: 1; /** ch_clr23 : WT; bitpos: [23]; default: 0; * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr23:1; + uint32_t ch_clr23: 1; /** ch_clr24 : WT; bitpos: [24]; default: 0; * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr24:1; + uint32_t ch_clr24: 1; /** ch_clr25 : WT; bitpos: [25]; default: 0; * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr25:1; + uint32_t ch_clr25: 1; /** ch_clr26 : WT; bitpos: [26]; default: 0; * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr26:1; + uint32_t ch_clr26: 1; /** ch_clr27 : WT; bitpos: [27]; default: 0; * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr27:1; + uint32_t ch_clr27: 1; /** ch_clr28 : WT; bitpos: [28]; default: 0; * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr28:1; + uint32_t ch_clr28: 1; /** ch_clr29 : WT; bitpos: [29]; default: 0; * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr29:1; + uint32_t ch_clr29: 1; /** ch_clr30 : WT; bitpos: [30]; default: 0; * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr30:1; + uint32_t ch_clr30: 1; /** ch_clr31 : WT; bitpos: [31]; default: 0; * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr31:1; + uint32_t ch_clr31: 1; }; uint32_t val; } soc_etm_ch_ena_ad0_clr_reg_t; @@ -2521,76 +2520,76 @@ typedef union { /** ch_set32 : WT; bitpos: [0]; default: 0; * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set32:1; + uint32_t ch_set32: 1; /** ch_set33 : WT; bitpos: [1]; default: 0; * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set33:1; + uint32_t ch_set33: 1; /** ch_set34 : WT; bitpos: [2]; default: 0; * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set34:1; + uint32_t ch_set34: 1; /** ch_set35 : WT; bitpos: [3]; default: 0; * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set35:1; + uint32_t ch_set35: 1; /** ch_set36 : WT; bitpos: [4]; default: 0; * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set36:1; + uint32_t ch_set36: 1; /** ch_set37 : WT; bitpos: [5]; default: 0; * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set37:1; + uint32_t ch_set37: 1; /** ch_set38 : WT; bitpos: [6]; default: 0; * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set38:1; + uint32_t ch_set38: 1; /** ch_set39 : WT; bitpos: [7]; default: 0; * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set39:1; + uint32_t ch_set39: 1; /** ch_set40 : WT; bitpos: [8]; default: 0; * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set40:1; + uint32_t ch_set40: 1; /** ch_set41 : WT; bitpos: [9]; default: 0; * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set41:1; + uint32_t ch_set41: 1; /** ch_set42 : WT; bitpos: [10]; default: 0; * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set42:1; + uint32_t ch_set42: 1; /** ch_set43 : WT; bitpos: [11]; default: 0; * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set43:1; + uint32_t ch_set43: 1; /** ch_set44 : WT; bitpos: [12]; default: 0; * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set44:1; + uint32_t ch_set44: 1; /** ch_set45 : WT; bitpos: [13]; default: 0; * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set45:1; + uint32_t ch_set45: 1; /** ch_set46 : WT; bitpos: [14]; default: 0; * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set46:1; + uint32_t ch_set46: 1; /** ch_set47 : WT; bitpos: [15]; default: 0; * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set47:1; + uint32_t ch_set47: 1; /** ch_set48 : WT; bitpos: [16]; default: 0; * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set48:1; + uint32_t ch_set48: 1; /** ch_set49 : WT; bitpos: [17]; default: 0; * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable */ - uint32_t ch_set49:1; - uint32_t reserved_18:14; + uint32_t ch_set49: 1; + uint32_t reserved_18: 14; }; uint32_t val; } soc_etm_ch_ena_ad1_set_reg_t; @@ -2603,1479 +2602,107 @@ typedef union { /** ch_clr32 : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr32:1; + uint32_t ch_clr32: 1; /** ch_clr33 : WT; bitpos: [1]; default: 0; * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr33:1; + uint32_t ch_clr33: 1; /** ch_clr34 : WT; bitpos: [2]; default: 0; * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr34:1; + uint32_t ch_clr34: 1; /** ch_clr35 : WT; bitpos: [3]; default: 0; * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr35:1; + uint32_t ch_clr35: 1; /** ch_clr36 : WT; bitpos: [4]; default: 0; * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr36:1; + uint32_t ch_clr36: 1; /** ch_clr37 : WT; bitpos: [5]; default: 0; * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr37:1; + uint32_t ch_clr37: 1; /** ch_clr38 : WT; bitpos: [6]; default: 0; * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr38:1; + uint32_t ch_clr38: 1; /** ch_clr39 : WT; bitpos: [7]; default: 0; * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr39:1; + uint32_t ch_clr39: 1; /** ch_clr40 : WT; bitpos: [8]; default: 0; * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr40:1; + uint32_t ch_clr40: 1; /** ch_clr41 : WT; bitpos: [9]; default: 0; * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr41:1; + uint32_t ch_clr41: 1; /** ch_clr42 : WT; bitpos: [10]; default: 0; * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr42:1; + uint32_t ch_clr42: 1; /** ch_clr43 : WT; bitpos: [11]; default: 0; * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr43:1; + uint32_t ch_clr43: 1; /** ch_clr44 : WT; bitpos: [12]; default: 0; * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr44:1; + uint32_t ch_clr44: 1; /** ch_clr45 : WT; bitpos: [13]; default: 0; * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr45:1; + uint32_t ch_clr45: 1; /** ch_clr46 : WT; bitpos: [14]; default: 0; * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr46:1; + uint32_t ch_clr46: 1; /** ch_clr47 : WT; bitpos: [15]; default: 0; * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr47:1; + uint32_t ch_clr47: 1; /** ch_clr48 : WT; bitpos: [16]; default: 0; * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr48:1; + uint32_t ch_clr48: 1; /** ch_clr49 : WT; bitpos: [17]; default: 0; * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear */ - uint32_t ch_clr49:1; - uint32_t reserved_18:14; + uint32_t ch_clr49: 1; + uint32_t reserved_18: 14; }; uint32_t val; } soc_etm_ch_ena_ad1_clr_reg_t; -/** Type of ch0_evt_id register - * Channel0 event id register +/** Type of chn_evt_id register + * Channeln event id register */ typedef union { struct { - /** ch0_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch0_evt_id + /** evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures chn_evt_id */ - uint32_t ch0_evt_id:8; - uint32_t reserved_8:24; + uint32_t evt_id: 8; + uint32_t reserved_8: 24; }; uint32_t val; -} soc_etm_ch0_evt_id_reg_t; +} soc_etm_chn_evt_id_reg_t; -/** Type of ch0_task_id register - * Channel0 task id register +/** Type of chn_task_id register + * Channeln task id register */ typedef union { struct { - /** ch0_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch0_task_id + /** chn_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures chn_task_id */ - uint32_t ch0_task_id:8; - uint32_t reserved_8:24; + uint32_t task_id: 8; + uint32_t reserved_8: 24; }; uint32_t val; -} soc_etm_ch0_task_id_reg_t; - -/** Type of ch1_evt_id register - * Channel1 event id register - */ -typedef union { - struct { - /** ch1_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch1_evt_id - */ - uint32_t ch1_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch1_evt_id_reg_t; - -/** Type of ch1_task_id register - * Channel1 task id register - */ -typedef union { - struct { - /** ch1_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch1_task_id - */ - uint32_t ch1_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch1_task_id_reg_t; - -/** Type of ch2_evt_id register - * Channel2 event id register - */ -typedef union { - struct { - /** ch2_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch2_evt_id - */ - uint32_t ch2_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch2_evt_id_reg_t; - -/** Type of ch2_task_id register - * Channel2 task id register - */ -typedef union { - struct { - /** ch2_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch2_task_id - */ - uint32_t ch2_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch2_task_id_reg_t; - -/** Type of ch3_evt_id register - * Channel3 event id register - */ -typedef union { - struct { - /** ch3_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch3_evt_id - */ - uint32_t ch3_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch3_evt_id_reg_t; - -/** Type of ch3_task_id register - * Channel3 task id register - */ -typedef union { - struct { - /** ch3_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch3_task_id - */ - uint32_t ch3_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch3_task_id_reg_t; - -/** Type of ch4_evt_id register - * Channel4 event id register - */ -typedef union { - struct { - /** ch4_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch4_evt_id - */ - uint32_t ch4_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch4_evt_id_reg_t; - -/** Type of ch4_task_id register - * Channel4 task id register - */ -typedef union { - struct { - /** ch4_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch4_task_id - */ - uint32_t ch4_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch4_task_id_reg_t; - -/** Type of ch5_evt_id register - * Channel5 event id register - */ -typedef union { - struct { - /** ch5_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch5_evt_id - */ - uint32_t ch5_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch5_evt_id_reg_t; - -/** Type of ch5_task_id register - * Channel5 task id register - */ -typedef union { - struct { - /** ch5_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch5_task_id - */ - uint32_t ch5_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch5_task_id_reg_t; - -/** Type of ch6_evt_id register - * Channel6 event id register - */ -typedef union { - struct { - /** ch6_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch6_evt_id - */ - uint32_t ch6_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch6_evt_id_reg_t; - -/** Type of ch6_task_id register - * Channel6 task id register - */ -typedef union { - struct { - /** ch6_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch6_task_id - */ - uint32_t ch6_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch6_task_id_reg_t; - -/** Type of ch7_evt_id register - * Channel7 event id register - */ -typedef union { - struct { - /** ch7_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch7_evt_id - */ - uint32_t ch7_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch7_evt_id_reg_t; - -/** Type of ch7_task_id register - * Channel7 task id register - */ -typedef union { - struct { - /** ch7_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch7_task_id - */ - uint32_t ch7_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch7_task_id_reg_t; - -/** Type of ch8_evt_id register - * Channel8 event id register - */ -typedef union { - struct { - /** ch8_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch8_evt_id - */ - uint32_t ch8_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch8_evt_id_reg_t; - -/** Type of ch8_task_id register - * Channel8 task id register - */ -typedef union { - struct { - /** ch8_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch8_task_id - */ - uint32_t ch8_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch8_task_id_reg_t; - -/** Type of ch9_evt_id register - * Channel9 event id register - */ -typedef union { - struct { - /** ch9_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch9_evt_id - */ - uint32_t ch9_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch9_evt_id_reg_t; - -/** Type of ch9_task_id register - * Channel9 task id register - */ -typedef union { - struct { - /** ch9_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch9_task_id - */ - uint32_t ch9_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch9_task_id_reg_t; - -/** Type of ch10_evt_id register - * Channel10 event id register - */ -typedef union { - struct { - /** ch10_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch10_evt_id - */ - uint32_t ch10_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch10_evt_id_reg_t; - -/** Type of ch10_task_id register - * Channel10 task id register - */ -typedef union { - struct { - /** ch10_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch10_task_id - */ - uint32_t ch10_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch10_task_id_reg_t; - -/** Type of ch11_evt_id register - * Channel11 event id register - */ -typedef union { - struct { - /** ch11_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch11_evt_id - */ - uint32_t ch11_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch11_evt_id_reg_t; - -/** Type of ch11_task_id register - * Channel11 task id register - */ -typedef union { - struct { - /** ch11_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch11_task_id - */ - uint32_t ch11_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch11_task_id_reg_t; - -/** Type of ch12_evt_id register - * Channel12 event id register - */ -typedef union { - struct { - /** ch12_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch12_evt_id - */ - uint32_t ch12_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch12_evt_id_reg_t; - -/** Type of ch12_task_id register - * Channel12 task id register - */ -typedef union { - struct { - /** ch12_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch12_task_id - */ - uint32_t ch12_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch12_task_id_reg_t; - -/** Type of ch13_evt_id register - * Channel13 event id register - */ -typedef union { - struct { - /** ch13_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch13_evt_id - */ - uint32_t ch13_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch13_evt_id_reg_t; - -/** Type of ch13_task_id register - * Channel13 task id register - */ -typedef union { - struct { - /** ch13_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch13_task_id - */ - uint32_t ch13_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch13_task_id_reg_t; - -/** Type of ch14_evt_id register - * Channel14 event id register - */ -typedef union { - struct { - /** ch14_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch14_evt_id - */ - uint32_t ch14_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch14_evt_id_reg_t; - -/** Type of ch14_task_id register - * Channel14 task id register - */ -typedef union { - struct { - /** ch14_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch14_task_id - */ - uint32_t ch14_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch14_task_id_reg_t; - -/** Type of ch15_evt_id register - * Channel15 event id register - */ -typedef union { - struct { - /** ch15_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch15_evt_id - */ - uint32_t ch15_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch15_evt_id_reg_t; - -/** Type of ch15_task_id register - * Channel15 task id register - */ -typedef union { - struct { - /** ch15_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch15_task_id - */ - uint32_t ch15_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch15_task_id_reg_t; - -/** Type of ch16_evt_id register - * Channel16 event id register - */ -typedef union { - struct { - /** ch16_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch16_evt_id - */ - uint32_t ch16_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch16_evt_id_reg_t; - -/** Type of ch16_task_id register - * Channel16 task id register - */ -typedef union { - struct { - /** ch16_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch16_task_id - */ - uint32_t ch16_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch16_task_id_reg_t; - -/** Type of ch17_evt_id register - * Channel17 event id register - */ -typedef union { - struct { - /** ch17_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch17_evt_id - */ - uint32_t ch17_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch17_evt_id_reg_t; - -/** Type of ch17_task_id register - * Channel17 task id register - */ -typedef union { - struct { - /** ch17_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch17_task_id - */ - uint32_t ch17_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch17_task_id_reg_t; - -/** Type of ch18_evt_id register - * Channel18 event id register - */ -typedef union { - struct { - /** ch18_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch18_evt_id - */ - uint32_t ch18_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch18_evt_id_reg_t; - -/** Type of ch18_task_id register - * Channel18 task id register - */ -typedef union { - struct { - /** ch18_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch18_task_id - */ - uint32_t ch18_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch18_task_id_reg_t; - -/** Type of ch19_evt_id register - * Channel19 event id register - */ -typedef union { - struct { - /** ch19_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch19_evt_id - */ - uint32_t ch19_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch19_evt_id_reg_t; - -/** Type of ch19_task_id register - * Channel19 task id register - */ -typedef union { - struct { - /** ch19_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch19_task_id - */ - uint32_t ch19_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch19_task_id_reg_t; - -/** Type of ch20_evt_id register - * Channel20 event id register - */ -typedef union { - struct { - /** ch20_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch20_evt_id - */ - uint32_t ch20_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch20_evt_id_reg_t; - -/** Type of ch20_task_id register - * Channel20 task id register - */ -typedef union { - struct { - /** ch20_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch20_task_id - */ - uint32_t ch20_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch20_task_id_reg_t; - -/** Type of ch21_evt_id register - * Channel21 event id register - */ -typedef union { - struct { - /** ch21_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch21_evt_id - */ - uint32_t ch21_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch21_evt_id_reg_t; - -/** Type of ch21_task_id register - * Channel21 task id register - */ -typedef union { - struct { - /** ch21_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch21_task_id - */ - uint32_t ch21_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch21_task_id_reg_t; - -/** Type of ch22_evt_id register - * Channel22 event id register - */ -typedef union { - struct { - /** ch22_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch22_evt_id - */ - uint32_t ch22_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch22_evt_id_reg_t; - -/** Type of ch22_task_id register - * Channel22 task id register - */ -typedef union { - struct { - /** ch22_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch22_task_id - */ - uint32_t ch22_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch22_task_id_reg_t; - -/** Type of ch23_evt_id register - * Channel23 event id register - */ -typedef union { - struct { - /** ch23_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch23_evt_id - */ - uint32_t ch23_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch23_evt_id_reg_t; - -/** Type of ch23_task_id register - * Channel23 task id register - */ -typedef union { - struct { - /** ch23_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch23_task_id - */ - uint32_t ch23_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch23_task_id_reg_t; - -/** Type of ch24_evt_id register - * Channel24 event id register - */ -typedef union { - struct { - /** ch24_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch24_evt_id - */ - uint32_t ch24_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch24_evt_id_reg_t; - -/** Type of ch24_task_id register - * Channel24 task id register - */ -typedef union { - struct { - /** ch24_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch24_task_id - */ - uint32_t ch24_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch24_task_id_reg_t; - -/** Type of ch25_evt_id register - * Channel25 event id register - */ -typedef union { - struct { - /** ch25_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch25_evt_id - */ - uint32_t ch25_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch25_evt_id_reg_t; - -/** Type of ch25_task_id register - * Channel25 task id register - */ -typedef union { - struct { - /** ch25_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch25_task_id - */ - uint32_t ch25_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch25_task_id_reg_t; - -/** Type of ch26_evt_id register - * Channel26 event id register - */ -typedef union { - struct { - /** ch26_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch26_evt_id - */ - uint32_t ch26_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch26_evt_id_reg_t; - -/** Type of ch26_task_id register - * Channel26 task id register - */ -typedef union { - struct { - /** ch26_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch26_task_id - */ - uint32_t ch26_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch26_task_id_reg_t; - -/** Type of ch27_evt_id register - * Channel27 event id register - */ -typedef union { - struct { - /** ch27_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch27_evt_id - */ - uint32_t ch27_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch27_evt_id_reg_t; - -/** Type of ch27_task_id register - * Channel27 task id register - */ -typedef union { - struct { - /** ch27_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch27_task_id - */ - uint32_t ch27_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch27_task_id_reg_t; - -/** Type of ch28_evt_id register - * Channel28 event id register - */ -typedef union { - struct { - /** ch28_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch28_evt_id - */ - uint32_t ch28_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch28_evt_id_reg_t; - -/** Type of ch28_task_id register - * Channel28 task id register - */ -typedef union { - struct { - /** ch28_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch28_task_id - */ - uint32_t ch28_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch28_task_id_reg_t; - -/** Type of ch29_evt_id register - * Channel29 event id register - */ -typedef union { - struct { - /** ch29_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch29_evt_id - */ - uint32_t ch29_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch29_evt_id_reg_t; - -/** Type of ch29_task_id register - * Channel29 task id register - */ -typedef union { - struct { - /** ch29_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch29_task_id - */ - uint32_t ch29_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch29_task_id_reg_t; - -/** Type of ch30_evt_id register - * Channel30 event id register - */ -typedef union { - struct { - /** ch30_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch30_evt_id - */ - uint32_t ch30_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch30_evt_id_reg_t; - -/** Type of ch30_task_id register - * Channel30 task id register - */ -typedef union { - struct { - /** ch30_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch30_task_id - */ - uint32_t ch30_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch30_task_id_reg_t; - -/** Type of ch31_evt_id register - * Channel31 event id register - */ -typedef union { - struct { - /** ch31_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch31_evt_id - */ - uint32_t ch31_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch31_evt_id_reg_t; - -/** Type of ch31_task_id register - * Channel31 task id register - */ -typedef union { - struct { - /** ch31_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch31_task_id - */ - uint32_t ch31_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch31_task_id_reg_t; - -/** Type of ch32_evt_id register - * Channel32 event id register - */ -typedef union { - struct { - /** ch32_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch32_evt_id - */ - uint32_t ch32_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch32_evt_id_reg_t; - -/** Type of ch32_task_id register - * Channel32 task id register - */ -typedef union { - struct { - /** ch32_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch32_task_id - */ - uint32_t ch32_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch32_task_id_reg_t; - -/** Type of ch33_evt_id register - * Channel33 event id register - */ -typedef union { - struct { - /** ch33_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch33_evt_id - */ - uint32_t ch33_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch33_evt_id_reg_t; - -/** Type of ch33_task_id register - * Channel33 task id register - */ -typedef union { - struct { - /** ch33_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch33_task_id - */ - uint32_t ch33_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch33_task_id_reg_t; - -/** Type of ch34_evt_id register - * Channel34 event id register - */ -typedef union { - struct { - /** ch34_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch34_evt_id - */ - uint32_t ch34_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch34_evt_id_reg_t; - -/** Type of ch34_task_id register - * Channel34 task id register - */ -typedef union { - struct { - /** ch34_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch34_task_id - */ - uint32_t ch34_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch34_task_id_reg_t; - -/** Type of ch35_evt_id register - * Channel35 event id register - */ -typedef union { - struct { - /** ch35_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch35_evt_id - */ - uint32_t ch35_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch35_evt_id_reg_t; - -/** Type of ch35_task_id register - * Channel35 task id register - */ -typedef union { - struct { - /** ch35_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch35_task_id - */ - uint32_t ch35_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch35_task_id_reg_t; - -/** Type of ch36_evt_id register - * Channel36 event id register - */ -typedef union { - struct { - /** ch36_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch36_evt_id - */ - uint32_t ch36_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch36_evt_id_reg_t; - -/** Type of ch36_task_id register - * Channel36 task id register - */ -typedef union { - struct { - /** ch36_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch36_task_id - */ - uint32_t ch36_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch36_task_id_reg_t; - -/** Type of ch37_evt_id register - * Channel37 event id register - */ -typedef union { - struct { - /** ch37_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch37_evt_id - */ - uint32_t ch37_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch37_evt_id_reg_t; - -/** Type of ch37_task_id register - * Channel37 task id register - */ -typedef union { - struct { - /** ch37_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch37_task_id - */ - uint32_t ch37_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch37_task_id_reg_t; - -/** Type of ch38_evt_id register - * Channel38 event id register - */ -typedef union { - struct { - /** ch38_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch38_evt_id - */ - uint32_t ch38_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch38_evt_id_reg_t; - -/** Type of ch38_task_id register - * Channel38 task id register - */ -typedef union { - struct { - /** ch38_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch38_task_id - */ - uint32_t ch38_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch38_task_id_reg_t; - -/** Type of ch39_evt_id register - * Channel39 event id register - */ -typedef union { - struct { - /** ch39_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch39_evt_id - */ - uint32_t ch39_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch39_evt_id_reg_t; - -/** Type of ch39_task_id register - * Channel39 task id register - */ -typedef union { - struct { - /** ch39_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch39_task_id - */ - uint32_t ch39_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch39_task_id_reg_t; - -/** Type of ch40_evt_id register - * Channel40 event id register - */ -typedef union { - struct { - /** ch40_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch40_evt_id - */ - uint32_t ch40_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch40_evt_id_reg_t; - -/** Type of ch40_task_id register - * Channel40 task id register - */ -typedef union { - struct { - /** ch40_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch40_task_id - */ - uint32_t ch40_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch40_task_id_reg_t; - -/** Type of ch41_evt_id register - * Channel41 event id register - */ -typedef union { - struct { - /** ch41_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch41_evt_id - */ - uint32_t ch41_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch41_evt_id_reg_t; - -/** Type of ch41_task_id register - * Channel41 task id register - */ -typedef union { - struct { - /** ch41_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch41_task_id - */ - uint32_t ch41_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch41_task_id_reg_t; - -/** Type of ch42_evt_id register - * Channel42 event id register - */ -typedef union { - struct { - /** ch42_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch42_evt_id - */ - uint32_t ch42_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch42_evt_id_reg_t; - -/** Type of ch42_task_id register - * Channel42 task id register - */ -typedef union { - struct { - /** ch42_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch42_task_id - */ - uint32_t ch42_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch42_task_id_reg_t; - -/** Type of ch43_evt_id register - * Channel43 event id register - */ -typedef union { - struct { - /** ch43_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch43_evt_id - */ - uint32_t ch43_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch43_evt_id_reg_t; - -/** Type of ch43_task_id register - * Channel43 task id register - */ -typedef union { - struct { - /** ch43_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch43_task_id - */ - uint32_t ch43_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch43_task_id_reg_t; - -/** Type of ch44_evt_id register - * Channel44 event id register - */ -typedef union { - struct { - /** ch44_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch44_evt_id - */ - uint32_t ch44_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch44_evt_id_reg_t; - -/** Type of ch44_task_id register - * Channel44 task id register - */ -typedef union { - struct { - /** ch44_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch44_task_id - */ - uint32_t ch44_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch44_task_id_reg_t; - -/** Type of ch45_evt_id register - * Channel45 event id register - */ -typedef union { - struct { - /** ch45_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch45_evt_id - */ - uint32_t ch45_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch45_evt_id_reg_t; - -/** Type of ch45_task_id register - * Channel45 task id register - */ -typedef union { - struct { - /** ch45_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch45_task_id - */ - uint32_t ch45_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch45_task_id_reg_t; - -/** Type of ch46_evt_id register - * Channel46 event id register - */ -typedef union { - struct { - /** ch46_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch46_evt_id - */ - uint32_t ch46_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch46_evt_id_reg_t; - -/** Type of ch46_task_id register - * Channel46 task id register - */ -typedef union { - struct { - /** ch46_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch46_task_id - */ - uint32_t ch46_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch46_task_id_reg_t; - -/** Type of ch47_evt_id register - * Channel47 event id register - */ -typedef union { - struct { - /** ch47_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch47_evt_id - */ - uint32_t ch47_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch47_evt_id_reg_t; - -/** Type of ch47_task_id register - * Channel47 task id register - */ -typedef union { - struct { - /** ch47_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch47_task_id - */ - uint32_t ch47_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch47_task_id_reg_t; - -/** Type of ch48_evt_id register - * Channel48 event id register - */ -typedef union { - struct { - /** ch48_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch48_evt_id - */ - uint32_t ch48_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch48_evt_id_reg_t; - -/** Type of ch48_task_id register - * Channel48 task id register - */ -typedef union { - struct { - /** ch48_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch48_task_id - */ - uint32_t ch48_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch48_task_id_reg_t; - -/** Type of ch49_evt_id register - * Channel49 event id register - */ -typedef union { - struct { - /** ch49_evt_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch49_evt_id - */ - uint32_t ch49_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch49_evt_id_reg_t; - -/** Type of ch49_task_id register - * Channel49 task id register - */ -typedef union { - struct { - /** ch49_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures ch49_task_id - */ - uint32_t ch49_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch49_task_id_reg_t; +} soc_etm_chn_task_id_reg_t; /** Type of evt_st0_clr register * Events trigger status clear register @@ -4086,162 +2713,162 @@ typedef union { * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch0_rise_edge_st_clr:1; + uint32_t gpio_evt_ch0_rise_edge_st_clr: 1; /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch1_rise_edge_st_clr:1; + uint32_t gpio_evt_ch1_rise_edge_st_clr: 1; /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch2_rise_edge_st_clr:1; + uint32_t gpio_evt_ch2_rise_edge_st_clr: 1; /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch3_rise_edge_st_clr:1; + uint32_t gpio_evt_ch3_rise_edge_st_clr: 1; /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch4_rise_edge_st_clr:1; + uint32_t gpio_evt_ch4_rise_edge_st_clr: 1; /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch5_rise_edge_st_clr:1; + uint32_t gpio_evt_ch5_rise_edge_st_clr: 1; /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch6_rise_edge_st_clr:1; + uint32_t gpio_evt_ch6_rise_edge_st_clr: 1; /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch7_rise_edge_st_clr:1; + uint32_t gpio_evt_ch7_rise_edge_st_clr: 1; /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch0_fall_edge_st_clr:1; + uint32_t gpio_evt_ch0_fall_edge_st_clr: 1; /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch1_fall_edge_st_clr:1; + uint32_t gpio_evt_ch1_fall_edge_st_clr: 1; /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch2_fall_edge_st_clr:1; + uint32_t gpio_evt_ch2_fall_edge_st_clr: 1; /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch3_fall_edge_st_clr:1; + uint32_t gpio_evt_ch3_fall_edge_st_clr: 1; /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch4_fall_edge_st_clr:1; + uint32_t gpio_evt_ch4_fall_edge_st_clr: 1; /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch5_fall_edge_st_clr:1; + uint32_t gpio_evt_ch5_fall_edge_st_clr: 1; /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch6_fall_edge_st_clr:1; + uint32_t gpio_evt_ch6_fall_edge_st_clr: 1; /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch7_fall_edge_st_clr:1; + uint32_t gpio_evt_ch7_fall_edge_st_clr: 1; /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch0_any_edge_st_clr:1; + uint32_t gpio_evt_ch0_any_edge_st_clr: 1; /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch1_any_edge_st_clr:1; + uint32_t gpio_evt_ch1_any_edge_st_clr: 1; /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch2_any_edge_st_clr:1; + uint32_t gpio_evt_ch2_any_edge_st_clr: 1; /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch3_any_edge_st_clr:1; + uint32_t gpio_evt_ch3_any_edge_st_clr: 1; /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch4_any_edge_st_clr:1; + uint32_t gpio_evt_ch4_any_edge_st_clr: 1; /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch5_any_edge_st_clr:1; + uint32_t gpio_evt_ch5_any_edge_st_clr: 1; /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch6_any_edge_st_clr:1; + uint32_t gpio_evt_ch6_any_edge_st_clr: 1; /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_ch7_any_edge_st_clr:1; + uint32_t gpio_evt_ch7_any_edge_st_clr: 1; /** gpio_evt_zero_det_pos0_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_zero_det_pos0_st_clr:1; + uint32_t gpio_evt_zero_det_pos0_st_clr: 1; /** gpio_evt_zero_det_neg0_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_zero_det_neg0_st_clr:1; + uint32_t gpio_evt_zero_det_neg0_st_clr: 1; /** gpio_evt_zero_det_pos1_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_zero_det_pos1_st_clr:1; + uint32_t gpio_evt_zero_det_pos1_st_clr: 1; /** gpio_evt_zero_det_neg1_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_evt_zero_det_neg1_st_clr:1; + uint32_t gpio_evt_zero_det_neg1_st_clr: 1; /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch0_st_clr: 1; /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch1_st_clr: 1; /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch2_st_clr: 1; /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch3_st_clr: 1; }; uint32_t val; } soc_etm_evt_st0_clr_reg_t; @@ -4255,162 +2882,162 @@ typedef union { * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch4_st_clr: 1; /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch5_st_clr: 1; /** ledc_evt_duty_chng_end_ch6_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch6_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch6_st_clr: 1; /** ledc_evt_duty_chng_end_ch7_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_duty_chng_end_ch7_st_clr:1; + uint32_t ledc_evt_duty_chng_end_ch7_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch6_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch6_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch6_st_clr: 1; /** ledc_evt_ovf_cnt_pls_ch7_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_ovf_cnt_pls_ch7_st_clr:1; + uint32_t ledc_evt_ovf_cnt_pls_ch7_st_clr: 1; /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_time_ovf_timer0_st_clr:1; + uint32_t ledc_evt_time_ovf_timer0_st_clr: 1; /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_time_ovf_timer1_st_clr:1; + uint32_t ledc_evt_time_ovf_timer1_st_clr: 1; /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_time_ovf_timer2_st_clr:1; + uint32_t ledc_evt_time_ovf_timer2_st_clr: 1; /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_evt_time_ovf_timer3_st_clr:1; + uint32_t ledc_evt_time_ovf_timer3_st_clr: 1; /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t ledc_evt_timer0_cmp_st_clr:1; + uint32_t ledc_evt_timer0_cmp_st_clr: 1; /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t ledc_evt_timer1_cmp_st_clr:1; + uint32_t ledc_evt_timer1_cmp_st_clr: 1; /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t ledc_evt_timer2_cmp_st_clr:1; + uint32_t ledc_evt_timer2_cmp_st_clr: 1; /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t ledc_evt_timer3_cmp_st_clr:1; + uint32_t ledc_evt_timer3_cmp_st_clr: 1; /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1; + uint32_t tg0_evt_cnt_cmp_timer0_st_clr: 1; /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1; + uint32_t tg0_evt_cnt_cmp_timer1_st_clr: 1; /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1; + uint32_t tg1_evt_cnt_cmp_timer0_st_clr: 1; /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1; + uint32_t tg1_evt_cnt_cmp_timer1_st_clr: 1; /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t systimer_evt_cnt_cmp0_st_clr:1; + uint32_t systimer_evt_cnt_cmp0_st_clr: 1; /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t systimer_evt_cnt_cmp1_st_clr:1; + uint32_t systimer_evt_cnt_cmp1_st_clr: 1; /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t systimer_evt_cnt_cmp2_st_clr:1; + uint32_t systimer_evt_cnt_cmp2_st_clr: 1; /** mcpwm0_evt_timer0_stop_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer0_stop_st_clr:1; + uint32_t mcpwm0_evt_timer0_stop_st_clr: 1; /** mcpwm0_evt_timer1_stop_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer1_stop_st_clr:1; + uint32_t mcpwm0_evt_timer1_stop_st_clr: 1; /** mcpwm0_evt_timer2_stop_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer2_stop_st_clr:1; + uint32_t mcpwm0_evt_timer2_stop_st_clr: 1; /** mcpwm0_evt_timer0_tez_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer0_tez_st_clr:1; + uint32_t mcpwm0_evt_timer0_tez_st_clr: 1; /** mcpwm0_evt_timer1_tez_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer1_tez_st_clr:1; + uint32_t mcpwm0_evt_timer1_tez_st_clr: 1; }; uint32_t val; } soc_etm_evt_st1_clr_reg_t; @@ -4424,162 +3051,162 @@ typedef union { * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer2_tez_st_clr:1; + uint32_t mcpwm0_evt_timer2_tez_st_clr: 1; /** mcpwm0_evt_timer0_tep_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer0_tep_st_clr:1; + uint32_t mcpwm0_evt_timer0_tep_st_clr: 1; /** mcpwm0_evt_timer1_tep_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer1_tep_st_clr:1; + uint32_t mcpwm0_evt_timer1_tep_st_clr: 1; /** mcpwm0_evt_timer2_tep_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_evt_timer2_tep_st_clr:1; + uint32_t mcpwm0_evt_timer2_tep_st_clr: 1; /** mcpwm0_evt_op0_tea_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op0_tea_st_clr:1; + uint32_t mcpwm0_evt_op0_tea_st_clr: 1; /** mcpwm0_evt_op1_tea_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op1_tea_st_clr:1; + uint32_t mcpwm0_evt_op1_tea_st_clr: 1; /** mcpwm0_evt_op2_tea_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op2_tea_st_clr:1; + uint32_t mcpwm0_evt_op2_tea_st_clr: 1; /** mcpwm0_evt_op0_teb_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op0_teb_st_clr:1; + uint32_t mcpwm0_evt_op0_teb_st_clr: 1; /** mcpwm0_evt_op1_teb_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op1_teb_st_clr:1; + uint32_t mcpwm0_evt_op1_teb_st_clr: 1; /** mcpwm0_evt_op2_teb_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op2_teb_st_clr:1; + uint32_t mcpwm0_evt_op2_teb_st_clr: 1; /** mcpwm0_evt_f0_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_evt_f0_st_clr:1; + uint32_t mcpwm0_evt_f0_st_clr: 1; /** mcpwm0_evt_f1_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_evt_f1_st_clr:1; + uint32_t mcpwm0_evt_f1_st_clr: 1; /** mcpwm0_evt_f2_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_evt_f2_st_clr:1; + uint32_t mcpwm0_evt_f2_st_clr: 1; /** mcpwm0_evt_f0_clr_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_f0_clr_st_clr:1; + uint32_t mcpwm0_evt_f0_clr_st_clr: 1; /** mcpwm0_evt_f1_clr_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_f1_clr_st_clr:1; + uint32_t mcpwm0_evt_f1_clr_st_clr: 1; /** mcpwm0_evt_f2_clr_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_f2_clr_st_clr:1; + uint32_t mcpwm0_evt_f2_clr_st_clr: 1; /** mcpwm0_evt_tz0_cbc_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_tz0_cbc_st_clr:1; + uint32_t mcpwm0_evt_tz0_cbc_st_clr: 1; /** mcpwm0_evt_tz1_cbc_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_tz1_cbc_st_clr:1; + uint32_t mcpwm0_evt_tz1_cbc_st_clr: 1; /** mcpwm0_evt_tz2_cbc_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_tz2_cbc_st_clr:1; + uint32_t mcpwm0_evt_tz2_cbc_st_clr: 1; /** mcpwm0_evt_tz0_ost_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_tz0_ost_st_clr:1; + uint32_t mcpwm0_evt_tz0_ost_st_clr: 1; /** mcpwm0_evt_tz1_ost_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_tz1_ost_st_clr:1; + uint32_t mcpwm0_evt_tz1_ost_st_clr: 1; /** mcpwm0_evt_tz2_ost_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_tz2_ost_st_clr:1; + uint32_t mcpwm0_evt_tz2_ost_st_clr: 1; /** mcpwm0_evt_cap0_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_evt_cap0_st_clr:1; + uint32_t mcpwm0_evt_cap0_st_clr: 1; /** mcpwm0_evt_cap1_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_evt_cap1_st_clr:1; + uint32_t mcpwm0_evt_cap1_st_clr: 1; /** mcpwm0_evt_cap2_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_evt_cap2_st_clr:1; + uint32_t mcpwm0_evt_cap2_st_clr: 1; /** mcpwm0_evt_op0_tee1_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op0_tee1_st_clr:1; + uint32_t mcpwm0_evt_op0_tee1_st_clr: 1; /** mcpwm0_evt_op1_tee1_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op1_tee1_st_clr:1; + uint32_t mcpwm0_evt_op1_tee1_st_clr: 1; /** mcpwm0_evt_op2_tee1_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op2_tee1_st_clr:1; + uint32_t mcpwm0_evt_op2_tee1_st_clr: 1; /** mcpwm0_evt_op0_tee2_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op0_tee2_st_clr:1; + uint32_t mcpwm0_evt_op0_tee2_st_clr: 1; /** mcpwm0_evt_op1_tee2_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op1_tee2_st_clr:1; + uint32_t mcpwm0_evt_op1_tee2_st_clr: 1; /** mcpwm0_evt_op2_tee2_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_evt_op2_tee2_st_clr:1; + uint32_t mcpwm0_evt_op2_tee2_st_clr: 1; /** mcpwm1_evt_timer0_stop_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer0_stop_st_clr:1; + uint32_t mcpwm1_evt_timer0_stop_st_clr: 1; }; uint32_t val; } soc_etm_evt_st2_clr_reg_t; @@ -4593,162 +3220,162 @@ typedef union { * Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer1_stop_st_clr:1; + uint32_t mcpwm1_evt_timer1_stop_st_clr: 1; /** mcpwm1_evt_timer2_stop_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer2_stop_st_clr:1; + uint32_t mcpwm1_evt_timer2_stop_st_clr: 1; /** mcpwm1_evt_timer0_tez_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer0_tez_st_clr:1; + uint32_t mcpwm1_evt_timer0_tez_st_clr: 1; /** mcpwm1_evt_timer1_tez_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer1_tez_st_clr:1; + uint32_t mcpwm1_evt_timer1_tez_st_clr: 1; /** mcpwm1_evt_timer2_tez_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer2_tez_st_clr:1; + uint32_t mcpwm1_evt_timer2_tez_st_clr: 1; /** mcpwm1_evt_timer0_tep_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer0_tep_st_clr:1; + uint32_t mcpwm1_evt_timer0_tep_st_clr: 1; /** mcpwm1_evt_timer1_tep_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer1_tep_st_clr:1; + uint32_t mcpwm1_evt_timer1_tep_st_clr: 1; /** mcpwm1_evt_timer2_tep_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_evt_timer2_tep_st_clr:1; + uint32_t mcpwm1_evt_timer2_tep_st_clr: 1; /** mcpwm1_evt_op0_tea_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op0_tea_st_clr:1; + uint32_t mcpwm1_evt_op0_tea_st_clr: 1; /** mcpwm1_evt_op1_tea_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op1_tea_st_clr:1; + uint32_t mcpwm1_evt_op1_tea_st_clr: 1; /** mcpwm1_evt_op2_tea_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op2_tea_st_clr:1; + uint32_t mcpwm1_evt_op2_tea_st_clr: 1; /** mcpwm1_evt_op0_teb_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op0_teb_st_clr:1; + uint32_t mcpwm1_evt_op0_teb_st_clr: 1; /** mcpwm1_evt_op1_teb_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op1_teb_st_clr:1; + uint32_t mcpwm1_evt_op1_teb_st_clr: 1; /** mcpwm1_evt_op2_teb_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op2_teb_st_clr:1; + uint32_t mcpwm1_evt_op2_teb_st_clr: 1; /** mcpwm1_evt_f0_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_evt_f0_st_clr:1; + uint32_t mcpwm1_evt_f0_st_clr: 1; /** mcpwm1_evt_f1_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_evt_f1_st_clr:1; + uint32_t mcpwm1_evt_f1_st_clr: 1; /** mcpwm1_evt_f2_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_evt_f2_st_clr:1; + uint32_t mcpwm1_evt_f2_st_clr: 1; /** mcpwm1_evt_f0_clr_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_f0_clr_st_clr:1; + uint32_t mcpwm1_evt_f0_clr_st_clr: 1; /** mcpwm1_evt_f1_clr_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_f1_clr_st_clr:1; + uint32_t mcpwm1_evt_f1_clr_st_clr: 1; /** mcpwm1_evt_f2_clr_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_f2_clr_st_clr:1; + uint32_t mcpwm1_evt_f2_clr_st_clr: 1; /** mcpwm1_evt_tz0_cbc_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_tz0_cbc_st_clr:1; + uint32_t mcpwm1_evt_tz0_cbc_st_clr: 1; /** mcpwm1_evt_tz1_cbc_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_tz1_cbc_st_clr:1; + uint32_t mcpwm1_evt_tz1_cbc_st_clr: 1; /** mcpwm1_evt_tz2_cbc_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_tz2_cbc_st_clr:1; + uint32_t mcpwm1_evt_tz2_cbc_st_clr: 1; /** mcpwm1_evt_tz0_ost_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_tz0_ost_st_clr:1; + uint32_t mcpwm1_evt_tz0_ost_st_clr: 1; /** mcpwm1_evt_tz1_ost_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_tz1_ost_st_clr:1; + uint32_t mcpwm1_evt_tz1_ost_st_clr: 1; /** mcpwm1_evt_tz2_ost_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_tz2_ost_st_clr:1; + uint32_t mcpwm1_evt_tz2_ost_st_clr: 1; /** mcpwm1_evt_cap0_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_evt_cap0_st_clr:1; + uint32_t mcpwm1_evt_cap0_st_clr: 1; /** mcpwm1_evt_cap1_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_evt_cap1_st_clr:1; + uint32_t mcpwm1_evt_cap1_st_clr: 1; /** mcpwm1_evt_cap2_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_evt_cap2_st_clr:1; + uint32_t mcpwm1_evt_cap2_st_clr: 1; /** mcpwm1_evt_op0_tee1_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op0_tee1_st_clr:1; + uint32_t mcpwm1_evt_op0_tee1_st_clr: 1; /** mcpwm1_evt_op1_tee1_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op1_tee1_st_clr:1; + uint32_t mcpwm1_evt_op1_tee1_st_clr: 1; /** mcpwm1_evt_op2_tee1_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op2_tee1_st_clr:1; + uint32_t mcpwm1_evt_op2_tee1_st_clr: 1; }; uint32_t val; } soc_etm_evt_st3_clr_reg_t; @@ -4762,162 +3389,162 @@ typedef union { * Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op0_tee2_st_clr:1; + uint32_t mcpwm1_evt_op0_tee2_st_clr: 1; /** mcpwm1_evt_op1_tee2_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op1_tee2_st_clr:1; + uint32_t mcpwm1_evt_op1_tee2_st_clr: 1; /** mcpwm1_evt_op2_tee2_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_evt_op2_tee2_st_clr:1; + uint32_t mcpwm1_evt_op2_tee2_st_clr: 1; /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t adc_evt_conv_cmplt0_st_clr:1; + uint32_t adc_evt_conv_cmplt0_st_clr: 1; /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t adc_evt_eq_above_thresh0_st_clr:1; + uint32_t adc_evt_eq_above_thresh0_st_clr: 1; /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t adc_evt_eq_above_thresh1_st_clr:1; + uint32_t adc_evt_eq_above_thresh1_st_clr: 1; /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t adc_evt_eq_below_thresh0_st_clr:1; + uint32_t adc_evt_eq_below_thresh0_st_clr: 1; /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t adc_evt_eq_below_thresh1_st_clr:1; + uint32_t adc_evt_eq_below_thresh1_st_clr: 1; /** adc_evt_result_done0_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t adc_evt_result_done0_st_clr:1; + uint32_t adc_evt_result_done0_st_clr: 1; /** adc_evt_stopped0_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t adc_evt_stopped0_st_clr:1; + uint32_t adc_evt_stopped0_st_clr: 1; /** adc_evt_started0_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t adc_evt_started0_st_clr:1; + uint32_t adc_evt_started0_st_clr: 1; /** regdma_evt_done0_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_done0_st_clr:1; + uint32_t regdma_evt_done0_st_clr: 1; /** regdma_evt_done1_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_done1_st_clr:1; + uint32_t regdma_evt_done1_st_clr: 1; /** regdma_evt_done2_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_done2_st_clr:1; + uint32_t regdma_evt_done2_st_clr: 1; /** regdma_evt_done3_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_done3_st_clr:1; + uint32_t regdma_evt_done3_st_clr: 1; /** regdma_evt_err0_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_err0_st_clr:1; + uint32_t regdma_evt_err0_st_clr: 1; /** regdma_evt_err1_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_err1_st_clr:1; + uint32_t regdma_evt_err1_st_clr: 1; /** regdma_evt_err2_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_err2_st_clr:1; + uint32_t regdma_evt_err2_st_clr: 1; /** regdma_evt_err3_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t regdma_evt_err3_st_clr:1; + uint32_t regdma_evt_err3_st_clr: 1; /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tmpsnsr_evt_over_limit_st_clr:1; + uint32_t tmpsnsr_evt_over_limit_st_clr: 1; /** i2s0_evt_rx_done_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t i2s0_evt_rx_done_st_clr:1; + uint32_t i2s0_evt_rx_done_st_clr: 1; /** i2s0_evt_tx_done_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t i2s0_evt_tx_done_st_clr:1; + uint32_t i2s0_evt_tx_done_st_clr: 1; /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t i2s0_evt_x_words_received_st_clr:1; + uint32_t i2s0_evt_x_words_received_st_clr: 1; /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t i2s0_evt_x_words_sent_st_clr:1; + uint32_t i2s0_evt_x_words_sent_st_clr: 1; /** i2s1_evt_rx_done_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t i2s1_evt_rx_done_st_clr:1; + uint32_t i2s1_evt_rx_done_st_clr: 1; /** i2s1_evt_tx_done_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t i2s1_evt_tx_done_st_clr:1; + uint32_t i2s1_evt_tx_done_st_clr: 1; /** i2s1_evt_x_words_received_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t i2s1_evt_x_words_received_st_clr:1; + uint32_t i2s1_evt_x_words_received_st_clr: 1; /** i2s1_evt_x_words_sent_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t i2s1_evt_x_words_sent_st_clr:1; + uint32_t i2s1_evt_x_words_sent_st_clr: 1; /** i2s2_evt_rx_done_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t i2s2_evt_rx_done_st_clr:1; + uint32_t i2s2_evt_rx_done_st_clr: 1; /** i2s2_evt_tx_done_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t i2s2_evt_tx_done_st_clr:1; + uint32_t i2s2_evt_tx_done_st_clr: 1; /** i2s2_evt_x_words_received_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t i2s2_evt_x_words_received_st_clr:1; + uint32_t i2s2_evt_x_words_received_st_clr: 1; /** i2s2_evt_x_words_sent_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t i2s2_evt_x_words_sent_st_clr:1; + uint32_t i2s2_evt_x_words_sent_st_clr: 1; }; uint32_t val; } soc_etm_evt_st4_clr_reg_t; @@ -4931,162 +3558,162 @@ typedef union { * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t ulp_evt_err_intr_st_clr:1; + uint32_t ulp_evt_err_intr_st_clr: 1; /** ulp_evt_halt_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t ulp_evt_halt_st_clr:1; + uint32_t ulp_evt_halt_st_clr: 1; /** ulp_evt_start_intr_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t ulp_evt_start_intr_st_clr:1; + uint32_t ulp_evt_start_intr_st_clr: 1; /** rtc_evt_tick_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t rtc_evt_tick_st_clr:1; + uint32_t rtc_evt_tick_st_clr: 1; /** rtc_evt_ovf_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t rtc_evt_ovf_st_clr:1; + uint32_t rtc_evt_ovf_st_clr: 1; /** rtc_evt_cmp_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t rtc_evt_cmp_st_clr:1; + uint32_t rtc_evt_cmp_st_clr: 1; /** pdma_ahb_evt_in_done_ch0_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_done_ch0_st_clr:1; + uint32_t pdma_ahb_evt_in_done_ch0_st_clr: 1; /** pdma_ahb_evt_in_done_ch1_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_done_ch1_st_clr:1; + uint32_t pdma_ahb_evt_in_done_ch1_st_clr: 1; /** pdma_ahb_evt_in_done_ch2_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_done_ch2_st_clr:1; + uint32_t pdma_ahb_evt_in_done_ch2_st_clr: 1; /** pdma_ahb_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_suc_eof_ch0_st_clr:1; + uint32_t pdma_ahb_evt_in_suc_eof_ch0_st_clr: 1; /** pdma_ahb_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_suc_eof_ch1_st_clr:1; + uint32_t pdma_ahb_evt_in_suc_eof_ch1_st_clr: 1; /** pdma_ahb_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_suc_eof_ch2_st_clr:1; + uint32_t pdma_ahb_evt_in_suc_eof_ch2_st_clr: 1; /** pdma_ahb_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st_clr:1; + uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st_clr: 1; /** pdma_ahb_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st_clr:1; + uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st_clr: 1; /** pdma_ahb_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st_clr:1; + uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st_clr: 1; /** pdma_ahb_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_fifo_full_ch0_st_clr:1; + uint32_t pdma_ahb_evt_in_fifo_full_ch0_st_clr: 1; /** pdma_ahb_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_fifo_full_ch1_st_clr:1; + uint32_t pdma_ahb_evt_in_fifo_full_ch1_st_clr: 1; /** pdma_ahb_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_in_fifo_full_ch2_st_clr:1; + uint32_t pdma_ahb_evt_in_fifo_full_ch2_st_clr: 1; /** pdma_ahb_evt_out_done_ch0_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_done_ch0_st_clr:1; + uint32_t pdma_ahb_evt_out_done_ch0_st_clr: 1; /** pdma_ahb_evt_out_done_ch1_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_done_ch1_st_clr:1; + uint32_t pdma_ahb_evt_out_done_ch1_st_clr: 1; /** pdma_ahb_evt_out_done_ch2_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_done_ch2_st_clr:1; + uint32_t pdma_ahb_evt_out_done_ch2_st_clr: 1; /** pdma_ahb_evt_out_eof_ch0_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_eof_ch0_st_clr:1; + uint32_t pdma_ahb_evt_out_eof_ch0_st_clr: 1; /** pdma_ahb_evt_out_eof_ch1_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_eof_ch1_st_clr:1; + uint32_t pdma_ahb_evt_out_eof_ch1_st_clr: 1; /** pdma_ahb_evt_out_eof_ch2_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_eof_ch2_st_clr:1; + uint32_t pdma_ahb_evt_out_eof_ch2_st_clr: 1; /** pdma_ahb_evt_out_total_eof_ch0_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_total_eof_ch0_st_clr:1; + uint32_t pdma_ahb_evt_out_total_eof_ch0_st_clr: 1; /** pdma_ahb_evt_out_total_eof_ch1_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_total_eof_ch1_st_clr:1; + uint32_t pdma_ahb_evt_out_total_eof_ch1_st_clr: 1; /** pdma_ahb_evt_out_total_eof_ch2_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_total_eof_ch2_st_clr:1; + uint32_t pdma_ahb_evt_out_total_eof_ch2_st_clr: 1; /** pdma_ahb_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st_clr:1; + uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st_clr: 1; /** pdma_ahb_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st_clr:1; + uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st_clr: 1; /** pdma_ahb_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st_clr:1; + uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st_clr: 1; /** pdma_ahb_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_fifo_full_ch0_st_clr:1; + uint32_t pdma_ahb_evt_out_fifo_full_ch0_st_clr: 1; /** pdma_ahb_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_fifo_full_ch1_st_clr:1; + uint32_t pdma_ahb_evt_out_fifo_full_ch1_st_clr: 1; }; uint32_t val; } soc_etm_evt_st5_clr_reg_t; @@ -5100,162 +3727,162 @@ typedef union { * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_evt_out_fifo_full_ch2_st_clr:1; + uint32_t pdma_ahb_evt_out_fifo_full_ch2_st_clr: 1; /** pdma_axi_evt_in_done_ch0_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_done_ch0_st_clr:1; + uint32_t pdma_axi_evt_in_done_ch0_st_clr: 1; /** pdma_axi_evt_in_done_ch1_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_done_ch1_st_clr:1; + uint32_t pdma_axi_evt_in_done_ch1_st_clr: 1; /** pdma_axi_evt_in_done_ch2_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_done_ch2_st_clr:1; + uint32_t pdma_axi_evt_in_done_ch2_st_clr: 1; /** pdma_axi_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_suc_eof_ch0_st_clr:1; + uint32_t pdma_axi_evt_in_suc_eof_ch0_st_clr: 1; /** pdma_axi_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_suc_eof_ch1_st_clr:1; + uint32_t pdma_axi_evt_in_suc_eof_ch1_st_clr: 1; /** pdma_axi_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_suc_eof_ch2_st_clr:1; + uint32_t pdma_axi_evt_in_suc_eof_ch2_st_clr: 1; /** pdma_axi_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_fifo_empty_ch0_st_clr:1; + uint32_t pdma_axi_evt_in_fifo_empty_ch0_st_clr: 1; /** pdma_axi_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_fifo_empty_ch1_st_clr:1; + uint32_t pdma_axi_evt_in_fifo_empty_ch1_st_clr: 1; /** pdma_axi_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_fifo_empty_ch2_st_clr:1; + uint32_t pdma_axi_evt_in_fifo_empty_ch2_st_clr: 1; /** pdma_axi_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_fifo_full_ch0_st_clr:1; + uint32_t pdma_axi_evt_in_fifo_full_ch0_st_clr: 1; /** pdma_axi_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_fifo_full_ch1_st_clr:1; + uint32_t pdma_axi_evt_in_fifo_full_ch1_st_clr: 1; /** pdma_axi_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_in_fifo_full_ch2_st_clr:1; + uint32_t pdma_axi_evt_in_fifo_full_ch2_st_clr: 1; /** pdma_axi_evt_out_done_ch0_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_done_ch0_st_clr:1; + uint32_t pdma_axi_evt_out_done_ch0_st_clr: 1; /** pdma_axi_evt_out_done_ch1_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_done_ch1_st_clr:1; + uint32_t pdma_axi_evt_out_done_ch1_st_clr: 1; /** pdma_axi_evt_out_done_ch2_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_done_ch2_st_clr:1; + uint32_t pdma_axi_evt_out_done_ch2_st_clr: 1; /** pdma_axi_evt_out_eof_ch0_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_eof_ch0_st_clr:1; + uint32_t pdma_axi_evt_out_eof_ch0_st_clr: 1; /** pdma_axi_evt_out_eof_ch1_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_eof_ch1_st_clr:1; + uint32_t pdma_axi_evt_out_eof_ch1_st_clr: 1; /** pdma_axi_evt_out_eof_ch2_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_eof_ch2_st_clr:1; + uint32_t pdma_axi_evt_out_eof_ch2_st_clr: 1; /** pdma_axi_evt_out_total_eof_ch0_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_total_eof_ch0_st_clr:1; + uint32_t pdma_axi_evt_out_total_eof_ch0_st_clr: 1; /** pdma_axi_evt_out_total_eof_ch1_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_total_eof_ch1_st_clr:1; + uint32_t pdma_axi_evt_out_total_eof_ch1_st_clr: 1; /** pdma_axi_evt_out_total_eof_ch2_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_total_eof_ch2_st_clr:1; + uint32_t pdma_axi_evt_out_total_eof_ch2_st_clr: 1; /** pdma_axi_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_fifo_empty_ch0_st_clr:1; + uint32_t pdma_axi_evt_out_fifo_empty_ch0_st_clr: 1; /** pdma_axi_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_fifo_empty_ch1_st_clr:1; + uint32_t pdma_axi_evt_out_fifo_empty_ch1_st_clr: 1; /** pdma_axi_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_fifo_empty_ch2_st_clr:1; + uint32_t pdma_axi_evt_out_fifo_empty_ch2_st_clr: 1; /** pdma_axi_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_fifo_full_ch0_st_clr:1; + uint32_t pdma_axi_evt_out_fifo_full_ch0_st_clr: 1; /** pdma_axi_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_fifo_full_ch1_st_clr:1; + uint32_t pdma_axi_evt_out_fifo_full_ch1_st_clr: 1; /** pdma_axi_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_evt_out_fifo_full_ch2_st_clr:1; + uint32_t pdma_axi_evt_out_fifo_full_ch2_st_clr: 1; /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pmu_evt_sleep_weekup_st_clr:1; + uint32_t pmu_evt_sleep_weekup_st_clr: 1; /** dma2d_evt_in_done_ch0_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_in_done_ch0_st_clr:1; + uint32_t dma2d_evt_in_done_ch0_st_clr: 1; /** dma2d_evt_in_done_ch1_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_in_done_ch1_st_clr:1; + uint32_t dma2d_evt_in_done_ch1_st_clr: 1; /** dma2d_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_in_suc_eof_ch0_st_clr:1; + uint32_t dma2d_evt_in_suc_eof_ch0_st_clr: 1; }; uint32_t val; } soc_etm_evt_st6_clr_reg_t; @@ -5269,53 +3896,53 @@ typedef union { * Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_in_suc_eof_ch1_st_clr:1; + uint32_t dma2d_evt_in_suc_eof_ch1_st_clr: 1; /** dma2d_evt_out_done_ch0_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_done_ch0_st_clr:1; + uint32_t dma2d_evt_out_done_ch0_st_clr: 1; /** dma2d_evt_out_done_ch1_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_done_ch1_st_clr:1; + uint32_t dma2d_evt_out_done_ch1_st_clr: 1; /** dma2d_evt_out_done_ch2_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_done_ch2_st_clr:1; + uint32_t dma2d_evt_out_done_ch2_st_clr: 1; /** dma2d_evt_out_eof_ch0_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_eof_ch0_st_clr:1; + uint32_t dma2d_evt_out_eof_ch0_st_clr: 1; /** dma2d_evt_out_eof_ch1_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_eof_ch1_st_clr:1; + uint32_t dma2d_evt_out_eof_ch1_st_clr: 1; /** dma2d_evt_out_eof_ch2_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_eof_ch2_st_clr:1; + uint32_t dma2d_evt_out_eof_ch2_st_clr: 1; /** dma2d_evt_out_total_eof_ch0_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_total_eof_ch0_st_clr:1; + uint32_t dma2d_evt_out_total_eof_ch0_st_clr: 1; /** dma2d_evt_out_total_eof_ch1_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_total_eof_ch1_st_clr:1; + uint32_t dma2d_evt_out_total_eof_ch1_st_clr: 1; /** dma2d_evt_out_total_eof_ch2_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_evt_out_total_eof_ch2_st_clr:1; - uint32_t reserved_10:22; + uint32_t dma2d_evt_out_total_eof_ch2_st_clr: 1; + uint32_t reserved_10: 22; }; uint32_t val; } soc_etm_evt_st7_clr_reg_t; @@ -5329,162 +3956,162 @@ typedef union { * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch0_set_st_clr:1; + uint32_t gpio_task_ch0_set_st_clr: 1; /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch1_set_st_clr:1; + uint32_t gpio_task_ch1_set_st_clr: 1; /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch2_set_st_clr:1; + uint32_t gpio_task_ch2_set_st_clr: 1; /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch3_set_st_clr:1; + uint32_t gpio_task_ch3_set_st_clr: 1; /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch4_set_st_clr:1; + uint32_t gpio_task_ch4_set_st_clr: 1; /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch5_set_st_clr:1; + uint32_t gpio_task_ch5_set_st_clr: 1; /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch6_set_st_clr:1; + uint32_t gpio_task_ch6_set_st_clr: 1; /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch7_set_st_clr:1; + uint32_t gpio_task_ch7_set_st_clr: 1; /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch0_clear_st_clr:1; + uint32_t gpio_task_ch0_clear_st_clr: 1; /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch1_clear_st_clr:1; + uint32_t gpio_task_ch1_clear_st_clr: 1; /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch2_clear_st_clr:1; + uint32_t gpio_task_ch2_clear_st_clr: 1; /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch3_clear_st_clr:1; + uint32_t gpio_task_ch3_clear_st_clr: 1; /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch4_clear_st_clr:1; + uint32_t gpio_task_ch4_clear_st_clr: 1; /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch5_clear_st_clr:1; + uint32_t gpio_task_ch5_clear_st_clr: 1; /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch6_clear_st_clr:1; + uint32_t gpio_task_ch6_clear_st_clr: 1; /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t gpio_task_ch7_clear_st_clr:1; + uint32_t gpio_task_ch7_clear_st_clr: 1; /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch0_toggle_st_clr:1; + uint32_t gpio_task_ch0_toggle_st_clr: 1; /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch1_toggle_st_clr:1; + uint32_t gpio_task_ch1_toggle_st_clr: 1; /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch2_toggle_st_clr:1; + uint32_t gpio_task_ch2_toggle_st_clr: 1; /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch3_toggle_st_clr:1; + uint32_t gpio_task_ch3_toggle_st_clr: 1; /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch4_toggle_st_clr:1; + uint32_t gpio_task_ch4_toggle_st_clr: 1; /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch5_toggle_st_clr:1; + uint32_t gpio_task_ch5_toggle_st_clr: 1; /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch6_toggle_st_clr:1; + uint32_t gpio_task_ch6_toggle_st_clr: 1; /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t gpio_task_ch7_toggle_st_clr:1; + uint32_t gpio_task_ch7_toggle_st_clr: 1; /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer0_res_update_st_clr:1; + uint32_t ledc_task_timer0_res_update_st_clr: 1; /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer1_res_update_st_clr:1; + uint32_t ledc_task_timer1_res_update_st_clr: 1; /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer2_res_update_st_clr:1; + uint32_t ledc_task_timer2_res_update_st_clr: 1; /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer3_res_update_st_clr:1; + uint32_t ledc_task_timer3_res_update_st_clr: 1; /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch0_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch0_st_clr: 1; /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch1_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch1_st_clr: 1; /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch2_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch2_st_clr: 1; /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch3_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch3_st_clr: 1; }; uint32_t val; } soc_etm_task_st0_clr_reg_t; @@ -5498,162 +4125,162 @@ typedef union { * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch4_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch4_st_clr: 1; /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch5_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch5_st_clr: 1; /** ledc_task_duty_scale_update_ch6_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch6_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch6_st_clr: 1; /** ledc_task_duty_scale_update_ch7_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t ledc_task_duty_scale_update_ch7_st_clr:1; + uint32_t ledc_task_duty_scale_update_ch7_st_clr: 1; /** ledc_task_timer0_cap_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer0_cap_st_clr:1; + uint32_t ledc_task_timer0_cap_st_clr: 1; /** ledc_task_timer1_cap_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer1_cap_st_clr:1; + uint32_t ledc_task_timer1_cap_st_clr: 1; /** ledc_task_timer2_cap_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer2_cap_st_clr:1; + uint32_t ledc_task_timer2_cap_st_clr: 1; /** ledc_task_timer3_cap_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer3_cap_st_clr:1; + uint32_t ledc_task_timer3_cap_st_clr: 1; /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch0_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch0_st_clr: 1; /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch1_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch1_st_clr: 1; /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch2_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch2_st_clr: 1; /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch3_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch3_st_clr: 1; /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch4_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch4_st_clr: 1; /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch5_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch5_st_clr: 1; /** ledc_task_sig_out_dis_ch6_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch6_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch6_st_clr: 1; /** ledc_task_sig_out_dis_ch7_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_sig_out_dis_ch7_st_clr:1; + uint32_t ledc_task_sig_out_dis_ch7_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch6_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch6_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch6_st_clr: 1; /** ledc_task_ovf_cnt_rst_ch7_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_ovf_cnt_rst_ch7_st_clr:1; + uint32_t ledc_task_ovf_cnt_rst_ch7_st_clr: 1; /** ledc_task_timer0_rst_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer0_rst_st_clr:1; + uint32_t ledc_task_timer0_rst_st_clr: 1; /** ledc_task_timer1_rst_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer1_rst_st_clr:1; + uint32_t ledc_task_timer1_rst_st_clr: 1; /** ledc_task_timer2_rst_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer2_rst_st_clr:1; + uint32_t ledc_task_timer2_rst_st_clr: 1; /** ledc_task_timer3_rst_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer3_rst_st_clr:1; + uint32_t ledc_task_timer3_rst_st_clr: 1; /** ledc_task_timer0_resume_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer0_resume_st_clr:1; + uint32_t ledc_task_timer0_resume_st_clr: 1; /** ledc_task_timer1_resume_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer1_resume_st_clr:1; + uint32_t ledc_task_timer1_resume_st_clr: 1; /** ledc_task_timer2_resume_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer2_resume_st_clr:1; + uint32_t ledc_task_timer2_resume_st_clr: 1; /** ledc_task_timer3_resume_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer3_resume_st_clr:1; + uint32_t ledc_task_timer3_resume_st_clr: 1; }; uint32_t val; } soc_etm_task_st1_clr_reg_t; @@ -5667,162 +4294,162 @@ typedef union { * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer0_pause_st_clr:1; + uint32_t ledc_task_timer0_pause_st_clr: 1; /** ledc_task_timer1_pause_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer1_pause_st_clr:1; + uint32_t ledc_task_timer1_pause_st_clr: 1; /** ledc_task_timer2_pause_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer2_pause_st_clr:1; + uint32_t ledc_task_timer2_pause_st_clr: 1; /** ledc_task_timer3_pause_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_timer3_pause_st_clr:1; + uint32_t ledc_task_timer3_pause_st_clr: 1; /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch0_st_clr:1; + uint32_t ledc_task_gamma_restart_ch0_st_clr: 1; /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch1_st_clr:1; + uint32_t ledc_task_gamma_restart_ch1_st_clr: 1; /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch2_st_clr:1; + uint32_t ledc_task_gamma_restart_ch2_st_clr: 1; /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch3_st_clr:1; + uint32_t ledc_task_gamma_restart_ch3_st_clr: 1; /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch4_st_clr:1; + uint32_t ledc_task_gamma_restart_ch4_st_clr: 1; /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch5_st_clr:1; + uint32_t ledc_task_gamma_restart_ch5_st_clr: 1; /** ledc_task_gamma_restart_ch6_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch6_st_clr:1; + uint32_t ledc_task_gamma_restart_ch6_st_clr: 1; /** ledc_task_gamma_restart_ch7_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_restart_ch7_st_clr:1; + uint32_t ledc_task_gamma_restart_ch7_st_clr: 1; /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch0_st_clr:1; + uint32_t ledc_task_gamma_pause_ch0_st_clr: 1; /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch1_st_clr:1; + uint32_t ledc_task_gamma_pause_ch1_st_clr: 1; /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch2_st_clr:1; + uint32_t ledc_task_gamma_pause_ch2_st_clr: 1; /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch3_st_clr:1; + uint32_t ledc_task_gamma_pause_ch3_st_clr: 1; /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch4_st_clr:1; + uint32_t ledc_task_gamma_pause_ch4_st_clr: 1; /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch5_st_clr:1; + uint32_t ledc_task_gamma_pause_ch5_st_clr: 1; /** ledc_task_gamma_pause_ch6_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch6_st_clr:1; + uint32_t ledc_task_gamma_pause_ch6_st_clr: 1; /** ledc_task_gamma_pause_ch7_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_pause_ch7_st_clr:1; + uint32_t ledc_task_gamma_pause_ch7_st_clr: 1; /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch0_st_clr:1; + uint32_t ledc_task_gamma_resume_ch0_st_clr: 1; /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch1_st_clr:1; + uint32_t ledc_task_gamma_resume_ch1_st_clr: 1; /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch2_st_clr:1; + uint32_t ledc_task_gamma_resume_ch2_st_clr: 1; /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch3_st_clr:1; + uint32_t ledc_task_gamma_resume_ch3_st_clr: 1; /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch4_st_clr:1; + uint32_t ledc_task_gamma_resume_ch4_st_clr: 1; /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch5_st_clr:1; + uint32_t ledc_task_gamma_resume_ch5_st_clr: 1; /** ledc_task_gamma_resume_ch6_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch6_st_clr:1; + uint32_t ledc_task_gamma_resume_ch6_st_clr: 1; /** ledc_task_gamma_resume_ch7_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t ledc_task_gamma_resume_ch7_st_clr:1; + uint32_t ledc_task_gamma_resume_ch7_st_clr: 1; /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_start_timer0_st_clr:1; + uint32_t tg0_task_cnt_start_timer0_st_clr: 1; /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_alarm_start_timer0_st_clr:1; + uint32_t tg0_task_alarm_start_timer0_st_clr: 1; /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_stop_timer0_st_clr:1; + uint32_t tg0_task_cnt_stop_timer0_st_clr: 1; /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_reload_timer0_st_clr:1; + uint32_t tg0_task_cnt_reload_timer0_st_clr: 1; }; uint32_t val; } soc_etm_task_st2_clr_reg_t; @@ -5836,162 +4463,162 @@ typedef union { * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_cap_timer0_st_clr:1; + uint32_t tg0_task_cnt_cap_timer0_st_clr: 1; /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_start_timer1_st_clr:1; + uint32_t tg0_task_cnt_start_timer1_st_clr: 1; /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_alarm_start_timer1_st_clr:1; + uint32_t tg0_task_alarm_start_timer1_st_clr: 1; /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_stop_timer1_st_clr:1; + uint32_t tg0_task_cnt_stop_timer1_st_clr: 1; /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_reload_timer1_st_clr:1; + uint32_t tg0_task_cnt_reload_timer1_st_clr: 1; /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg0_task_cnt_cap_timer1_st_clr:1; + uint32_t tg0_task_cnt_cap_timer1_st_clr: 1; /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_start_timer0_st_clr:1; + uint32_t tg1_task_cnt_start_timer0_st_clr: 1; /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_alarm_start_timer0_st_clr:1; + uint32_t tg1_task_alarm_start_timer0_st_clr: 1; /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_stop_timer0_st_clr:1; + uint32_t tg1_task_cnt_stop_timer0_st_clr: 1; /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_reload_timer0_st_clr:1; + uint32_t tg1_task_cnt_reload_timer0_st_clr: 1; /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_cap_timer0_st_clr:1; + uint32_t tg1_task_cnt_cap_timer0_st_clr: 1; /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_start_timer1_st_clr:1; + uint32_t tg1_task_cnt_start_timer1_st_clr: 1; /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_alarm_start_timer1_st_clr:1; + uint32_t tg1_task_alarm_start_timer1_st_clr: 1; /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_stop_timer1_st_clr:1; + uint32_t tg1_task_cnt_stop_timer1_st_clr: 1; /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_reload_timer1_st_clr:1; + uint32_t tg1_task_cnt_reload_timer1_st_clr: 1; /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tg1_task_cnt_cap_timer1_st_clr:1; + uint32_t tg1_task_cnt_cap_timer1_st_clr: 1; /** mcpwm0_task_cmpr0_a_up_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_cmpr0_a_up_st_clr:1; + uint32_t mcpwm0_task_cmpr0_a_up_st_clr: 1; /** mcpwm0_task_cmpr1_a_up_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_cmpr1_a_up_st_clr:1; + uint32_t mcpwm0_task_cmpr1_a_up_st_clr: 1; /** mcpwm0_task_cmpr2_a_up_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_cmpr2_a_up_st_clr:1; + uint32_t mcpwm0_task_cmpr2_a_up_st_clr: 1; /** mcpwm0_task_cmpr0_b_up_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_cmpr0_b_up_st_clr:1; + uint32_t mcpwm0_task_cmpr0_b_up_st_clr: 1; /** mcpwm0_task_cmpr1_b_up_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_cmpr1_b_up_st_clr:1; + uint32_t mcpwm0_task_cmpr1_b_up_st_clr: 1; /** mcpwm0_task_cmpr2_b_up_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_cmpr2_b_up_st_clr:1; + uint32_t mcpwm0_task_cmpr2_b_up_st_clr: 1; /** mcpwm0_task_gen_stop_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_gen_stop_st_clr:1; + uint32_t mcpwm0_task_gen_stop_st_clr: 1; /** mcpwm0_task_timer0_syn_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_timer0_syn_st_clr:1; + uint32_t mcpwm0_task_timer0_syn_st_clr: 1; /** mcpwm0_task_timer1_syn_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_timer1_syn_st_clr:1; + uint32_t mcpwm0_task_timer1_syn_st_clr: 1; /** mcpwm0_task_timer2_syn_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_timer2_syn_st_clr:1; + uint32_t mcpwm0_task_timer2_syn_st_clr: 1; /** mcpwm0_task_timer0_period_up_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_timer0_period_up_st_clr:1; + uint32_t mcpwm0_task_timer0_period_up_st_clr: 1; /** mcpwm0_task_timer1_period_up_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_timer1_period_up_st_clr:1; + uint32_t mcpwm0_task_timer1_period_up_st_clr: 1; /** mcpwm0_task_timer2_period_up_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_timer2_period_up_st_clr:1; + uint32_t mcpwm0_task_timer2_period_up_st_clr: 1; /** mcpwm0_task_tz0_ost_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_task_tz0_ost_st_clr:1; + uint32_t mcpwm0_task_tz0_ost_st_clr: 1; /** mcpwm0_task_tz1_ost_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_task_tz1_ost_st_clr:1; + uint32_t mcpwm0_task_tz1_ost_st_clr: 1; /** mcpwm0_task_tz2_ost_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm0_task_tz2_ost_st_clr:1; + uint32_t mcpwm0_task_tz2_ost_st_clr: 1; }; uint32_t val; } soc_etm_task_st3_clr_reg_t; @@ -6005,162 +4632,162 @@ typedef union { * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_clr0_ost_st_clr:1; + uint32_t mcpwm0_task_clr0_ost_st_clr: 1; /** mcpwm0_task_clr1_ost_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_clr1_ost_st_clr:1; + uint32_t mcpwm0_task_clr1_ost_st_clr: 1; /** mcpwm0_task_clr2_ost_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm0_task_clr2_ost_st_clr:1; + uint32_t mcpwm0_task_clr2_ost_st_clr: 1; /** mcpwm0_task_cap0_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_task_cap0_st_clr:1; + uint32_t mcpwm0_task_cap0_st_clr: 1; /** mcpwm0_task_cap1_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_task_cap1_st_clr:1; + uint32_t mcpwm0_task_cap1_st_clr: 1; /** mcpwm0_task_cap2_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm0_task_cap2_st_clr:1; + uint32_t mcpwm0_task_cap2_st_clr: 1; /** mcpwm1_task_cmpr0_a_up_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_cmpr0_a_up_st_clr:1; + uint32_t mcpwm1_task_cmpr0_a_up_st_clr: 1; /** mcpwm1_task_cmpr1_a_up_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_cmpr1_a_up_st_clr:1; + uint32_t mcpwm1_task_cmpr1_a_up_st_clr: 1; /** mcpwm1_task_cmpr2_a_up_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_cmpr2_a_up_st_clr:1; + uint32_t mcpwm1_task_cmpr2_a_up_st_clr: 1; /** mcpwm1_task_cmpr0_b_up_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_cmpr0_b_up_st_clr:1; + uint32_t mcpwm1_task_cmpr0_b_up_st_clr: 1; /** mcpwm1_task_cmpr1_b_up_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_cmpr1_b_up_st_clr:1; + uint32_t mcpwm1_task_cmpr1_b_up_st_clr: 1; /** mcpwm1_task_cmpr2_b_up_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_cmpr2_b_up_st_clr:1; + uint32_t mcpwm1_task_cmpr2_b_up_st_clr: 1; /** mcpwm1_task_gen_stop_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_gen_stop_st_clr:1; + uint32_t mcpwm1_task_gen_stop_st_clr: 1; /** mcpwm1_task_timer0_syn_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_timer0_syn_st_clr:1; + uint32_t mcpwm1_task_timer0_syn_st_clr: 1; /** mcpwm1_task_timer1_syn_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_timer1_syn_st_clr:1; + uint32_t mcpwm1_task_timer1_syn_st_clr: 1; /** mcpwm1_task_timer2_syn_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_timer2_syn_st_clr:1; + uint32_t mcpwm1_task_timer2_syn_st_clr: 1; /** mcpwm1_task_timer0_period_up_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_timer0_period_up_st_clr:1; + uint32_t mcpwm1_task_timer0_period_up_st_clr: 1; /** mcpwm1_task_timer1_period_up_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_timer1_period_up_st_clr:1; + uint32_t mcpwm1_task_timer1_period_up_st_clr: 1; /** mcpwm1_task_timer2_period_up_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_timer2_period_up_st_clr:1; + uint32_t mcpwm1_task_timer2_period_up_st_clr: 1; /** mcpwm1_task_tz0_ost_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_task_tz0_ost_st_clr:1; + uint32_t mcpwm1_task_tz0_ost_st_clr: 1; /** mcpwm1_task_tz1_ost_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_task_tz1_ost_st_clr:1; + uint32_t mcpwm1_task_tz1_ost_st_clr: 1; /** mcpwm1_task_tz2_ost_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t mcpwm1_task_tz2_ost_st_clr:1; + uint32_t mcpwm1_task_tz2_ost_st_clr: 1; /** mcpwm1_task_clr0_ost_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_clr0_ost_st_clr:1; + uint32_t mcpwm1_task_clr0_ost_st_clr: 1; /** mcpwm1_task_clr1_ost_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_clr1_ost_st_clr:1; + uint32_t mcpwm1_task_clr1_ost_st_clr: 1; /** mcpwm1_task_clr2_ost_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t mcpwm1_task_clr2_ost_st_clr:1; + uint32_t mcpwm1_task_clr2_ost_st_clr: 1; /** mcpwm1_task_cap0_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_task_cap0_st_clr:1; + uint32_t mcpwm1_task_cap0_st_clr: 1; /** mcpwm1_task_cap1_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_task_cap1_st_clr:1; + uint32_t mcpwm1_task_cap1_st_clr: 1; /** mcpwm1_task_cap2_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t mcpwm1_task_cap2_st_clr:1; + uint32_t mcpwm1_task_cap2_st_clr: 1; /** adc_task_sample0_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t adc_task_sample0_st_clr:1; + uint32_t adc_task_sample0_st_clr: 1; /** adc_task_sample1_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t adc_task_sample1_st_clr:1; + uint32_t adc_task_sample1_st_clr: 1; /** adc_task_start0_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t adc_task_start0_st_clr:1; + uint32_t adc_task_start0_st_clr: 1; /** adc_task_stop0_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t adc_task_stop0_st_clr:1; + uint32_t adc_task_stop0_st_clr: 1; }; uint32_t val; } soc_etm_task_st4_clr_reg_t; @@ -6174,162 +4801,162 @@ typedef union { * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t regdma_task_start0_st_clr:1; + uint32_t regdma_task_start0_st_clr: 1; /** regdma_task_start1_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t regdma_task_start1_st_clr:1; + uint32_t regdma_task_start1_st_clr: 1; /** regdma_task_start2_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t regdma_task_start2_st_clr:1; + uint32_t regdma_task_start2_st_clr: 1; /** regdma_task_start3_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t regdma_task_start3_st_clr:1; + uint32_t regdma_task_start3_st_clr: 1; /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tmpsnsr_task_start_sample_st_clr:1; + uint32_t tmpsnsr_task_start_sample_st_clr: 1; /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t tmpsnsr_task_stop_sample_st_clr:1; + uint32_t tmpsnsr_task_stop_sample_st_clr: 1; /** i2s0_task_start_rx_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s0_task_start_rx_st_clr:1; + uint32_t i2s0_task_start_rx_st_clr: 1; /** i2s0_task_start_tx_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s0_task_start_tx_st_clr:1; + uint32_t i2s0_task_start_tx_st_clr: 1; /** i2s0_task_stop_rx_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s0_task_stop_rx_st_clr:1; + uint32_t i2s0_task_stop_rx_st_clr: 1; /** i2s0_task_stop_tx_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s0_task_stop_tx_st_clr:1; + uint32_t i2s0_task_stop_tx_st_clr: 1; /** i2s1_task_start_rx_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s1_task_start_rx_st_clr:1; + uint32_t i2s1_task_start_rx_st_clr: 1; /** i2s1_task_start_tx_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s1_task_start_tx_st_clr:1; + uint32_t i2s1_task_start_tx_st_clr: 1; /** i2s1_task_stop_rx_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s1_task_stop_rx_st_clr:1; + uint32_t i2s1_task_stop_rx_st_clr: 1; /** i2s1_task_stop_tx_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s1_task_stop_tx_st_clr:1; + uint32_t i2s1_task_stop_tx_st_clr: 1; /** i2s2_task_start_rx_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s2_task_start_rx_st_clr:1; + uint32_t i2s2_task_start_rx_st_clr: 1; /** i2s2_task_start_tx_st_clr : WT; bitpos: [15]; default: 0; * Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s2_task_start_tx_st_clr:1; + uint32_t i2s2_task_start_tx_st_clr: 1; /** i2s2_task_stop_rx_st_clr : WT; bitpos: [16]; default: 0; * Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s2_task_stop_rx_st_clr:1; + uint32_t i2s2_task_stop_rx_st_clr: 1; /** i2s2_task_stop_tx_st_clr : WT; bitpos: [17]; default: 0; * Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t i2s2_task_stop_tx_st_clr:1; + uint32_t i2s2_task_stop_tx_st_clr: 1; /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [18]; default: 0; * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t ulp_task_wakeup_cpu_st_clr:1; + uint32_t ulp_task_wakeup_cpu_st_clr: 1; /** ulp_task_int_cpu_st_clr : WT; bitpos: [19]; default: 0; * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t ulp_task_int_cpu_st_clr:1; + uint32_t ulp_task_int_cpu_st_clr: 1; /** rtc_task_start_st_clr : WT; bitpos: [20]; default: 0; * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t rtc_task_start_st_clr:1; + uint32_t rtc_task_start_st_clr: 1; /** rtc_task_stop_st_clr : WT; bitpos: [21]; default: 0; * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t rtc_task_stop_st_clr:1; + uint32_t rtc_task_stop_st_clr: 1; /** rtc_task_clr_st_clr : WT; bitpos: [22]; default: 0; * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No * effect\\1: Clear */ - uint32_t rtc_task_clr_st_clr:1; + uint32_t rtc_task_clr_st_clr: 1; /** rtc_task_triggerflw_st_clr : WT; bitpos: [23]; default: 0; * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t rtc_task_triggerflw_st_clr:1; + uint32_t rtc_task_triggerflw_st_clr: 1; /** pdma_ahb_task_in_start_ch0_st_clr : WT; bitpos: [24]; default: 0; * Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_task_in_start_ch0_st_clr:1; + uint32_t pdma_ahb_task_in_start_ch0_st_clr: 1; /** pdma_ahb_task_in_start_ch1_st_clr : WT; bitpos: [25]; default: 0; * Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_task_in_start_ch1_st_clr:1; + uint32_t pdma_ahb_task_in_start_ch1_st_clr: 1; /** pdma_ahb_task_in_start_ch2_st_clr : WT; bitpos: [26]; default: 0; * Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_task_in_start_ch2_st_clr:1; + uint32_t pdma_ahb_task_in_start_ch2_st_clr: 1; /** pdma_ahb_task_out_start_ch0_st_clr : WT; bitpos: [27]; default: 0; * Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_task_out_start_ch0_st_clr:1; + uint32_t pdma_ahb_task_out_start_ch0_st_clr: 1; /** pdma_ahb_task_out_start_ch1_st_clr : WT; bitpos: [28]; default: 0; * Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_task_out_start_ch1_st_clr:1; + uint32_t pdma_ahb_task_out_start_ch1_st_clr: 1; /** pdma_ahb_task_out_start_ch2_st_clr : WT; bitpos: [29]; default: 0; * Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_ahb_task_out_start_ch2_st_clr:1; + uint32_t pdma_ahb_task_out_start_ch2_st_clr: 1; /** pdma_axi_task_in_start_ch0_st_clr : WT; bitpos: [30]; default: 0; * Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_task_in_start_ch0_st_clr:1; + uint32_t pdma_axi_task_in_start_ch0_st_clr: 1; /** pdma_axi_task_in_start_ch1_st_clr : WT; bitpos: [31]; default: 0; * Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_task_in_start_ch1_st_clr:1; + uint32_t pdma_axi_task_in_start_ch1_st_clr: 1; }; uint32_t val; } soc_etm_task_st5_clr_reg_t; @@ -6343,78 +4970,78 @@ typedef union { * Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_task_in_start_ch2_st_clr:1; + uint32_t pdma_axi_task_in_start_ch2_st_clr: 1; /** pdma_axi_task_out_start_ch0_st_clr : WT; bitpos: [1]; default: 0; * Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_task_out_start_ch0_st_clr:1; + uint32_t pdma_axi_task_out_start_ch0_st_clr: 1; /** pdma_axi_task_out_start_ch1_st_clr : WT; bitpos: [2]; default: 0; * Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_task_out_start_ch1_st_clr:1; + uint32_t pdma_axi_task_out_start_ch1_st_clr: 1; /** pdma_axi_task_out_start_ch2_st_clr : WT; bitpos: [3]; default: 0; * Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t pdma_axi_task_out_start_ch2_st_clr:1; + uint32_t pdma_axi_task_out_start_ch2_st_clr: 1; /** pmu_task_sleep_req_st_clr : WT; bitpos: [4]; default: 0; * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, * No effect\\1: Clear */ - uint32_t pmu_task_sleep_req_st_clr:1; + uint32_t pmu_task_sleep_req_st_clr: 1; /** dma2d_task_in_start_ch0_st_clr : WT; bitpos: [5]; default: 0; * Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_in_start_ch0_st_clr:1; + uint32_t dma2d_task_in_start_ch0_st_clr: 1; /** dma2d_task_in_start_ch1_st_clr : WT; bitpos: [6]; default: 0; * Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_in_start_ch1_st_clr:1; + uint32_t dma2d_task_in_start_ch1_st_clr: 1; /** dma2d_task_in_dscr_ready_ch0_st_clr : WT; bitpos: [7]; default: 0; * Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_in_dscr_ready_ch0_st_clr:1; + uint32_t dma2d_task_in_dscr_ready_ch0_st_clr: 1; /** dma2d_task_in_dscr_ready_ch1_st_clr : WT; bitpos: [8]; default: 0; * Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_in_dscr_ready_ch1_st_clr:1; + uint32_t dma2d_task_in_dscr_ready_ch1_st_clr: 1; /** dma2d_task_out_start_ch0_st_clr : WT; bitpos: [9]; default: 0; * Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_out_start_ch0_st_clr:1; + uint32_t dma2d_task_out_start_ch0_st_clr: 1; /** dma2d_task_out_start_ch1_st_clr : WT; bitpos: [10]; default: 0; * Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_out_start_ch1_st_clr:1; + uint32_t dma2d_task_out_start_ch1_st_clr: 1; /** dma2d_task_out_start_ch2_st_clr : WT; bitpos: [11]; default: 0; * Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0: * Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_out_start_ch2_st_clr:1; + uint32_t dma2d_task_out_start_ch2_st_clr: 1; /** dma2d_task_out_dscr_ready_ch0_st_clr : WT; bitpos: [12]; default: 0; * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_out_dscr_ready_ch0_st_clr:1; + uint32_t dma2d_task_out_dscr_ready_ch0_st_clr: 1; /** dma2d_task_out_dscr_ready_ch1_st_clr : WT; bitpos: [13]; default: 0; * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_out_dscr_ready_ch1_st_clr:1; + uint32_t dma2d_task_out_dscr_ready_ch1_st_clr: 1; /** dma2d_task_out_dscr_ready_ch2_st_clr : WT; bitpos: [14]; default: 0; * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger * status.\\0: Invalid, No effect\\1: Clear */ - uint32_t dma2d_task_out_dscr_ready_ch2_st_clr:1; - uint32_t reserved_15:17; + uint32_t dma2d_task_out_dscr_ready_ch2_st_clr: 1; + uint32_t reserved_15: 17; }; uint32_t val; } soc_etm_task_st6_clr_reg_t; @@ -6428,13 +5055,12 @@ typedef union { * Configures whether or not to open register clock gate.\\0: Open the clock gate only * when application writes registers\\1: Force open the clock gate for register */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t clk_en: 1; + uint32_t reserved_1: 31; }; uint32_t val; } soc_etm_clk_en_reg_t; - /** Group: Version Register */ /** Type of date register * ETM date register @@ -6444,120 +5070,23 @@ typedef union { /** date : R/W; bitpos: [27:0]; default: 36712497; * Configures the version. */ - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } soc_etm_date_reg_t; - -typedef struct { +typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; - volatile soc_etm_ch0_evt_id_reg_t ch0_evt_id; - volatile soc_etm_ch0_task_id_reg_t ch0_task_id; - volatile soc_etm_ch1_evt_id_reg_t ch1_evt_id; - volatile soc_etm_ch1_task_id_reg_t ch1_task_id; - volatile soc_etm_ch2_evt_id_reg_t ch2_evt_id; - volatile soc_etm_ch2_task_id_reg_t ch2_task_id; - volatile soc_etm_ch3_evt_id_reg_t ch3_evt_id; - volatile soc_etm_ch3_task_id_reg_t ch3_task_id; - volatile soc_etm_ch4_evt_id_reg_t ch4_evt_id; - volatile soc_etm_ch4_task_id_reg_t ch4_task_id; - volatile soc_etm_ch5_evt_id_reg_t ch5_evt_id; - volatile soc_etm_ch5_task_id_reg_t ch5_task_id; - volatile soc_etm_ch6_evt_id_reg_t ch6_evt_id; - volatile soc_etm_ch6_task_id_reg_t ch6_task_id; - volatile soc_etm_ch7_evt_id_reg_t ch7_evt_id; - volatile soc_etm_ch7_task_id_reg_t ch7_task_id; - volatile soc_etm_ch8_evt_id_reg_t ch8_evt_id; - volatile soc_etm_ch8_task_id_reg_t ch8_task_id; - volatile soc_etm_ch9_evt_id_reg_t ch9_evt_id; - volatile soc_etm_ch9_task_id_reg_t ch9_task_id; - volatile soc_etm_ch10_evt_id_reg_t ch10_evt_id; - volatile soc_etm_ch10_task_id_reg_t ch10_task_id; - volatile soc_etm_ch11_evt_id_reg_t ch11_evt_id; - volatile soc_etm_ch11_task_id_reg_t ch11_task_id; - volatile soc_etm_ch12_evt_id_reg_t ch12_evt_id; - volatile soc_etm_ch12_task_id_reg_t ch12_task_id; - volatile soc_etm_ch13_evt_id_reg_t ch13_evt_id; - volatile soc_etm_ch13_task_id_reg_t ch13_task_id; - volatile soc_etm_ch14_evt_id_reg_t ch14_evt_id; - volatile soc_etm_ch14_task_id_reg_t ch14_task_id; - volatile soc_etm_ch15_evt_id_reg_t ch15_evt_id; - volatile soc_etm_ch15_task_id_reg_t ch15_task_id; - volatile soc_etm_ch16_evt_id_reg_t ch16_evt_id; - volatile soc_etm_ch16_task_id_reg_t ch16_task_id; - volatile soc_etm_ch17_evt_id_reg_t ch17_evt_id; - volatile soc_etm_ch17_task_id_reg_t ch17_task_id; - volatile soc_etm_ch18_evt_id_reg_t ch18_evt_id; - volatile soc_etm_ch18_task_id_reg_t ch18_task_id; - volatile soc_etm_ch19_evt_id_reg_t ch19_evt_id; - volatile soc_etm_ch19_task_id_reg_t ch19_task_id; - volatile soc_etm_ch20_evt_id_reg_t ch20_evt_id; - volatile soc_etm_ch20_task_id_reg_t ch20_task_id; - volatile soc_etm_ch21_evt_id_reg_t ch21_evt_id; - volatile soc_etm_ch21_task_id_reg_t ch21_task_id; - volatile soc_etm_ch22_evt_id_reg_t ch22_evt_id; - volatile soc_etm_ch22_task_id_reg_t ch22_task_id; - volatile soc_etm_ch23_evt_id_reg_t ch23_evt_id; - volatile soc_etm_ch23_task_id_reg_t ch23_task_id; - volatile soc_etm_ch24_evt_id_reg_t ch24_evt_id; - volatile soc_etm_ch24_task_id_reg_t ch24_task_id; - volatile soc_etm_ch25_evt_id_reg_t ch25_evt_id; - volatile soc_etm_ch25_task_id_reg_t ch25_task_id; - volatile soc_etm_ch26_evt_id_reg_t ch26_evt_id; - volatile soc_etm_ch26_task_id_reg_t ch26_task_id; - volatile soc_etm_ch27_evt_id_reg_t ch27_evt_id; - volatile soc_etm_ch27_task_id_reg_t ch27_task_id; - volatile soc_etm_ch28_evt_id_reg_t ch28_evt_id; - volatile soc_etm_ch28_task_id_reg_t ch28_task_id; - volatile soc_etm_ch29_evt_id_reg_t ch29_evt_id; - volatile soc_etm_ch29_task_id_reg_t ch29_task_id; - volatile soc_etm_ch30_evt_id_reg_t ch30_evt_id; - volatile soc_etm_ch30_task_id_reg_t ch30_task_id; - volatile soc_etm_ch31_evt_id_reg_t ch31_evt_id; - volatile soc_etm_ch31_task_id_reg_t ch31_task_id; - volatile soc_etm_ch32_evt_id_reg_t ch32_evt_id; - volatile soc_etm_ch32_task_id_reg_t ch32_task_id; - volatile soc_etm_ch33_evt_id_reg_t ch33_evt_id; - volatile soc_etm_ch33_task_id_reg_t ch33_task_id; - volatile soc_etm_ch34_evt_id_reg_t ch34_evt_id; - volatile soc_etm_ch34_task_id_reg_t ch34_task_id; - volatile soc_etm_ch35_evt_id_reg_t ch35_evt_id; - volatile soc_etm_ch35_task_id_reg_t ch35_task_id; - volatile soc_etm_ch36_evt_id_reg_t ch36_evt_id; - volatile soc_etm_ch36_task_id_reg_t ch36_task_id; - volatile soc_etm_ch37_evt_id_reg_t ch37_evt_id; - volatile soc_etm_ch37_task_id_reg_t ch37_task_id; - volatile soc_etm_ch38_evt_id_reg_t ch38_evt_id; - volatile soc_etm_ch38_task_id_reg_t ch38_task_id; - volatile soc_etm_ch39_evt_id_reg_t ch39_evt_id; - volatile soc_etm_ch39_task_id_reg_t ch39_task_id; - volatile soc_etm_ch40_evt_id_reg_t ch40_evt_id; - volatile soc_etm_ch40_task_id_reg_t ch40_task_id; - volatile soc_etm_ch41_evt_id_reg_t ch41_evt_id; - volatile soc_etm_ch41_task_id_reg_t ch41_task_id; - volatile soc_etm_ch42_evt_id_reg_t ch42_evt_id; - volatile soc_etm_ch42_task_id_reg_t ch42_task_id; - volatile soc_etm_ch43_evt_id_reg_t ch43_evt_id; - volatile soc_etm_ch43_task_id_reg_t ch43_task_id; - volatile soc_etm_ch44_evt_id_reg_t ch44_evt_id; - volatile soc_etm_ch44_task_id_reg_t ch44_task_id; - volatile soc_etm_ch45_evt_id_reg_t ch45_evt_id; - volatile soc_etm_ch45_task_id_reg_t ch45_task_id; - volatile soc_etm_ch46_evt_id_reg_t ch46_evt_id; - volatile soc_etm_ch46_task_id_reg_t ch46_task_id; - volatile soc_etm_ch47_evt_id_reg_t ch47_evt_id; - volatile soc_etm_ch47_task_id_reg_t ch47_task_id; - volatile soc_etm_ch48_evt_id_reg_t ch48_evt_id; - volatile soc_etm_ch48_task_id_reg_t ch48_task_id; - volatile soc_etm_ch49_evt_id_reg_t ch49_evt_id; - volatile soc_etm_ch49_task_id_reg_t ch49_task_id; + volatile struct { + soc_etm_chn_evt_id_reg_t evt_id; + soc_etm_chn_task_id_reg_t task_id; + } channel[50]; volatile soc_etm_evt_st0_reg_t evt_st0; volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; volatile soc_etm_evt_st1_reg_t evt_st1; @@ -6592,6 +5121,7 @@ typedef struct { volatile soc_etm_date_reg_t date; } soc_etm_dev_t; +extern soc_etm_dev_t SOC_ETM; #ifndef __cplusplus _Static_assert(sizeof(soc_etm_dev_t) == 0x228, "Invalid size of soc_etm_dev_t structure");