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Merge branch 'bugfix/recalib_bbpll_before_tuning_v4.4' into 'release/v4.4'

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fix(bbpll): fix bbpll may not lock or not stable bug for stop early (ESP32C2/S3/C6/H2) (v4.4)

See merge request espressif/esp-idf!28287
This commit is contained in:
Michael (XIAO Xufeng) 2024-01-18 11:00:21 +08:00
commit 90f913734b
3 changed files with 38 additions and 1 deletions
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20
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@ -277,6 +277,7 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
/* WAIT CALIBRATION DONE */
while (!GET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE));
esp_rom_delay_us(10);
/* BBPLL CALIBRATION STOP */
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
@ -599,6 +600,25 @@ static bool rtc_clk_set_bbpll_always_on(void)
return is_bbpll_on;
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
void rtc_clk_recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
rtc_clk_cpu_freq_get_config(&old_config);
// There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
// - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
// Turn off the BBPLL and do calibration again to fix the issue.
// - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
// requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
if (old_config.source == RTC_CPU_FREQ_SRC_PLL) {
rtc_clk_cpu_freq_set_xtal();
rtc_clk_cpu_freq_set_config(&old_config);
}
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

9
components/esp_system/Kconfig
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@ -499,4 +499,13 @@ menu "ESP System Settings"
Using level 4 interrupt for Interrupt Watchdog and other system checks.
endchoice
config ESP_SYSTEM_BBPLL_RECALIB
bool "Re-calibration BBPLL at startup"
depends on IDF_TARGET_ESP32S3
default y
help
This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
ESP-IDF version v5.2 and above.
endmenu # ESP System Settings

10
components/esp_system/port/cpu_start.c
View File

@ -427,8 +427,16 @@ void IRAM_ATTR call_start_cpu0(void)
* In this stage, we re-configure the Flash (and MSPI) to required configuration
*/
spi_flash_init_chip_state();
// In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
// Do calibration again here so that we can use better clock for the timing tuning.
#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
extern void rtc_clk_recalib_bbpll(void);
rtc_clk_recalib_bbpll();
#endif
#if CONFIG_IDF_TARGET_ESP32S3
//On other chips, this feature is not provided by HW, or hasn't been tested yet.
// This function needs to be called when PLL is enabled
// On other chips, this feature is not provided by HW, or hasn't been tested yet.
spi_timing_flash_tuning();
#endif