diff --git a/components/newlib/time.c b/components/newlib/time.c
index 30c7ca7f40..7595ab82b8 100644
--- a/components/newlib/time.c
+++ b/components/newlib/time.c
@@ -85,9 +85,8 @@ static void IRAM_ATTR frc_timer_isr()
 {
     // Write to FRC_TIMER_INT_REG may not take effect in some cases (root cause TBD)
     // This extra write works around this issue.
-    // There is no register at DR_REG_FRC_TIMER_BASE + 0x60 (in fact, any DPORT register address can be used).
-    WRITE_PERI_REG(DR_REG_FRC_TIMER_BASE + 0x60, 0xabababab);
-    // Clear interrupt status
+    // FRC_TIMER_LOAD_REG(0) is used here, but any other DPORT register address can also be used.
+    WRITE_PERI_REG(FRC_TIMER_LOAD_REG(0), FRC_TIMER_LOAD_VALUE(0));
     WRITE_PERI_REG(FRC_TIMER_INT_REG(0), FRC_TIMER_INT_CLR);
     s_microseconds += FRC1_ISR_PERIOD_US;
 }