Merge branch 'master' into feature/freertos_static_buffers

This commit is contained in:
Ivan Grokhotkov 2016-10-17 16:02:09 +08:00
commit 8f82a83c2c
33 changed files with 22232 additions and 546 deletions

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@ -62,7 +62,7 @@ build_ssc:
expire_in: 6 mos
script:
- git clone ssh://git@gitlab.espressif.cn:27227/yinling/SSC.git
- git clone $GITLAB_SSH_SERVER/yinling/SSC.git
- cd SSC
- git checkout ${CI_BUILD_REF_NAME} || echo "Using SSC default branch..."
- make defconfig
@ -105,47 +105,33 @@ test_build_system:
script:
- ./make/test_build_system.sh
# template for test jobs
.test_template: &test_template
stage: test
when: on_success
test_report:
stage: deploy
only:
- master
- triggers
tags:
- test_report
allow_failure: true
variables:
# need user to set SDK_NAME and CONFIG_FILE (may need to set BIN_PATH and APP_NAME later) in before_script
SCRIPT_PATH: /home/gitlab-runner/auto_test_script
BIN_PATH: ${CI_PROJECT_DIR}/SSC/build/
APP_NAME: ssc
LOG_PATH: $CI_PROJECT_DIR/$CI_BUILD_REF
LOG_PATH: "$CI_PROJECT_DIR/$CI_BUILD_REF"
TEST_CASE_FILE_PATH: "$CI_PROJECT_DIR/components/idf_test"
REPORT_PATH: "$CI_PROJECT_DIR/CI_Test_Report"
artifacts:
when: always
paths:
- $LOG_PATH
- $REPORT_PATH
expire_in: 6 mos
script:
- cd $SCRIPT_PATH
- python CIRunner.py -l $LOG_PATH -c $SDK_NAME/$CONFIG_FILE bin_path $APP_NAME $BIN_PATH
sanity_test:
<<: *test_template
tags:
- ESP32
- SSC_T1_1
- SSC_T2_1
- SSC_T1_WAN
before_script:
- SDK_NAME=ESP32_IDF
- CONFIG_FILE=sanity_test.yml
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
# generate report
- python CITestReport.py -l $LOG_PATH -t $TEST_CASE_FILE_PATH -p $REPORT_PATH
push_master_to_github:
before_script:
before_script:
- echo "Not setting up GitLab key, not fetching submodules"
stage: deploy
only:
@ -165,3 +151,250 @@ push_master_to_github:
- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
- git remote add github git@github.com:espressif/esp-idf.git
- git push --follow-tags github HEAD:master
# AUTO GENERATED PART START, DO NOT MODIFY CONTENT BELOW
# template for test jobs
.test_template: &test_template
stage: test
when: on_success
only:
- master
- triggers
allow_failure: true
variables:
# LOCAL_ENV_CONFIG_PATH: define in template and jobs can overwrite if required
LOCAL_ENV_CONFIG_PATH: /home/gitlab-runner/LocalConfig/ESP32_IDF
BIN_PATH: "$CI_PROJECT_DIR/SSC/build/"
APP_NAME: "ssc"
LOG_PATH: "$CI_PROJECT_DIR/$CI_BUILD_REF"
# append test level folder to TEST_CASE_FILE_PATH in before_script of test job
TEST_CASE_FILE_PATH: "$CI_PROJECT_DIR/components/idf_test"
# jobs MUST set CONFIG_FILE in before_script, and overwrite the variables above if necessary
artifacts:
when: always
paths:
- $LOG_PATH
expire_in: 6 mos
script:
# add gitlab ssh key
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo -n $GITLAB_KEY > ~/.ssh/id_rsa_base64
- base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
- chmod 600 ~/.ssh/id_rsa
- echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
# run test
- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH bin_path $APP_NAME $BIN_PATH
# template for overnight test jobs
.test_template_night: &test_template_night
<<: *test_template
only:
# can only be triggered
- triggers
script:
# must be night build triggers, otherwise exit without test
- test $NIGHT_BUILD = "Yes" || exit 0
# add gitlab ssh key
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo -n $GITLAB_KEY > ~/.ssh/id_rsa_base64
- base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
- chmod 600 ~/.ssh/id_rsa
- echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
# run test
- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH bin_path $APP_NAME $BIN_PATH
IT_Function_SYS_01:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_SYS_01.yml
IT_Function_WIFI_01:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_01.yml
IT_Function_WIFI_02:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_02.yml
IT_Function_TCPIP_01:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_01.yml
IT_Function_TCPIP_02:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_02.yml
IT_Function_TCPIP_03:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_03.yml
IT_Function_TCPIP_04:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_04.yml
IT_Function_TCPIP_05:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_05.yml
IT_Function_TCPIP_06:
<<: *test_template_night
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_06.yml
IT_Function_WIFI_03:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T3_PhyMode
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_03.yml
IT_Function_WIFI_04:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_APC
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_04.yml
IT_Function_WIFI_05:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_WEP
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_05.yml
IT_Function_WIFI_06:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T2_PhyMode
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_06.yml
IT_Function_TCPIP_07:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T1_2
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_07.yml
IT_Function_TCPIP_08:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_08.yml
IT_Function_TCPIP_09:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_09.yml
IT_Function_TCPIP_10:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T1_2
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_10.yml
IT_Function_TCPIP_11:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_11.yml
IT_Function_TCPIP_12:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T1_2
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_12.yml

View File

@ -1,368 +1,368 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_err.h"
#include "esp_intr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/xtensa_api.h"
#include "driver/gpio.h"
#include "soc/soc.h"
//TODO: move debug options to menuconfig
#define GPIO_DBG_ENABLE (0)
#define GPIO_WARNING_ENABLE (0)
#define GPIO_ERROR_ENABLE (0)
#define GPIO_INFO_ENABLE (0)
//DBG INFOR
#if GPIO_INFO_ENABLE
#define GPIO_INFO ets_printf
#else
#define GPIO_INFO(...)
#endif
#if GPIO_WARNING_ENABLE
#define GPIO_WARNING(format,...) do{\
ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_WARNING(...)
#endif
#if GPIO_ERROR_ENABLE
#define GPIO_ERROR(format,...) do{\
ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_ERROR(...)
#endif
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
GPIO_PIN_REG_0,
GPIO_PIN_REG_1,
GPIO_PIN_REG_2,
GPIO_PIN_REG_3,
GPIO_PIN_REG_4,
GPIO_PIN_REG_5,
GPIO_PIN_REG_6,
GPIO_PIN_REG_7,
GPIO_PIN_REG_8,
GPIO_PIN_REG_9,
GPIO_PIN_REG_10,
GPIO_PIN_REG_11,
GPIO_PIN_REG_12,
GPIO_PIN_REG_13,
GPIO_PIN_REG_14,
GPIO_PIN_REG_15,
GPIO_PIN_REG_16,
GPIO_PIN_REG_17,
GPIO_PIN_REG_18,
GPIO_PIN_REG_19,
0,
GPIO_PIN_REG_21,
GPIO_PIN_REG_22,
GPIO_PIN_REG_23,
0,
GPIO_PIN_REG_25,
GPIO_PIN_REG_26,
GPIO_PIN_REG_27,
0,
0,
0,
0,
GPIO_PIN_REG_32,
GPIO_PIN_REG_33,
GPIO_PIN_REG_34,
GPIO_PIN_REG_35,
GPIO_PIN_REG_36,
GPIO_PIN_REG_37,
GPIO_PIN_REG_38,
GPIO_PIN_REG_39
};
static int is_valid_gpio(int gpio_num)
{
if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) {
GPIO_ERROR("GPIO io_num=%d does not exist\n",gpio_num);
return 0;
}
return 1;
}
esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(intr_type >= GPIO_INTR_MAX) {
GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type);
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].int_type = intr_type;
return ESP_OK;
}
esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(xPortGetCoreID() == 0) {
GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
} else {
GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
}
return ESP_OK;
}
esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr
return ESP_OK;
}
static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
{
if(gpio_num >= 34) {
GPIO_ERROR("io_num=%d can only be input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
{
if(!GPIO_IS_VALID_GPIO(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(level) {
if(gpio_num < 32) {
GPIO.out_w1ts = (1 << gpio_num);
} else {
GPIO.out1_w1ts.data = (1 << (gpio_num - 32));
}
} else {
if(gpio_num < 32) {
GPIO.out_w1tc = (1 << gpio_num);
} else {
GPIO.out1_w1tc.data = (1 << (gpio_num - 32));
}
}
return ESP_OK;
}
int gpio_get_level(gpio_num_t gpio_num)
{
if(gpio_num < 32) {
return (GPIO.in >> gpio_num) & 0x1;
} else {
return (GPIO.in1.data >> (gpio_num - 32)) & 0x1;
}
}
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
switch(pull) {
case GPIO_PULLUP_ONLY:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLDOWN_ONLY:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLUP_PULLDOWN:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_FLOATING:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
default:
GPIO_ERROR("Unknown pull up/down mode,gpio_num=%u,pull=%u\n",gpio_num,pull);
ret = ESP_ERR_INVALID_ARG;
break;
}
return ret;
}
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) {
GPIO_ERROR("io_num=%d can only be input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
if(mode & GPIO_MODE_DEF_INPUT) {
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
} else {
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
}
if(mode & GPIO_MODE_DEF_OUTPUT) {
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
} else {
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
}
if(mode & GPIO_MODE_DEF_OD) {
GPIO.pin[gpio_num].pad_driver = 1;
} else {
GPIO.pin[gpio_num].pad_driver = 0;
}
return ret;
}
esp_err_t gpio_config(gpio_config_t *pGPIOConfig)
{
uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
uint32_t io_reg = 0;
uint32_t io_num = 0;
uint64_t bit_valid = 0;
if(pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
GPIO_ERROR("GPIO_PIN mask error \n");
return ESP_ERR_INVALID_ARG;
}
if((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
//GPIO 34/35/36/37/38/39 can only be used as input mode;
if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
GPIO_ERROR("GPIO34-39 can only be used as input mode\n");
return ESP_ERR_INVALID_ARG;
}
}
do {
io_reg = GPIO_PIN_MUX_REG[io_num];
if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) {
GPIO_INFO("Gpio%02d |Mode:",io_num);
if((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
GPIO_INFO("INPUT ");
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]);
} else {
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]);
}
if((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
GPIO_INFO("OD ");
GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */
} else {
GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */
}
if((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
GPIO_INFO("OUTPUT ");
gpio_output_enable(io_num);
} else {
gpio_output_disable(io_num);
}
GPIO_INFO("|");
if(pGPIOConfig->pull_up_en) {
GPIO_INFO("PU ");
PIN_PULLUP_EN(io_reg);
} else {
PIN_PULLUP_DIS(io_reg);
}
if(pGPIOConfig->pull_down_en) {
GPIO_INFO("PD ");
PIN_PULLDWN_EN(io_reg);
} else {
PIN_PULLDWN_DIS(io_reg);
}
GPIO_INFO("Intr:%d |\n",pGPIOConfig->intr_type);
gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
if(pGPIOConfig->intr_type) {
gpio_intr_enable(io_num);
} else {
gpio_intr_disable(io_num);
}
PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */
} else if(bit_valid && (io_reg == 0)) {
GPIO_WARNING("io_num=%d does not exist\n",io_num);
}
io_num++;
} while(io_num < GPIO_PIN_COUNT);
return ESP_OK;
}
esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg)
{
if(fn == NULL) {
return ESP_ERR_INVALID_ARG;
}
ESP_INTR_DISABLE(gpio_intr_num);
intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num);
xt_set_interrupt_handler(gpio_intr_num, fn, arg);
ESP_INTR_ENABLE(gpio_intr_num);
return ESP_OK;
}
/*only level interrupt can be used for wake-up function*/
esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
GPIO.pin[gpio_num].int_type = intr_type;
GPIO.pin[gpio_num].wakeup_enable = 0x1;
} else {
GPIO_ERROR("GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u\n",gpio_num);
ret = ESP_ERR_INVALID_ARG;
}
return ret;
}
esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].wakeup_enable = 0;
return ESP_OK;
}
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_err.h"
#include "esp_intr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/xtensa_api.h"
#include "driver/gpio.h"
#include "soc/soc.h"
//TODO: move debug options to menuconfig
#define GPIO_DBG_ENABLE (0)
#define GPIO_WARNING_ENABLE (0)
#define GPIO_ERROR_ENABLE (0)
#define GPIO_INFO_ENABLE (0)
//DBG INFOR
#if GPIO_INFO_ENABLE
#define GPIO_INFO ets_printf
#else
#define GPIO_INFO(...)
#endif
#if GPIO_WARNING_ENABLE
#define GPIO_WARNING(format,...) do{\
ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_WARNING(...)
#endif
#if GPIO_ERROR_ENABLE
#define GPIO_ERROR(format,...) do{\
ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_ERROR(...)
#endif
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
GPIO_PIN_REG_0,
GPIO_PIN_REG_1,
GPIO_PIN_REG_2,
GPIO_PIN_REG_3,
GPIO_PIN_REG_4,
GPIO_PIN_REG_5,
GPIO_PIN_REG_6,
GPIO_PIN_REG_7,
GPIO_PIN_REG_8,
GPIO_PIN_REG_9,
GPIO_PIN_REG_10,
GPIO_PIN_REG_11,
GPIO_PIN_REG_12,
GPIO_PIN_REG_13,
GPIO_PIN_REG_14,
GPIO_PIN_REG_15,
GPIO_PIN_REG_16,
GPIO_PIN_REG_17,
GPIO_PIN_REG_18,
GPIO_PIN_REG_19,
0,
GPIO_PIN_REG_21,
GPIO_PIN_REG_22,
GPIO_PIN_REG_23,
0,
GPIO_PIN_REG_25,
GPIO_PIN_REG_26,
GPIO_PIN_REG_27,
0,
0,
0,
0,
GPIO_PIN_REG_32,
GPIO_PIN_REG_33,
GPIO_PIN_REG_34,
GPIO_PIN_REG_35,
GPIO_PIN_REG_36,
GPIO_PIN_REG_37,
GPIO_PIN_REG_38,
GPIO_PIN_REG_39
};
static int is_valid_gpio(int gpio_num)
{
if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) {
GPIO_ERROR("GPIO io_num=%d does not exist\n",gpio_num);
return 0;
}
return 1;
}
esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(intr_type >= GPIO_INTR_MAX) {
GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type);
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].int_type = intr_type;
return ESP_OK;
}
esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(xPortGetCoreID() == 0) {
GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
} else {
GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
}
return ESP_OK;
}
esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr
return ESP_OK;
}
static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
{
if(gpio_num >= 34) {
GPIO_ERROR("io_num=%d can only be input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
{
if(!GPIO_IS_VALID_GPIO(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(level) {
if(gpio_num < 32) {
GPIO.out_w1ts = (1 << gpio_num);
} else {
GPIO.out1_w1ts.data = (1 << (gpio_num - 32));
}
} else {
if(gpio_num < 32) {
GPIO.out_w1tc = (1 << gpio_num);
} else {
GPIO.out1_w1tc.data = (1 << (gpio_num - 32));
}
}
return ESP_OK;
}
int gpio_get_level(gpio_num_t gpio_num)
{
if(gpio_num < 32) {
return (GPIO.in >> gpio_num) & 0x1;
} else {
return (GPIO.in1.data >> (gpio_num - 32)) & 0x1;
}
}
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
switch(pull) {
case GPIO_PULLUP_ONLY:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLDOWN_ONLY:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLUP_PULLDOWN:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_FLOATING:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
default:
GPIO_ERROR("Unknown pull up/down mode,gpio_num=%u,pull=%u\n",gpio_num,pull);
ret = ESP_ERR_INVALID_ARG;
break;
}
return ret;
}
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) {
GPIO_ERROR("io_num=%d can only be input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
if(mode & GPIO_MODE_DEF_INPUT) {
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
} else {
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
}
if(mode & GPIO_MODE_DEF_OUTPUT) {
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
} else {
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
}
if(mode & GPIO_MODE_DEF_OD) {
GPIO.pin[gpio_num].pad_driver = 1;
} else {
GPIO.pin[gpio_num].pad_driver = 0;
}
return ret;
}
esp_err_t gpio_config(gpio_config_t *pGPIOConfig)
{
uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
uint32_t io_reg = 0;
uint32_t io_num = 0;
uint64_t bit_valid = 0;
if(pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
GPIO_ERROR("GPIO_PIN mask error \n");
return ESP_ERR_INVALID_ARG;
}
if((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
//GPIO 34/35/36/37/38/39 can only be used as input mode;
if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
GPIO_ERROR("GPIO34-39 can only be used as input mode\n");
return ESP_ERR_INVALID_ARG;
}
}
do {
io_reg = GPIO_PIN_MUX_REG[io_num];
if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) {
GPIO_INFO("Gpio%02d |Mode:",io_num);
if((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
GPIO_INFO("INPUT ");
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]);
} else {
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]);
}
if((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
GPIO_INFO("OD ");
GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */
} else {
GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */
}
if((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
GPIO_INFO("OUTPUT ");
gpio_output_enable(io_num);
} else {
gpio_output_disable(io_num);
}
GPIO_INFO("|");
if(pGPIOConfig->pull_up_en) {
GPIO_INFO("PU ");
PIN_PULLUP_EN(io_reg);
} else {
PIN_PULLUP_DIS(io_reg);
}
if(pGPIOConfig->pull_down_en) {
GPIO_INFO("PD ");
PIN_PULLDWN_EN(io_reg);
} else {
PIN_PULLDWN_DIS(io_reg);
}
GPIO_INFO("Intr:%d |\n",pGPIOConfig->intr_type);
gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
if(pGPIOConfig->intr_type) {
gpio_intr_enable(io_num);
} else {
gpio_intr_disable(io_num);
}
PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */
} else if(bit_valid && (io_reg == 0)) {
GPIO_WARNING("io_num=%d does not exist\n",io_num);
}
io_num++;
} while(io_num < GPIO_PIN_COUNT);
return ESP_OK;
}
esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg)
{
if(fn == NULL) {
return ESP_ERR_INVALID_ARG;
}
ESP_INTR_DISABLE(gpio_intr_num);
intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num);
xt_set_interrupt_handler(gpio_intr_num, fn, arg);
ESP_INTR_ENABLE(gpio_intr_num);
return ESP_OK;
}
/*only level interrupt can be used for wake-up function*/
esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
GPIO.pin[gpio_num].int_type = intr_type;
GPIO.pin[gpio_num].wakeup_enable = 0x1;
} else {
GPIO_ERROR("GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u\n",gpio_num);
ret = ESP_ERR_INVALID_ARG;
}
return ret;
}
esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].wakeup_enable = 0;
return ESP_OK;
}

View File

@ -15,7 +15,7 @@
#include <freertos/heap_regions.h>
#include "heap_alloc_caps.h"
#include "esp_heap_alloc_caps.h"
#include "spiram.h"
#include "esp_log.h"
@ -40,23 +40,23 @@ Tag descriptors. These describe the capabilities of a bit of memory that's tagge
Each tag contains NO_PRIOS entries; later entries are only taken if earlier ones can't fulfill the memory request.
*/
static const uint32_t tagDesc[][NO_PRIOS]={
{ MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 }, //Tag 0: Plain ole D-port RAM
{ 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, //Tag 1: Plain ole D-port RAM which has an alias on the I-port
{ MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 }, //Tag 2: IRAM
{ MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //Tag 3-8: PID 2-7 IRAM
{ MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //Tag 9-14: PID 2-7 DRAM
{ MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data
{ MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End
{ MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 }, //Tag 0: Plain ole D-port RAM
{ 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, //Tag 1: Plain ole D-port RAM which has an alias on the I-port
{ MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 }, //Tag 2: IRAM
{ MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //Tag 3-8: PID 2-7 IRAM
{ MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //Tag 9-14: PID 2-7 DRAM
{ MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data
{ MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End
};
/*
@ -79,81 +79,81 @@ be sorted from low to high start address.
This array is *NOT* const because it gets modified depending on what pools are/aren't available.
*/
static HeapRegionTagged_t regions[]={
{ (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available
{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT
{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT
{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
{ (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
{ (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
{ (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
{ (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
{ (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
{ (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
{ (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
{ (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
{ (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
{ (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
{ (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
{ (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
{ (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
{ (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
{ (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
{ (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
{ (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0
{ (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1
{ (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
{ (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
{ (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
{ (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
{ (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
{ (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
{ (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
{ (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
{ (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
{ (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
{ (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
{ (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
{ (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
{ (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
{ (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
{ (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
{ NULL, 0, 0, 0} //end
{ (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available
{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT
{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT
{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
{ (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
{ (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
{ (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
{ (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
{ (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
{ (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
{ (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
{ (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
{ (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
{ (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
{ (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
{ (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
{ (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
{ (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
{ (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
{ (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
{ (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0
{ (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1
{ (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
{ (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
{ (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
{ (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
{ (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
{ (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
{ (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
{ (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
{ (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
{ (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
{ (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
{ (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
{ (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
{ (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
{ (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
{ (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
{ NULL, 0, 0, 0} //end
};
//Modify regions array to disable the given range of memory.
static void disable_mem_region(void *from, void *to) {
int i;
//Align from and to on word boundaries
from=(void*)((uint32_t)from&~3);
to=(void*)(((uint32_t)to+3)&~3);
for (i=0; regions[i].xSizeInBytes!=0; i++) {
void *regStart=regions[i].pucStartAddress;
void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes;
if (regStart>=from && regEnd<=to) {
//Entire region falls in the range. Disable entirely.
regions[i].xTag=-1;
} else if (regStart>=from && regEnd>to && regStart<to) {
//Start of the region falls in the range. Modify address/len.
int overlap=(uint8_t *)to-(uint8_t *)regStart;
regions[i].pucStartAddress+=overlap;
regions[i].xSizeInBytes-=overlap;
if (regions[i].xExecAddr) regions[i].xExecAddr+=overlap;
} else if (regStart<from && regEnd>from && regEnd<=to) {
//End of the region falls in the range. Modify length.
regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
} else if (regStart<from && regEnd>to) {
//Range punches a hole in the region! We do not support this.
ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i);
regions[i].xTag=-1; //Just disable memory region. That'll teach them!
}
}
int i;
//Align from and to on word boundaries
from=(void*)((uint32_t)from&~3);
to=(void*)(((uint32_t)to+3)&~3);
for (i=0; regions[i].xSizeInBytes!=0; i++) {
void *regStart=regions[i].pucStartAddress;
void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes;
if (regStart>=from && regEnd<=to) {
//Entire region falls in the range. Disable entirely.
regions[i].xTag=-1;
} else if (regStart>=from && regEnd>to && regStart<to) {
//Start of the region falls in the range. Modify address/len.
int overlap=(uint8_t *)to-(uint8_t *)regStart;
regions[i].pucStartAddress+=overlap;
regions[i].xSizeInBytes-=overlap;
if (regions[i].xExecAddr) regions[i].xExecAddr+=overlap;
} else if (regStart<from && regEnd>from && regEnd<=to) {
//End of the region falls in the range. Modify length.
regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
} else if (regStart<from && regEnd>to) {
//Range punches a hole in the region! We do not support this.
ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i);
regions[i].xTag=-1; //Just disable memory region. That'll teach them!
}
}
}
@ -170,52 +170,52 @@ ToDo: The regions are different when stuff like trace memory, BT, ... is used. M
Same with loading of apps. Same with using SPI RAM.
*/
void heap_alloc_caps_init() {
int i;
//Disable the bits of memory where this code is loaded.
disable_mem_region(&_bss_start, &_heap_start);
disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region
disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5
int i;
//Disable the bits of memory where this code is loaded.
disable_mem_region(&_bss_start, &_heap_start);
disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region
disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5
// TODO: this region should be checked, since we don't need to knock out all region finally
disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
// TODO: this region should be checked, since we don't need to knock out all region finally
disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
#if CONFIG_MEMMAP_BT
disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region
disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region
#endif
#if CONFIG_MEMMAP_TRACEMEM
disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region
disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region
#endif
#if 0
enable_spi_sram();
enable_spi_sram();
#else
disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed
disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed
#endif
//The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory,
//it's useful to coalesce adjacent regions that have the same tag.
//The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory,
//it's useful to coalesce adjacent regions that have the same tag.
for (i=1; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) &&
regions[i].xTag == regions[i-1].xTag ) {
regions[i-1].xTag=-1;
regions[i].pucStartAddress=regions[i-1].pucStartAddress;
regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes;
}
}
for (i=1; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) &&
regions[i].xTag == regions[i-1].xTag ) {
regions[i-1].xTag=-1;
regions[i].pucStartAddress=regions[i-1].pucStartAddress;
regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes;
}
}
ESP_EARLY_LOGI(TAG, "Initializing heap allocator:");
for (i=0; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].xTag != -1) {
ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i,
(int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
}
}
//Initialize the malloc implementation.
vPortDefineHeapRegionsTagged( regions );
ESP_EARLY_LOGI(TAG, "Initializing heap allocator:");
for (i=0; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].xTag != -1) {
ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i,
(int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
}
}
//Initialize the malloc implementation.
vPortDefineHeapRegionsTagged( regions );
}
/*
@ -223,7 +223,7 @@ Standard malloc() implementation. Will return ho-hum byte-accessible data memory
*/
void *pvPortMalloc( size_t xWantedSize )
{
return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT );
return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT );
}
/*
@ -231,30 +231,30 @@ Routine to allocate a bit of memory with certain capabilities. caps is a bitfiel
*/
void *pvPortMallocCaps( size_t xWantedSize, uint32_t caps )
{
int prio;
int tag, j;
void *ret=NULL;
uint32_t remCaps;
for (prio=0; prio<NO_PRIOS; prio++) {
//Iterate over tag descriptors for this priority
for (tag=0; tagDesc[tag][prio]!=MALLOC_CAP_INVALID; tag++) {
if ((tagDesc[tag][prio]&caps)!=0) {
//Tag has at least one of the caps requested. If caps has other bits set that this prio
//doesn't cover, see if they're available in other prios.
remCaps=caps&(~tagDesc[tag][prio]); //Remaining caps to be fulfilled
j=prio+1;
while (remCaps!=0 && j<NO_PRIOS) {
remCaps=remCaps&(~tagDesc[tag][j]);
j++;
}
if (remCaps==0) {
//This tag can satisfy all the requested capabilities. See if we can grab some memory using it.
ret=pvPortMallocTagged(xWantedSize, tag);
if (ret!=NULL) return ret;
}
}
}
}
//Nothing usable found.
return NULL;
int prio;
int tag, j;
void *ret=NULL;
uint32_t remCaps;
for (prio=0; prio<NO_PRIOS; prio++) {
//Iterate over tag descriptors for this priority
for (tag=0; tagDesc[tag][prio]!=MALLOC_CAP_INVALID; tag++) {
if ((tagDesc[tag][prio]&caps)!=0) {
//Tag has at least one of the caps requested. If caps has other bits set that this prio
//doesn't cover, see if they're available in other prios.
remCaps=caps&(~tagDesc[tag][prio]); //Remaining caps to be fulfilled
j=prio+1;
while (remCaps!=0 && j<NO_PRIOS) {
remCaps=remCaps&(~tagDesc[tag][j]);
j++;
}
if (remCaps==0) {
//This tag can satisfy all the requested capabilities. See if we can grab some memory using it.
ret=pvPortMallocTagged(xWantedSize, tag);
if (ret!=NULL) return ret;
}
}
}
}
//Nothing usable found.
return NULL;
}

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@ -0,0 +1,34 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef HEAP_ALLOC_CAPS_H
#define HEAP_ALLOC_CAPS_H
#define MALLOC_CAP_EXEC (1<<0) //Memory must be able to run executable code
#define MALLOC_CAP_32BIT (1<<1) //Memory must allow for aligned 32-bit data accesses
#define MALLOC_CAP_8BIT (1<<2) //Memory must allow for 8/16/...-bit data accesses
#define MALLOC_CAP_DMA (1<<3) //Memory must be able to accessed by DMA
#define MALLOC_CAP_PID2 (1<<4) //Memory must be mapped to PID2 memory space
#define MALLOC_CAP_PID3 (1<<5) //Memory must be mapped to PID3 memory space
#define MALLOC_CAP_PID4 (1<<6) //Memory must be mapped to PID4 memory space
#define MALLOC_CAP_PID5 (1<<7) //Memory must be mapped to PID5 memory space
#define MALLOC_CAP_PID6 (1<<8) //Memory must be mapped to PID6 memory space
#define MALLOC_CAP_PID7 (1<<9) //Memory must be mapped to PID7 memory space
#define MALLOC_CAP_SPISRAM (1<<10) //Memory must be in SPI SRAM
#define MALLOC_CAP_INVALID (1<<31) //Memory can't be used / list end marker
void heap_alloc_caps_init();
void *pvPortMallocCaps(size_t xWantedSize, uint32_t caps);
#endif

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@ -3482,7 +3482,6 @@ static void prvAddCurrentTaskToDelayedList( const BaseType_t xCoreID, const Tick
BaseType_t xTaskGetAffinity( TaskHandle_t xTask )
{
TCB_t *pxTCB;
UBaseType_t uxReturn;
pxTCB = prvGetTCBFromHandle( xTask );

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@ -0,0 +1,61 @@
# Note: The test cases in this folder are for Espressif internal use.
# Goto internal project wiki Testing page for detail about this folder.
## File Structure
```
test --- CIConfigs --- sanity_test1.yml (Runner config files)
| |-- stress_test1.yml
|-- TestCaseAll.yml (TestCaseFiles)
|-- TestEnvAll.yml (TestCaseFiles)
|-- InitialConditionAll.yml (TestCaseFiles)
|-- TestCaseScript --- ... (Test case scripts)
```
1. CIConfigs folder
* config for CI config files are put in this folder
* CI config files configs the cases and some other options for the CI job with same name
1. Test case files
* TestCaseAll.yml (test cases)
* InitialConditionAll.yml (initial conditions)
* TestEnvAll.yml (test environments)
* [how to modify test cases](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Design/TestCaseFiles.DesignNote.md)
1. Test case scripts
* some cases are implemented by specified script. those scripts are put in this folder.
## Modify test cases
1. check if the "SDK" of the test case only contain the current SDK
* if Yes, then just modify the test case behavior
* if No:
1. then remove current SDK name from "SDK" of the test case
2. Add a new test case, and set "SDK" only support current SDK name
2. use [auto_test_script](https://gitlab.espressif.cn:6688/yinling/auto_test_script) to load the modified case and verify the modification
3. create a merge request and assign to HYL (or add comment @yinling for merging test).
After review it will be merged to SDK and will be The cases will be synced to database in auto_test_script.
## Run test case locally
1. clone auto_test_script (ssh://git@gitlab.espressif.cn:27227/yinling/auto_test_script.git) from gitlab
2. create test environment:
1. search test case (search test case ID in components/test/TestCaseAll.yml, get the "test environment" value
2. goto [test environment list](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Documents/TestEnvList.md), find the link and goto the environment detail page
3. create test environment according to figure and description
4. [config test environment](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Design/TestEnvConfig.DesignNote.md). All parameters in table "Parameters require config before use" MUST be configured.
3. run test cases with [CIRunner.py](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Design/RunnerConfigs.DesignNote.md)
## exclude known issues for CI
the test cases listed in file "KnownIssues" will be excluded by CI when calculating results
Editing KnownIssues file is very simple, one single line for the ID for each case.
```
TCPIP_TCP_0101
TCPIP_TCP_0201
...
```

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@ -0,0 +1,5 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [SYS_MISC_0101, SYS_MISC_0201]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_DHCP_0302, TCPIP_DHCP_0302, TCPIP_DHCP_0301, TCPIP_TCP_0403, TCPIP_TCP_0402,
TCPIP_TCP_0401, TCPIP_TCP_0407, TCPIP_TCP_0406, ^TCPIP_TCP_0411, TCPIP_TCP_0404,
TCPIP_TCP_0408, TCPIP_TCP_0110, TCPIP_TCP_0115, TCPIP_IP_0101, TCPIP_IP_0102,
^TCPIP_IGMP_0102, ^TCPIP_IGMP_0101, ^TCPIP_IGMP_0104, TCPIP_IGMP_0104, TCPIP_IGMP_0103,
TCPIP_IGMP_0102, TCPIP_IGMP_0101, TCPIP_UDP_0108, TCPIP_UDP_0106, TCPIP_UDP_0107,
TCPIP_UDP_0105, TCPIP_UDP_0101, TCPIP_IGMP_0204, TCPIP_IGMP_0201, TCPIP_IGMP_0202]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [TCPIP_IGMP_0203, ^TCPIP_TCP_0403, ^TCPIP_TCP_0408, TCPIP_UDP_0201, TCPIP_UDP_0202,
^TCPIP_DHCP_0301, ^TCPIP_TCP_0101, ^TCPIP_TCP_0103, ^TCPIP_TCP_0105, ^TCPIP_TCP_0104,
^TCPIP_TCP_0107, ^TCPIP_TCP_0106, ^TCPIP_DHCP_0210, ^TCPIP_DHCP_0211, ^TCPIP_TCP_0404,
TCPIP_TCP_0212, TCPIP_TCP_0210, ^TCPIP_TCP_0406, ^TCPIP_TCP_0407, ^TCPIP_TCP_0401,
^TCPIP_TCP_0210, ^TCPIP_TCP_0212, TCPIP_DHCP_0211, TCPIP_DHCP_0210, TCPIP_DHCP_0101,
TCPIP_DHCP_0103, TCPIP_DHCP_0102, TCPIP_DHCP_0206, TCPIP_DHCP_0207, ^TCPIP_IP_0102]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_UDP_0105, ^TCPIP_UDP_0107, ^TCPIP_UDP_0106, ^TCPIP_UDP_0101, TCPIP_TCP_0203,
TCPIP_TCP_0202, ^TCPIP_UDP_0108, ^TCPIP_IGMP_0201, ^TCPIP_IGMP_0203, ^TCPIP_IGMP_0202,
^TCPIP_IGMP_0103, TCPIP_UDP_0114, TCPIP_UDP_0113, TCPIP_UDP_0112, TCPIP_DHCP_0205,
TCPIP_DHCP_0202, TCPIP_DHCP_0203, ^TCPIP_TCP_0102, TCPIP_TCP_0106, TCPIP_TCP_0107,
TCPIP_TCP_0104, TCPIP_TCP_0105, TCPIP_TCP_0102, TCPIP_TCP_0103, TCPIP_TCP_0101,
^TCPIP_TCP_0116, ^TCPIP_TCP_0114, ^TCPIP_TCP_0115, ^TCPIP_TCP_0112, ^TCPIP_TCP_0113]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_TCP_0110, ^TCPIP_TCP_0111, TCPIP_DHCP_0209, ^TCPIP_DHCP_0209, ^TCPIP_DHCP_0207,
^TCPIP_DHCP_0206, ^TCPIP_DHCP_0205, ^TCPIP_DHCP_0204, ^TCPIP_DHCP_0203, ^TCPIP_DHCP_0202,
^TCPIP_DHCP_0201, TCPIP_TCP_0204, TCPIP_TCP_0207, TCPIP_TCP_0206, TCPIP_TCP_0201,
^TCPIP_DHCP_0101, ^TCPIP_DHCP_0102, ^TCPIP_DHCP_0103, ^TCPIP_DHCP_0208, TCPIP_TCP_0208,
^TCPIP_TCP_0202, ^TCPIP_TCP_0203, TCPIP_DHCP_0204, ^TCPIP_TCP_0201, ^TCPIP_TCP_0206,
^TCPIP_TCP_0207, ^TCPIP_TCP_0204, TCPIP_DHCP_0201, ^TCPIP_TCP_0208, TCPIP_DHCP_0208]

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@ -0,0 +1,8 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_IGMP_0204, ^TCPIP_TCP_0412, TCPIP_TCP_0411, TCPIP_TCP_0412, ^TCPIP_UDP_0112,
^TCPIP_UDP_0113, ^TCPIP_UDP_0114, ^TCPIP_UDP_0202, ^TCPIP_UDP_0201, ^TCPIP_IP_0101,
^TCPIP_TCP_0402, TCPIP_TCP_0114, TCPIP_TCP_0116, TCPIP_TCP_0111, TCPIP_TCP_0113,
TCPIP_TCP_0112]

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@ -0,0 +1,5 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [TCPIP_TCP_0405, ^TCPIP_TCP_0405]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [TCPIP_ICMP_0101, TCPIP_ICMP_0101, TCPIP_ICMP_0101, TCPIP_ICMP_0101, TCPIP_ICMP_0101,
TCPIP_DNS_0102, TCPIP_DNS_0102, TCPIP_DNS_0102, TCPIP_DNS_0102, TCPIP_DNS_0102,
TCPIP_DNS_0101, TCPIP_DNS_0101, TCPIP_DNS_0101, TCPIP_DNS_0101, TCPIP_DNS_0101,
^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101,
TCPIP_UDP_0109, TCPIP_UDP_0109, TCPIP_UDP_0109, TCPIP_UDP_0109, TCPIP_UDP_0109,
TCPIP_UDP_0104, TCPIP_UDP_0104, TCPIP_UDP_0104, TCPIP_UDP_0104, TCPIP_UDP_0104]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [TCPIP_UDP_0102, TCPIP_UDP_0102, TCPIP_UDP_0102, TCPIP_UDP_0102, TCPIP_UDP_0102,
TCPIP_UDP_0103, TCPIP_UDP_0103, TCPIP_UDP_0103, TCPIP_UDP_0103, TCPIP_UDP_0103,
^TCPIP_UDP_0307, ^TCPIP_UDP_0307, ^TCPIP_UDP_0307, ^TCPIP_UDP_0307, ^TCPIP_UDP_0307,
^TCPIP_UDP_0306, ^TCPIP_UDP_0306, ^TCPIP_UDP_0306, ^TCPIP_UDP_0306, ^TCPIP_UDP_0306,
^TCPIP_UDP_0305, ^TCPIP_UDP_0305, ^TCPIP_UDP_0305, ^TCPIP_UDP_0305, ^TCPIP_UDP_0305,
^TCPIP_UDP_0304, ^TCPIP_UDP_0304, ^TCPIP_UDP_0304, ^TCPIP_UDP_0304, ^TCPIP_UDP_0304]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [^TCPIP_UDP_0303, ^TCPIP_UDP_0303, ^TCPIP_UDP_0303, ^TCPIP_UDP_0303, ^TCPIP_UDP_0303,
^TCPIP_UDP_0302, ^TCPIP_UDP_0302, ^TCPIP_UDP_0302, ^TCPIP_UDP_0302, ^TCPIP_UDP_0302,
^TCPIP_UDP_0301, ^TCPIP_UDP_0301, ^TCPIP_UDP_0301, ^TCPIP_UDP_0301, ^TCPIP_UDP_0301,
^TCPIP_UDP_0104, ^TCPIP_UDP_0104, ^TCPIP_UDP_0104, ^TCPIP_UDP_0104, ^TCPIP_UDP_0104,
^TCPIP_UDP_0103, ^TCPIP_UDP_0103, ^TCPIP_UDP_0103, ^TCPIP_UDP_0103, ^TCPIP_UDP_0103,
^TCPIP_UDP_0102, ^TCPIP_UDP_0102, ^TCPIP_UDP_0102, ^TCPIP_UDP_0102, ^TCPIP_UDP_0102]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [TCPIP_UDP_0111, TCPIP_UDP_0111, TCPIP_UDP_0111, TCPIP_UDP_0111, TCPIP_UDP_0111,
TCPIP_UDP_0110, TCPIP_UDP_0110, TCPIP_UDP_0110, TCPIP_UDP_0110, TCPIP_UDP_0110,
^TCPIP_DNS_0101, ^TCPIP_DNS_0101, ^TCPIP_DNS_0101, ^TCPIP_DNS_0101, ^TCPIP_DNS_0101,
^TCPIP_DNS_0103, ^TCPIP_DNS_0103, ^TCPIP_DNS_0103, ^TCPIP_DNS_0103, ^TCPIP_DNS_0103,
^TCPIP_DNS_0102, ^TCPIP_DNS_0102, ^TCPIP_DNS_0102, ^TCPIP_DNS_0102, ^TCPIP_DNS_0102,
TCPIP_UDP_0304, TCPIP_UDP_0304, TCPIP_UDP_0304, TCPIP_UDP_0304, TCPIP_UDP_0304]

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@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [TCPIP_UDP_0305, TCPIP_UDP_0305, TCPIP_UDP_0305, TCPIP_UDP_0305, TCPIP_UDP_0305,
TCPIP_UDP_0306, TCPIP_UDP_0306, TCPIP_UDP_0306, TCPIP_UDP_0306, TCPIP_UDP_0306,
TCPIP_UDP_0307, TCPIP_UDP_0307, TCPIP_UDP_0307, TCPIP_UDP_0307, TCPIP_UDP_0307,
TCPIP_UDP_0301, TCPIP_UDP_0301, TCPIP_UDP_0301, TCPIP_UDP_0301, TCPIP_UDP_0301,
TCPIP_UDP_0302, TCPIP_UDP_0302, TCPIP_UDP_0302, TCPIP_UDP_0302, TCPIP_UDP_0302,
TCPIP_UDP_0303, TCPIP_UDP_0303, TCPIP_UDP_0303, TCPIP_UDP_0303, TCPIP_UDP_0303]

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@ -0,0 +1,6 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [TCPIP_DNS_0103, TCPIP_DNS_0103, TCPIP_DNS_0103, TCPIP_DNS_0103, TCPIP_DNS_0103,
^TCPIP_UDP_0110, ^TCPIP_UDP_0110, ^TCPIP_UDP_0110, ^TCPIP_UDP_0110, ^TCPIP_UDP_0110]

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Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^WIFI_CONN_0601, ^WIFI_ADDR_0101, WIFI_SCAN_0103, WIFI_SCAN_0102, WIFI_SCAN_0101,
WIFI_SCAN_0105, WIFI_SCAN_0104, ^WIFI_CONN_0103, WIFI_CONN_0201, WIFI_CONN_0904,
^WIFI_SCAN_0102, ^WIFI_SCAN_0103, ^WIFI_SCAN_0104, ^WIFI_SCAN_0105, WIFI_CONN_0401,
WIFI_ADDR_0101, WIFI_ADDR_0102, WIFI_CONN_0301, ^WIFI_CONN_0801, ^WIFI_CONN_0301,
WIFI_CONN_0501, WIFI_CONN_0502, ^WIFI_CONN_0401, WIFI_MODE_0101, WIFI_MODE_0103,
WIFI_MODE_0102, ^WIFI_CONN_0904, ^WIFI_CONN_0901, WIFI_CONN_0601, ^WIFI_CONN_0201]

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Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^WIFI_ADDR_0102, WIFI_CONN_0901, WIFI_CONN_0801, ^WIFI_CONN_0104, WIFI_CONN_0104,
WIFI_CONN_0101, WIFI_CONN_0102, WIFI_CONN_0103, ^WIFI_SCAN_0101, ^WIFI_CONN_0101,
^WIFI_CONN_0502, ^WIFI_CONN_0501]

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Config: {execute count: 1, execute order: in order}
DUT: [SSC3, SSC2, SSC1]
Filter:
- Add:
ID: [WIFI_PHY_0502, WIFI_PHY_0503, WIFI_PHY_0501, WIFI_PHY_0506, WIFI_PHY_0505,
WIFI_PHY_0504]

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Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [^WIFI_CONN_0902, WIFI_CONN_0902]

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Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [^WIFI_CONN_0903, WIFI_CONN_0903]

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Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [WIFI_SCAN_0301, WIFI_SCAN_0303, WIFI_SCAN_0304, WIFI_SCAN_0302, WIFI_SCAN_0201,
WIFI_PHY_0403, WIFI_PHY_0402, WIFI_PHY_0401, WIFI_PHY_0407, WIFI_PHY_0406, WIFI_PHY_0405,
WIFI_PHY_0404, WIFI_PHY_0408]

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# NOT SUPPORT
# ICMP send Ping not supported
TCPIP_ICMP_0101
^TCPIP_ICMP_0101
# IGMP cases are not supported for now
TCPIP_IGMP_0101
TCPIP_IGMP_0102
TCPIP_IGMP_0103
TCPIP_IGMP_0104
TCPIP_IGMP_0201
TCPIP_IGMP_0202
TCPIP_IGMP_0203
TCPIP_IGMP_0204
^TCPIP_IGMP_0101
^TCPIP_IGMP_0102
^TCPIP_IGMP_0103
^TCPIP_IGMP_0104
^TCPIP_IGMP_0201
^TCPIP_IGMP_0202
^TCPIP_IGMP_0203
^TCPIP_IGMP_0204
# BUG
# auth change event
WIFI_CONN_0801
# disconnect reason
WIFI_CONN_0904
^WIFI_CONN_0904
WIFI_CONN_0901
^WIFI_CONN_0901
# Wifi connect issue
WIFI_CONN_0104
^WIFI_CONN_0104
# DHCP issues
^TCPIP_DHCP_0301
TCPIP_DHCP_0301
TCPIP_DHCP_0101
TCPIP_DHCP_0207
^TCPIP_DHCP_0207
TCPIP_DHCP_0208
^TCPIP_DHCP_0208
# TCP issue
TCPIP_TCP_0402
^TCPIP_TCP_0406
^TCPIP_TCP_0401
TCPIP_TCP_0210
^TCPIP_TCP_0210
TCPIP_TCP_0103
# UDP issue
TCPIP_UDP_0103
^TCPIP_UDP_0103
TCPIP_UDP_0110
^TCPIP_UDP_0110

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test environment:
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_1,
test environment detail: 'PC has 2 wired NIC connected to AP.
PC has 1 WiFi NIC.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_2,
test environment detail: 'PC has 1 WiFi NIC.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_3,
test environment detail: 'Able to access WAN after connect to AP.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_ADC,
test environment detail: 'PC has 1 wired NIC connected to AP.
Analog input connect to AT1 TOUT.
Multimeter connect to input, able to measure input voltage.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_APC1,
test environment detail: "PC has 1 wired NIC connected to AP.\nPC has 1 wired NIC\
\ connected to APC (static IP within the same subnet with APC). \nAPC control\
\ AP power supply. \nPC has 1 WiFi NIC. \n1 AT target connect with PC by UART\
\ (AT and LOG port).", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_APC2,
test environment detail: "Able to access WAN after connect to AP.\nPC has 1 wired\
\ NIC connected to APC (static IP within the same subnet with APC). \nAPC control\
\ AP power supply.\nPC has 1 WiFi NIC.\n1 AT target connect with PC by UART (AT\
\ and LOG port).", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_HighSpeedUART,
test environment detail: 'PC has 2 wired NIC connected to AP.
PC has 1 WiFi NIC.
1 AT target connect with PC by high speed UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_SmartConfigIOT,
test environment detail: '1 AT target connect with PC by UART (AT and LOG port).
PC has 1 wired NIC connect to Common AP.
Several AP are placed near AT target.
Several smart phone installed test APK are placed near AT target.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_1,
test environment detail: 'PC has 1 wired NIC connected to AP.
PC has 1 WiFi NIC.
2 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_JAP,
test environment detail: "Several AP are placed near AT target.\nPC has 1 wired\
\ NIC connected to APC (static IP within the same subnet with APC).\nAPC control\
\ power supply for all APs. \n2 AT target connect with PC by UART (AT and LOG\
\ port).", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_Sleep,
test environment detail: 'AP support DTIM placed with AT target.
2 AT target connect with PC by UART (AT and LOG port).
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of AT1.
AT1''s light sleep wakeup pin and wakeup indication connect with AT2''s GPIO.',
test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_SmartConfig,
test environment detail: '2 AT target connect with PC by UART (AT and LOG port).
PC has 1 WiFi NIC.
One HT20 AP and One HT40 AP are placed near target.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: IR_T2_1, test environment detail: '[TBD] 本测试为非自动测试, 红外能够做到数据收发吻合即可通过', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: NVS_T1_1,
test environment detail: '1 NVS target connect with PC by UART.
1 SSC target connect with PC by UART.
SSC2 GPIO connect to NVS1 power control pin.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: SSC_1, additional param list: '',
basic param list: '', script path: EnvBase.py, tag: PWM_T1_1, test environment detail: "[TBD]\
\ 1. PWM OS SDK 以及 Non-OS SDK的测试建议分开进行, 放在不同的文件夹, 防止文件命名混淆\n2. 分析CSV文件的Python脚本只能分析单个channel\
\ \n3. 如果Init脚本打印\"Network Error\" 检查TCP Server是不是正常发送data", test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_1,
test environment detail: 'PC has 2 wired NIC connected to AP.
PC has 1 WiFi NIC.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_2,
test environment detail: 'Able to access WAN after connect to AP.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_8089,
test environment detail: 'PC has 1 wired NIC connected to AP.
1 8089 tablet able to run iperf test placed near SSC1.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_ADC,
test environment detail: 'PC has 1 wired NIC connected to AP.
Analog input connect to SSC1 TOUT.
Multimeter connect to input, able to measure input voltage.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_APC,
test environment detail: "PC has 1 wired NIC connected to AP.\nPC has 1 wired NIC\
\ connected to APC (static IP within the same subnet with APC). \nAPC control\
\ AP power supply. \nPC has 1 WiFi NIC. \n1 SSC target connect with PC by UART.",
test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_Enterprise,
test environment detail: "AP use WPA2-Etherprise is placed near SSC1. \n1 SSC target\
\ connect with PC by UART.", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_IOT1,
test environment detail: 'PC has 1 WiFi NIC.
1 SSC target connect with PC by UART.
AP todo IOT test are placed near SSC1.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T1_InitData,
test environment detail: '2 SSC target connect with PC by UART.
SSC1 use 40M crystal oscillator.
SSC2 use normal 26M crystal oscillator.
SSC2 GPIO connect to SSC1 power control pin.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_ShieldBox,
test environment detail: 'refer to figure.
All APs and APC should be set to the same IP subnet.
PC wired NIC should set static IP address within the same subnet with AP.
Must use onboard wired NIC.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_TempBox,
test environment detail: '1 SSC target connect with PC by UART.
Put SSC target to temperature box.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: SSC_1, additional param list: '',
basic param list: '', script path: EnvBase.py, tag: SSC_T1_Timer, test environment detail: '[TBD]
通过串口工具调节Timer, 将GPIO_13端口连接到逻辑分析仪', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_VDD33,
test environment detail: '1 SSC target connect with PC by UART.
Multimeter connect to VDD33, able to measure voltage.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_WEP,
test environment detail: '1 SSC target connect with PC by UART.
One WEP share key AP placed near SSC1.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_1,
test environment detail: 'PC has 1 wired NIC connected to AP.
PC has 1 WiFi NIC.
2 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: SSC_T2_GPIO1, test environment detail: '[TBD] 2个ESP_8266通过UART连到PC, ESP_8266的
GPIO_6相连', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: SSC_T2_GPIO2, test environment detail: '[TBD] 1. 2个ESP_8266通过UART连到PC, ESP_8266的
GPIO_15通过面包板相连
2. 可借助面包板, 将GPIO_15, 以及中断函数被打开的8266板的GPIO_2 相连', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: SSC_T2_GPIO3, test environment detail: '[TBD] 2个ESP_8266通过UART连到PC, ESP_8266之间需要测试的Target_GPIO相连',
test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_PhyMode,
test environment detail: '2 SSC target connect with PC by UART.
PC has one WiFi NIC support capture wlan packet using libpcap.
Set 4 AP with phy mode 11b, 11g, 11n HT20, 11n HT40.
Put 4 APs near SSC targets.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_ShieldBox,
test environment detail: '2 SSC target connect with PC by UART.
Put them to Shield box.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_Sleep1,
test environment detail: 'AP support DTIM placed with AT target.
2 SSC target connect with PC by UART.
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of SSC1.
SSC1''s light sleep wakeup pin and wakeup indication connect with AT2''s GPIO.
SSC1''s XPD connect with RSTB.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_Sleep2,
test environment detail: 'AP support DTIM placed with AT target.
2 SSC target connect with PC by UART.
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of SSC1.
SSC1''s RSTB pin connect with AT2''s GPIO.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_SmartConfig,
test environment detail: '2 SSC target connect with PC by UART.
PC has 1 WiFi NIC.
One HT20 AP and One HT40 AP are placed near target.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 3.0, script path: EnvBase.py, tag: SSC_T3_PhyMode,
test environment detail: '3 SSC target connect with PC by UART.
PC has one WiFi NIC support capture wlan packet using libpcap.
Set 4 AP with (HT20, channel1), (HT20, channel2), (HT40, channel1), (HT40, channel2).
Put 4 APs near SSC targets.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 5.0, script path: EnvBase.py, tag: SSC_T5_1,
test environment detail: 5 SSC target connect with PC by UART., test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T6_1,
test environment detail: 'PC has 1 wired NIC connected to AP.
PC has 1 WiFi NIC.
6 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: TempSensor_T1_1,
test environment detail: 'Tempeture sensor target connect with PC by UART.
AP support DTIM placed with AT target.
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of TempSensor1.
PC has 1 wired NIC connected to switch.
APC, AP also connect with swtich.
All devices connected with switch use the same IP subnet.
APC control AP power supply.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: SSC_1, additional param list: '',
basic param list: '', script path: EnvBase.py, tag: UART_T1_1, test environment detail: '[TBD]
将ESP_8266通过UART连到PC', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: UART_T1_2, test environment detail: '[TBD] ESP_8266通过UART_0通过USB, UART_1 TXD
通过 TTLcable 连到PC', test script: EnvBase}
- {PC OS: linux, Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: WebServer_T1_1,
test environment detail: 'Web Server target connect with PC by UART.
PC has 1 wired NIC connected to switch.
APC, AP also connect with swtich.
All devices connected with switch use same IP subnet.
APC control AP power supply.', test script: EnvBase}
- {PC OS: linux, Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: WebServer_T1_2,
test environment detail: 'Web Server target connect with PC by UART.
4 PC with WiFi NIC placed near WebServer1.', test script: EnvBase}

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test cases: []

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test environment:
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_1,
test environment detail: 'PC has 2 wired NIC connected to AP.
PC has 1 WiFi NIC.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_2,
test environment detail: 'PC has 1 WiFi NIC.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_3,
test environment detail: 'Able to access WAN after connect to AP.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_ADC,
test environment detail: 'PC has 1 wired NIC connected to AP.
Analog input connect to AT1 TOUT.
Multimeter connect to input, able to measure input voltage.
1 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_APC1,
test environment detail: "PC has 1 wired NIC connected to AP.\nPC has 1 wired NIC\
\ connected to APC (static IP within the same subnet with APC). \nAPC control\
\ AP power supply. \nPC has 1 WiFi NIC. \n1 AT target connect with PC by UART\
\ (AT and LOG port).", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_APC2,
test environment detail: "Able to access WAN after connect to AP.\nPC has 1 wired\
\ NIC connected to APC (static IP within the same subnet with APC). \nAPC control\
\ AP power supply.\nPC has 1 WiFi NIC.\n1 AT target connect with PC by UART (AT\
\ and LOG port).", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_HighSpeedUART,
test environment detail: 'PC has 2 wired NIC connected to AP.
PC has 1 WiFi NIC.
1 AT target connect with PC by high speed UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: AT_T1_SmartConfigIOT,
test environment detail: '1 AT target connect with PC by UART (AT and LOG port).
PC has 1 wired NIC connect to Common AP.
Several AP are placed near AT target.
Several smart phone installed test APK are placed near AT target.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_1,
test environment detail: 'PC has 1 wired NIC connected to AP.
PC has 1 WiFi NIC.
2 AT target connect with PC by UART (AT and LOG port).', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_JAP,
test environment detail: "Several AP are placed near AT target.\nPC has 1 wired\
\ NIC connected to APC (static IP within the same subnet with APC).\nAPC control\
\ power supply for all APs. \n2 AT target connect with PC by UART (AT and LOG\
\ port).", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_Sleep,
test environment detail: 'AP support DTIM placed with AT target.
2 AT target connect with PC by UART (AT and LOG port).
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of AT1.
AT1''s light sleep wakeup pin and wakeup indication connect with AT2''s GPIO.',
test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: AT_T2_SmartConfig,
test environment detail: '2 AT target connect with PC by UART (AT and LOG port).
PC has 1 WiFi NIC.
One HT20 AP and One HT40 AP are placed near target.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: IR_T2_1, test environment detail: '[TBD] 本测试为非自动测试, 红外能够做到数据收发吻合即可通过', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: NVS_T1_1,
test environment detail: '1 NVS target connect with PC by UART.
1 SSC target connect with PC by UART.
SSC2 GPIO connect to NVS1 power control pin.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: SSC_1, additional param list: '',
basic param list: '', script path: EnvBase.py, tag: PWM_T1_1, test environment detail: "[TBD]\
\ 1. PWM OS SDK 以及 Non-OS SDK的测试建议分开进行, 放在不同的文件夹, 防止文件命名混淆\n2. 分析CSV文件的Python脚本只能分析单个channel\
\ \n3. 如果Init脚本打印\"Network Error\" 检查TCP Server是不是正常发送data", test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_1,
test environment detail: 'PC has 2 wired NIC connected to AP.
PC has 1 WiFi NIC.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_2,
test environment detail: 'Able to access WAN after connect to AP.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_8089,
test environment detail: 'PC has 1 wired NIC connected to AP.
1 8089 tablet able to run iperf test placed near SSC1.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_ADC,
test environment detail: 'PC has 1 wired NIC connected to AP.
Analog input connect to SSC1 TOUT.
Multimeter connect to input, able to measure input voltage.
1 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_APC,
test environment detail: "PC has 1 wired NIC connected to AP.\nPC has 1 wired NIC\
\ connected to APC (static IP within the same subnet with APC). \nAPC control\
\ AP power supply. \nPC has 1 WiFi NIC. \n1 SSC target connect with PC by UART.",
test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_Enterprise,
test environment detail: "AP use WPA2-Etherprise is placed near SSC1. \n1 SSC target\
\ connect with PC by UART.", test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_IOT1,
test environment detail: 'PC has 1 WiFi NIC.
1 SSC target connect with PC by UART.
AP todo IOT test are placed near SSC1.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T1_InitData,
test environment detail: '2 SSC target connect with PC by UART.
SSC1 use 40M crystal oscillator.
SSC2 use normal 26M crystal oscillator.
SSC2 GPIO connect to SSC1 power control pin.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_ShieldBox,
test environment detail: 'refer to figure.
All APs and APC should be set to the same IP subnet.
PC wired NIC should set static IP address within the same subnet with AP.
Must use onboard wired NIC.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_TempBox,
test environment detail: '1 SSC target connect with PC by UART.
Put SSC target to temperature box.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: SSC_1, additional param list: '',
basic param list: '', script path: EnvBase.py, tag: SSC_T1_Timer, test environment detail: '[TBD]
通过串口工具调节Timer, 将GPIO_13端口连接到逻辑分析仪', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_VDD33,
test environment detail: '1 SSC target connect with PC by UART.
Multimeter connect to VDD33, able to measure voltage.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T1_WEP,
test environment detail: '1 SSC target connect with PC by UART.
One WEP share key AP placed near SSC1.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_1,
test environment detail: 'PC has 1 wired NIC connected to AP.
PC has 1 WiFi NIC.
2 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: SSC_T2_GPIO1, test environment detail: '[TBD] 2个ESP_8266通过UART连到PC, ESP_8266的
GPIO_6相连', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: SSC_T2_GPIO2, test environment detail: '[TBD] 1. 2个ESP_8266通过UART连到PC, ESP_8266的
GPIO_15通过面包板相连
2. 可借助面包板, 将GPIO_15, 以及中断函数被打开的8266板的GPIO_2 相连', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: SSC_T2_GPIO3, test environment detail: '[TBD] 2个ESP_8266通过UART连到PC, ESP_8266之间需要测试的Target_GPIO相连',
test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_PhyMode,
test environment detail: '2 SSC target connect with PC by UART.
PC has one WiFi NIC support capture wlan packet using libpcap.
Set 4 AP with phy mode 11b, 11g, 11n HT20, 11n HT40.
Put 4 APs near SSC targets.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_ShieldBox,
test environment detail: '2 SSC target connect with PC by UART.
Put them to Shield box.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_Sleep1,
test environment detail: 'AP support DTIM placed with AT target.
2 SSC target connect with PC by UART.
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of SSC1.
SSC1''s light sleep wakeup pin and wakeup indication connect with AT2''s GPIO.
SSC1''s XPD connect with RSTB.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_Sleep2,
test environment detail: 'AP support DTIM placed with AT target.
2 SSC target connect with PC by UART.
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of SSC1.
SSC1''s RSTB pin connect with AT2''s GPIO.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 2.0, script path: EnvBase.py, tag: SSC_T2_SmartConfig,
test environment detail: '2 SSC target connect with PC by UART.
PC has 1 WiFi NIC.
One HT20 AP and One HT40 AP are placed near target.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 3.0, script path: EnvBase.py, tag: SSC_T3_PhyMode,
test environment detail: '3 SSC target connect with PC by UART.
PC has one WiFi NIC support capture wlan packet using libpcap.
Set 4 AP with (HT20, channel1), (HT20, channel2), (HT40, channel1), (HT40, channel2).
Put 4 APs near SSC targets.', test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 5.0, script path: EnvBase.py, tag: SSC_T5_1,
test environment detail: 5 SSC target connect with PC by UART., test script: EnvBase}
- {PC OS: '', Special: N, Target Count: 1.0, script path: EnvBase.py, tag: SSC_T6_1,
test environment detail: 'PC has 1 wired NIC connected to AP.
PC has 1 WiFi NIC.
6 SSC target connect with PC by UART.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: TempSensor_T1_1,
test environment detail: 'Tempeture sensor target connect with PC by UART.
AP support DTIM placed with AT target.
Multimeter connect with PC via GPIB.
Series multimeter between GND and VCC of TempSensor1.
PC has 1 wired NIC connected to switch.
APC, AP also connect with swtich.
All devices connected with switch use the same IP subnet.
APC control AP power supply.', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: SSC_1, additional param list: '',
basic param list: '', script path: EnvBase.py, tag: UART_T1_1, test environment detail: '[TBD]
将ESP_8266通过UART连到PC', test script: EnvBase}
- {PC OS: '', Special: Y, Target Count: 1.0, UART ports: 'SSC1
SSC2', additional param list: '', basic param list: '', script path: EnvBase.py,
tag: UART_T1_2, test environment detail: '[TBD] ESP_8266通过UART_0通过USB, UART_1 TXD
通过 TTLcable 连到PC', test script: EnvBase}
- {PC OS: linux, Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: WebServer_T1_1,
test environment detail: 'Web Server target connect with PC by UART.
PC has 1 wired NIC connected to switch.
APC, AP also connect with swtich.
All devices connected with switch use same IP subnet.
APC control AP power supply.', test script: EnvBase}
- {PC OS: linux, Special: Y, Target Count: 1.0, script path: EnvBase.py, tag: WebServer_T1_2,
test environment detail: 'Web Server target connect with PC by UART.
4 PC with WiFi NIC placed near WebServer1.', test script: EnvBase}