docs(usb/host): Update maintainer docs for ESP32-P4

components/soc/esp32p4/include/soc/usb_dwc_cfg.h

@@ -17,7 +17,7 @@ Configuration Set ID: 11
 /* 3.1 Basic Config Parameters */
 #define OTG_MODE                0
 #define OTG_ARCHITECTURE        2
-#define OTG_SINGLE_POINT        0
+#define OTG_SINGLE_POINT        1
 #define OTG_ENABLE_LPM          0
 #define OTG_EN_DED_TX_FIFO      1
 #define OTG_EN_DESC_DMA         1

docs/docs_not_updated/esp32p4.txt

@@ -11,11 +11,6 @@ api-guides/wifi-security.rst
 api-reference/peripherals/adc_continuous.rst
 api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/usb_host.rst
-api-reference/peripherals/usb_host/usb_host_notes_arch.rst
-api-reference/peripherals/usb_host/usb_host_notes_index.rst
-api-reference/peripherals/usb_host/usb_host_notes_dwc_otg.rst
-api-reference/peripherals/usb_host/usb_host_notes_design.rst
-api-reference/peripherals/usb_host/usb_host_notes_usbh.rst
 api-reference/peripherals/usb_device.rst
 api-reference/peripherals/touch_element.rst
 api-reference/peripherals/touch_pad.rst

docs/en/api-reference/peripherals/usb_host/usb_host_notes_arch.rst

@@ -37,7 +37,7 @@ The layers of the Host Stack are described in the following table. The layers ar
       - ``usb_host.h``, ``usb_host.c``
       - The USB Host Library layer is the lowest public API layer of the Host Stack and presents the concept of USB Host Clients. The abstraction of clients allows for multiple class drivers to coexist simultaneously (where each class roughly maps to a single client) and also acts as a mechanism for division of labor (where each client is responsible for its own processing and event handling).
     * - Host Class Drivers
-      - See the `ESP-IDF Extra Components repository <https://github.com/espressif/idf-extra-components>`_ or the USB Host examples in ESP-IDF (via :example:`peripherals/usb/host`).
+      - See the `ESP-USB repository <https://github.com/espressif/esp-usb>`_ or the USB Host examples in ESP-IDF (via :example:`peripherals/usb/host`).
       - The Host Class Drivers implement the host side of a particular device class (e.g., CDC, MSC, HID). The exposed API is specific to each class driver.
 
 Layer Dependencies

docs/en/api-reference/peripherals/usb_host/usb_host_notes_dwc_otg.rst

@@ -89,26 +89,51 @@ Hardware Configuration
 
 The DWC_OTG IP is configurable. The notable Host related configurations of the {IDF_TARGET_NAME}'s DWC_OTG are listed below:
 
-.. list-table:: {IDF_TARGET_NAME}'s DWC_OTG Configuration
-    :widths: 70 30
-    :header-rows: 1
+.. only:: esp32p4
 
-    * - Description
-      - Configuration
-    * - Host and Device Mode support with OTG
-      - ``OTG_MODE = 0``
-    * - Full Speed (FS) and Low Speed (LS) support
-      - ``OTG_FSPHY_INTERFACE = 1``, ``OTG_HSPHY_INTERFACE = 0``
-    * - Internal DMA controller with Scatter/Gather DMA
-      - ``OTG_ARCHITECTURE = 2``, ``OTG_EN_DESC_DMA = 1``
-    * - FS Hubs are supported but HS Hub are not (i.e., split transfers not supported)
-      - ``OTG_SINGLE_POINT = 0``
-    * - 8 Host Mode channels
-      - ``OTG_NUM_HOST_CHAN = 8``
-    * - All transfer types supported, including ISOC and INTR OUT transfers
-      - ``OTG_EN_PERIO_HOST = 1``
-    * - Dynamically sized Data FIFO of 1024 bytes (256 lines)
-      - ``OTG_DFIFO_DYNAMIC = 1``, ``OTG_DFIFO_DEPTH = 256``
+    .. list-table:: {IDF_TARGET_NAME}'s DWC_OTG Configuration
+        :widths: 70 30
+        :header-rows: 1
+
+        * - Description
+          - Configuration
+        * - Host and Device Mode support with OTG
+          - ``OTG_MODE = 0``
+        * - High Speed (HS), Full Speed (FS) and Low Speed (LS) support
+          - ``OTG_FSPHY_INTERFACE = 2``, ``OTG_HSPHY_INTERFACE = 3``
+        * - Internal DMA controller with Scatter/Gather DMA
+          - ``OTG_ARCHITECTURE = 2``, ``OTG_EN_DESC_DMA = 1``
+        * - Split transfers not supported
+          - ``OTG_SINGLE_POINT = 1``
+        * - 16 Host Mode channels
+          - ``OTG_NUM_HOST_CHAN = 16``
+        * - All transfer types supported, including ISOC and INTR OUT transfers
+          - ``OTG_EN_PERIO_HOST = 1``
+        * - Dynamically sized Data FIFO of 4096 bytes (1024 lines)
+          - ``OTG_DFIFO_DYNAMIC = 1``, ``OTG_DFIFO_DEPTH = 1024``
+        * - Only 4 periodic and 4 non-periodic transactions per microframe
+          - ``OTG_NPERIO_TX_QUEUE_DEPTH = 4``, ``OTG_PERIO_TX_QUEUE_DEPTH = 4``
+
+.. only:: esp32s2 or esp32s3
+
+    .. list-table:: {IDF_TARGET_NAME}'s DWC_OTG Configuration
+        :widths: 70 30
+        :header-rows: 1
+
+        * - Description
+          - Configuration
+        * - Host and Device Mode support with OTG
+          - ``OTG_MODE = 0``
+        * - Full Speed (FS) and Low Speed (LS) support
+          - ``OTG_FSPHY_INTERFACE = 1``, ``OTG_HSPHY_INTERFACE = 0``
+        * - Internal DMA controller with Scatter/Gather DMA
+          - ``OTG_ARCHITECTURE = 2``, ``OTG_EN_DESC_DMA = 1``
+        * - 8 Host Mode channels
+          - ``OTG_NUM_HOST_CHAN = 8``
+        * - All transfer types supported, including ISOC and INTR OUT transfers
+          - ``OTG_EN_PERIO_HOST = 1``
+        * - Dynamically sized Data FIFO of 1024 bytes (256 lines)
+          - ``OTG_DFIFO_DYNAMIC = 1``, ``OTG_DFIFO_DEPTH = 256``
 
 Scatter/Gather DMA Transfer
 ---------------------------