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esp_flash_api fixes

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negativekelvin 2021-07-23 02:35:27 -07:00 committed by GitHub
parent 166c30e7b2
commit 8e6700c156
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 16 additions and 10 deletions
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26
components/spi_flash/esp_flash_api.c
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@ -460,6 +460,9 @@ esp_err_t IRAM_ATTR esp_flash_erase_region(esp_flash_t *chip, uint32_t start, ui
// Can only erase multiples of the sector size, starting at sector boundary // Can only erase multiples of the sector size, starting at sector boundary
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
if (len == 0) {
return ESP_OK;
}
err = ESP_OK; err = ESP_OK;
// Check for write protected regions overlapping the erase region // Check for write protected regions overlapping the erase region
@ -522,6 +525,8 @@ esp_err_t IRAM_ATTR esp_flash_erase_region(esp_flash_t *chip, uint32_t start, ui
len_remain -= sector_size; len_remain -= sector_size;
} }
assert(len_remain < len);
if (err != ESP_OK || len_remain == 0) { if (err != ESP_OK || len_remain == 0) {
// On ESP32, the cache re-enable is in the end() function, while flush_cache should // On ESP32, the cache re-enable is in the end() function, while flush_cache should
// happen when the cache is still disabled on ESP32. Break before the end() function and // happen when the cache is still disabled on ESP32. Break before the end() function and
@ -668,14 +673,14 @@ esp_err_t IRAM_ATTR esp_flash_set_protected_region(esp_flash_t *chip, const esp_
esp_err_t IRAM_ATTR esp_flash_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length) esp_err_t IRAM_ATTR esp_flash_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length)
{ {
if (length == 0) {
return ESP_OK;
}
esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip); esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
VERIFY_CHIP_OP(read); VERIFY_CHIP_OP(read);
if (buffer == NULL || address > chip->size || address+length > chip->size) { if (buffer == NULL || address > chip->size || address+length > chip->size) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
if (length == 0) {
return ESP_OK;
}
//when the cache is disabled, only the DRAM can be read, check whether we need to receive in another buffer in DRAM. //when the cache is disabled, only the DRAM can be read, check whether we need to receive in another buffer in DRAM.
bool direct_read = chip->host->driver->supports_direct_read(chip->host, buffer); bool direct_read = chip->host->driver->supports_direct_read(chip->host, buffer);
@ -735,15 +740,15 @@ esp_err_t IRAM_ATTR esp_flash_read(esp_flash_t *chip, void *buffer, uint32_t add
esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length) esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
{ {
if (length == 0) {
return ESP_OK;
}
esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip); esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
VERIFY_CHIP_OP(write); VERIFY_CHIP_OP(write);
CHECK_WRITE_ADDRESS(chip, address, length); CHECK_WRITE_ADDRESS(chip, address, length);
if (buffer == NULL || address > chip->size || address+length > chip->size) { if (buffer == NULL || address > chip->size || address+length > chip->size) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
if (length == 0) {
return ESP_OK;
}
//when the cache is disabled, only the DRAM can be read, check whether we need to copy the data first //when the cache is disabled, only the DRAM can be read, check whether we need to copy the data first
bool direct_write = chip->host->driver->supports_direct_write(chip->host, buffer); bool direct_write = chip->host->driver->supports_direct_write(chip->host, buffer);
@ -786,6 +791,7 @@ esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint3
err = chip->chip_drv->write(chip, write_buf, write_addr, write_len); err = chip->chip_drv->write(chip, write_buf, write_addr, write_len);
len_remain -= write_len; len_remain -= write_len;
assert(len_remain < length);
if (err != ESP_OK || len_remain == 0) { if (err != ESP_OK || len_remain == 0) {
// On ESP32, the cache re-enable is in the end() function, while flush_cache should // On ESP32, the cache re-enable is in the end() function, while flush_cache should
@ -810,10 +816,6 @@ esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint3
esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t address, const void *buffer, uint32_t length) esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t address, const void *buffer, uint32_t length)
{ {
if (length == 0) {
return ESP_OK;
}
esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip); esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
// Flash encryption only support on main flash. // Flash encryption only support on main flash.
if (chip != esp_flash_default_chip) { if (chip != esp_flash_default_chip) {
@ -829,6 +831,10 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
if (length == 0) {
return ESP_OK;
}
if ((length % 16) != 0) { if ((length % 16) != 0) {
ESP_EARLY_LOGE(TAG, "flash encrypted write length must be multiple of 16"); ESP_EARLY_LOGE(TAG, "flash encrypted write length must be multiple of 16");
return ESP_ERR_INVALID_SIZE; return ESP_ERR_INVALID_SIZE;