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esp_flash_api fixes
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166c30e7b2
commit
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@ -460,6 +460,9 @@ esp_err_t IRAM_ATTR esp_flash_erase_region(esp_flash_t *chip, uint32_t start, ui
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// Can only erase multiples of the sector size, starting at sector boundary
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return ESP_ERR_INVALID_ARG;
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}
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if (len == 0) {
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return ESP_OK;
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}
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err = ESP_OK;
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// Check for write protected regions overlapping the erase region
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@ -522,6 +525,8 @@ esp_err_t IRAM_ATTR esp_flash_erase_region(esp_flash_t *chip, uint32_t start, ui
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len_remain -= sector_size;
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}
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assert(len_remain < len);
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if (err != ESP_OK || len_remain == 0) {
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// On ESP32, the cache re-enable is in the end() function, while flush_cache should
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// happen when the cache is still disabled on ESP32. Break before the end() function and
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@ -668,14 +673,14 @@ esp_err_t IRAM_ATTR esp_flash_set_protected_region(esp_flash_t *chip, const esp_
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esp_err_t IRAM_ATTR esp_flash_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length)
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{
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if (length == 0) {
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return ESP_OK;
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}
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esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
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VERIFY_CHIP_OP(read);
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if (buffer == NULL || address > chip->size || address+length > chip->size) {
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return ESP_ERR_INVALID_ARG;
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}
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if (length == 0) {
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return ESP_OK;
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}
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//when the cache is disabled, only the DRAM can be read, check whether we need to receive in another buffer in DRAM.
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bool direct_read = chip->host->driver->supports_direct_read(chip->host, buffer);
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@ -735,15 +740,15 @@ esp_err_t IRAM_ATTR esp_flash_read(esp_flash_t *chip, void *buffer, uint32_t add
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esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
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{
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if (length == 0) {
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return ESP_OK;
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}
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esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
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VERIFY_CHIP_OP(write);
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CHECK_WRITE_ADDRESS(chip, address, length);
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if (buffer == NULL || address > chip->size || address+length > chip->size) {
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return ESP_ERR_INVALID_ARG;
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}
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if (length == 0) {
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return ESP_OK;
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}
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//when the cache is disabled, only the DRAM can be read, check whether we need to copy the data first
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bool direct_write = chip->host->driver->supports_direct_write(chip->host, buffer);
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@ -786,6 +791,7 @@ esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint3
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err = chip->chip_drv->write(chip, write_buf, write_addr, write_len);
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len_remain -= write_len;
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assert(len_remain < length);
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if (err != ESP_OK || len_remain == 0) {
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// On ESP32, the cache re-enable is in the end() function, while flush_cache should
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@ -810,10 +816,6 @@ esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint3
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esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t address, const void *buffer, uint32_t length)
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{
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if (length == 0) {
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return ESP_OK;
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}
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esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
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// Flash encryption only support on main flash.
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if (chip != esp_flash_default_chip) {
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@ -829,6 +831,10 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres
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return ESP_ERR_INVALID_ARG;
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}
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if (length == 0) {
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return ESP_OK;
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}
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if ((length % 16) != 0) {
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ESP_EARLY_LOGE(TAG, "flash encrypted write length must be multiple of 16");
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return ESP_ERR_INVALID_SIZE;
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