From 3d46e6ed1df42bde75ac414a13ed9a9f80383c4a Mon Sep 17 00:00:00 2001 From: zwx Date: Wed, 31 Jul 2024 17:22:06 +0800 Subject: [PATCH] feat(802.15.4): support 802.15.4 on esp32c5 --- components/soc/esp32c5/ieee802154_periph.c | 12 + .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 + .../soc/esp32c5/include/soc/ieee802154_reg.h | 523 ++++++++++++++++++ .../esp32c5/include/soc/ieee802154_struct.h | 462 ++++++++++++++++ .../soc/esp32c5/include/soc/periph_defs.h | 1 + components/soc/esp32c5/include/soc/reg_base.h | 1 + components/soc/esp32c5/include/soc/soc_caps.h | 1 + .../soc/esp32c6/include/soc/ieee802154_reg.h | 1 - components/soc/esp32c6/include/soc/reg_base.h | 1 + .../soc/esp32h2/include/soc/ieee802154_reg.h | 1 - components/soc/esp32h2/include/soc/reg_base.h | 1 + examples/ieee802154/.build-test-rules.yml | 2 +- examples/ieee802154/ieee802154_cli/README.md | 6 +- examples/openthread/.build-test-rules.yml | 17 +- examples/openthread/ot_cli/README.md | 4 +- examples/openthread/ot_rcp/README.md | 4 +- examples/zigbee/.build-test-rules.yml | 8 + 17 files changed, 1035 insertions(+), 14 deletions(-) create mode 100644 components/soc/esp32c5/ieee802154_periph.c create mode 100644 components/soc/esp32c5/include/soc/ieee802154_reg.h create mode 100644 components/soc/esp32c5/include/soc/ieee802154_struct.h diff --git a/components/soc/esp32c5/ieee802154_periph.c b/components/soc/esp32c5/ieee802154_periph.c new file mode 100644 index 0000000000..ec346c396e --- /dev/null +++ b/components/soc/esp32c5/ieee802154_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ieee802154_periph.h" + +const ieee802154_conn_t ieee802154_periph = { + .module = PERIPH_IEEE802154_MODULE, + .irq_id = ETS_ZB_MAC_INTR_SOURCE, +}; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 4ae350b6d2..c8f5ad9974 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -151,6 +151,10 @@ config SOC_SECURE_BOOT_SUPPORTED bool default y +config SOC_IEEE802154_SUPPORTED + bool + default y + config SOC_APM_SUPPORTED bool default y diff --git a/components/soc/esp32c5/include/soc/ieee802154_reg.h b/components/soc/esp32c5/include/soc/ieee802154_reg.h new file mode 100644 index 0000000000..e1a9db3190 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ieee802154_reg.h @@ -0,0 +1,523 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif +// TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready. + +#define IEEE802154_COMMAND_REG (IEEE802154_REG_BASE + 0x0000) +#define IEEE802154_OPCODE 0x000000FF +#define IEEE802154_OPCODE_S 0 + +#define IEEE802154_CTRL_CFG_REG (IEEE802154_REG_BASE + 0x0004) +#define IEEE802154_MAC_INF3_ENABLE (BIT(31)) +#define IEEE802154_MAC_INF3_ENABLE_S 31 +#define IEEE802154_MAC_INF2_ENABLE (BIT(30)) +#define IEEE802154_MAC_INF2_ENABLE_S 30 +#define IEEE802154_MAC_INF1_ENABLE (BIT(29)) +#define IEEE802154_MAC_INF1_ENABLE_S 29 +#define IEEE802154_MAC_INF0_ENABLE (BIT(28)) +#define IEEE802154_MAC_INF0_ENABLE_S 28 +#define IEEE802154_RX_DONE_TRIGGER_IDLE (BIT(27)) +#define IEEE802154_RX_DONE_TRIGGER_IDLE_S 27 +#define IEEE802154_FORCE_RX_ENB (BIT(26)) +#define IEEE802154_FORCE_RX_ENB_S 26 +#define IEEE802154_NO_RSS_TRK_ENB (BIT(25)) +#define IEEE802154_NO_RSS_TRK_ENB_S 25 +#define IEEE802154_BIT_ORDER (BIT(24)) +#define IEEE802154_BIT_ORDER_S 24 +#define IEEE802154_COEX_ARB_DELAY 0x000000FF +#define IEEE802154_COEX_ARB_DELAY_S 16 +#define IEEE802154_FILTER_ENHANCE (BIT(14)) +#define IEEE802154_FILTER_ENHANCE_S 14 +#define IEEE802154_AUTOPEND_ENHANCE (BIT(12)) +#define IEEE802154_AUTOPEND_ENHANCE_S 12 +#define IEEE802154_DIS_FRAME_VERSION_RSV_FILTER (BIT(11)) +#define IEEE802154_DIS_FRAME_VERSION_RSV_FILTER_S 11 +#define IEEE802154_PROMISCUOUS_MODE (BIT(7)) +#define IEEE802154_PROMISCUOUS_MODE_S 7 +#define IEEE802154_PAN_COORDINATOR (BIT(6)) +#define IEEE802154_PAN_COORDINATOR_S 6 +#define IEEE802154_DIS_IFS_CONTROL (BIT(5)) +#define IEEE802154_DIS_IFS_CONTROL_S 5 +#define IEEE802154_HW_AUTO_ACK_RX_EN (BIT(3)) +#define IEEE802154_HW_AUTO_ACK_RX_EN_S 3 +#define HW_ENHANCE_ACK_TX_EN (BIT(1)) +#define HW_ENHANCE_ACK_TX_EN_S 1 +#define IEEE802154_HW_AUTO_ACK_TX_EN (BIT(0)) +#define IEEE802154_HW_AUTO_ACK_TX_EN_S 0 + +#define IEEE802154_INF0_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0008) +#define IEEE802154_MAC_INF0_SHORT_ADDR 0x0000FFFF +#define IEEE802154_MAC_INF0_SHORT_ADDR_S 0 + +#define IEEE802154_INF0_PAN_ID_REG (IEEE802154_REG_BASE + 0x000C) +#define IEEE802154_MAC_INF0_PAN_ID 0x0000FFFF +#define IEEE802154_MAC_INF0_PAN_ID_S 0 + +#define IEEE802154_INF0_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0010) +#define IEEE802154_MAC_INF0_EXTEND_ADDR0 0xFFFFFFFF +#define IEEE802154_MAC_INF0_EXTEND_ADDR0_S 0 + +#define IEEE802154_INF0_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0014) +#define IEEE802154_MAC_INF0_EXTEND_ADDR1 0xFFFFFFFF +#define IEEE802154_MAC_INF0_EXTEND_ADDR1_S 0 + +#define IEEE802154_INF1_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0018) +#define IEEE802154_MAC_INF1_SHORT_ADDR 0x0000FFFF +#define IEEE802154_MAC_INF1_SHORT_ADDR_S 0 + +#define IEEE802154_INF1_PAN_ID_REG (IEEE802154_REG_BASE + 0x001C) +#define IEEE802154_MAC_INF1_PAN_ID 0x0000FFFF +#define IEEE802154_MAC_INF1_PAN_ID_S 0 + +#define IEEE802154_INF1_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0020) +#define IEEE802154_MAC_INF1_EXTEND_ADDR0 0xFFFFFFFF +#define IEEE802154_MAC_INF1_EXTEND_ADDR0_S 0 + +#define IEEE802154_INF1_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0024) +#define IEEE802154_MAC_INF1_EXTEND_ADDR1 0xFFFFFFFF +#define IEEE802154_MAC_INF1_EXTEND_ADDR1_S 0 + +#define IEEE802154_INF2_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0028) +#define IEEE802154_MAC_INF2_SHORT_ADDR 0x0000FFFF +#define IEEE802154_MAC_INF2_SHORT_ADDR_S 0 + +#define IEEE802154_INF2_PAN_ID_REG (IEEE802154_REG_BASE + 0x002C) +#define IEEE802154_MAC_INF2_PAN_ID 0x0000FFFF +#define IEEE802154_MAC_INF2_PAN_ID_S 0 + +#define IEEE802154_INF2_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0030) +#define IEEE802154_MAC_INF2_EXTEND_ADDR0 0xFFFFFFFF +#define IEEE802154_MAC_INF2_EXTEND_ADDR0_S 0 + +#define IEEE802154_INF2_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0034) +#define IEEE802154_MAC_INF2_EXTEND_ADDR1 0xFFFFFFFF +#define IEEE802154_MAC_INF2_EXTEND_ADDR1_S 0 + +#define IEEE802154_INF3_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0038) +#define IEEE802154_MAC_INF3_SHORT_ADDR 0x0000FFFF +#define IEEE802154_MAC_INF3_SHORT_ADDR_S 0 + +#define IEEE802154_INF3_PAN_ID_REG (IEEE802154_REG_BASE + 0x003C) +#define IEEE802154_MAC_INF3_PAN_ID 0x0000FFFF +#define IEEE802154_MAC_INF3_PAN_ID_S 0 + +#define IEEE802154_INF3_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0040) +#define IEEE802154_MAC_INF3_EXTEND_ADDR0 0xFFFFFFFF +#define IEEE802154_MAC_INF3_EXTEND_ADDR0_S 0 + +#define IEEE802154_INF3_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0044) +#define IEEE802154_MAC_INF3_EXTEND_ADDR1 0xFFFFFFFF +#define IEEE802154_MAC_INF3_EXTEND_ADDR1_S 0 + +#define IEEE802154_CHANNEL_REG (IEEE802154_REG_BASE + 0x0048) +#define IEEE802154_HOP 0x0000007F +#define IEEE802154_HOP_S 0 + +#define IEEE802154_TX_POWER_REG (IEEE802154_REG_BASE + 0x004C) +#define IEEE802154_TX_POWER 0x0000001F +#define IEEE802154_TX_POWER_S 0 + +#define IEEE802154_ED_SCAN_DURATION_REG (IEEE802154_REG_BASE + 0x0050) +#define IEEE802154_ED_SCAN_WAIT_DLY 0x0000000F +#define IEEE802154_ED_SCAN_WAIT_DLY_S 24 +#define IEEE802154_ED_SCAN_DURATION 0x00FFFFFF +#define IEEE802154_ED_SCAN_DURATION_S 0 + +#define IEEE802154_ED_SCAN_CFG_REG (IEEE802154_REG_BASE + 0x0054) +#define IEEE802154_CCA_BUSY (BIT(24)) +#define IEEE802154_CCA_BUSY_S 24 +#define IEEE802154_ED_RSS 0x000000FF +#define IEEE802154_ED_RSS_S 16 +#define IEEE802154_CCA_MODE 0x00000003 +#define IEEE802154_CCA_MODE_S 14 +#define IEEE802154_DIS_ED_POWER_SEL (BIT(13)) +#define IEEE802154_DIS_ED_POWER_SEL_S 13 +#define IEEE802154_ED_SAMPLE_MODE 0x00000003 +#define IEEE802154_ED_SAMPLE_MODE_S 11 +#define IEEE802154_CCA_ED_THRESHOLD 0x000000FF +#define IEEE802154_CCA_ED_THRESHOLD_S 0 + +#define IEEE802154_IFS_REG (IEEE802154_REG_BASE + 0x0058) +#define IEEE802154_LIFS 0x000003FF +#define IEEE802154_LIFS_S 16 +#define IEEE802154_SIFS 0x000000FF +#define IEEE802154_SIFS_S 0 + +#define IEEE802154_ACK_TIMEOUT_REG (IEEE802154_REG_BASE + 0x005C) +#define IEEE802154_ACK_TIMEOUT 0x0000FFFF +#define IEEE802154_ACK_TIMEOUT_S 0 + +#define IEEE802154_EVENT_EN_REG (IEEE802154_REG_BASE + 0x0060) +#define IEEE802154_EVENT_EN 0x00001FFF +#define IEEE802154_EVENT_EN_S 0 + +#define IEEE802154_EVENT_STATUS_REG (IEEE802154_REG_BASE + 0x0064) +#define IEEE802154_EVENT_STATUS 0x00001FFF +#define IEEE802154_EVENT_STATUS_S 0 + +#define IEEE802154_RX_ABORT_INTR_CTRL_REG (IEEE802154_REG_BASE + 0x0068) +#define IEEE802154_RX_ABORT_INTR_CTRL 0x7FFFFFFF +#define IEEE802154_RX_ABORT_INTR_CTRL_S 0 + +#define IEEE802154_ACK_FRAME_PENDING_EN_REG (IEEE802154_REG_BASE + 0x006c) +#define IEEE802154_ACK_TX_ACK_TIMEOUT 0x0000FFFF +#define IEEE802154_ACK_TX_ACK_TIMEOUT_S 16 +#define IEEE802154_ACK_FRAME_PENDING_EN (BIT(0)) +#define IEEE802154_ACK_FRAME_PENDING_EN_S 0 + +#define IEEE802154_COEX_PTI_REG (IEEE802154_REG_BASE + 0x0070) +#define IEEE802154_CLOSE_RF_SEL (BIT(8)) +#define IEEE802154_CLOSE_RF_SEL_S 8 +#define IEEE802154_COEX_ACK_PTI 0x0000000F +#define IEEE802154_COEX_ACK_PTI_S 4 +#define IEEE802154_COEX_PTI 0x0000000F +#define IEEE802154_COEX_PTI_S 0 + +#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL_REG (IEEE802154_REG_BASE + 0x0078) +#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL 0x7FFFFFFF +#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL_S 0 + +#define IEEE802154_ENHANCE_ACK_CFG_REG (IEEE802154_REG_BASE + 0x7C) +#define IEEE802154_TX_ENH_ACK_GENERATE_DONE_NOTIFY 0xFFFFFFFF +#define IEEE802154_TX_ENH_ACK_GENERATE_DONE_NOTIFY_S 0 + +#define IEEE802154_RX_STATUS_REG (IEEE802154_REG_BASE + 0x0080) +#define IEEE802154_SFD_MATCH (BIT(21)) +#define IEEE802154_SFD_MATCH_S 21 +#define IEEE802154_PREAMBLE_MATCH (BIT(20)) +#define IEEE802154_PREAMBLE_MATCH_S 20 +#define IEEE802154_RX_STATE 0x00000007 +#define IEEE802154_RX_STATE_S 16 +#define IEEE802154_RX_ABORT_STATUS 0x0000001F +#define IEEE802154_RX_ABORT_STATUS_S 4 +#define IEEE802154_FILTER_FAIL_STATUS 0x0000000F +#define IEEE802154_FILTER_FAIL_STATUS_S 0 + +#define IEEE802154_TX_STATUS_REG (IEEE802154_REG_BASE + 0x0084) +#define IEEE802154_TX_SEC_ERROR_CODE 0x0000000F +#define IEEE802154_TX_SEC_ERROR_CODE_S 16 +#define IEEE802154_TX_ABORT_STATUS 0x0000001F +#define IEEE802154_TX_ABORT_STATUS_S 4 +#define IEEE802154_TX_STATE 0x0000000F +#define IEEE802154_TX_STATE_S 0 + +#define IEEE802154_TXRX_STATUS_REG (IEEE802154_REG_BASE + 0x0088) +#define IEEE802154_RF_CTRL_STATE 0x0000000F +#define IEEE802154_RF_CTRL_STATE_S 16 +#define IEEE802154_ED_TRIGGER_TX_PROC (BIT(11)) +#define IEEE802154_ED_TRIGGER_TX_PROC_S 11 +#define IEEE802154_ED_PROC (BIT(10)) +#define IEEE802154_ED_PROC_S 10 +#define IEEE802154_RX_PROC (BIT(9)) +#define IEEE802154_RX_PROC_S 9 +#define IEEE802154_TX_PROC (BIT(8)) +#define IEEE802154_TX_PROC_S 8 +#define IEEE802154_TXRX_STATE 0x0000000F +#define IEEE802154_TXRX_STATE_S 0 + +#define IEEE802154_TX_CCM_SCHEDULE_STATUS_REG (IEEE802154_REG_BASE + 0x008c) +#define IEEE802154_TX_CCM_SCHEDULE_STATUS 0x7FFFFFFF +#define IEEE802154_TX_CCM_SCHEDULE_STATUS_S 0 + +#define IEEE802154_RX_LENGTH_REG (IEEE802154_REG_BASE + 0x00a4) +#define IEEE802154_RX_LENGTH 0x0000007F +#define IEEE802154_RX_LENGTH_S 0 + +#define IEEE802154_TIME0_THRESHOLD_REG (IEEE802154_REG_BASE + 0x00a8) +#define IEEE802154_TIMER0_THRESHOLD 0xFFFFFFFF +#define IEEE802154_TIMER0_THRESHOLD_S 0 + +#define IEEE802154_TIME0_VALUE_REG (IEEE802154_REG_BASE + 0x00ac) +#define IEEE802154_TIMER0_VALUE 0xFFFFFFFF +#define IEEE802154_TIMER0_VALUE_S 0 + +#define IEEE802154_TIME1_THRESHOLD_REG (IEEE802154_REG_BASE + 0x00b0) +#define IEEE802154_TIMER1_THRESHOLD 0xFFFFFFFF +#define IEEE802154_TIMER1_THRESHOLD_S 0 + +#define IEEE802154_TIME1_VALUE_REG (IEEE802154_REG_BASE + 0x00b4) +#define IEEE802154_TIMER1_VALUE 0xFFFFFFFF +#define IEEE802154_TIMER1_VALUE_S 0 + +#define IEEE802154_CLK_COUNTER_MATCH_VAL_REG (IEEE802154_REG_BASE + 0x00b8) +#define IEEE802154_CLK_COUNT_MATCH_VAL 0x0000FFFF +#define IEEE802154_CLK_COUNT_MATCH_VAL_S 0 + +#define IEEE802154_CLK_COUNTER_REG (IEEE802154_REG_BASE + 0x00bc) +#define IEEE802154_CLK_625US_CNT 0x0000FFFF +#define IEEE802154_CLK_625US_CNT_S 0 + +#define IEEE802154_IFS_COUNTER_REG (IEEE802154_REG_BASE + 0x00c0) +#define IEEE802154_IFS_COUNTER_EN (BIT(16)) +#define IEEE802154_IFS_COUNTER_EN_S 16 +#define IEEE802154_IFS_COUNTER 0x000003FF +#define IEEE802154_IFS_COUNTER_S 0 + +#define IEEE802154_SFD_WAIT_SYMBOL_REG (IEEE802154_REG_BASE + 0x00c4) +#define IEEE802154_SFD_WAIT_SYMBOL_NUM 0x0000000F +#define IEEE802154_SFD_WAIT_SYMBOL_NUM_S 0 + +#define IEEE802154_TXRX_PATH_DELAY_REG (IEEE802154_REG_BASE + 0x00c8) +#define IEEE802154_RX_PATH_DELAY 0x0000003F +#define IEEE802154_RX_PATH_DELAY_S 16 +#define IEEE802154_TX_PATH_DELAY 0x0000003F +#define IEEE802154_TX_PATH_DELAY_S 0 + +#define IEEE802154_BB_CLK_REG (IEEE802154_REG_BASE + 0x00cc) +#define IEEE802154_BB_CLK_FREQ_MINUS_1 0x0000001F +#define IEEE802154_BB_CLK_FREQ_MINUS_1_S 0 + +#define IEEE802154_TXDMA_ADDR_REG (IEEE802154_REG_BASE + 0x00D0) +#define IEEE802154_TXDMA_ADDR 0xFFFFFFFF +#define IEEE802154_TXDMA_ADDR_S 0 + +#define IEEE802154_TXDMA_CTRL_STATE_REG (IEEE802154_REG_BASE + 0x00D4) +#define IEEE802154_TXDMA_FETCH_BYTE_CNT 0x0000007F +#define IEEE802154_TXDMA_FETCH_BYTE_CNT_S 24 +#define IEEE802154_TXDMA_STATE 0x0000001F +#define IEEE802154_TXDMA_STATE_S 16 +#define IEEE802154_TXDMA_FILL_ENTRY 0x00000007 +#define IEEE802154_TXDMA_FILL_ENTRY_S 4 +#define IEEE802154_TXDMA_WATER_LEVEL 0x00000007 +#define IEEE802154_TXDMA_WATER_LEVEL_S 0 + +#define IEEE802154_TXDMA_ERR_REG (IEEE802154_REG_BASE + 0x00D8) +#define IEEE802154_TXDMA_ERR 0x0000000F +#define IEEE802154_TXDMA_ERR_S 0 + +#define IEEE802154_RXDMA_ADDR_REG (IEEE802154_REG_BASE + 0x00E0) +#define IEEE802154_RXDMA_ADDR 0xFFFFFFFF +#define IEEE802154_RXDMA_ADDR_S 0 + +#define IEEE802154_RXDMA_CTRL_STATE_REG (IEEE802154_REG_BASE + 0x00E4) +#define IEEE802154_RXDMA_APPEND_FREQ_OFFSET (BIT(25)) +#define IEEE802154_RXDMA_APPEND_FREQ_OFFSET_S 25 +#define IEEE802154_RXDMA_APPEND_LQI_OFFSET (BIT(24)) +#define IEEE802154_RXDMA_APPEND_LQI_OFFSET_S 24 +#define IEEE802154_RXDMA_STATE 0x0000001F +#define IEEE802154_RXDMA_STATE_S 16 +#define IEEE802154_RXDMA_WATER_LEVEL 0x00000007 +#define IEEE802154_RXDMA_WATER_LEVEL_S 0 + +#define IEEE802154_RXDMA_ERR_REG (IEEE802154_REG_BASE + 0x00E8) +#define IEEE802154_RXDMA_ERR 0x0000000F +#define IEEE802154_RXDMA_ERR_S 0 + +#define IEEE802154_DMA_GCK_CFG_REG (IEEE802154_REG_BASE + 0x00F0) +#define IEEE802154_DMA_GCK_CFG (BIT(0)) +#define IEEE802154_DMA_GCK_CFG_S 0 + +#define IEEE802154_DMA_DUMMY_REG (IEEE802154_REG_BASE + 0x00F4) +#define IEEE802154_DMA_DUMMY_DATA 0xFFFFFFFF +#define IEEE802154_DMA_DUMMY_DATA_S + +#define IEEE802154_PAON_DELAY_REG (IEEE802154_REG_BASE + 0x0100) +#define IEEE802154_PAON_DELAY 0x000003FF +#define IEEE802154_PAON_DELAY_S 0 + +#define IEEE802154_TXON_DELAY_REG (IEEE802154_REG_BASE + 0x0104) +#define IEEE802154_TXON_DELAY 0x000003FF +#define IEEE802154_TXON_DELAY_S 0 + +#define IEEE802154_TXEN_STOP_DELAY_REG (IEEE802154_REG_BASE + 0x0108) +#define IEEE802154_TXEN_STOP_DLY 0x0000003F +#define IEEE802154_TXEN_STOP_DLY_S 0 + +#define IEEE802154_TXOFF_DELAY_REG (IEEE802154_REG_BASE + 0x010c) +#define IEEE802154_TXOFF_DELAY 0x0000003F +#define IEEE802154_TXOFF_DELAY_S 0 + +#define IEEE802154_RXON_DELAY_REG (IEEE802154_REG_BASE + 0x0110) +#define IEEE802154_RXON_DELAY 0x000007FF +#define IEEE802154_RXON_DELAY_S 0 + +#define IEEE802154_TXRX_SWITCH_DELAY_REG (IEEE802154_REG_BASE + 0x0114) +#define IEEE802154_TXRX_SWITCH_DELAY 0x000003FF +#define IEEE802154_TXRX_SWITCH_DELAY_S 0 + +#define IEEE802154_CONT_RX_DELAY_REG (IEEE802154_REG_BASE + 0x0118) +#define IEEE802154_CONT_RX_DELAY 0x0000003F +#define IEEE802154_CONT_RX_DELAY_S 0 + +#define IEEE802154_DCDC_CTRL_REG (IEEE802154_REG_BASE + 0x011c) +#define IEEE802154_TX_DCDC_UP (BIT(31)) +#define IEEE802154_TX_DCDC_UP_S 31 +#define IEEE802154_DCDC_CTRL_EN (BIT(16)) +#define IEEE802154_DCDC_CTRL_EN_S 16 +#define IEEE802154_DCDC_DOWN_DELAY 0x000000FF +#define IEEE802154_DCDC_DOWN_DELAY_S 8 +#define IEEE802154_DCDC_PRE_UP_DELAY 0x000000FF +#define IEEE802154_DCDC_PRE_UP_DELAY_S 0 + +#define IEEE802154_DEBUG_CTRL_REG (IEEE802154_REG_BASE + 0x0120) +#define IEEE802154_DEBUG_TRIGGER_DUMP_EN (BIT(31)) +#define IEEE802154_DEBUG_TRIGGER_DUMP_EN_S 31 +#define IEEE802154_DEBUG_STATE_MATCH_DUMP_EN (BIT(30)) +#define IEEE802154_DEBUG_STATE_MATCH_DUMP_EN_S 30 +#define IEEE802154_DEBUG_TRIGGER_PULSE_SELECT 0x00000007 +#define IEEE802154_DEBUG_TRIGGER_PULSE_SELECT_S 24 +#define IEEE802154_DEBUG_TRIGGER_STATE_MATCH_VALUE 0x0000001F +#define IEEE802154_DEBUG_TRIGGER_STATE_MATCH_VALUE_S 16 +#define IEEE802154_DEBUG_SER_DEBUG_SEL 0x0000000F +#define IEEE802154_DEBUG_SER_DEBUG_SEL_S 12 +#define IEEE802154_DEBUG_TRIGGER_STATE_SELECT 0x0000000F +#define IEEE802154_DEBUG_TRIGGER_STATE_SELECT_S 8 +#define IEEE802154_DEBUG_SIGNAL_SEL 0x00000007 +#define IEEE802154_DEBUG_SIGNAL_SEL_S 0 + +#define IEEE802154_SEC_CTRL_REG (IEEE802154_REG_BASE + 0x0128) +#define IEEE802154_SEC_PAYLOAD_OFFSET 0x0000007F +#define IEEE802154_SEC_PAYLOAD_OFFSET_S 8 +#define IEEE802154_SEC_EN (BIT(0)) +#define IEEE802154_SEC_EN_S 0 + +#define IEEE802154_SEC_EXTEND_ADDRESS0_REG (IEEE802154_REG_BASE + 0x012c) +#define IEEE802154_SEC_EXTEND_ADDRESS0 0xFFFFFFFF +#define IEEE802154_SEC_EXTEND_ADDRESS0_S 0 + +#define IEEE802154_SEC_EXTEND_ADDRESS1_REG (IEEE802154_REG_BASE + 0x0130) +#define IEEE802154_SEC_EXTEND_ADDRESS1 0xFFFFFFFF +#define IEEE802154_SEC_EXTEND_ADDRESS1_S 0 + +#define IEEE802154_SEC_KEY0_REG (IEEE802154_REG_BASE + 0x0134) +#define IEEE802154_SEC_KEY0 0xFFFFFFFF +#define IEEE802154_SEC_KEY0_S 0 + +#define IEEE802154_SEC_KEY1_REG (IEEE802154_REG_BASE + 0x0138) +#define IEEE802154_SEC_KEY1 0xFFFFFFFF +#define IEEE802154_SEC_KEY1_S 0 + +#define IEEE802154_SEC_KEY2_REG (IEEE802154_REG_BASE + 0x013c) +#define IEEE802154_SEC_KEY2 0xFFFFFFFF +#define IEEE802154_SEC_KEY2_S 0 + +#define IEEE802154_SEC_KEY3_REG (IEEE802154_REG_BASE + 0x0140) +#define IEEE802154_SEC_KEY3 0xFFFFFFFF +#define IEEE802154_SEC_KEY3_S 0 + +#define IEEE802154_SFD_TIMEOUT_CNT_REG (IEEE802154_REG_BASE + 0x0144) +#define IEEE802154_SFD_TIMEOUT_CNT 0x0000FFFF +#define IEEE802154_SFD_TIMEOUT_CNT_S 0 + +#define IEEE802154_CRC_ERROR_CNT_REG (IEEE802154_REG_BASE + 0x0148) +#define IEEE802154_CRC_ERROR_CNT 0x0000FFFF +#define IEEE802154_CRC_ERROR_CNT_S 0 + +#define IEEE802154_ED_ABORT_CNT_REG (IEEE802154_REG_BASE + 0x014c) +#define IEEE802154_ED_ABORT_CNT 0x0000FFFF +#define IEEE802154_ED_ABORT_CNT_S 0 + +#define IEEE802154_CCA_FAIL_CNT_REG (IEEE802154_REG_BASE + 0x0150) +#define IEEE802154_CCA_FAIL_CNT 0x0000FFFF +#define IEEE802154_CCA_FAIL_CNT_S 0 + +#define IEEE802154_RX_FILTER_FAIL_CNT_REG (IEEE802154_REG_BASE + 0x0154) +#define IEEE802154_RX_FILTER_FAIL_CNT 0x0000FFFF +#define IEEE802154_RX_FILTER_FAIL_CNT_S 0 + +#define IEEE802154_NO_RSS_DETECT_CNT_REG (IEEE802154_REG_BASE + 0x0158) +#define IEEE802154_NO_RSS_DETECT_CNT 0x0000FFFF +#define IEEE802154_NO_RSS_DETECT_CNT_S 0 + +#define IEEE802154_RX_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x015c) +#define IEEE802154_RX_ABORT_COEX_CNT 0x0000FFFF +#define IEEE802154_RX_ABORT_COEX_CNT_S 0 + +#define IEEE802154_RX_RESTART_CNT_REG (IEEE802154_REG_BASE + 0x0160) +#define IEEE802154_RX_RESTART_CNT 0x0000FFFF +#define IEEE802154_RX_RESTART_CNT_S 0 + +#define IEEE802154_TX_ACK_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0164) +#define IEEE802154_TX_ACK_ABORT_COEX_CNT 0x0000FFFF +#define IEEE802154_TX_ACK_ABORT_COEX_CNT_S 0 + +#define IEEE802154_ED_SCAN_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0168) +#define IEEE802154_ED_SCAN_COEX_CNT 0x0000FFFF +#define IEEE802154_ED_SCAN_COEX_CNT_S 0 + +#define IEEE802154_RX_ACK_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x016c) +#define IEEE802154_RX_ACK_ABORT_COEX_CNT 0x0000FFFF +#define IEEE802154_RX_ACK_ABORT_COEX_CNT_S 0 + +#define IEEE802154_RX_ACK_TIMEOUT_CNT_REG (IEEE802154_REG_BASE + 0x0170) +#define IEEE802154_RX_ACK_TIMEOUT_CNT 0x0000FFFF +#define IEEE802154_RX_ACK_TIMEOUT_CNT_S 0 + +#define IEEE802154_TX_BREAK_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0174) +#define IEEE802154_TX_BREAK_COEX_CNT 0x0000FFFF +#define IEEE802154_TX_BREAK_COEX_CNT_S 0 + +#define IEEE802154_TX_SECURITY_ERROR_CNT_REG (IEEE802154_REG_BASE + 0x0178) +#define IEEE802154_TX_SECURITY_ERROR_CNT 0x0000FFFF +#define IEEE802154_TX_SECURITY_ERROR_CNT_S 0 + +#define IEEE802154_CCA_BUSY_CNT_REG (IEEE802154_REG_BASE + 0x017c) +#define IEEE802154_CCA_BUSY_CNT 0x0000FFFF +#define IEEE802154_CCA_BUSY_CNT_S 0 + +#define IEEE802154_ERROR_CNT_CLEAR_REG (IEEE802154_REG_BASE + 0x0180) +#define IEEE802154_SFD_TIMEOUT_CNT_CLEAR (BIT(14)) +#define IEEE802154_SFD_TIMEOUT_CNT_CLEAR_S 14 +#define IEEE802154_CRC_ERROR_CNT_CLEAR (BIT(13)) +#define IEEE802154_CRC_ERROR_CNT_CLEAR_S 13 +#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR (BIT(12)) +#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR_S 12 +#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR (BIT(11)) +#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR_S 11 +#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR (BIT(10)) +#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR_S 10 +#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR (BIT(9)) +#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR_S 9 +#define IEEE802154_RX_RESTART_CNT_CLEAR (BIT(8)) +#define IEEE802154_RX_RESTART_CNT_CLEAR_S 8 +#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR (BIT(7)) +#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR_S 7 +#define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR (BIT(6)) +#define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR_S 6 +#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR (BIT(5)) +#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR_S 5 +#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR (BIT(4)) +#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR_S 4 +#define IEEE802154_ED_ABORT_CNT_CLEAR (BIT(3)) +#define IEEE802154_ED_ABORT_CNT_CLEAR_S 3 +#define IEEE802154_CCA_FAIL_CNT_CLEAR (BIT(2)) +#define IEEE802154_CCA_FAIL_CNT_CLEAR_S 2 +#define IEEE802154_CCA_BUSY_CNT_CLEAR (BIT(1)) +#define IEEE802154_CCA_BUSY_CNT_CLEAR_S 1 +#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR (BIT(0)) +#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR_S 0 + +#define IEEE802154_MAC_DATE_REG (IEEE802154_REG_BASE + 0x0184) +#define IEEE802154_MAC_DATE 0xFFFFFFFF +#define IEEE802154_MAC_DATE_S 0 +#define IEEE802154_MAC_DATE_VERSION 0x220622 + +// For ETM feature. +#define ETM_REG_BASE 0x600A8800 +#define ETM_CHEN_AD0_REG (ETM_REG_BASE + 0x0000) +#define ETM_CHENSET_AD0_REG (ETM_REG_BASE + 0x0004) +#define ETM_CHENCLR_AD0_REG (ETM_REG_BASE + 0x0008) +#define ETM_CH0_EVT_ID_REG (ETM_REG_BASE + 0x0018) +#define ETM_CH0_TASK_ID_REG (ETM_REG_BASE + 0x001C) + +#define ETM_CH_OFFSET 0x08 + +#define ETM_EVENT_TIMER1_OVERFLOW 58 +#define ETM_EVENT_TIMER0_OVERFLOW 59 +#define ETM_TASK_ED_TRIG_TX 64 +#define ETM_TASK_RX_START 65 +#define ETM_TASK_TX_START 68 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ieee802154_struct.h b/components/soc/esp32c5/include/soc/ieee802154_struct.h new file mode 100644 index 0000000000..385c831270 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ieee802154_struct.h @@ -0,0 +1,462 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready. +typedef volatile struct esp_ieee802154_s { + union { + struct { + uint32_t cmd: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } cmd; // 0x00 + + union { + struct { + uint32_t auto_ack_tx: 1; + uint32_t auto_enhack: 1; + uint32_t reserved2: 1; + uint32_t auto_ack_rx: 1; + uint32_t reserved4: 1; + uint32_t ifs_dis: 1; + uint32_t coordinator: 1; + uint32_t promiscuous: 1; + uint32_t reserved8: 3; + uint32_t version_filter_dis: 1; + uint32_t pending_enhance: 1; + uint32_t reserved13: 1; + uint32_t filter_enhance_dis: 1; + uint32_t reserved15: 1; + uint32_t coex_arb_delay: 8; + uint32_t bit_order: 1; + uint32_t no_rssi_trigger_break_en: 1; + uint32_t coex_force_rx: 1; + uint32_t rx_done_trig_idle: 1; + uint32_t multipan_mask: 4; + }; + uint32_t val; + } conf; // 0x04 + + struct { + union { + struct { + uint32_t addr: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } short_addr; // 0x08 + + union { + struct { + uint32_t id: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } panid; // 0x0c + + uint32_t ext_addr0; // 0x10 + uint32_t ext_addr1; // 0x14 + } multipan[4]; + + union { + struct { + uint32_t freq: 7; + uint32_t reserved7: 25; + }; + uint32_t val; + } channel; //0x48 + + union { + struct { + uint32_t power: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } txpower; //0x4c + + union { + struct { + uint32_t duration: 24; + uint32_t delay: 4; + uint32_t reserved28: 4; + }; + uint32_t val; + } ed_duration; //0x50 + + union { + struct { + uint32_t cca_threshold: 8; + uint32_t reserved8: 3; + uint32_t ed_sample_rate: 2; + uint32_t ed_sample_mode: 1; + uint32_t cca_mode: 2; + uint32_t ed_rss: 8; + uint32_t cca_busy: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } ed_cfg; //0x54 + + union { + struct { + uint32_t sifs: 8; + uint32_t reserved8: 8; + uint32_t lifs: 10; + uint32_t reserved26: 6; + }; + uint32_t val; + } ifs_cfg; //0x58 + + union { + struct { + uint32_t timeout: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } ack_timeout; //0x5c + + union { + struct { + uint32_t events: 13; + uint32_t reserved13: 19; + }; + uint32_t val; + } event_en; //0x60 + + union { + struct { + uint32_t events: 13; + uint32_t reserved13: 19; + }; + uint32_t val; + } event_status; //0x64 + + union { + struct { + uint32_t rx_abort_en: 31; + uint32_t reserved31: 1; + }; + uint32_t val; + } rx_abort_event_en; //0x68 + + union { + struct { + uint32_t pending: 1; + uint32_t reserved1: 15; + uint32_t pending_timeout: 16; + }; + uint32_t val; + } pending_cfg; //0x6c + + union { + struct { + uint32_t pti: 4; + uint32_t hw_ack_pti: 4; + uint32_t close_rf_sel: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } pti; //0x70 + + uint32_t reserved_74; //0x74 + + union { + struct { + uint32_t tx_abort_en: 31; + uint32_t reserved31: 1; + }; + uint32_t val; + } tx_abort_event_en; //0x78 + + uint32_t enhack_generate_done_notify; //0x7c + + union { + struct { + uint32_t filter_fail_reason: 4; + uint32_t rx_abort_reason: 5; + uint32_t reserved9: 7; + uint32_t rx_state: 3; + uint32_t reserved19: 1; + uint32_t preamble_match: 1; + uint32_t sfd_match: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } rx_status; // 0x80 + + union { + struct { + uint32_t tx_state: 4; + uint32_t tx_abort_reason: 5; + uint32_t reserved9: 7; + uint32_t tx_security_error: 4; + uint32_t reserved20: 12; + }; + uint32_t val; + } tx_status; //0x84 + + union { + struct { + uint32_t txrx_status: 4; + uint32_t reserved4: 4; + uint32_t tx_proc: 1; + uint32_t rx_proc: 1; + uint32_t ed_proc: 1; + uint32_t ed_trig_tx_proc: 1; + uint32_t reserved12: 4; + uint32_t rf_ctrl_state: 4; + uint32_t reserved20: 12; + }; + uint32_t val; + } txrx_status; //0x88 + + uint32_t tx_sec_schedule_state; //0x8c + + union { + struct { + uint32_t pkt_gck: 1; + uint32_t ctrl_gck: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_gck_cfg; //0x90 + + uint32_t reserved_94; //0x94 + uint32_t reserved_98; //0x98 + uint32_t reserved_9c; //0x9c + uint32_t reserved_a0; //0xa0 + + uint32_t rx_length; //0xa4 + + uint32_t timer0_threshold; //0xa8 + uint32_t timer0_value; //0xac + uint32_t timer1_threshold; //0xb0 + uint32_t timer1_value; //0xb4 + uint32_t clk_counter_threshold; //0xb8 + uint32_t clk_counter_value; //0xbc + + union { + struct { + uint32_t ifs_counter: 10; + uint32_t reserved10: 6; + uint32_t ifs_counter_en: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } ifs_counter_cfg; //0xc0 + + union { + struct { + uint32_t sfd_wait_symbol_num: 4; + uint32_t reserved4: 28; + }; + uint32_t val; + } sfd_wait; //0xc4 + + union { + struct { + uint32_t tx_path_delay: 6; + uint32_t reserved6: 10; + uint32_t rx_path_delay: 6; + uint32_t reserved624: 10; + }; + uint32_t val; + } txrx_path_delay; //0xc8 + + uint32_t bb_clk; //0xcc + uint32_t dma_tx_addr; //0xd0 + + union { + struct { + uint32_t txdma_water_level: 3; + uint32_t reserved3: 1; + uint32_t txdma_fill_entry: 3; + uint32_t reserved7: 9; + uint32_t txdma_ctrl_state: 5; + uint32_t reserved21: 3; + uint32_t txdma_fetch_byte_cnt: 7; + uint32_t reserved31: 1; + }; + uint32_t val; + } dma_tx_cfg; //0xd4 + + uint32_t dma_tx_err; //0xd8 + + uint32_t reserved_dc; //0xdc + + uint32_t dma_rx_addr; //0xe0 + + union { + struct { + uint32_t rxdma_water_level: 3; + uint32_t reserved3: 13; + uint32_t rxdma_ctrl_state: 5; + uint32_t reserved21: 3; + uint32_t rxdma_append_lqi: 1; + uint32_t rxdma_append_freq_offset: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } dma_rx_cfg; //0xe4 + + uint32_t dma_rx_err; //0xe8 + + uint32_t reserved_ec; //x0ec + + uint32_t dma_gck; //0xf0 + uint32_t dma_dummy_data; //0xf4 + uint32_t reserved_f8; //0xf8 + uint32_t reserved_fc; //0xfc + + union { + struct { + uint32_t delay: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } pa_on_delay; //0x100 + + union { + struct { + uint32_t delay: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } tx_on_delay; //0x104 + + union { + struct { + uint32_t delay: 6; + uint32_t reserved6: 26; + }; + uint32_t val; + } txen_stop_delay; //0x108 + + union { + struct { + uint32_t delay: 6; + uint32_t reserved6: 26; + }; + uint32_t val; + } tx_off_delay; //0x10c + + union { + struct { + uint32_t delay: 11; + uint32_t reserved11: 21; + }; + uint32_t val; + } rx_on_delay; //0x110 + + union { + struct { + uint32_t delay: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } txrx_switch_delay; //0x114 + + uint32_t cont_rx_delay; //0x118 + + union { + struct { + uint32_t dcdc_pre_up_delay: 8; + uint32_t dcdc_down_delay: 8; + uint32_t dcdc_ctrl_en: 1; + uint32_t reserved17: 14; + uint32_t tx_dcdc_up: 1; + }; + uint32_t val; + } dcdc_ctrl; //0x11c + + union { + struct { + uint32_t debug_sel: 3; + uint32_t reserved3: 5; + uint32_t trig_st_sel: 4; + uint32_t ser_debug_sel: 4; + uint32_t trig_st_match_val: 5; + uint32_t reserved21: 3; + uint32_t trig_pulse_sel: 3; + uint32_t reserved27: 3; + uint32_t trig_st_match_dump_en: 1; + uint32_t trig_pulse_dump_en: 1; + }; + uint32_t val; + } debug_ctrl; //0x120 + + uint32_t tx_dma_err_sts_reg; //0x124 + union { + struct { + uint32_t tx_security_en: 1; + uint32_t reserved1: 7; + uint32_t security_offset: 7; + uint32_t reserved15: 17; + }; + uint32_t val; + } security_ctrl; //0x128 + + uint32_t security_addr0; //0x12c + uint32_t security_addr1; //0x130 + uint32_t security_key0; //0x134 + uint32_t security_key1; //0x138 + uint32_t security_key2; //0x13c + uint32_t security_key3; //0x140 + + uint32_t debug_sfd_timeout_cnt; //0x144 + uint32_t debug_crc_error_cnt; //0x148 + uint32_t debug_ed_abort_cnt; //0x14c + uint32_t debug_cca_fail_cnt; //0x150 + uint32_t debug_rx_filter_fail_cnt; //0x154 + uint32_t debug_no_rss_detect_cnt; //0x158 + uint32_t debug_rx_abort_coex_cnt; //0x15c + uint32_t debug_rx_restart_cnt; //0x160 + uint32_t debug_tx_ack_abort_coex_cnt; //0x164 + uint32_t debug_ed_scan_break_coex_cnt; //0x168 + uint32_t debug_rx_ack_abort_coex_cnt; //0x16c + uint32_t debug_rx_ack_timeout_cnt; //0x170 + uint32_t debug_tx_break_coex_cnt; //0x174 + uint32_t debug_tx_security_error_cnt; //0x178 + uint32_t debug_cca_busy_cnt; //0x17c + + union { + struct { + uint32_t debug_ed_scan_break_coex_cnt: 1; + uint32_t debug_cca_busy_cnt: 1; + uint32_t debug_cca_fail_cnt: 1; + uint32_t debug_ed_abort_cnt: 1; + uint32_t debug_tx_security_error_cnt: 1; + uint32_t debug_tx_break_coex_cnt: 1; + uint32_t debug_tx_ack_abort_coex_cnt: 1; + uint32_t debug_rx_ack_timeout_cnt: 1; + uint32_t debug_rx_restart_cnt: 1; + uint32_t debug_rx_ack_abort_coex_cnt: 1; + uint32_t debug_rx_abort_coex_cnt: 1; + uint32_t debug_no_rss_detect_cnt: 1; + uint32_t debug_rx_filter_fail_cnt: 1; + uint32_t debug_crc_error_cnt: 1; + uint32_t debug_sfd_timeout_cnt: 1; + uint32_t reserved15: 17; + }; + uint32_t val; + } debug_cnt_clr; //0x180 + + uint32_t i154_version; //0x184 + +} esp_ieee802154_t; + +extern esp_ieee802154_t IEEE802154; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/periph_defs.h b/components/soc/esp32c5/include/soc/periph_defs.h index 04f5b92e49..f1d0108342 100644 --- a/components/soc/esp32c5/include/soc/periph_defs.h +++ b/components/soc/esp32c5/include/soc/periph_defs.h @@ -67,6 +67,7 @@ typedef enum { /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ PERIPH_WIFI_MODULE, PERIPH_BT_MODULE, + PERIPH_IEEE802154_MODULE, PERIPH_COEX_MODULE, PERIPH_PHY_MODULE, PERIPH_ANA_I2C_MASTER_MODULE, diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h index 8fd62877a3..6197746bbd 100644 --- a/components/soc/esp32c5/include/soc/reg_base.h +++ b/components/soc/esp32c5/include/soc/reg_base.h @@ -78,6 +78,7 @@ #define PWDET_CONF_REG 0x600A0810 #define DR_REG_I2C_ANA_MST_BASE 0x600AF800 +#define IEEE802154_REG_BASE 0x600A3000 /** * @brief LP System (RTC) Modules diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 5edd46e785..da3130bef6 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -56,6 +56,7 @@ #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 #define SOC_FLASH_ENC_SUPPORTED 1 #define SOC_SECURE_BOOT_SUPPORTED 1 +#define SOC_IEEE802154_SUPPORTED 1 // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 #define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */ #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 diff --git a/components/soc/esp32c6/include/soc/ieee802154_reg.h b/components/soc/esp32c6/include/soc/ieee802154_reg.h index db8e6e12bf..4aa7013a9e 100644 --- a/components/soc/esp32c6/include/soc/ieee802154_reg.h +++ b/components/soc/esp32c6/include/soc/ieee802154_reg.h @@ -12,7 +12,6 @@ extern "C" { #endif // TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready. -#define IEEE802154_REG_BASE 0x600A3000 #define IEEE802154_COMMAND_REG (IEEE802154_REG_BASE + 0x0000) #define IEEE802154_OPCODE 0x000000FF diff --git a/components/soc/esp32c6/include/soc/reg_base.h b/components/soc/esp32c6/include/soc/reg_base.h index 7d8339605e..f2da385dc1 100644 --- a/components/soc/esp32c6/include/soc/reg_base.h +++ b/components/soc/esp32c6/include/soc/reg_base.h @@ -80,3 +80,4 @@ #define DR_REG_EXTMEM_BASE 0x600C8000 #define PWDET_CONF_REG 0x600A0810 +#define IEEE802154_REG_BASE 0x600A3000 diff --git a/components/soc/esp32h2/include/soc/ieee802154_reg.h b/components/soc/esp32h2/include/soc/ieee802154_reg.h index 3c480348ba..d1564b002e 100644 --- a/components/soc/esp32h2/include/soc/ieee802154_reg.h +++ b/components/soc/esp32h2/include/soc/ieee802154_reg.h @@ -13,7 +13,6 @@ extern "C" { #endif // TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready. -#define IEEE802154_REG_BASE 0x600A3000 #define IEEE802154_COMMAND_REG (IEEE802154_REG_BASE + 0x0000) #define IEEE802154_OPCODE 0x000000FF diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h index 70d5d8b212..e3801b9c9a 100644 --- a/components/soc/esp32h2/include/soc/reg_base.h +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -69,3 +69,4 @@ #define DR_REG_CACHE_BASE 0x600C8000 #define PWDET_CONF_REG 0x600A0810 +#define IEEE802154_REG_BASE 0x600A3000 diff --git a/examples/ieee802154/.build-test-rules.yml b/examples/ieee802154/.build-test-rules.yml index da1aefce19..d86f42e77b 100644 --- a/examples/ieee802154/.build-test-rules.yml +++ b/examples/ieee802154/.build-test-rules.yml @@ -13,7 +13,7 @@ examples/ieee802154/ieee802154_cli: enable: - if: SOC_IEEE802154_SUPPORTED == 1 disable_test: - - if: IDF_TARGET == "esp32h2" + - if: IDF_TARGET not in ["esp32c6"] temporary: true reason: only test on esp32c6 <<: *ieee802154_dependencies diff --git a/examples/ieee802154/ieee802154_cli/README.md b/examples/ieee802154/ieee802154_cli/README.md index 584a8d4ca8..839c8eae38 100644 --- a/examples/ieee802154/ieee802154_cli/README.md +++ b/examples/ieee802154/ieee802154_cli/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | # IEEE802.15.4 Command Line Example @@ -314,7 +314,7 @@ I (6580547) i154cmd: 00 11 22 33 44 55 66 77 ``` #### tx -l \ -Transmit IEEE 802154 MAC frame wich has a length=\. +Transmit IEEE 802154 MAC frame which has a length=\. * -C: Set cca trigging tx mode true. ```bash > tx -l 10 diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index 4b1dc50b25..0a85007f19 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -22,31 +22,40 @@ examples/openthread/ot_br: enable: - if: SOC_WIFI_SUPPORTED == 1 and IDF_TARGET != "esp32c5" disable_test: - - if: IDF_TARGET in ["esp32", "esp32c3", "esp32c2", "esp32c6", "esp32s2", "esp32c5"] - temporary: true + - if: IDF_TARGET not in ["esp32s3"] reason: only test on esp32s3 <<: *openthread_dependencies examples/openthread/ot_cli: enable: - if: SOC_IEEE802154_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET not in ["esp32h2", "esp32c6"] + reason: only test on esp32h2 and esp32c6 <<: *openthread_dependencies examples/openthread/ot_rcp: enable: - if: SOC_IEEE802154_SUPPORTED == 1 disable_test: - - if: IDF_TARGET == "esp32h2" - temporary: true + - if: IDF_TARGET not in ["esp32c6"] reason: only test on esp32c6 <<: *openthread_dependencies examples/openthread/ot_sleepy_device/deep_sleep: enable: - if: SOC_IEEE802154_SUPPORTED == 1 + disable: + - if: IDF_TARGET in ["esp32c5"] + temporary: true + reason: Not supported yet, TZ-958 <<: [*openthread_dependencies, *openthread_sleep_dependencies] examples/openthread/ot_sleepy_device/light_sleep: enable: - if: SOC_IEEE802154_SUPPORTED == 1 + disable: + - if: IDF_TARGET in ["esp32c5"] + temporary: true + reason: Not supported yet, TZ-958 <<: [*openthread_dependencies, *openthread_sleep_dependencies] diff --git a/examples/openthread/ot_cli/README.md b/examples/openthread/ot_cli/README.md index 8535276959..2a02e8b89b 100644 --- a/examples/openthread/ot_cli/README.md +++ b/examples/openthread/ot_cli/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | # OpenThread Command Line Example diff --git a/examples/openthread/ot_rcp/README.md b/examples/openthread/ot_rcp/README.md index a3f1b8eefd..46bf3ef6a7 100644 --- a/examples/openthread/ot_rcp/README.md +++ b/examples/openthread/ot_rcp/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | # OpenThread Radio Co-Processor (RCP) Example diff --git a/examples/zigbee/.build-test-rules.yml b/examples/zigbee/.build-test-rules.yml index 7f14991ad8..a8abfba2d4 100644 --- a/examples/zigbee/.build-test-rules.yml +++ b/examples/zigbee/.build-test-rules.yml @@ -15,11 +15,19 @@ examples/zigbee/esp_zigbee_gateway: examples/zigbee/esp_zigbee_rcp: enable: - if: SOC_IEEE802154_SUPPORTED == 1 + disable: + - if: IDF_TARGET == "esp32c5" + temporary: true + reason: Not supported yet <<: *zigbee_dependencies examples/zigbee/light_sample: enable: - if: SOC_IEEE802154_SUPPORTED == 1 + disable: + - if: IDF_TARGET == "esp32c5" + temporary: true + reason: Not supported yet disable_test: - if: IDF_TARGET == "esp32c6" temporary: true