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hal: workaround for UART FIFO read on ESP32 with -O2 optimization

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This commit is contained in:
Omar Chebib 2021-03-09 14:18:28 +08:00
parent da1ed49a65
commit 8db219c292
1 changed files with 3 additions and 0 deletions
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components/soc/esp32/include/hal/uart_ll.h
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@ -167,6 +167,9 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2); uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
for(uint32_t i = 0; i < rd_len; i++) { for(uint32_t i = 0; i < rd_len; i++) {
buf[i] = READ_PERI_REG(fifo_addr); buf[i] = READ_PERI_REG(fifo_addr);
#ifdef CONFIG_COMPILER_OPTIMIZATION_PERF
__asm__ __volatile__("nop");
#endif
} }
} }