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Merge branch 'bugfix/fix_some_wifi_coexist_issue_v5.1' into 'release/v5.1'

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fix(coex): fix some wifi coexist issue v5.1

See merge request espressif/esp-idf!29660
This commit is contained in:
Jiang Jiang Jian 2024-03-15 12:27:58 +08:00
commit 8d3b3dfefa
15 changed files with 24 additions and 14 deletions
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2
components/esp_coex/lib

@ -1 +1 @@
Subproject commit 496ee81e168881cad93f9a813802e7f7a6daec92
Subproject commit 2717868407a01878a49d19794538b6da120597ae

4
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
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@ -1474,7 +1474,7 @@ ebuf_list_remove = 0x40001adc;
GetAccess = 0x40001aec;
hal_mac_is_low_rate_enabled = 0x40001af0;
hal_mac_tx_get_blockack = 0x40001af4;
hal_mac_tx_set_ppdu = 0x40001af8;
/*hal_mac_tx_set_ppdu = 0x40001af8;*/
ic_get_trc = 0x40001afc;
/* ic_mac_deinit = 0x40001b00; */
ic_mac_init = 0x40001b04;
@ -1561,7 +1561,7 @@ ppTask = 0x40001c44;
ppTxPkt = 0x40001c48;
ppTxProtoProc = 0x40001c4c;
ppTxqUpdateBitmap = 0x40001c50;
pp_coex_tx_request = 0x40001c54;
/*pp_coex_tx_request = 0x40001c54;*/
pp_hdrsize = 0x40001c58;
pp_post = 0x40001c5c;
pp_process_hmac_waiting_txq = 0x40001c60;

2
components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
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@ -6,7 +6,7 @@
esf_buf_alloc = 0x400015bc;
esf_buf_alloc_dynamic = 0x400015c0;
esf_buf_recycle = 0x400015c4;
hal_mac_tx_set_ppdu = 0x400015d4;
/*hal_mac_tx_set_ppdu = 0x400015d4;*/
ic_mac_deinit = 0x400015dc;
lmacDiscardMSDU = 0x400015f4;
/*lmacSetTxFrame = 0x40001628;*/

2
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
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@ -1591,7 +1591,7 @@ ppTask = 0x40001720;
ppTxPkt = 0x40001724;
ppTxProtoProc = 0x40001728;
ppTxqUpdateBitmap = 0x4000172c;
pp_coex_tx_request = 0x40001730;
/*pp_coex_tx_request = 0x40001730;*/
pp_hdrsize = 0x40001734;
pp_post = 0x40001738;
pp_process_hmac_waiting_txq = 0x4000173c;

2
components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
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@ -111,7 +111,7 @@ ppSubFromAMPDU = 0x40000d38;
//ppTxPkt = 0x40000d40;
ppTxProtoProc = 0x40000d44;
ppTxqUpdateBitmap = 0x40000d48;
pp_coex_tx_request = 0x40000d4c;
/*pp_coex_tx_request = 0x40000d4c;*/
pp_hdrsize = 0x40000d50;
pp_post = 0x40000d54;
pp_process_hmac_waiting_txq = 0x40000d58;

2
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
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@ -1894,7 +1894,7 @@ ppSubFromAMPDU = 0x40005694;
ppTxPkt = 0x400056ac;
ppTxProtoProc = 0x400056b8;
ppTxqUpdateBitmap = 0x400056c4;
pp_coex_tx_request = 0x400056d0;
/*pp_coex_tx_request = 0x400056d0;*/
pp_hdrsize = 0x400056dc;
pp_post = 0x400056e8;
pp_process_hmac_waiting_txq = 0x400056f4;

2
components/esp_system/port/soc/esp32c2/clk.c
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@ -246,7 +246,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */

2
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -289,7 +289,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */

2
components/esp_system/port/soc/esp32c6/clk.c
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@ -286,7 +286,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */

2
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -280,7 +280,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */

2
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -306,7 +306,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL32K | DPORT_LPCLK_SEL_XTAL | DPORT_LPCLK_SEL_8M | DPORT_LPCLK_SEL_RTC_SLOW);
DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);

2
components/esp_system/port/soc/esp32s3/clk.c
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@ -309,7 +309,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit 1d8de29af0ed77f82fd4f6eb581af6ee6bad847f
Subproject commit ac36b61c8b4845c435fb7318ff7bc00bb0abc6a6

5
examples/mesh/manual_networking/partitions.csv Normal file
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@ -0,0 +1,5 @@
# Name, Type, SubType, Offset, Size, Flags
# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
nvs, data, nvs, 0x9000, 0x6000,
phy_init, data, phy, 0xf000, 0x1000,
factory, app, factory, 0x10000, 1200K,
1 # Name, Type, SubType, Offset, Size, Flags
2 # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
3 nvs, data, nvs, 0x9000, 0x6000,
4 phy_init, data, phy, 0xf000, 0x1000,
5 factory, app, factory, 0x10000, 1200K,

5
examples/mesh/manual_networking/sdkconfig.defaults Normal file
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@ -0,0 +1,5 @@
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_OFFSET=0x8000
CONFIG_PARTITION_TABLE_MD5=y