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emac: optimise iperf performane

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This commit is contained in:
laokaiyao 2021-07-14 20:03:54 +08:00
parent 05d0298656
commit 8d18a9c614
5 changed files with 10 additions and 8 deletions
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2
components/esp_eth/include/esp_eth_mac.h
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@ -391,7 +391,7 @@ typedef struct {
#define ETH_MAC_DEFAULT_CONFIG() \
{ \
.sw_reset_timeout_ms = 100, \
.rx_task_stack_size = 4096, \
.rx_task_stack_size = 2048, \
.rx_task_prio = 15, \
.smi_mdc_gpio_num = 23, \
.smi_mdio_gpio_num = 18, \

2
components/esp_eth/src/esp_eth_mac_esp.c
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@ -353,7 +353,7 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
}
ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
/* set smi clock */
emac_hal_set_csr_clock_range(&emac->hal, esp_clk_apb_freq());
emac_hal_set_csr_clock_range(&emac->hal, esp_clk_apb_freq() / 1e6);
/* reset descriptor chain */
emac_hal_reset_desc_chain(&emac->hal);
/* init mac registers by default */

8
components/hal/emac_hal.c
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@ -141,7 +141,7 @@ void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
{
/* Tell MAC system clock Frequency, which will determine the frequency range of MDC(1MHz~2.5MHz) */
/* Tell MAC system clock Frequency in MHz, which will determine the frequency range of MDC(1MHz~2.5MHz) */
if (freq >= 20 && freq < 35) {
emac_ll_set_csr_clock_division(hal->mac_regs, 2); // CSR clock/16
} else if (freq >= 35 && freq < 60) {
@ -150,7 +150,7 @@ void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
emac_ll_set_csr_clock_division(hal->mac_regs, 0); // CSR clock/42
} else if (freq >= 100 && freq < 150) {
emac_ll_set_csr_clock_division(hal->mac_regs, 1); // CSR clock/62
} else if (freq > 150 && freq < 250) {
} else if (freq >= 150 && freq < 250) {
emac_ll_set_csr_clock_division(hal->mac_regs, 4); // CSR clock/102
} else {
emac_ll_set_csr_clock_division(hal->mac_regs, 5); // CSR clock/124
@ -281,8 +281,8 @@ void emac_hal_init_dma_default(emac_hal_context_t *hal)
emac_ll_recv_store_forward_enable(hal->dma_regs, true);
/* Enable Flushing of Received Frames because of the unavailability of receive descriptors or buffers */
emac_ll_flush_recv_frame_enable(hal->dma_regs, true);
/* Enable Transmit Store Forward */
emac_ll_trans_store_forward_enable(hal->dma_regs, true);
/* Disable Transmit Store Forward */
emac_ll_trans_store_forward_enable(hal->dma_regs, false);
/* Flush Transmit FIFO */
emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
/* Transmit Threshold Control */

4
components/hal/esp32/include/hal/emac_ll.h
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@ -137,7 +137,7 @@ extern "C" {
#define EMAC_LL_INTR_OVERFLOW_ENABLE 0x00000010U
#define EMAC_LL_INTR_UNDERFLOW_ENABLE 0x00000020U
#define EMAC_LL_INTR_RECEIVE_ENABLE 0x00000040U
#define EMAC_LL_INTR_REVEIVE_BUFF_UNAVAILABLE_ENABLE 0x00000080U
#define EMAC_LL_INTR_RECEIVE_BUFF_UNAVAILABLE_ENABLE 0x00000080U
#define EMAC_LL_INTR_RECEIVE_STOP_ENABLE 0x00000100U
#define EMAC_LL_INTR_RECEIVE_TIMEOUT_ENABLE 0x00000200U
#define EMAC_LL_INTR_TRANSMIT_FIRST_BYTE_ENABLE 0x00000400U
@ -406,7 +406,7 @@ static inline void emac_ll_flush_recv_frame_enable(emac_dma_dev_t *dma_regs, boo
static inline void emac_ll_trans_store_forward_enable(emac_dma_dev_t *dma_regs, bool enable)
{
dma_regs->dmaoperation_mode.tx_str_fwd = !enable;
dma_regs->dmaoperation_mode.tx_str_fwd = enable;
}
static inline void emac_ll_flush_trans_fifo_enable(emac_dma_dev_t *dma_regs, bool enable)

2
examples/ethernet/iperf/sdkconfig.defaults
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@ -12,4 +12,6 @@ CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
CONFIG_ESP_TASK_WDT=n
CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=n