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feat(soc): rename rtc_wdt_reg to lp_wdt_reg
This commit is contained in:
Armando
parent
0959c0cb96
commit
8cf0e5d5b8
@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,506 +11,313 @@
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extern "C" {
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#endif
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// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
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/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
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#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
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/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
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#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
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/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
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#define RTC_WDT_RESET_LENGTH_100_NS 0
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#define RTC_WDT_RESET_LENGTH_200_NS 1
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#define RTC_WDT_RESET_LENGTH_300_NS 2
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#define RTC_WDT_RESET_LENGTH_400_NS 3
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#define RTC_WDT_RESET_LENGTH_500_NS 4
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#define RTC_WDT_RESET_LENGTH_800_NS 5
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#define RTC_WDT_RESET_LENGTH_1600_NS 6
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#define RTC_WDT_RESET_LENGTH_3200_NS 7
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#define LP_WDT_RTC_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
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/* LP_WDT_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
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/*description: .*/
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#define LP_WDT_WDT_EN (BIT(31))
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#define LP_WDT_WDT_EN_M (BIT(31))
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#define LP_WDT_WDT_EN_V 0x1
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#define LP_WDT_WDT_EN_S 31
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/* LP_WDT_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
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/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
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reset stage en.*/
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#define LP_WDT_WDT_STG0 0x00000007
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#define LP_WDT_WDT_STG0_M ((LP_WDT_WDT_STG0_V)<<(LP_WDT_WDT_STG0_S))
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#define LP_WDT_WDT_STG0_V 0x7
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#define LP_WDT_WDT_STG0_S 28
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/* LP_WDT_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
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/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
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reset stage en.*/
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#define LP_WDT_WDT_STG1 0x00000007
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#define LP_WDT_WDT_STG1_M ((LP_WDT_WDT_STG1_V)<<(LP_WDT_WDT_STG1_S))
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#define LP_WDT_WDT_STG1_V 0x7
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#define LP_WDT_WDT_STG1_S 25
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/* LP_WDT_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
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/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
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reset stage en.*/
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#define LP_WDT_WDT_STG2 0x00000007
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#define LP_WDT_WDT_STG2_M ((LP_WDT_WDT_STG2_V)<<(LP_WDT_WDT_STG2_S))
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#define LP_WDT_WDT_STG2_V 0x7
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#define LP_WDT_WDT_STG2_S 22
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/* LP_WDT_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
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/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
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reset stage en.*/
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#define LP_WDT_WDT_STG3 0x00000007
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#define LP_WDT_WDT_STG3_M ((LP_WDT_WDT_STG3_V)<<(LP_WDT_WDT_STG3_S))
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#define LP_WDT_WDT_STG3_V 0x7
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#define LP_WDT_WDT_STG3_S 19
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/* LP_WDT_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
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/*description: CPU reset counter length.*/
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#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007
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#define LP_WDT_WDT_CPU_RESET_LENGTH_M ((LP_WDT_WDT_CPU_RESET_LENGTH_V)<<(LP_WDT_WDT_CPU_RESET_LENGTH_S))
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#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x7
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#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
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/* LP_WDT_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
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/*description: system reset counter length.*/
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#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007
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#define LP_WDT_WDT_SYS_RESET_LENGTH_M ((LP_WDT_WDT_SYS_RESET_LENGTH_V)<<(LP_WDT_WDT_SYS_RESET_LENGTH_S))
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#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x7
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#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
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/* LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
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/*description: enable WDT in flash boot.*/
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/** LP_WDT_CONFIG0_REG register
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* need_des
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*/
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#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
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/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
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* need_des
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*/
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#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
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#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
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#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
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#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
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/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
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#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
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#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
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#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
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/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
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#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
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#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
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#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
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/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
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* need_des
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*/
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#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
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#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (BIT(12))
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#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x1
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#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
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#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
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#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
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/* LP_WDT_WDT_PAUSE_IN_SLP : R/W ;bitpos:[11] ;default: 1'd1 ; */
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/*description: pause WDT in sleep.*/
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#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(11))
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#define LP_WDT_WDT_PAUSE_IN_SLP_M (BIT(11))
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#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x1
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#define LP_WDT_WDT_PAUSE_IN_SLP_S 11
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/* LP_WDT_WDT_CHIP_RESET_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
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/*description: wdt reset whole chip enable.*/
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#define LP_WDT_WDT_CHIP_RESET_EN (BIT(10))
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#define LP_WDT_WDT_CHIP_RESET_EN_M (BIT(10))
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#define LP_WDT_WDT_CHIP_RESET_EN_V 0x1
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#define LP_WDT_WDT_CHIP_RESET_EN_S 10
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/* LP_WDT_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[9:2] ;default: 8'd20 ; */
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/*description: chip reset siginal pulse width.*/
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#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FF
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#define LP_WDT_WDT_CHIP_RESET_WIDTH_M ((LP_WDT_WDT_CHIP_RESET_WIDTH_V)<<(LP_WDT_WDT_CHIP_RESET_WIDTH_S))
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#define LP_WDT_WDT_CHIP_RESET_WIDTH_V 0xFF
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#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 2
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/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
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* need_des
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*/
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#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
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#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
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#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
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#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
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/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
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* need_des
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*/
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#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
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#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
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#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
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#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
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/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_STG3 0x00000007U
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#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
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#define LP_WDT_WDT_STG3_V 0x00000007U
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#define LP_WDT_WDT_STG3_S 19
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/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_STG2 0x00000007U
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#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
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#define LP_WDT_WDT_STG2_V 0x00000007U
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#define LP_WDT_WDT_STG2_S 22
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/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_STG1 0x00000007U
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#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
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#define LP_WDT_WDT_STG1_V 0x00000007U
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#define LP_WDT_WDT_STG1_S 25
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/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_STG0 0x00000007U
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#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
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#define LP_WDT_WDT_STG0_V 0x00000007U
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#define LP_WDT_WDT_STG0_S 28
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/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
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* need_des
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*/
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#define LP_WDT_WDT_EN (BIT(31))
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#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
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#define LP_WDT_WDT_EN_V 0x00000001U
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#define LP_WDT_WDT_EN_S 31
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#define LP_WDT_RTC_WDTCPURST_REG (DR_REG_LP_WDT_BASE + 0x4)
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/* LP_WDT_WDT_CORE0CPU_RESET_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
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/*description: enable WDT reset CORE0 CPU.*/
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#define LP_WDT_WDT_CORE0CPU_RESET_EN (BIT(31))
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#define LP_WDT_WDT_CORE0CPU_RESET_EN_M (BIT(31))
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#define LP_WDT_WDT_CORE0CPU_RESET_EN_V 0x1
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#define LP_WDT_WDT_CORE0CPU_RESET_EN_S 31
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/* LP_WDT_WDT_CORE1CPU_RESET_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
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/*description: enable WDT reset CORE1 CPU.*/
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#define LP_WDT_WDT_CORE1CPU_RESET_EN (BIT(30))
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#define LP_WDT_WDT_CORE1CPU_RESET_EN_M (BIT(30))
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#define LP_WDT_WDT_CORE1CPU_RESET_EN_V 0x1
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#define LP_WDT_WDT_CORE1CPU_RESET_EN_S 30
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/* LP_WDT_WDT_CORE2CPU_RESET_EN : R/W ;bitpos:[29] ;default: 1'd0 ; */
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/*description: enable WDT reset CORE2 CPU.*/
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#define LP_WDT_WDT_CORE2CPU_RESET_EN (BIT(29))
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#define LP_WDT_WDT_CORE2CPU_RESET_EN_M (BIT(29))
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#define LP_WDT_WDT_CORE2CPU_RESET_EN_V 0x1
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#define LP_WDT_WDT_CORE2CPU_RESET_EN_S 29
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/* LP_WDT_WDT_CORE3CPU_RESET_EN : R/W ;bitpos:[28] ;default: 1'd0 ; */
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/*description: enable WDT reset CORE3 CPU.*/
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#define LP_WDT_WDT_CORE3CPU_RESET_EN (BIT(28))
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#define LP_WDT_WDT_CORE3CPU_RESET_EN_M (BIT(28))
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#define LP_WDT_WDT_CORE3CPU_RESET_EN_V 0x1
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#define LP_WDT_WDT_CORE3CPU_RESET_EN_S 28
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/* LP_WDT_WDT_LP_CPU_RESET_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
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/*description: enable WDT reset LP CPU.*/
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#define LP_WDT_WDT_LP_CPU_RESET_EN (BIT(27))
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#define LP_WDT_WDT_LP_CPU_RESET_EN_M (BIT(27))
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#define LP_WDT_WDT_LP_CPU_RESET_EN_V 0x1
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#define LP_WDT_WDT_LP_CPU_RESET_EN_S 27
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/* LP_WDT_WDT_LP_PERI_RESET_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
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/*description: enable WDT reset LP PERI.*/
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#define LP_WDT_WDT_LP_PERI_RESET_EN (BIT(26))
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#define LP_WDT_WDT_LP_PERI_RESET_EN_M (BIT(26))
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#define LP_WDT_WDT_LP_PERI_RESET_EN_V 0x1
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#define LP_WDT_WDT_LP_PERI_RESET_EN_S 26
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#define LP_WDT_RTC_WDTCONFIG1_REG (DR_REG_LP_WDT_BASE + 0x8)
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/* LP_WDT_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
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/*description: .*/
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#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFF
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#define LP_WDT_WDT_STG0_HOLD_M ((LP_WDT_WDT_STG0_HOLD_V)<<(LP_WDT_WDT_STG0_HOLD_S))
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#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFF
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/** LP_WDT_CONFIG1_REG register
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* need_des
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*/
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#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
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/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
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* need_des
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*/
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#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
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#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
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#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
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#define LP_WDT_WDT_STG0_HOLD_S 0
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#define LP_WDT_RTC_WDTCONFIG2_REG (DR_REG_LP_WDT_BASE + 0xC)
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/* LP_WDT_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
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/*description: .*/
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#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFF
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#define LP_WDT_WDT_STG1_HOLD_M ((LP_WDT_WDT_STG1_HOLD_V)<<(LP_WDT_WDT_STG1_HOLD_S))
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#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFF
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/** LP_WDT_CONFIG2_REG register
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* need_des
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*/
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#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
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/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
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* need_des
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*/
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#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
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#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
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#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
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#define LP_WDT_WDT_STG1_HOLD_S 0
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#define LP_WDT_RTC_WDTCONFIG3_REG (DR_REG_LP_WDT_BASE + 0x10)
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/* LP_WDT_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
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/*description: .*/
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#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFF
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#define LP_WDT_WDT_STG2_HOLD_M ((LP_WDT_WDT_STG2_HOLD_V)<<(LP_WDT_WDT_STG2_HOLD_S))
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#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFF
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/** LP_WDT_CONFIG3_REG register
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* need_des
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*/
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#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
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/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
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* need_des
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*/
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#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
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#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
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#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
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#define LP_WDT_WDT_STG2_HOLD_S 0
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#define LP_WDT_RTC_WDTCONFIG4_REG (DR_REG_LP_WDT_BASE + 0x14)
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/* LP_WDT_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
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/*description: .*/
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#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFF
|
||||
#define LP_WDT_WDT_STG3_HOLD_M ((LP_WDT_WDT_STG3_HOLD_V)<<(LP_WDT_WDT_STG3_HOLD_S))
|
||||
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFF
|
||||
/** LP_WDT_CONFIG4_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
|
||||
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
|
||||
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG3_HOLD_S 0
|
||||
|
||||
#define LP_WDT_RTC_WDTFEED_REG (DR_REG_LP_WDT_BASE + 0x18)
|
||||
/* LP_WDT_RTC_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define LP_WDT_RTC_WDT_FEED (BIT(31))
|
||||
#define LP_WDT_RTC_WDT_FEED_M (BIT(31))
|
||||
#define LP_WDT_RTC_WDT_FEED_V 0x1
|
||||
#define LP_WDT_RTC_WDT_FEED_S 31
|
||||
/** LP_WDT_FEED_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
|
||||
/** LP_WDT_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_FEED (BIT(31))
|
||||
#define LP_WDT_FEED_M (LP_WDT_FEED_V << LP_WDT_FEED_S)
|
||||
#define LP_WDT_FEED_V 0x00000001U
|
||||
#define LP_WDT_FEED_S 31
|
||||
|
||||
#define LP_WDT_RTC_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1C)
|
||||
/* LP_WDT_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
|
||||
/*description: .*/
|
||||
#define LP_WDT_WDT_WKEY 0xFFFFFFFF
|
||||
#define LP_WDT_WDT_WKEY_M ((LP_WDT_WDT_WKEY_V)<<(LP_WDT_WDT_WKEY_S))
|
||||
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFF
|
||||
/** LP_WDT_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
|
||||
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
|
||||
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_WKEY_S 0
|
||||
|
||||
#define LP_WDT_RTC_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x20)
|
||||
/* LP_WDT_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: automatically feed swd when int comes.*/
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(31))
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_M (BIT(31))
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x1
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_S 31
|
||||
/* LP_WDT_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b1 ; */
|
||||
/*description: disabel SWD.*/
|
||||
#define LP_WDT_SWD_DISABLE (BIT(30))
|
||||
#define LP_WDT_SWD_DISABLE_M (BIT(30))
|
||||
#define LP_WDT_SWD_DISABLE_V 0x1
|
||||
#define LP_WDT_SWD_DISABLE_S 30
|
||||
/* LP_WDT_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: Sw feed swd.*/
|
||||
#define LP_WDT_SWD_FEED (BIT(29))
|
||||
#define LP_WDT_SWD_FEED_M (BIT(29))
|
||||
#define LP_WDT_SWD_FEED_V 0x1
|
||||
#define LP_WDT_SWD_FEED_S 29
|
||||
/* LP_WDT_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: reset swd reset flag.*/
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(28))
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_M (BIT(28))
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x1
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_S 28
|
||||
/* LP_WDT_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
|
||||
/*description: adjust signal width send to swd.*/
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FF
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_M ((LP_WDT_SWD_SIGNAL_WIDTH_V)<<(LP_WDT_SWD_SIGNAL_WIDTH_S))
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x3FF
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_S 18
|
||||
/* LP_WDT_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: swd interrupt for feeding.*/
|
||||
#define LP_WDT_SWD_FEED_INT (BIT(1))
|
||||
#define LP_WDT_SWD_FEED_INT_M (BIT(1))
|
||||
#define LP_WDT_SWD_FEED_INT_V 0x1
|
||||
#define LP_WDT_SWD_FEED_INT_S 1
|
||||
/* LP_WDT_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: swd reset flag.*/
|
||||
/** LP_WDT_SWD_CONFIG_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
|
||||
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
|
||||
#define LP_WDT_SWD_RESET_FLAG_M (BIT(0))
|
||||
#define LP_WDT_SWD_RESET_FLAG_V 0x1
|
||||
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
|
||||
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
|
||||
#define LP_WDT_SWD_RESET_FLAG_S 0
|
||||
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
|
||||
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
|
||||
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
|
||||
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_DISABLE (BIT(30))
|
||||
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
|
||||
#define LP_WDT_SWD_DISABLE_V 0x00000001U
|
||||
#define LP_WDT_SWD_DISABLE_S 30
|
||||
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_FEED (BIT(31))
|
||||
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
|
||||
#define LP_WDT_SWD_FEED_V 0x00000001U
|
||||
#define LP_WDT_SWD_FEED_S 31
|
||||
|
||||
#define LP_WDT_RTC_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24)
|
||||
/* LP_WDT_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
|
||||
/*description: swd write protect.*/
|
||||
#define LP_WDT_SWD_WKEY 0xFFFFFFFF
|
||||
#define LP_WDT_SWD_WKEY_M ((LP_WDT_SWD_WKEY_V)<<(LP_WDT_SWD_WKEY_S))
|
||||
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFF
|
||||
/** LP_WDT_SWD_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
|
||||
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
|
||||
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
|
||||
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
|
||||
#define LP_WDT_SWD_WKEY_S 0
|
||||
|
||||
#define LP_WDT_WDT_CLK_EN_REG (DR_REG_LP_WDT_BASE + 0x28)
|
||||
/* LP_WDT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define LP_WDT_CLK_EN (BIT(0))
|
||||
#define LP_WDT_CLK_EN_M (BIT(0))
|
||||
#define LP_WDT_CLK_EN_V 0x1
|
||||
#define LP_WDT_CLK_EN_S 0
|
||||
/** LP_WDT_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
|
||||
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
|
||||
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
|
||||
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_RAW_S 31
|
||||
|
||||
#define LP_WDT_INT_ENA_RTC_W1TS_REG (DR_REG_LP_WDT_BASE + 0x2C)
|
||||
/* LP_WDT_RTC_SWD_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable super watch dog interrupt.*/
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TS (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TS_M (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TS_V 0x1
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TS_S 1
|
||||
/* LP_WDT_RTC_WDT_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable RTC WDT interrupt.*/
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TS (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TS_M (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TS_V 0x1
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TS_S 0
|
||||
/** LP_WDT_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
|
||||
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_S 30
|
||||
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
|
||||
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_ST_S 31
|
||||
|
||||
#define LP_WDT_INT_ENA_RTC_W1TC_REG (DR_REG_LP_WDT_BASE + 0x30)
|
||||
/* LP_WDT_RTC_SWD_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable super watch dog interrupt.*/
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TC (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TC_M (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TC_V 0x1
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_W1TC_S 1
|
||||
/* LP_WDT_RTC_WDT_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable RTC WDT interrupt.*/
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TC (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TC_M (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TC_V 0x1
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_W1TC_S 0
|
||||
/** LP_WDT_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
|
||||
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
|
||||
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
|
||||
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_ENA_S 31
|
||||
|
||||
#define LP_WDT_INT_ENA_RTC_REG (DR_REG_LP_WDT_BASE + 0x34)
|
||||
/* LP_WDT_RTC_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: enable xtal32k_dead interrupt.*/
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_M (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_V 0x1
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_S 2
|
||||
/* LP_WDT_RTC_SWD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable super watch dog interrupt.*/
|
||||
#define LP_WDT_RTC_SWD_INT_ENA (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_M (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_V 0x1
|
||||
#define LP_WDT_RTC_SWD_INT_ENA_S 1
|
||||
/* LP_WDT_RTC_WDT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable RTC WDT interrupt.*/
|
||||
#define LP_WDT_RTC_WDT_INT_ENA (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_M (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_V 0x1
|
||||
#define LP_WDT_RTC_WDT_INT_ENA_S 0
|
||||
|
||||
#define LP_WDT_INT_RAW_RTC_REG (DR_REG_LP_WDT_BASE + 0x38)
|
||||
/* LP_WDT_RTC_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: xtal32k dead detection interrupt raw.*/
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_M (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_V 0x1
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_S 2
|
||||
/* LP_WDT_RTC_SWD_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: super watch dog interrupt raw.*/
|
||||
#define LP_WDT_RTC_SWD_INT_RAW (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_RAW_M (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_RAW_V 0x1
|
||||
#define LP_WDT_RTC_SWD_INT_RAW_S 1
|
||||
/* LP_WDT_RTC_WDT_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: RTC WDT interrupt raw.*/
|
||||
#define LP_WDT_RTC_WDT_INT_RAW (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_RAW_M (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_RAW_V 0x1
|
||||
#define LP_WDT_RTC_WDT_INT_RAW_S 0
|
||||
|
||||
#define LP_WDT_INT_SWD_ST_RTC_REG (DR_REG_LP_WDT_BASE + 0x3C)
|
||||
/* LP_WDT_RTC_XTAL32K_DEAD_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: xtal32k dead detection interrupt state.*/
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_M (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_V 0x1
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_S 2
|
||||
/* LP_WDT_RTC_SWD_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: super watch dog interrupt state.*/
|
||||
#define LP_WDT_RTC_SWD_INT_ST (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ST_M (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_ST_V 0x1
|
||||
#define LP_WDT_RTC_SWD_INT_ST_S 1
|
||||
/* LP_WDT_RTC_WDT_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: watch dog interrupt state.*/
|
||||
#define LP_WDT_RTC_WDT_INT_ST (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ST_M (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_ST_V 0x1
|
||||
#define LP_WDT_RTC_WDT_INT_ST_S 0
|
||||
|
||||
#define LP_WDT_INT_CLR_RTC_REG (DR_REG_LP_WDT_BASE + 0x40)
|
||||
/* LP_WDT_RTC_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Clear RTC WDT interrupt state.*/
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_M (BIT(2))
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_V 0x1
|
||||
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_S 2
|
||||
/* LP_WDT_RTC_SWD_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Clear super watch dog interrupt state.*/
|
||||
#define LP_WDT_RTC_SWD_INT_CLR (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_CLR_M (BIT(1))
|
||||
#define LP_WDT_RTC_SWD_INT_CLR_V 0x1
|
||||
#define LP_WDT_RTC_SWD_INT_CLR_S 1
|
||||
/* LP_WDT_RTC_WDT_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Clear RTC WDT interrupt state.*/
|
||||
#define LP_WDT_RTC_WDT_INT_CLR (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_CLR_M (BIT(0))
|
||||
#define LP_WDT_RTC_WDT_INT_CLR_V 0x1
|
||||
#define LP_WDT_RTC_WDT_INT_CLR_S 0
|
||||
|
||||
#define LP_WDT_RTC_EXT_XTL_CONF_REG (DR_REG_LP_WDT_BASE + 0x44)
|
||||
/* LP_WDT_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define LP_WDT_XTL_EXT_CTR_EN (BIT(31))
|
||||
#define LP_WDT_XTL_EXT_CTR_EN_M (BIT(31))
|
||||
#define LP_WDT_XTL_EXT_CTR_EN_V 0x1
|
||||
#define LP_WDT_XTL_EXT_CTR_EN_S 31
|
||||
/* LP_WDT_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: 0: power down XTAL at high level; 1: power down XTAL at low level.*/
|
||||
#define LP_WDT_XTL_EXT_CTR_LV (BIT(30))
|
||||
#define LP_WDT_XTL_EXT_CTR_LV_M (BIT(30))
|
||||
#define LP_WDT_XTL_EXT_CTR_LV_V 0x1
|
||||
#define LP_WDT_XTL_EXT_CTR_LV_S 30
|
||||
/* LP_WDT_RTC_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
|
||||
/*description: XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C.*/
|
||||
#define LP_WDT_RTC_XTAL32K_GPIO_SEL (BIT(23))
|
||||
#define LP_WDT_RTC_XTAL32K_GPIO_SEL_M (BIT(23))
|
||||
#define LP_WDT_RTC_XTAL32K_GPIO_SEL_V 0x1
|
||||
#define LP_WDT_RTC_XTAL32K_GPIO_SEL_S 23
|
||||
/* LP_WDT_RTC_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
|
||||
/*description: state of 32k_wdt.*/
|
||||
#define LP_WDT_RTC_WDT_STATE 0x00000007
|
||||
#define LP_WDT_RTC_WDT_STATE_M ((LP_WDT_RTC_WDT_STATE_V)<<(LP_WDT_RTC_WDT_STATE_S))
|
||||
#define LP_WDT_RTC_WDT_STATE_V 0x7
|
||||
#define LP_WDT_RTC_WDT_STATE_S 20
|
||||
/* LP_WDT_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
|
||||
/*description: DAC_XTAL_32K.*/
|
||||
#define LP_WDT_DAC_XTAL_32K 0x00000007
|
||||
#define LP_WDT_DAC_XTAL_32K_M ((LP_WDT_DAC_XTAL_32K_V)<<(LP_WDT_DAC_XTAL_32K_S))
|
||||
#define LP_WDT_DAC_XTAL_32K_V 0x7
|
||||
#define LP_WDT_DAC_XTAL_32K_S 17
|
||||
/* LP_WDT_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
|
||||
/*description: XPD_XTAL_32K.*/
|
||||
#define LP_WDT_XPD_XTAL_32K (BIT(16))
|
||||
#define LP_WDT_XPD_XTAL_32K_M (BIT(16))
|
||||
#define LP_WDT_XPD_XTAL_32K_V 0x1
|
||||
#define LP_WDT_XPD_XTAL_32K_S 16
|
||||
/* LP_WDT_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
|
||||
/*description: DRES_XTAL_32K.*/
|
||||
#define LP_WDT_DRES_XTAL_32K 0x00000007
|
||||
#define LP_WDT_DRES_XTAL_32K_M ((LP_WDT_DRES_XTAL_32K_V)<<(LP_WDT_DRES_XTAL_32K_S))
|
||||
#define LP_WDT_DRES_XTAL_32K_V 0x7
|
||||
#define LP_WDT_DRES_XTAL_32K_S 13
|
||||
/* LP_WDT_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
|
||||
/*description: xtal_32k gm control.*/
|
||||
#define LP_WDT_DGM_XTAL_32K 0x00000007
|
||||
#define LP_WDT_DGM_XTAL_32K_M ((LP_WDT_DGM_XTAL_32K_V)<<(LP_WDT_DGM_XTAL_32K_S))
|
||||
#define LP_WDT_DGM_XTAL_32K_V 0x7
|
||||
#define LP_WDT_DGM_XTAL_32K_S 10
|
||||
/* LP_WDT_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: 0: single-end buffer 1: differential buffer.*/
|
||||
#define LP_WDT_DBUF_XTAL_32K (BIT(9))
|
||||
#define LP_WDT_DBUF_XTAL_32K_M (BIT(9))
|
||||
#define LP_WDT_DBUF_XTAL_32K_V 0x1
|
||||
#define LP_WDT_DBUF_XTAL_32K_S 9
|
||||
/* LP_WDT_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: apply an internal clock to help xtal 32k to start.*/
|
||||
#define LP_WDT_ENCKINIT_XTAL_32K (BIT(8))
|
||||
#define LP_WDT_ENCKINIT_XTAL_32K_M (BIT(8))
|
||||
#define LP_WDT_ENCKINIT_XTAL_32K_V 0x1
|
||||
#define LP_WDT_ENCKINIT_XTAL_32K_S 8
|
||||
/* LP_WDT_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: Xtal 32k xpd control by sw or fsm.*/
|
||||
#define LP_WDT_XTAL32K_XPD_FORCE (BIT(7))
|
||||
#define LP_WDT_XTAL32K_XPD_FORCE_M (BIT(7))
|
||||
#define LP_WDT_XTAL32K_XPD_FORCE_V 0x1
|
||||
#define LP_WDT_XTAL32K_XPD_FORCE_S 7
|
||||
/* LP_WDT_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k switch back xtal when xtal is restarted.*/
|
||||
#define LP_WDT_XTAL32K_AUTO_RETURN (BIT(6))
|
||||
#define LP_WDT_XTAL32K_AUTO_RETURN_M (BIT(6))
|
||||
#define LP_WDT_XTAL32K_AUTO_RETURN_V 0x1
|
||||
#define LP_WDT_XTAL32K_AUTO_RETURN_S 6
|
||||
/* LP_WDT_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k restart xtal when xtal is dead.*/
|
||||
#define LP_WDT_XTAL32K_AUTO_RESTART (BIT(5))
|
||||
#define LP_WDT_XTAL32K_AUTO_RESTART_M (BIT(5))
|
||||
#define LP_WDT_XTAL32K_AUTO_RESTART_V 0x1
|
||||
#define LP_WDT_XTAL32K_AUTO_RESTART_S 5
|
||||
/* LP_WDT_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k switch to back up clock when xtal is dead.*/
|
||||
#define LP_WDT_XTAL32K_AUTO_BACKUP (BIT(4))
|
||||
#define LP_WDT_XTAL32K_AUTO_BACKUP_M (BIT(4))
|
||||
#define LP_WDT_XTAL32K_AUTO_BACKUP_V 0x1
|
||||
#define LP_WDT_XTAL32K_AUTO_BACKUP_S 4
|
||||
/* LP_WDT_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k external xtal clock force on.*/
|
||||
#define LP_WDT_XTAL32K_EXT_CLK_FO (BIT(3))
|
||||
#define LP_WDT_XTAL32K_EXT_CLK_FO_M (BIT(3))
|
||||
#define LP_WDT_XTAL32K_EXT_CLK_FO_V 0x1
|
||||
#define LP_WDT_XTAL32K_EXT_CLK_FO_S 3
|
||||
/* LP_WDT_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k watch dog sw reset.*/
|
||||
#define LP_WDT_XTAL32K_WDT_RESET (BIT(2))
|
||||
#define LP_WDT_XTAL32K_WDT_RESET_M (BIT(2))
|
||||
#define LP_WDT_XTAL32K_WDT_RESET_V 0x1
|
||||
#define LP_WDT_XTAL32K_WDT_RESET_S 2
|
||||
/* LP_WDT_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k watch dog clock force on.*/
|
||||
#define LP_WDT_XTAL32K_WDT_CLK_FO (BIT(1))
|
||||
#define LP_WDT_XTAL32K_WDT_CLK_FO_M (BIT(1))
|
||||
#define LP_WDT_XTAL32K_WDT_CLK_FO_V 0x1
|
||||
#define LP_WDT_XTAL32K_WDT_CLK_FO_S 1
|
||||
/* LP_WDT_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: xtal 32k watch dog enable.*/
|
||||
#define LP_WDT_XTAL32K_WDT_EN (BIT(0))
|
||||
#define LP_WDT_XTAL32K_WDT_EN_M (BIT(0))
|
||||
#define LP_WDT_XTAL32K_WDT_EN_V 0x1
|
||||
#define LP_WDT_XTAL32K_WDT_EN_S 0
|
||||
|
||||
#define LP_WDT_RTC_XTAL32K_CLK_FACTOR_REG (DR_REG_LP_WDT_BASE + 0x48)
|
||||
/* LP_WDT_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: xtal 32k watch dog backup clock factor.*/
|
||||
#define LP_WDT_XTAL32K_CLK_FACTOR 0xFFFFFFFF
|
||||
#define LP_WDT_XTAL32K_CLK_FACTOR_M ((LP_WDT_XTAL32K_CLK_FACTOR_V)<<(LP_WDT_XTAL32K_CLK_FACTOR_S))
|
||||
#define LP_WDT_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF
|
||||
#define LP_WDT_XTAL32K_CLK_FACTOR_S 0
|
||||
|
||||
#define LP_WDT_RTC_XTAL32K_CONF_REG (DR_REG_LP_WDT_BASE + 0x5C)
|
||||
/* LP_WDT_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
|
||||
/*description: if restarted xtal32k period is smaller than this, it is regarded as stable.*/
|
||||
#define LP_WDT_XTAL32K_STABLE_THRES 0x0000000F
|
||||
#define LP_WDT_XTAL32K_STABLE_THRES_M ((LP_WDT_XTAL32K_STABLE_THRES_V)<<(LP_WDT_XTAL32K_STABLE_THRES_S))
|
||||
#define LP_WDT_XTAL32K_STABLE_THRES_V 0xF
|
||||
#define LP_WDT_XTAL32K_STABLE_THRES_S 28
|
||||
/* LP_WDT_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
|
||||
/*description: If no clock detected for this amount of time,32k is regarded as dead.*/
|
||||
#define LP_WDT_XTAL32K_WDT_TIMEOUT 0x000000FF
|
||||
#define LP_WDT_XTAL32K_WDT_TIMEOUT_M ((LP_WDT_XTAL32K_WDT_TIMEOUT_V)<<(LP_WDT_XTAL32K_WDT_TIMEOUT_S))
|
||||
#define LP_WDT_XTAL32K_WDT_TIMEOUT_V 0xFF
|
||||
#define LP_WDT_XTAL32K_WDT_TIMEOUT_S 20
|
||||
/* LP_WDT_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
|
||||
/*description: cycles to wait to repower on xtal 32k.*/
|
||||
#define LP_WDT_XTAL32K_RESTART_WAIT 0x0000FFFF
|
||||
#define LP_WDT_XTAL32K_RESTART_WAIT_M ((LP_WDT_XTAL32K_RESTART_WAIT_V)<<(LP_WDT_XTAL32K_RESTART_WAIT_S))
|
||||
#define LP_WDT_XTAL32K_RESTART_WAIT_V 0xFFFF
|
||||
#define LP_WDT_XTAL32K_RESTART_WAIT_S 4
|
||||
/* LP_WDT_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
|
||||
/*description: cycles to wait to return noral xtal 32k.*/
|
||||
#define LP_WDT_XTAL32K_RETURN_WAIT 0x0000000F
|
||||
#define LP_WDT_XTAL32K_RETURN_WAIT_M ((LP_WDT_XTAL32K_RETURN_WAIT_V)<<(LP_WDT_XTAL32K_RETURN_WAIT_S))
|
||||
#define LP_WDT_XTAL32K_RETURN_WAIT_V 0xF
|
||||
#define LP_WDT_XTAL32K_RETURN_WAIT_S 0
|
||||
|
||||
#define LP_WDT_RTC_EFUSE_FORCE_REG (DR_REG_LP_WDT_BASE + 0x60)
|
||||
/* LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: lp_wdt flashboot en default choose efuse control bit.*/
|
||||
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE (BIT(1))
|
||||
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_M (BIT(1))
|
||||
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_V 0x1
|
||||
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_S 1
|
||||
/* LP_WDT_SWD_DISABLE_EFUSE_FORCE : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: swd disable default choose efuse control bit.*/
|
||||
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE (BIT(0))
|
||||
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_M (BIT(0))
|
||||
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_V 0x1
|
||||
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_S 0
|
||||
/** LP_WDT_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
|
||||
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
|
||||
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
|
||||
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_CLR_S 31
|
||||
|
||||
/** LP_WDT_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
|
||||
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
|
||||
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
|
||||
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
|
||||
#define LP_WDT_LP_WDT_DATE_S 0
|
||||
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CLK_EN (BIT(31))
|
||||
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
|
||||
#define LP_WDT_CLK_EN_V 0x00000001U
|
||||
#define LP_WDT_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -10,171 +10,301 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 2;
|
||||
uint32_t wdt_chip_reset_width : 8; /*chip reset siginal pulse width*/
|
||||
uint32_t wdt_chip_reset_en : 1; /*wdt reset whole chip enable*/
|
||||
uint32_t wdt_pause_in_slp : 1; /*pause WDT in sleep*/
|
||||
uint32_t wdt_flashboot_mod_en : 1; /*enable WDT in flash boot*/
|
||||
uint32_t wdt_sys_reset_length : 3; /*system reset counter length*/
|
||||
uint32_t wdt_cpu_reset_length : 3; /*CPU reset counter length*/
|
||||
uint32_t wdt_stg3 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
|
||||
uint32_t wdt_stg2 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
|
||||
uint32_t wdt_stg1 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
|
||||
uint32_t wdt_stg0 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
|
||||
uint32_t wdt_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdtconfig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t wdt_lp_peri_reset_en : 1; /*enable WDT reset LP PERI*/
|
||||
uint32_t wdt_lp_cpu_reset_en : 1; /*enable WDT reset LP CPU*/
|
||||
uint32_t wdt_core3cpu_reset_en : 1; /*enable WDT reset CORE3 CPU*/
|
||||
uint32_t wdt_core2cpu_reset_en : 1; /*enable WDT reset CORE2 CPU*/
|
||||
uint32_t wdt_core1cpu_reset_en : 1; /*enable WDT reset CORE1 CPU*/
|
||||
uint32_t wdt_core0cpu_reset_en : 1; /*enable WDT reset CORE0 CPU*/
|
||||
};
|
||||
uint32_t val;
|
||||
} wdtcpurst;
|
||||
uint32_t wdtconfig1;
|
||||
uint32_t wdtconfig2;
|
||||
uint32_t wdtconfig3;
|
||||
uint32_t wdtconfig4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t wdt_feed : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdtfeed;
|
||||
uint32_t wdtwprotect;
|
||||
union {
|
||||
struct {
|
||||
uint32_t swd_reset_flag : 1; /*swd reset flag*/
|
||||
uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/
|
||||
uint32_t reserved2 : 16;
|
||||
uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/
|
||||
uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/
|
||||
uint32_t swd_feed : 1; /*Sw feed swd*/
|
||||
uint32_t swd_disable : 1; /*disabel SWD*/
|
||||
uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/
|
||||
};
|
||||
uint32_t val;
|
||||
} swd_conf;
|
||||
uint32_t swd_wprotect;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdt_clk_en;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdt : 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t swd : 1; /*enable super watch dog interrupt*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdt : 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t swd : 1; /*enable super watch dog interrupt*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdt : 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t swd : 1; /*enable super watch dog interrupt*/
|
||||
uint32_t xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdt : 1; /*RTC WDT interrupt raw*/
|
||||
uint32_t swd : 1; /*super watch dog interrupt raw*/
|
||||
uint32_t xtal32k_dead : 1; /*xtal32k dead detection interrupt raw*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdt : 1; /*watch dog interrupt state*/
|
||||
uint32_t swd : 1; /*super watch dog interrupt state*/
|
||||
uint32_t xtal32k_dead : 1; /*xtal32k dead detection interrupt state*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_swd_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdt : 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t swd : 1; /*Clear super watch dog interrupt state*/
|
||||
uint32_t xtal32k_dead : 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_wdt_en : 1; /*xtal 32k watch dog enable*/
|
||||
uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/
|
||||
uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/
|
||||
uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/
|
||||
uint32_t xtal32k_auto_backup : 1; /*xtal 32k switch to back up clock when xtal is dead*/
|
||||
uint32_t xtal32k_auto_restart : 1; /*xtal 32k restart xtal when xtal is dead*/
|
||||
uint32_t xtal32k_auto_return : 1; /*xtal 32k switch back xtal when xtal is restarted*/
|
||||
uint32_t xtal32k_xpd_force : 1; /*Xtal 32k xpd control by sw or fsm*/
|
||||
uint32_t enckinit_xtal_32k : 1; /*apply an internal clock to help xtal 32k to start*/
|
||||
uint32_t dbuf_xtal_32k : 1; /*0: single-end buffer 1: differential buffer*/
|
||||
uint32_t dgm_xtal_32k : 3; /*xtal_32k gm control*/
|
||||
uint32_t dres_xtal_32k : 3; /*DRES_XTAL_32K*/
|
||||
uint32_t xpd_xtal_32k : 1; /*XPD_XTAL_32K*/
|
||||
uint32_t dac_xtal_32k : 3; /*DAC_XTAL_32K*/
|
||||
uint32_t wdt_state : 3; /*state of 32k_wdt*/
|
||||
uint32_t xtal32k_gpio_sel : 1; /*XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C*/
|
||||
uint32_t reserved24 : 6;
|
||||
uint32_t xtl_ext_ctr_lv : 1; /*0: power down XTAL at high level; 1: power down XTAL at low level*/
|
||||
uint32_t xtl_ext_ctr_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_xtl_conf;
|
||||
uint32_t xtal32k_clk_factor;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/
|
||||
uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/
|
||||
uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time,32k is regarded as dead*/
|
||||
uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this, it is regarded as stable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal32k_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t swd_disable_efuse_force : 1; /*swd disable default choose efuse control bit*/
|
||||
uint32_t wdt_flashboot_efuse_force : 1; /*lp_wdt flashboot en default choose efuse control bit*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_force;
|
||||
/** Group: configure_register */
|
||||
/** Type of config0 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_pause_in_slp:1;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en:1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en:1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en:1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length:3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length:3;
|
||||
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg3:3;
|
||||
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg2:3;
|
||||
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg1:3;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg0:3;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config0_reg_t;
|
||||
|
||||
/** Type of config1 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config1_reg_t;
|
||||
|
||||
/** Type of config2 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config2_reg_t;
|
||||
|
||||
/** Type of config3 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config3_reg_t;
|
||||
|
||||
/** Type of config4 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config4_reg_t;
|
||||
|
||||
/** Type of feed register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** feed : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_feed_reg_t;
|
||||
|
||||
/** Type of wprotect register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_wprotect_reg_t;
|
||||
|
||||
/** Type of swd_config register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_reset_flag:1;
|
||||
uint32_t reserved_1:17;
|
||||
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_auto_feed_en:1;
|
||||
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_rst_flag_clr:1;
|
||||
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_signal_width:10;
|
||||
/** swd_disable : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_disable:1;
|
||||
/** swd_feed : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_swd_config_reg_t;
|
||||
|
||||
/** Type of swd_wprotect register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_swd_wprotect_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_raw:1;
|
||||
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_raw:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_st:1;
|
||||
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_st:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_ena:1;
|
||||
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_ena:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_clr:1;
|
||||
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_clr_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_date:31;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile lp_wdt_config0_reg_t config0;
|
||||
volatile lp_wdt_config1_reg_t config1;
|
||||
volatile lp_wdt_config2_reg_t config2;
|
||||
volatile lp_wdt_config3_reg_t config3;
|
||||
volatile lp_wdt_config4_reg_t config4;
|
||||
volatile lp_wdt_feed_reg_t feed;
|
||||
volatile lp_wdt_wprotect_reg_t wprotect;
|
||||
volatile lp_wdt_swd_config_reg_t swd_config;
|
||||
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
|
||||
volatile lp_wdt_int_raw_reg_t int_raw;
|
||||
volatile lp_wdt_int_st_reg_t int_st;
|
||||
volatile lp_wdt_int_ena_reg_t int_ena;
|
||||
volatile lp_wdt_int_clr_reg_t int_clr;
|
||||
uint32_t reserved_034[242];
|
||||
volatile lp_wdt_date_reg_t date;
|
||||
} lp_wdt_dev_t;
|
||||
|
||||
extern lp_wdt_dev_t LP_WDT;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,324 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** RTC_WDT_CONFIG0_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG0_REG (DR_REG_RTC_WDT_BASE + 0x0)
|
||||
/** RTC_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP (BIT(9))
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP_M (RTC_WDT_WDT_PAUSE_IN_SLP_V << RTC_WDT_WDT_PAUSE_IN_SLP_S)
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP_S 9
|
||||
/** RTC_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN (BIT(10))
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN_M (RTC_WDT_WDT_APPCPU_RESET_EN_V << RTC_WDT_WDT_APPCPU_RESET_EN_S)
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN_S 10
|
||||
/** RTC_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN (BIT(11))
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN_M (RTC_WDT_WDT_PROCPU_RESET_EN_V << RTC_WDT_WDT_PROCPU_RESET_EN_S)
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN_S 11
|
||||
/** RTC_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_M (RTC_WDT_WDT_FLASHBOOT_MOD_EN_V << RTC_WDT_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_S 12
|
||||
/** RTC_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH_M (RTC_WDT_WDT_SYS_RESET_LENGTH_V << RTC_WDT_WDT_SYS_RESET_LENGTH_S)
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH_S 13
|
||||
/** RTC_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH_M (RTC_WDT_WDT_CPU_RESET_LENGTH_V << RTC_WDT_WDT_CPU_RESET_LENGTH_S)
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH_S 16
|
||||
/** RTC_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG3 0x00000007U
|
||||
#define RTC_WDT_WDT_STG3_M (RTC_WDT_WDT_STG3_V << RTC_WDT_WDT_STG3_S)
|
||||
#define RTC_WDT_WDT_STG3_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG3_S 19
|
||||
/** RTC_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG2 0x00000007U
|
||||
#define RTC_WDT_WDT_STG2_M (RTC_WDT_WDT_STG2_V << RTC_WDT_WDT_STG2_S)
|
||||
#define RTC_WDT_WDT_STG2_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG2_S 22
|
||||
/** RTC_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG1 0x00000007U
|
||||
#define RTC_WDT_WDT_STG1_M (RTC_WDT_WDT_STG1_V << RTC_WDT_WDT_STG1_S)
|
||||
#define RTC_WDT_WDT_STG1_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG1_S 25
|
||||
/** RTC_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG0 0x00000007U
|
||||
#define RTC_WDT_WDT_STG0_M (RTC_WDT_WDT_STG0_V << RTC_WDT_WDT_STG0_S)
|
||||
#define RTC_WDT_WDT_STG0_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG0_S 28
|
||||
/** RTC_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_EN (BIT(31))
|
||||
#define RTC_WDT_WDT_EN_M (RTC_WDT_WDT_EN_V << RTC_WDT_WDT_EN_S)
|
||||
#define RTC_WDT_WDT_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_EN_S 31
|
||||
|
||||
/** RTC_WDT_CONFIG1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG1_REG (DR_REG_RTC_WDT_BASE + 0x4)
|
||||
/** RTC_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG0_HOLD_M (RTC_WDT_WDT_STG0_HOLD_V << RTC_WDT_WDT_STG0_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_CONFIG2_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG2_REG (DR_REG_RTC_WDT_BASE + 0x8)
|
||||
/** RTC_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG1_HOLD_M (RTC_WDT_WDT_STG1_HOLD_V << RTC_WDT_WDT_STG1_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_CONFIG3_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG3_REG (DR_REG_RTC_WDT_BASE + 0xc)
|
||||
/** RTC_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG2_HOLD_M (RTC_WDT_WDT_STG2_HOLD_V << RTC_WDT_WDT_STG2_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_CONFIG4_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG4_REG (DR_REG_RTC_WDT_BASE + 0x10)
|
||||
/** RTC_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG3_HOLD_M (RTC_WDT_WDT_STG3_HOLD_V << RTC_WDT_WDT_STG3_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_FEED_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_FEED_REG (DR_REG_RTC_WDT_BASE + 0x14)
|
||||
/** RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_FEED (BIT(31))
|
||||
#define RTC_WDT_FEED_M (RTC_WDT_FEED_V << RTC_WDT_FEED_S)
|
||||
#define RTC_WDT_FEED_V 0x00000001U
|
||||
#define RTC_WDT_FEED_S 31
|
||||
|
||||
/** RTC_WDT_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x18)
|
||||
/** RTC_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_WKEY 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_WKEY_M (RTC_WDT_WDT_WKEY_V << RTC_WDT_WDT_WKEY_S)
|
||||
#define RTC_WDT_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_WKEY_S 0
|
||||
|
||||
/** RTC_WDT_SWD_CONFIG_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_CONFIG_REG (DR_REG_RTC_WDT_BASE + 0x1c)
|
||||
/** RTC_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_RESET_FLAG (BIT(0))
|
||||
#define RTC_WDT_SWD_RESET_FLAG_M (RTC_WDT_SWD_RESET_FLAG_V << RTC_WDT_SWD_RESET_FLAG_S)
|
||||
#define RTC_WDT_SWD_RESET_FLAG_V 0x00000001U
|
||||
#define RTC_WDT_SWD_RESET_FLAG_S 0
|
||||
/** RTC_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN (BIT(18))
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN_M (RTC_WDT_SWD_AUTO_FEED_EN_V << RTC_WDT_SWD_AUTO_FEED_EN_S)
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN_S 18
|
||||
/** RTC_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR (BIT(19))
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR_M (RTC_WDT_SWD_RST_FLAG_CLR_V << RTC_WDT_SWD_RST_FLAG_CLR_S)
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR_S 19
|
||||
/** RTC_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH_M (RTC_WDT_SWD_SIGNAL_WIDTH_V << RTC_WDT_SWD_SIGNAL_WIDTH_S)
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH_S 20
|
||||
/** RTC_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_DISABLE (BIT(30))
|
||||
#define RTC_WDT_SWD_DISABLE_M (RTC_WDT_SWD_DISABLE_V << RTC_WDT_SWD_DISABLE_S)
|
||||
#define RTC_WDT_SWD_DISABLE_V 0x00000001U
|
||||
#define RTC_WDT_SWD_DISABLE_S 30
|
||||
/** RTC_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_FEED (BIT(31))
|
||||
#define RTC_WDT_SWD_FEED_M (RTC_WDT_SWD_FEED_V << RTC_WDT_SWD_FEED_S)
|
||||
#define RTC_WDT_SWD_FEED_V 0x00000001U
|
||||
#define RTC_WDT_SWD_FEED_S 31
|
||||
|
||||
/** RTC_WDT_SWD_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x20)
|
||||
/** RTC_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_WKEY 0xFFFFFFFFU
|
||||
#define RTC_WDT_SWD_WKEY_M (RTC_WDT_SWD_WKEY_V << RTC_WDT_SWD_WKEY_S)
|
||||
#define RTC_WDT_SWD_WKEY_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_SWD_WKEY_S 0
|
||||
|
||||
/** RTC_WDT_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_RAW_REG (DR_REG_RTC_WDT_BASE + 0x24)
|
||||
/** RTC_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW_M (RTC_WDT_SUPER_WDT_INT_RAW_V << RTC_WDT_SUPER_WDT_INT_RAW_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_RAW (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_RAW_M (RTC_WDT_LP_WDT_INT_RAW_V << RTC_WDT_LP_WDT_INT_RAW_S)
|
||||
#define RTC_WDT_LP_WDT_INT_RAW_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_RAW_S 31
|
||||
|
||||
/** RTC_WDT_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_ST_REG (DR_REG_RTC_WDT_BASE + 0x28)
|
||||
/** RTC_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST_M (RTC_WDT_SUPER_WDT_INT_ST_V << RTC_WDT_SUPER_WDT_INT_ST_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_ST (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_ST_M (RTC_WDT_LP_WDT_INT_ST_V << RTC_WDT_LP_WDT_INT_ST_S)
|
||||
#define RTC_WDT_LP_WDT_INT_ST_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_ST_S 31
|
||||
|
||||
/** RTC_WDT_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_ENA_REG (DR_REG_RTC_WDT_BASE + 0x2c)
|
||||
/** RTC_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA_M (RTC_WDT_SUPER_WDT_INT_ENA_V << RTC_WDT_SUPER_WDT_INT_ENA_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_ENA (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_ENA_M (RTC_WDT_LP_WDT_INT_ENA_V << RTC_WDT_LP_WDT_INT_ENA_S)
|
||||
#define RTC_WDT_LP_WDT_INT_ENA_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_ENA_S 31
|
||||
|
||||
/** RTC_WDT_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_CLR_REG (DR_REG_RTC_WDT_BASE + 0x30)
|
||||
/** RTC_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR_M (RTC_WDT_SUPER_WDT_INT_CLR_V << RTC_WDT_SUPER_WDT_INT_CLR_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_CLR (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_CLR_M (RTC_WDT_LP_WDT_INT_CLR_V << RTC_WDT_LP_WDT_INT_CLR_S)
|
||||
#define RTC_WDT_LP_WDT_INT_CLR_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_CLR_S 31
|
||||
|
||||
/** RTC_WDT_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_DATE_REG (DR_REG_RTC_WDT_BASE + 0x3fc)
|
||||
/** RTC_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_DATE 0x7FFFFFFFU
|
||||
#define RTC_WDT_LP_WDT_DATE_M (RTC_WDT_LP_WDT_DATE_V << RTC_WDT_LP_WDT_DATE_S)
|
||||
#define RTC_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
|
||||
#define RTC_WDT_LP_WDT_DATE_S 0
|
||||
/** RTC_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CLK_EN (BIT(31))
|
||||
#define RTC_WDT_CLK_EN_M (RTC_WDT_CLK_EN_V << RTC_WDT_CLK_EN_S)
|
||||
#define RTC_WDT_CLK_EN_V 0x00000001U
|
||||
#define RTC_WDT_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,309 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: configure_register */
|
||||
/** Type of config0 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_pause_in_slp:1;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en:1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en:1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en:1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length:3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length:3;
|
||||
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg3:3;
|
||||
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg2:3;
|
||||
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg1:3;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg0:3;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_config0_reg_t;
|
||||
|
||||
/** Type of config1 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_config1_reg_t;
|
||||
|
||||
/** Type of config2 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_config2_reg_t;
|
||||
|
||||
/** Type of config3 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_config3_reg_t;
|
||||
|
||||
/** Type of config4 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_config4_reg_t;
|
||||
|
||||
/** Type of feed register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** feed : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_feed_reg_t;
|
||||
|
||||
/** Type of wprotect register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_wprotect_reg_t;
|
||||
|
||||
/** Type of swd_config register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_reset_flag:1;
|
||||
uint32_t reserved_1:17;
|
||||
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_auto_feed_en:1;
|
||||
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_rst_flag_clr:1;
|
||||
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_signal_width:10;
|
||||
/** swd_disable : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_disable:1;
|
||||
/** swd_feed : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_swd_config_reg_t;
|
||||
|
||||
/** Type of swd_wprotect register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_swd_wprotect_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_raw:1;
|
||||
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_raw:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_st:1;
|
||||
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_st:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_ena:1;
|
||||
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_ena:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_clr:1;
|
||||
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_int_clr_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_date:31;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_wdt_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile rtc_wdt_config0_reg_t config0;
|
||||
volatile rtc_wdt_config1_reg_t config1;
|
||||
volatile rtc_wdt_config2_reg_t config2;
|
||||
volatile rtc_wdt_config3_reg_t config3;
|
||||
volatile rtc_wdt_config4_reg_t config4;
|
||||
volatile rtc_wdt_feed_reg_t feed;
|
||||
volatile rtc_wdt_wprotect_reg_t wprotect;
|
||||
volatile rtc_wdt_swd_config_reg_t swd_config;
|
||||
volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect;
|
||||
volatile rtc_wdt_int_raw_reg_t int_raw;
|
||||
volatile rtc_wdt_int_st_reg_t int_st;
|
||||
volatile rtc_wdt_int_ena_reg_t int_ena;
|
||||
volatile rtc_wdt_int_clr_reg_t int_clr;
|
||||
uint32_t reserved_034[242];
|
||||
volatile rtc_wdt_date_reg_t date;
|
||||
} rtc_wdt_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(rtc_wdt_dev_t) == 0x400, "Invalid size of rtc_wdt_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user